JP2012004879A - Infrared solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an infrared solid-state imaging apparatus with detector arrays arranged two-dimensionally, capable of suppressing shading by controlling voltage distribution bias caused by a difference of a wiring resistance value generated by a stepped shape of a wiring.SOLUTION: An infrared solid-state imaging apparatus includes: a detector array 2 in which a temperature detectors 21 are two-dimensionally arranged; row selection lines 42 to which one pole of each of the temperature detectors 21 is commonly connected in each row; column signal lines 41 to which the other pole of each of the temperature detectors 21 is commonly connected in each column; a vertical scanning circuit 7 that sequentially selects the row selection lines 42 and connects them to a pixel voltage supply source; and a horizontal scanning circuit 6 that sequentially selects the column signal lines 41 and outputs an imaging output. The vertical scanning circuit 7 comprises buffer means 73 equalizing an electric potential of an input terminal and an output terminal, and a connection line of the pixel voltage supply source and the buffer means 73 is configured by commonly connecting one pole of each of dummy detectors 31 arranged in an array.

Description

  The present invention relates to an infrared solid-state imaging device in which infrared detection pixels that detect infrared rays by converting them into heat are two-dimensionally arranged.

  In a general infrared solid-state imaging device, pixels having a heat insulating structure are two-dimensionally arranged, and an infrared image is captured by utilizing the change in pixel temperature due to incident infrared rays. In the case of an uncooled infrared solid-state imaging device, a temperature sensor constituting a pixel is known that uses a silicon pn junction that converts a temperature change into a voltage change by a constant forward current.

  Further, in the infrared solid-state imaging device, the pixels are two-dimensionally arranged, connected by a selection line for each row, and connected by a signal line for each column. Each row selection line is selected in turn by the vertical scanning circuit and the vertical selection switch, and the pixel is energized from the power supply via the selected row selection line. The output of the pixel is transmitted to the integration circuit via the signal line, integrated and amplified by the integration circuit, and sequentially output to the output terminal by the horizontal scanning circuit and the horizontal selection switch. As a method for improving the temperature resolution of such an infrared solid-state imaging device, a method of reducing a noise component by reducing a differential resistance of a pn junction by increasing a bias current is effective.

  As a method for improving the temperature resolution of such an infrared solid-state imaging device, a method of reducing the noise component by reducing the differential resistance of the pn junction by increasing the bias current is effective. However, when a bias current is passed, Joule heat is generated in the pn junction, and self-overheating occurs in the pn junction, which causes a problem that the dynamic range of the temperature sensor is suppressed.

  As a method for solving this, an optical insensitive pixel column and a thermally insensitive pixel row are provided, and a self-heating component is fed back to the source voltage of the amplification transistor by the optical insensitive pixel column. Canceling the self-heating component and clamping the gate voltage of the amplifying transistor when a thermally insensitive pixel row is selected, thereby canceling the voltage distribution of the row selection line and preventing horizontal shading Is known (see, for example, Patent Document 1).

JP 2006-121652 A (6th page, FIG. 1)

  However, in such an infrared solid-state imaging device, a difference occurs in the resistance value of the wiring due to the step shape or finished shape of the generated wiring in the manufacturing process. As a result, the voltage distribution in the pixel voltage supply line is biased, which causes a problem that the output signal results in a bias failure or shading, and an accurate output result cannot be obtained. In the apparatus, the effect of shading suppression corresponding to the difference in resistance value of the wiring cannot be obtained. In addition, there is a problem that a difference in voltage distribution occurs due to a difference in temperature characteristics between the optical insensitive pixel column, the thermal insensitive pixel row, and the normal pixel.

  The present invention has been made to solve the above-described problems, and reduces the difference in resistance value between the pixel voltage supply line in the signal processing circuit and the column signal line in the detector array in the manufacturing process. At the same time, it is possible to obtain an infrared solid-state imaging device capable of suppressing bias failure and shading by matching the voltage distribution of the pixel voltage supply line and the column signal line in the detector array without being affected by the temperature characteristics.

  In the infrared solid-state imaging device according to the present invention, a detector array in which two-dimensionally arranged temperature detectors each having a temperature detecting unit composed of a pn junction diode covered with a heat insulating structure are arranged, and an anode of the pn junction diode is provided. A plurality of column signals in which a plurality of row selection lines electrically connected in common for each row and a cathode of the pn junction diode are electrically connected in common for each column and a first constant current source is connected to the end of each column A vertical scanning circuit for electrically connecting the selected line selection line and the pixel voltage supply source via the pixel voltage supply line, and the first constant current source. A second constant current source for supplying substantially the same amount of current, and both ends of the first constant current source and the second constant current source for the column signal line selected and selected in sequence. Via an integration circuit provided for each column signal line An infrared solid-state imaging device including a horizontal scanning circuit that outputs a pixel voltage connected to the pixel voltage supply source having a branch point in association with each row selection line. A switch and a buffer means for equalizing the potentials of the input end and the output end between each of the branch points and the row selection line, wherein the pixel voltage supply line is adjacent to the supply line; Using a dummy detection array in which dummy detectors having substantially the same structure as the temperature detector are arranged in the column direction between the branch points, one pole of each dummy detector is electrically connected And one end of the pixel voltage supply line is connected to a third constant current source, and the other end is connected to the other constant electrode. Connect to pixel voltage supply There.

According to the present invention, the pixel voltage supply line is formed by arranging dummy detectors having the same structure as the temperature detector and electrically connecting them in common, so that the pixel pitch of the temperature detector in the column signal line of the detector array The resistance value for each pixel and the resistance value for each pixel pitch of the dummy detector in the pixel voltage supply line are brought close to each other, and the pn junction diode of the dummy detector is electrically opened, and the pixel voltage supply line By providing buffer means for equalizing the potential at the branch point of the row and the selected line end of the selected row, the pixel voltage that is not affected by the electrical characteristics of the pn junction diode of the dummy detector Since the voltage distribution of the supply line can be matched with the voltage distribution of the column signal line, bias failure and shading can be suppressed.
The buffer means 73 equalizes the potential at the branch point of the row in the pixel voltage supply line 74 and the potential of the selection line 42 of the row.

It is a figure which shows the infrared solid-state imaging device concerning Embodiment 1 of this invention. It is the top view to which the temperature detector 21 in Embodiment 1 of this invention was expanded. It is sectional drawing of the A-A 'direction in FIG. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 1 of this invention. It is a figure which shows the buffer means in Embodiment 1 of this invention. 1 shows a configuration example of an integrating circuit according to Embodiment 1 of the present invention. It is a figure which shows the structural example of the dummy detector 31 in Embodiment 2 of this invention. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 1 of this invention. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 3 of this invention. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 3 of this invention. It is a figure which shows the buffer means in Embodiment 4 of this invention. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 5 of this invention. It is a schematic block diagram which shows the structure of the electric circuit of the infrared solid-state imaging device concerning Embodiment 6 of this invention.

Embodiment 1 FIG.
FIG. 1 shows an infrared solid-state imaging device according to the present embodiment. In the infrared solid-state imaging device according to the present embodiment, a detector array 2 in which a plurality of temperature detectors 21 are arranged on a substrate 1 and a horizontal scan for processing the electrical signals output from the temperature detectors 21 and outputting them to the outside. A circuit 6 and a vertical scanning circuit 7 are provided. The temperature detector 21 and the horizontal scanning circuit 6 are connected by a column signal line 41, and the temperature detector 21 and the vertical scanning circuit 7 are connected by a row selection line 42. Although FIG. 1 shows the case where the detector array 2 is 2 pixels × 3 pixels and the dummy detector array 3 is 2 pixels × 1 pixel, it goes without saying that other array sizes are possible.

  FIG. 2 is an enlarged plan view of the temperature detector 21 in the present embodiment. In the temperature detector 21, the temperature detection unit 211 is held hollow by two support legs 212. Each support leg has a wiring layer 213, and one of the wiring layers 213 is electrically connected to the column signal line 41. The other of the wiring layers 213 is electrically connected to the row selection line 42.

  FIG. 3 is a cross-sectional view in the A-A ′ direction in FIG. 2. As shown in FIG. 3, the temperature detector 21 is provided with a recess 216 in the center of the substrate 1, and the temperature detection unit 211 having a heat insulating structure has two wiring layers 213 wired from the two support legs 212 on the inner layer thereof. A pn junction diode 214 is configured. Here, at least one or more pn junction diodes 214 are connected in series, and the anode end is electrically connected to the row selection line 42 and the cathode end is electrically connected to the column signal line 41.

  Here, the temperature detection principle of the temperature detector 21 will be described. When infrared rays emitted from a subject to be imaged by the infrared solid-state imaging device are incident on the temperature detector 21 in the detector array 2, the temperature of the temperature detection unit 211 rises. At this time, the electrical characteristics of the pn junction diode 214 change according to the temperature change. A thermal image of the subject can be obtained by reading the electrical characteristics of each temperature detector 21 in the detector array 2 using this characteristic change. Since the substrate 1 and the temperature detection unit 211 are connected by the support legs 212, the temperature change of the temperature detection unit 211 increases as the thermal conductance of the support legs 212 decreases, and the temperature sensitivity of the temperature detector 21 increases.

  FIG. 4 is a schematic configuration diagram illustrating a configuration of an electric circuit of the infrared solid-state imaging device according to the present embodiment. A temperature detector 21 constitutes a detector array 2 in which the temperature detector 21 is two-dimensionally arranged. A row selection line 42 is commonly connected to each row of the detector array 2, and a column signal line 41 is commonly connected to each column.

  In the horizontal scanning circuit 6, a first constant current source 51, a second constant current source 52, and an integration circuit 62 having two input terminals are provided for each column, and one of the first constant current sources 51 is grounded. The other is connected to one end of the column signal line 41 of the column and one input end of the integration circuit 62 of the column. One of the second constant current sources 52 is grounded, and the other is connected to the other input terminal of the integration circuit 62 of the column in the column. Further, the other input terminals of the integrating circuits 62 of all the columns are connected in common. Here, the second constant current source 52 flows substantially the same current as the first constant current source 51.

  Further, the output terminals of the respective integrating circuits 62 are commonly connected via switches 63 provided in each column, and this connection line becomes the output terminal 8 of the infrared solid-state imaging device. Each of the switches 63 in each column is connected to the horizontal scanning means 61. Here, the horizontal scanning means 61 controls to sequentially scan in the column direction and short-circuit the switches 63 in the corresponding column.

  The vertical scanning circuit 7 includes a vertical scanning unit 71, a switch 72 and a buffer unit 73 associated with each row selection line 42, and a pixel voltage supply line 74 wired substantially in parallel with the column signal line 41. ing. Here, the pixel voltage supply line 74 is connected to one end of a third constant current source 53 that supplies substantially the same current as the first constant current source 51, and the pixel voltage supply source (see FIG. A pixel voltage is supplied from (not shown). The pixel voltage supply line 74 is connected to each row selection line 42 via a switch 72 and a buffer means 73 of the row corresponding to a branch line corresponding to the position of each row selection line 42. The vertical scanning means 71 controls to sequentially select the scanning in the row direction and to short-circuit the switch 72 in the corresponding row.

  The pixel voltage supply line 74 is provided with a dummy detector array 3 in which one dummy detector 31 is arranged between the branch points associated with the position of each row selection line 42. One of the poles is commonly connected. The other pole of the dummy detector 31 is electrically open. Here, the dummy detector 31 is the same as or similar in structure to the temperature detector 21, but has a configuration in which the connection with the temperature detection unit whose electrical characteristics change according to the temperature change is cut off.

  FIG. 5 is a diagram showing a configuration example of the buffer means 73 in the present embodiment. FIG. 5A is a voltage follower circuit in which the output terminal and the negative input terminal of the differential amplifier 731 are short-circuited. The branch point of the pixel voltage supply line 74 that is the input of the differential amplifier 731 is shown in FIG. The potentials of the differential amplifier 731 and the row selection line are equalized. FIG. 5B is obtained by adding a source grounding circuit to the output terminal of the differential amplifier 731 in FIG. Even when the current supply capability of the differential amplifier 731 is low, the grounded source circuit amplifies the current, so that a sufficient current can be supplied to the subsequent circuit.

  FIG. 6 shows a configuration example of the integrating circuit 62. The integrating circuit 62 shown in FIG. 6A converts the difference between two input signals input to the differential voltage-current conversion amplifier 621 into a current, The integration is performed by an integration capacitor 622 that is periodically reset to a predetermined voltage by a reset switch 623. The integrated output is sampled by a sampling and holding circuit 624 including a sample and hold transistor and a sample and hold capacitor. Are configured to be output. Here, the differential voltage-current conversion amplifier 621 is connected without negative feedback, and the product (= time constant) of its output impedance and the capacitance of the integration capacitor 622 is at least five times the integration time. Is set.

  On the other hand, the integration circuit 62 shown in FIG. 6B performs differential amplification using the differential amplifier 626 that performs negative feedback, and is periodically reset by the reset switch 623 using the differential amplifier 627. The integration is performed at 622, and the output after integration is sampled by the sampling hold circuit 624 and output through the buffer 625. The configuration using the differential voltage-current conversion amplifier 621 without negative feedback as shown in FIG. 6A is configured with a simpler circuit configuration than the integration circuit as shown in FIG. 6B. It is possible to achieve this, and the circuit scale can be reduced.

Next, the operation will be described in detail.
The vertical scanning circuit 7 performs scanning selection in the row direction by the vertical scanning means 71 and controls the switches 72 in the corresponding row to be short-circuited. As a result, the row selection line of the corresponding row is connected to the pixel voltage supply source via the buffer means 73. Next, the horizontal scanning circuit 6 controls the horizontal scanning means 61 to sequentially scan in the column direction and short-circuit the switches 63 in the corresponding column. As a result, each column signal line has a characteristic depending on a change in electrical characteristics in the temperature detector 21 of the corresponding column and the corresponding column, and is input to the integration circuit 62 of the column. Here, the voltage fluctuation is integrated and amplified by the integration circuit 62 of the column, and is output to the output terminal 8 of the infrared solid-state imaging device for each column selected by the horizontal scanning unit 61. A thermal image of the subject can be obtained by sequentially performing this operation in the row direction.

  Next, voltage generated at the element output terminal 8 of the infrared solid-state imaging device will be described.

  The resistance per pixel pitch of the dummy detector 31 in the pixel voltage supply line 74 is Rb, the resistance per pixel pitch of the temperature detector 21 in the row selection line 42 is Rd, and the resistance of the temperature detector 21 in the column signal line 41 is Rd. The resistance per pixel pitch is Rs, the voltage of the pn junction diode 214 in the pixel in the m-th row and the n-th column is Vf (m, n), and the constant currents of the constant current sources 51, 52, and 53 are Ic. Here, the detector array 2 is a two-dimensional array of M rows × N columns, where m represents an arbitrary row of the M rows and n represents an arbitrary column of the N columns.

At this time, in the M-row × N-column detector array 2, the voltage drop V ₊ from the pixel voltage supply source to one input terminal of the integration circuit 62 in the temperature detector 21 in the m-th row and n-th column is as follows: It is represented by the formula (1).

これはバッファ手段７３が画素用電圧供給線７４における当該行の分岐点での電位と当該行の選択線４２端との電位を等しくするものであるため、画素用電圧供給線７４には第三の定電流源５３による電流Ｉｃだけが流れ、行選択線４２への電流をバッファ手段７３がせき止めていることによる効果である。

This is because the buffer means 73 equalizes the potential at the branch point of the row of the pixel voltage supply line 74 and the potential of the selection line 42 end of the row. This is because only the current Ic from the constant current source 53 flows and the buffer unit 73 blocks the current to the row selection line 42.

Here, if the resistance per pixel pitch of the reference voltage supply line 64 is equal to the resistance Rd per pixel pitch of the row selection line 42, the nth column is supplied from the terminal of the reference voltage supply line 64. A voltage drop V ₋ from the reference voltage to the other input terminal of the integration circuit 62 is expressed by the following equation (2).

（１）式と（２）式より、電圧Ｖ_＋−Ｖ₋は、以下の（３）式で表される。

From the expressions (1) and (2), the voltage V ₊ -V ₋ is expressed by the following expression (3).

素子出力端子８に発生する電圧は、電圧Ｖ_＋−Ｖ₋を積分回路６２の利得倍したものである。電圧Ｖ_＋−Ｖ₋がｐｎ接合ダイオード２１４の電圧Ｖｆ（ｍ，ｎ）だけで決まるためには、ｎ列目にある全ての温度検出器２１において、以下の（４）式を満たすことであり、これを満たすときは、列信号線４１と画素用電圧供給線７４の電圧分布は同じになる。

The voltage generated at the element output terminal 8 is the voltage V ₊ −V ₋ multiplied by the gain of the integrating circuit 62. In order for the voltage V ₊ −V _{− to} be determined only by the voltage Vf (m, n) of the pn junction diode 214, all the temperature detectors 21 in the nth column must satisfy the following expression (4). When this is satisfied, the voltage distribution of the column signal line 41 and the pixel voltage supply line 74 is the same.

また、ｎ列目にある全ての温度検出器２１において、（４）式が成立するためには、以下の（５）式であればよい。

Further, in order to hold the equation (4) in all the temperature detectors 21 in the n-th column, the following equation (5) may be used.

このように、本発明の画素用電圧供給線７４は、構造が温度検出器２１と同じかもしくは同様であるダミー検出器３１を用いて共通配線したものであるため、画素用電圧供給線７４の１画素ピッチあたりの抵抗Ｒｂと列信号線４１の１画素ピッチあたりの抵抗Ｒｓは略同一の抵抗値であることから、（５）式を満たすこととなり、すなわち電圧Ｖ_＋−Ｖ₋がｐｎ接合ダイオード２１４の電圧Ｖｆ（ｍ，ｎ）だけで決まる。

Thus, the pixel voltage supply line 74 of the present invention is a common wiring using the dummy detector 31 having the same structure as or similar to that of the temperature detector 21. Since the resistance Rb per pixel pitch and the resistance Rs per pixel pitch of the column signal line 41 have substantially the same resistance value, the expression (5) is satisfied, that is, the voltage V ₊ -V ₋ is a pn junction. It is determined only by the voltage Vf (m, n) of the diode 214.

  From the above, in the infrared solid-state imaging device according to the present embodiment, the pixel voltage supply line 74 is configured by arranging the dummy detectors 31 having the same structure as the temperature detector 21 and electrically connecting them in common. Thus, the difference between the resistance value for each pixel pitch of the temperature detector 21 in the column signal line 41 of the detector array 2 and the resistance value for each pixel pitch of the dummy detector 31 in the pixel voltage supply line 74 can be made closer. Further, the pn junction diode of the dummy detector 31 is electrically opened to make the potential at the branch point of the row of the pixel voltage supply line 74 equal to the potential of the selected row selection line 42 end. 73 is provided, even when the temperature characteristics of the temperature detector 21 and the dummy detector 31 are different, the electric power generated by the pn junction diode of the dummy detector 31 is provided. The voltage distribution of the pixel voltage supply line 74 that is not affected by the characteristics can be obtained, and the voltage distribution of the column signal line 41 can be matched with this voltage distribution by the buffer means 73. There is a remarkable effect that can be suppressed.

  As the buffer means 73, for example, a voltage follower circuit in which the output terminal and the negative input terminal of the differential amplifier 731 shown in FIG.

For reference, a case where the buffer means 73 is not provided will be described. In the M-row × N-column detector array 2, the voltage drop V ₊ from the pixel voltage supply source to one input terminal of the integration circuit 62 in the m-th row and n-th column temperature detector 21 is expressed by the following (6). It is expressed by a formula.

この場合の電圧Ｖ_＋−Ｖ₋は（６）式と（２）式より（７）式で表される

In this case, the voltage V ₊ −V ₋ is expressed by equation (7) from equations (6) and (2).

従って、電圧Ｖ_＋−Ｖ₋がｐｎ接合ダイオード２１４の電圧Ｖｆ（ｍ，ｎ）だけで決まるためには、ｎ列目にある全ての温度検出器２１において、以下の（８）式を満たす必要がある。

Therefore, in order for the voltage V ₊ −V _{− to} be determined only by the voltage Vf (m, n) of the pn junction diode 214, all the temperature detectors 21 in the nth column must satisfy the following equation (8). There is.

ｎ列目にある全ての温度検出器２１において、（８）式が成立するためには、以下の（９）式であればよい。

In all the temperature detectors 21 in the n-th column, the following equation (9) may be used in order to establish the equation (8).

（９）式から明らかなように、バッファ手段７３がなければ、電圧Ｖ_＋−Ｖ₋がｐｎ接合ダイオード２１４の電圧Ｖｆ（ｍ，ｎ）だけで決まるためには、画素用電圧供給線７４の１画素ピッチあたりの抵抗Ｒｂと該列信号線４１の１画素ピッチあたりの抵抗Ｒｓとを同じ寸法、構造、または、材質では問題があるため、寸法、構造、または、材質を変える必要があった。さらに、検出器アレイ２の列数を変えると、画素用電圧供給線７４と検出器アレイ２の列信号線４１の抵抗値を見直す必要があることが明らかである。

As apparent from the equation (9), if the buffer means 73 is not provided, the voltage V ₊ −V ₋ can be determined only by the voltage Vf (m, n) of the pn junction diode 214. Since the resistance Rb per pixel pitch and the resistance Rs per pixel pitch of the column signal line 41 have a problem with the same size, structure, or material, it is necessary to change the size, structure, or material. . Further, when the number of columns of the detector array 2 is changed, it is apparent that the resistance values of the pixel voltage supply line 74 and the column signal line 41 of the detector array 2 need to be reviewed.

  As shown in FIG. 7, the dummy detector 31 closest to the third constant current source 53 and the third constant current source 53 have the same impedance as that of the pn junction diode 214 in the temperature detector 21. If a device is provided, a voltage drop from the pixel voltage supply source to the integrating circuit 62 via the buffer means 73, the switch 72, and the temperature detector 21, and from the pixel voltage supply source via the pixel voltage supply line 74. This is desirable because the difference from the voltage drop to the third constant current source 53 becomes more equal. Even if this is realized by connecting the cathode to the third constant current source 53 via the pn junction diode of the dummy detector 31 closest to the third constant current source 53, the same effect may be obtained. Absent.

Embodiment 2. FIG.
The dummy detector 31 in the first embodiment has substantially the same structure as the temperature detector 21, and the dummy detectors 31 are arranged and one pole of each dummy detector 31 is commonly wired. Although the voltage supply line 74 is formed, the dummy detector 31 achieves the intended purpose even if the dummy detector 31 has a structure that does not constitute a temperature detection unit and a support leg.

  FIG. 8 is a diagram showing a configuration example of the dummy detector 31 in the present embodiment, and FIG. 8A is a side view of the dummy detector 31 showing an example of the dummy detector 31 in the present embodiment. FIG. 8B is a diagram from the top of the dummy detector 31 showing two examples of the dummy detector 31 in the present embodiment.

  In this embodiment, as shown in FIG. 8A, the environmental temperature is changed by adopting a configuration in which the pn junction diode is omitted inside the temperature detection unit that is held hollow by the support leg of the dummy detector 31. Sometimes, even if the temperature characteristics of the temperature detector 21 and the dummy detector 31 are different, the dummy detector 31 has nothing to change the electrical characteristics depending on the temperature, so the voltage of the pixel voltage supply line 74 Since the distribution is not affected by the electrical characteristics depending on the environmental temperature, the voltage distribution of the column signal line 41 and the pixel voltage supply line 74 is equal to the voltage distribution independent of the environmental temperature.

  As described above, the infrared solid-state imaging device according to the present embodiment can obtain an infrared imaging result in which the influence on the environmental temperature is further suppressed.

  Further, it goes without saying that the same effect can be obtained even when the supporting leg and the temperature detecting unit are omitted from the dummy detector 31 as shown in FIG. 8B.

Embodiment 3 FIG.
In the first embodiment and the second embodiment, the dummy detection array is configured in a single-row arrangement, but in the third embodiment, an infrared solid-state imaging device having a configuration in which the dummy detection arrays are two-dimensionally arranged is shown.

  FIG. 9 is a schematic configuration diagram illustrating a configuration of an electric circuit of the infrared solid-state imaging device according to the third embodiment. Except for the dummy detector array, which is a feature of the present embodiment, the structure, configuration, and operation of components having the same reference numerals as those in the first embodiment or the second embodiment are the same as those in the first or second embodiment. Here, detailed description will be made only for the dummy detector array, which is a feature of the present embodiment.

  The dummy detector array 3 of the infrared solid-state imaging device according to the present embodiment is arranged in a plurality of rows of three or more columns, and the pixel voltage supply line 74 is connected by commonly connecting one pole of the dummy detectors in the inner column. Constitute.

  Here, it is considered that variations due to pattern density occur at the time of etching in the central portion and the outer peripheral portion of the detector array. In the first and second embodiments, since the dummy detector array 3 is arranged in a plurality of rows and one column, the column signal line 41 of the detector array 2 is the central portion, and the pixel voltage supply line 74 of the dummy detector array 3 is the outer peripheral portion. And a slight difference remains in the wiring structure and the resistance value. On the other hand, in the infrared solid-state imaging device according to the present invention, since the dummy detector array 3 has a plurality of rows and three columns, the column signal line 41 of the detector array 2 and the pixel voltage of the dummy detector array 3 are used. Both of the supply lines 74 correspond to the central portion, and the wiring structure and thus the difference in resistance value is reduced.

  As described above, the pixel voltage supply line 74 is configured using the dummy detectors in the center column of the dummy detector array arranged in three columns as in the present embodiment, so that the outer side of the detector array 2 The structures of the column signal lines 41 other than the columns and the pixel voltage supply lines 74 of the dummy detector array 3 are more congruent than those of the first and second embodiments, and the resistance values are closer to the same value. (5) It is approximated by the formula. Therefore, the pixel voltage supply line 74 and the column signal line 41 of the detector array 2 may have the same size, structure, or material. Furthermore, even if the number of columns of the detector array 2 is changed, it is not necessary to review the resistance values of the pixel voltage supply line 74 and the column signal line 41 of the detector array 2.

  Here, even if the dummy detector has the structure of the dummy detector in the second embodiment, the corresponding column of the dummy detectors in which the dummy detector array constitutes the pixel voltage supply line 74 in a plurality of rows of three or more columns is outside. It is self-evident that it is not necessary to have a sequence of

  As shown in FIG. 10, the pn junction diode 214 in the temperature detector 21 is further between the dummy detector 31 and the third constant current source 53 that are in the corresponding column and closest to the third constant current source 53. Is provided, the voltage drop from the pixel voltage supply source to the integrating circuit 62 via the buffer means 73, the switch 72, and the temperature detector 21, and the pixel voltage supply from the pixel voltage supply source. This is desirable because the difference from the voltage drop through line 74 to the third constant current source 53 is more equal. Even if this is realized by connecting the third constant current source 53 to the cathode via the pn junction diode of the dummy detector 31 closest to the third constant current source 53 in the corresponding column, the same effect is obtained. You don't mind getting.

Embodiment 4 FIG.
FIG. 11 is a diagram illustrating the buffer unit 73 of the infrared solid-state imaging device according to the fourth embodiment. The feature of this embodiment is the configuration of the buffer means 73, and the structure, configuration, and operation of the components having the same reference numerals as those of the above-described embodiment are the same. This is performed only for the buffer means 73 which is the feature of the above. In FIG. 11A, a switch 735 is provided between the buffer 734 and the buffer power source 732. The switch 735 is controlled to short-circuit the buffer 734 and the power source 732 for the buffer 734 only for a necessary period. On the other hand, in FIG. 11B, a switch 736 is provided between the buffer 734 and the ground potential for the buffer 734. The switch 736 is also controlled so as to short-circuit the buffer 734 and the ground potential for the buffer 734 only during a necessary period. The switch 735 or the switch 736 is short-circuit controlled in synchronization with the switch 72 in the vertical scanning circuit 7.

  As described above, by using the buffer means which is a feature of this embodiment as the buffer means of the above-described embodiment, it is possible to limit the period during which a steady current flows in each buffer means 73, thereby reducing power consumption. Is possible.

Embodiment 5 FIG.
FIG. 12 is a schematic configuration diagram showing a configuration of an electric circuit of the infrared solid-state imaging device according to the fifth embodiment. The feature of the present embodiment is the configuration of the buffer means 75, and the structure, configuration and operation of the components having the same reference numerals as those of the above-described embodiment are the same. This is performed only for the buffer means 75 which is a feature of the above. The buffer means 75 provided for each row is composed of an emitter follower circuit composed of an NPN-type bipolar transistor, the base terminal of each emitter follower circuit is connected to the pixel voltage supply line 74, and the collector terminal of each emitter follower circuit is common. The collector voltage supply line 76 is connected. The emitter terminal of each emitter follower circuit is connected to the row selection line 42 of the row via the switch 72 of the row. The current flowing through the pixel voltage supply line 74 is multiplied by the current amplification factor h _FE of the NPN bipolar transistor and supplied to the row selection line 42. The The emitter electrode of the emitter follower circuit, the current flows NIc by constant current source 51 of the N columns, when the current amplification factor h _FE is (10) holds, the voltage for pixels connected to the base electrode of the emitter-follower circuit A current Ic flows through the supply line 74. At this time, current (N−1) · Ic flows through the collector voltage supply line 76.

一般的には、バイポーラトランジスタの電流増幅率ｈ_ＦＥは大きくばらつくため、検出器アレイ２の各行に配置したエミッタホロワ回路２０の電流増幅率ｈ_ＦＥを均一に、かつ、式（１０）を満たすように製造することは、困難である。しかし、近年の半導体デバイス製造技術の向上により可能となってきている。

In general, since the large variation current amplification factor h _FE of the bipolar transistor, a uniform current amplification factor h _FE of the emitter follower circuit 20 arranged in each row of the detector array 2 and to satisfy equation (10) It is difficult to manufacture. However, this has become possible due to recent improvements in semiconductor device manufacturing technology.

Since the current Ic flows through the pixel voltage supply line 74, the voltage drop V ₊ from the pixel voltage supply source to one input terminal of the integration circuit 62 is expressed by equation (1), as in the first embodiment. Is done. For the n-th column, the voltage drop V ₋ from the reference voltage supply source to the other input terminal of the integrating circuit 62 is expressed by equation (6) as in the conventional case. Therefore, the voltage V ₊ −V ₋ is expressed by the expression (3) as in the first embodiment from the expressions (1) and (6).

  From the above, it is needless to say that the predetermined object can be achieved even if the buffer means of the above-described embodiment is constituted by an emitter follower circuit composed of an NPN-type bipolar transistor which is a feature of this embodiment.

Embodiment 6 FIG.
In the fifth embodiment, the buffer means is composed of an emitter follower circuit composed of an NPN type bipolar transistor. However, the buffer means can also be composed of an emitter follower circuit composed of a PNP type bipolar transistor.

FIG. 13 is a schematic configuration diagram illustrating a configuration of an electric circuit of the infrared solid-state imaging device according to the sixth embodiment. The feature of the present embodiment is the configuration of the buffer means 77, and the structure, configuration, and operation of the components having the same reference numerals as those of the above-described embodiment are the same. This is performed only for the buffer means 77 which is a feature of the above. The buffer means 77 provided for each row is composed of an emitter follower circuit composed of a PNP-type bipolar transistor, the base terminal of each emitter follower circuit is connected to the pixel voltage supply line 74, and the emitter terminals of the respective emitter follower circuits are common. The emitter voltage supply line 78 is connected. The collector terminal of each emitter follower circuit is connected to the row selection line 42 of the row via the switch 72 of the row. The current flowing through the pixel voltage supply line 74 is multiplied by the current amplification factor h _FE of the PNP bipolar transistor and supplied to the row selection line 42. The The collector electrode of the emitter follower circuit, the current flows NIc by constant current source 51 of the N columns, when the current amplification factor h _FE is (11) holds, the voltage for pixels connected to the base electrode of the emitter-follower circuit A current Ic flows through the supply line 74. At this time, current (N + 1) · Ic flows through the emitter voltage supply line 78.

From the above, it goes without saying that the predetermined object similar to that of the fifth embodiment can be achieved even if the buffer means of the above-described embodiment is constituted by an emitter follower circuit composed of a PNP bipolar transistor, which is a feature of the present embodiment. Yes.

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Detector array 21 Temperature detector 211 Temperature detection part 214 Pn junction diode 3 Dummy detector array 31 Dummy detector 41 Column signal line 42 Row selection line 51 1st constant current source 52 2nd constant current source 53 Third constant current source 6 Horizontal scanning circuit 62 Integration circuit 7 Vertical scanning circuit 73 Buffer means 74 Pixel voltage supply line

Claims (6)

A detector array in which two-dimensionally arranged temperature detectors each having a temperature detecting unit composed of a pn junction diode covered with a heat insulating structure;
A plurality of row selection lines in which anodes of the pn junction diodes are electrically connected in common for each row;
A plurality of column signal lines in which the cathodes of the pn junction diodes are electrically connected in common to each column and the first constant current source is connected to the end of each column;
A vertical scanning circuit that sequentially connects the row selection lines and electrically selects the selected row selection lines and the pixel voltage supply lines;
A second constant current source for supplying substantially the same amount of current as the first constant current source;
The column signal lines are sequentially selected and the voltage across the first constant current source and the second constant current source for the selected column signal line is output via an integration circuit provided for each column signal line. An infrared solid-state imaging device comprising a horizontal scanning circuit that
The vertical scanning circuit includes a pixel voltage supply line connected to the pixel voltage supply source having a branch point in association with each row selection line, and between each branch point and the row selection line. And a buffer means for equalizing the potentials of the switch and the input end and the output end,
The pixel voltage supply line uses a dummy detection array in which dummy detectors each having a structure substantially the same as that of the temperature detector are arranged in the column direction between the adjacent branch points. An infrared solid-state imaging device comprising: a pn junction diode having at least one electrode electrically open. The infrared solid-state imaging device according to claim 1, wherein the dummy detector has a configuration in which the temperature detection unit is omitted from substantially the same structure as the temperature detector. The dummy detection array is two-dimensionally arranged in three or more columns,
3. The pixel voltage supply line is configured by using the dummy detectors arranged in any one of the inner columns of the dummy detection array. Infrared solid-state imaging device. The buffer means is connected to a power source or a ground via a switch,
4. The infrared solid-state imaging device according to claim 1, wherein the switch is electrically connected only in a predetermined period in each row. 5. The infrared solid-state imaging device according to any one of claims 1 to 4, wherein the buffer means includes an emitter follower circuit including a bipolar transistor. The integration circuit converts the voltage difference between the first constant current source and the second constant current source into a current by a differential voltage current conversion amplifier, and integrates it into a capacitor that is periodically reset to a constant voltage. The infrared solid-state imaging device according to any one of claims 1 to 5, wherein:

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