JP2012004373A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device.SOLUTION: A substrate 1C comprises: an SOI region 1A in which a semiconductor substrate 2, an insulating layer 3, and a semiconductor layer 4 are stacked; and a bulk region 1B including the semiconductor substrate 2. In MISFETs formed on the semiconductor layer 4 in the SOI region 1A, impurities are not introduced into channel regions, whereas in MISFETs formed on the semiconductor substrate 2 in the bulk region 1B, impurities are introduced into channel regions. When the MISFETs in the SOI region 1A are formed, ion implantation, channel doping ion implantation, and halo ion implantation for well region formation are not performed, in order that impurities are not introduced into the channel regions of the MISFETs. When the MISFETs in the bulk region 1B are formed, ion implantation, channel doping ion implantation, and halo ion implantation for well region formation are performed.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a technique effective when applied to the manufacture of a semiconductor device having a MISFET.

  A semiconductor device is manufactured by forming a semiconductor element such as a MISFET on a semiconductor substrate, forming a multilayer wiring structure on the semiconductor substrate, and connecting the semiconductor elements.

  Patent Documents 1 to 9 describe techniques for forming a MISFET in an SOI structure.

JP 2009-170718 A JP 2009-135140 A JP 2009-94369 A JP 2008-22732 A JP 2009-78672 A JP 2007-42730 A JP 2007-194547 A JP 2007-179602 A JP 2005-179602 A

  According to the study of the present inventor, the following has been found.

  A semiconductor device having a MISFET can be manufactured as follows. That is, an element isolation region is formed in a semiconductor substrate, and channel doping ion implantation for adjusting the threshold value of the MISFET is performed in an active region defined by the element isolation region, and then a gate insulating film and a gate electrode are formed. To do. Then, an extension region for LDD and a halo region are formed by ion implantation using the gate electrode as a mask, and then a sidewall insulating film is formed on the sidewall of the gate electrode, and the gate electrode and the sidewall insulating film are used as a mask. By implantation, source / drain regions having a higher impurity concentration than the extension region are formed. Thereafter, a metal silicide layer is formed on the source / drain regions by a salicide process.

  Along with miniaturization and high performance of semiconductor devices, miniaturization of elements (such as MISFETs) formed on a semiconductor substrate is also progressing. However, as the miniaturization accelerates, the characteristic variation represented by the threshold value of MISFET increases, and the adjacent MISFETs having the same processing shape also have different threshold values. Equipment performance and manufacturing yield will be reduced. The main cause of the variation in the threshold value of the MISFET is the discreteness of the channel impurity distribution that determines the threshold value of the MISFET. This variation is called random variation, and the random variation is the product of the gate length and the gate width ( It is inversely proportional to the square root of the gate area. In a semiconductor device to which a miniaturization process is applied, a MISFET having the smallest gate length and gate width is used for a memory such as an SRAM. Therefore, as miniaturization progresses, random variation increases and the memory does not operate normally. come. Further, in addition to the reduction in gate length and gate width due to miniaturization, the increase in channel impurity concentration accompanying the reduction in the thickness of the gate insulating film contributes to further increasing the variation in the threshold value of the MISFET. Therefore, in order to improve the performance of the semiconductor device, it is desired to reduce random variations.

  Also, when taking measures to reduce random variations, if the same measures are applied uniformly to all elements formed on the semiconductor substrate, the same measures are taken for elements that are likely to cause random variations and elements that are less likely to occur. As a result, the design of the entire semiconductor device needs to be changed drastically, increasing the time, labor, and cost associated with the design change.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the performance of a semiconductor device while achieving miniaturization.

  Another object of the present invention is to provide a technique capable of improving the performance of a semiconductor device while facilitating a design change of the semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment includes a semiconductor substrate having a first region having an SOI structure in which an insulating layer is embedded and a second region in which the insulating layer is not embedded and does not have an SOI structure. This is a semiconductor device in which a plurality of MISFETs are formed. Of the plurality of MISFETs, no impurity is introduced into the channel region of the MISFET formed in the first region, and no impurity is introduced into the channel region of the MISFET formed in the second region. Yes.

  In addition, a method of manufacturing a semiconductor device according to a representative embodiment includes a first region having an SOI structure in which an insulating layer is embedded, and a second region having no SOI structure in which the insulating layer is not embedded. Are prepared, a first MISFET is formed in the first region of the semiconductor substrate, and a second MISFET is formed in the second region of the semiconductor substrate. The step is performed so that impurities are not ion-implanted into the channel region of the first MISFET formed in the first region.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the representative embodiment, the performance of the semiconductor device can be improved.

  Further, the performance of the semiconductor device can be improved while miniaturization is achieved.

  Further, the performance of the semiconductor device can be improved while facilitating the design change of the semiconductor device.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; It is a top view of the semiconductor device which is other embodiments of the present invention. It is a top view of the semiconductor device which is other embodiments of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46; FIG. 48 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 47; FIG. 49 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 48; FIG. 50 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 49; FIG. 51 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 50; FIG. 52 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 51; FIG. 53 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 52; FIG. 54 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 53; FIG. 55 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 54; FIG. 56 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 55; FIG. 57 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 56;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The semiconductor device of this embodiment and its manufacturing process will be described with reference to the drawings. 1 to 22 are fragmentary cross-sectional views of a semiconductor device according to an embodiment of the present invention during the manufacturing process. The semiconductor device of the present embodiment is a semiconductor device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 1, an SOI (SOI: Silicon On Insulator) substrate 1 is prepared. The SOI substrate 1 is formed on a semiconductor substrate 2 made of single crystal silicon, an insulating layer (embedded insulating film) 3 made of silicon oxide or the like formed on the main surface of the semiconductor substrate 2, and an upper surface of the insulating layer 3. And a semiconductor layer 4 made of single crystal silicon.

  The SOI substrate 1 can be manufactured by using various methods, and for example, can be manufactured by bonding and polishing two semiconductor substrates (semiconductor wafers). The SOI substrate 1 can also be manufactured using another method, for example, a smart cut process. The thickness of the semiconductor layer 4 (thickness in the direction perpendicular to the main surface of the SOI substrate 1) is thinner than the thickness of the semiconductor substrate 2. The thickness of the semiconductor layer 4 can be about 10 to 50 nm, for example, and the thickness of the insulating layer 3 can be about 10 to 50 nm, for example. The thickness of the semiconductor substrate 2 can be about 300 to 750 μm, for example.

  The SOI substrate 1 does not have the SOI structure because the SOI region 1A, which is a region (planar region) where the SOI structure is maintained until the semiconductor device is completed, and the semiconductor layer 4 and the insulating layer 3 are removed later (however, The semiconductor substrate 2 has a bulk region 1B which is a region (planar region). In the case of an SOI structure, a silicon layer (a single crystal silicon layer) can be preferably used as a semiconductor layer over an insulating layer, but the present invention is not limited to this. For example, in Embodiment 4 described later, a semiconductor layer other than a silicon single crystal is used as the semiconductor layer on the insulating layer.

  Next, as shown in FIG. 2, an element isolation region (element isolation structure) 5 is formed on the SOI substrate 1. The element isolation region 5 is formed of an insulator (for example, silicon oxide) embedded in the element isolation groove 5a. The element isolation trench 5 a and the element isolation region 5 filling the element isolation trench 5 a penetrate the semiconductor layer 4 and the insulating layer 3, and the bottom of the element isolation region 5 reaches the semiconductor substrate 2. Located in. That is, the element isolation region 5 is embedded in the element isolation groove 5 a formed over the semiconductor layer 4, the insulating layer 3, and the semiconductor substrate 2. For this reason, a part of the element isolation region 5 is located below the lower surface of the insulating layer 3.

  In the element isolation region 5, an element isolation groove 5 a that penetrates the semiconductor layer 4 and the insulating layer 3 and has a bottom portion located in the semiconductor substrate 2 is formed on the main surface of the SOI substrate 1 (semiconductor layer 4). It can be formed by using an etching technique or the like and embedding an insulating film in the element isolation trench 5a using a film forming technique or a CMP technique.

  Next, as shown in FIG. 3, a photoresist pattern PR1 that covers the bulk region 1B of the SOI substrate 1 and exposes the SOI region 1A of the SOI substrate 1 is formed on the SOI substrate 1 by using a photolithography technique. It is formed on the main surface of the semiconductor layer 4. Then, ion implantation for threshold adjustment is performed in the SOI region 1A of the SOI substrate 1. This ion implantation is indicated by an arrow labeled P1 in FIG. 3, and is hereinafter referred to as ion implantation P1. In FIG. 3, the region into which the impurity is introduced by the ion implantation P <b> 1 is denoted by reference numeral 6 and is indicated as a semiconductor region (impurity diffusion layer) 6.

  The ion implantation P1 is an ion implantation for controlling a threshold value of a MISFET to be formed later in the SOI region 1A. In this ion implantation P1, impurity ions are introduced into the semiconductor substrate 2 of the SOI substrate 1 in the SOI region 1A, but impurity ions are prevented from being introduced into the semiconductor layer 4 of the SOI substrate 1. Further, in this ion implantation P1, since the photoresist pattern PR1 functions as an ion implantation blocking mask, no impurities are introduced into the bulk region 1B of the SOI substrate 1.

  What is important in the present embodiment is that impurity ions are not implanted into the semiconductor layer 4 of the SOI substrate 1 in the ion implantation P1, which is different from the present embodiment in that the SOI substrate is used in the ion implantation P1. This is because when impurity ions are implanted into one semiconductor layer 4, it causes variations in threshold values of MISFETs formed later in the SOI region 1 </ b> A.

  For this reason, the ion implantation P1 is performed with such a high implantation energy that impurity ions can penetrate the semiconductor layer 4. The ion implantation energy is adjusted by the thickness of the semiconductor layer 4 and the thickness of the insulating layer 3 and is set so that at least the projected distance of impurity ions is located in the semiconductor substrate 2. Thus, impurity ions can be implanted into the semiconductor substrate 2 in the SOI region 1A without implanting impurity ions into the semiconductor layer 4 in the SOI region 1A by the ion implantation P1.

  In the ion implantation P1, impurities are ion-implanted into the semiconductor substrate 2 below the insulating layer 3 in the SOI region 1A, but also in a region close to the insulating layer 3 in the semiconductor substrate 2 (region adjacent to the insulating layer 3). Preferably, impurity ions are implanted. That is, it is preferable that the semiconductor region 6 formed in the semiconductor substrate 2 is in contact with (is adjacent to) the insulating layer 3. By adjusting the impurity concentration of the semiconductor region 6 by the implantation amount (dose amount) of the ion implantation P1, the threshold value of the MISFET formed later in the SOI region 1A can be controlled. Therefore, in the manufactured semiconductor device, an impurity is introduced into a region (corresponding to the semiconductor region 6) adjacent to the insulating layer 3 in the semiconductor substrate 2 below the insulating layer 3 in the SOI region 1A. After the ion implantation P1, the photoresist pattern PR1 is removed.

  Next, as shown in FIG. 4, a photoresist pattern PR2 that covers the SOI region 1A of the SOI substrate 1 and exposes the bulk region 1B of the SOI substrate 1 is formed on the SOI substrate 1 by using a photolithography technique. It is formed on the main surface of the semiconductor layer 4.

  Next, the semiconductor layer 4 and the insulating layer 3 in the bulk region 1B are removed by etching using the photoresist pattern PR2 as an etching mask. At this time, since the SOI region 1A is covered with the photoresist pattern PR2, the semiconductor layer 4 and the insulating layer 3 in the SOI region 1A remain without being removed. As a result, the semiconductor substrate 2 is exposed (not the SOI structure) in the bulk region 1B, and the SOI structure (laminated structure of the semiconductor substrate 2, the insulating layer 3, and the semiconductor layer 4) is maintained in the SOI region 1A.

  The SOI substrate 1 at this stage is referred to as a substrate 1C. Here, the bulk region 1B of the substrate 1C is configured by the semiconductor substrate 2 with the semiconductor layer 4 and the insulating layer 3 removed, and the SOI region 1A of the substrate 1C has an SOI structure (the semiconductor substrate 2, the insulating layer 3, and the semiconductor layer). 4 is maintained). Hereinafter, the main surface (or surface) of the substrate 1C is synonymous with the main surface (or surface) of the semiconductor layer 4 in the SOI region 1A and the main surface (or surface) of the semiconductor substrate 2 in the bulk region 1B. . The substrate 1C includes the SOI region 1A and the bulk region 1B. The SOI region 1A can be regarded as a region having an SOI structure in which the insulating layer 3 is embedded, and the bulk region 1B includes the insulating layer 3 It can be regarded as a region that is not buried and does not have an SOI structure. Specifically, the SOI region 1A of the substrate 1C is a region having a stacked structure (SOI structure) in which the semiconductor substrate 2, the insulating layer 3 on the semiconductor substrate 2, and the semiconductor layer 4 on the insulating layer 3 are stacked. In addition, the bulk region 1B of the substrate 1C is a region in which the entire thickness is constituted by the semiconductor substrate 2. However, the SOI region 1A and the bulk region 1B may include a region where the element isolation regions 5 and 5b exist in the thickness direction.

  Thereafter, the photoresist pattern PR2 is removed. In the bulk region 1B, a part of the element isolation region 5 (portion located below the lower surface of the insulating layer 3) is embedded in the semiconductor substrate 2 even after the semiconductor layer 4 and the insulating layer 3 are removed. This becomes the element isolation region 5b of the bulk region 1B.

  Here, the bulk region 1B has a low breakdown voltage MIS formation region 1BL that is a region where a low breakdown voltage MISFET is formed and a high breakdown voltage MIS formation region 1BH that is a region where a high breakdown voltage MISFET is formed.

  Next, a thin insulating film (through film, not shown here) for preventing surface contamination is formed on the surface of the substrate 1C (that is, the surface of the semiconductor substrate 2 in the bulk region 1B and the surface of the semiconductor layer 4 in the SOI region 1A). Then, as shown in FIG. 5, a photoresist pattern PR3 is formed on the main surface of the substrate 1C by using a photolithography technique. The photoresist pattern PR3 is formed so as to cover the SOI region 1A and the low breakdown voltage MIS formation region 1BL of the bulk region 1B and to expose the high breakdown voltage MIS formation region 1BH of the bulk region 1B. This photoresist pattern PR3 can function as an ion implantation blocking mask for the SOI region 1A and the low breakdown voltage MIS formation region 1BL of the bulk region 1B.

  Next, in the high breakdown voltage MIS formation region 1BH of the bulk region 1B, ion implantation (that is, channel dope ion implantation) P2 for adjusting the threshold value of the MISFET to be formed later is performed on the upper layer (surface layer) portion of the semiconductor substrate 2. Do. In FIG. 5, the channel dope ion implantation P2 is schematically indicated by an arrow. Further, in the channel dope ion implantation P2, impurities are introduced into the upper layer (surface layer) portion of the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH of the bulk region 1B. In FIG. 5, the impurities introduced by the channel dope ion implantation P2 ( Impurity ions) are schematically indicated by X marks and are denoted by reference numeral 15 (in FIG. 6 and thereafter, the X marks indicating the impurities 15 introduced by the channel dope ion implantation P2 are not shown). Since the semiconductor layer 4 and the semiconductor substrate 2 in the SOI region 1A and the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL in the bulk region 1B are covered with the photoresist pattern PR3, impurities are introduced during the channel dope ion implantation P2. Ions are not implanted. Thereafter, the photoresist pattern PR3 is removed.

  Next, as shown in FIG. 6, a photoresist pattern PR4 is formed on the main surface of the substrate 1C using a photolithography technique. The photoresist pattern PR4 is formed so as to cover the SOI region 1A and the high breakdown voltage MIS formation region 1BH of the bulk region 1B and to expose the low breakdown voltage MIS formation region 1BL of the bulk region 1B. The photoresist pattern PR4 can function as an ion implantation blocking mask for the SOI region 1A and the high breakdown voltage MIS formation region 1BH.

  Next, in the low breakdown voltage MIS formation region 1BL of the bulk region 1B, ion implantation (that is, channel dope ion implantation) P3 for adjusting the threshold value of the MISFET to be formed later is performed on the upper layer (surface layer) portion of the semiconductor substrate 2. Do. In FIG. 6, the channel dope ion implantation P3 is schematically indicated by an arrow. Further, in the channel dope ion implantation P3, impurities are introduced into the upper layer (surface layer) portion of the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL of the bulk region 1B, and in FIG. 6, the impurities introduced by the channel dope ion implantation P3 ( Impurity ions) are schematically indicated by x marks and are denoted by reference numeral 16 (in FIG. 7 and subsequent figures, the x marks indicating the impurities 16 introduced by the channel dope ion implantation P3 are not shown). Since the semiconductor layer 4 and the semiconductor substrate 2 in the SOI region 1A and the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B are covered with the photoresist pattern PR4, impurities are introduced during the channel dope ion implantation P3. Ions are not implanted. Thereafter, the photoresist pattern PR4 is removed.

  Impurities are introduced (doped) into the channel region of the MISFET formed in the high breakdown voltage MIS formation region 1BH of the bulk region 1B by the channel dope ion implantation P2. Further, impurities are introduced (doped) into the channel region of the MISFET formed in the low breakdown voltage MIS formation region 1BL of the bulk region 1B by the channel dope ion implantation P3. That is, in channel dope ion implantation, impurities (impurity ions) are introduced (doped) into a region including the channel region of the MISFET. The “channel region of the MISFET” here corresponds to a region that becomes a channel region of the MISFET when the MISFET is formed afterwards even though the MISFET is not formed at the channel doping ion implantation stage.

  What is important in the present embodiment is that channel doping ion implantation (here, channel doping ion implantations P2 and P3) is performed on the semiconductor substrate 2 in the bulk region 1B, but channel doping is performed on the semiconductor layer 4 in the SOI region 1A. The ion implantation is not performed. Therefore, when channel-doped ion implantation (here, channel-doped ion implantations P2 and P3) is performed on the semiconductor substrate 2 in the bulk region 1B, the SOI region 1A has an ion implantation blocking mask (here, the photoresist pattern PR3 and photoresist pattern PR3). Cover with PR4).

  Next, as shown in FIG. 7, a p-type well PW1 is formed in the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B, and p is formed in the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL in the bulk region 1B. A mold well PW2 is formed. Each of the p-type well PW1 and the p-type well PW2 can be formed by ion implantation using a photoresist pattern (not shown) as an ion implantation blocking mask. The number of steps can be reduced if the ion implantation for forming the p-type well PW1 and the ion implantation for forming the p-type well PW2 are performed in the same ion implantation step, but they may be performed as different ion implantation steps. The channel dope ion implantation P2 and P3 can be performed after the p-type well PW1 and the p-type well PW2 are formed.

  In this embodiment, ion implantation for forming a well region is performed on the semiconductor substrate 2 in the bulk region 1B, but ion implantation for forming the well region is performed on the semiconductor layer 4 in the SOI region 1A. Don't do it. Therefore, at the time of ion implantation for forming the p-type well PW1 and ion implantation for forming the p-type well PW2, the SOI region 1A has a photoresist pattern (not shown) as an ion implantation blocking mask. The impurity ions are not implanted into the semiconductor layer 4 in the SOI region 1A.

  In the high breakdown voltage MIS formation region 1BH of the bulk region 1B, a region into which impurities are introduced by channel doping ion implantation P2 (channel doped layer) is formed shallow in the upper layer portion of the semiconductor substrate 2, and the p-type well PW1 is formed on the semiconductor substrate. 2 is formed deeper than the channel dope layer. Further, in the low breakdown voltage MIS formation region 1BL of the bulk region 1B, a region into which impurities are introduced by channel dope ion implantation P3 (channel dope layer) is formed shallow in the upper layer portion of the semiconductor substrate 2, and the p-type well PW2 is The semiconductor substrate 2 is formed deeper than the channel dope layer.

  Next, after the surface (main surface) of the substrate 1C is cleaned (for example, unnecessary oxide film is removed) by wet etching using a hydrofluoric acid (HF) aqueous solution, as shown in FIG. A gate insulating film 7a is formed on the semiconductor layer 4 in the region 1A, a gate insulating film 7b is formed on the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B, and a low breakdown voltage MIS formation region 1BL in the bulk region 1B. A gate insulating film 7 c is formed on the semiconductor substrate 2. The gate insulation film 7b formed in the high breakdown voltage MIS formation region 1BH is thicker and has a higher breakdown voltage than the gate insulation film 7a formed in the SOI region 1A and the gate insulation film 7c formed in the low breakdown voltage MIS formation region 1BL.

  The gate insulating films 7a, 7b, and 7c having different thicknesses can be formed as follows, for example.

  That is, after an insulating film for the gate insulating film 7b is formed on the entire main surface of the substrate 1C by thermal oxidation and CVD, this insulating film is removed by etching in the SOI region 1A and the low breakdown voltage MIS formation region 1BL. This insulating film is left in the breakdown voltage MIS formation region 1BH. Then, a silicon oxide film is formed on the main surface of the substrate 1C by thermal oxidation. As a result, gate insulating films 7a and 7c made of a thin silicon oxide film (thermal oxide film) are formed on the semiconductor layer 4 in the SOI region 1A and the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL in the bulk region 1B. In the high breakdown voltage MIS formation region 1BH, the thickness of the insulating film for the gate insulating film 7b is increased, resulting in a thick gate insulating film 7b. When it is necessary to make the gate insulating film 7a thinner than the gate insulating film 7c, the silicon oxide film on the surface of the semiconductor layer 4 in the SOI region 1A is removed by etching, and then the main surface of the substrate 1C is again formed by thermal oxidation. A silicon oxide film may be formed.

  Since the high breakdown voltage gate insulating film 7b is thicker than the gate insulating film 7a in the SOI region 1A and the gate insulating film 7c in the low breakdown voltage MIS formation region 1BL, the breakdown voltage of the MISFET formed in the high breakdown voltage MIS formation region 1BH is The breakdown voltage of the MISFET formed in the SOI region 1A and the MISFET formed in the low breakdown voltage MIS formation region 1BL is higher.

  Next, as shown in FIG. 9, over the entire main surface of the substrate 1C (that is, on the gate insulating films 7a, 7b, 7c), a polycrystalline silicon film (doped layer) is formed as a conductor film for forming a gate electrode. After a silicon film 8 such as a polysilicon film is formed, an insulating film 9 such as a silicon nitride film is formed on the silicon film 8. It is preferable to continuously form the silicon film 8 after forming the gate insulating films 7a, 7b, and 7c. Then, after patterning the insulating film 9 using a photolithography method and a dry etching method, the silicon film 8 is patterned by dry etching using the patterned insulating film 9 as a hard mask (etching mask). When the silicon film 8 is dry-etched, the etching is stopped when the gate insulating film in each region (the SOI region 1A and the bulk region 1B) is exposed, and the substrate 1C (the semiconductor layer 4 and the bulk region 1B in the SOI region 1A) is stopped. It is preferable that the semiconductor substrate 2) is not excessively etched. Thereafter, the insulating film 9 is removed by etching or the like.

  The patterned silicon film 8 forms gate electrodes GE1, GE2, GE3 as shown in FIG. Among these, the gate electrode GE1 is formed on the semiconductor layer 4 via the gate insulating film 7a in the SOI region 1A. The gate electrode GE2 is formed on the semiconductor substrate 2 (p-type well PW1) via the gate insulating film 7b in the high breakdown voltage MIS formation region 1BH of the bulk region 1B. The gate electrode GE3 is formed on the semiconductor substrate 2 (p-type well PW2) via the gate insulating film 7c in the low breakdown voltage MIS formation region 1BL of the bulk region 1B.

  As another form, the gate electrodes GE1, GE2, and GE3 are formed by patterning the silicon film 8 by dry etching using a photoresist pattern formed on the silicon film 8 without forming the insulating film 9. You can also.

  In the present embodiment, one of the main features is that a semiconductor device manufacturing process is performed so that impurities are not ion-implanted into the channel region of the MISFET formed in the SOI region 1A. For this reason, before the gate electrode GE1 to be formed in the SOI region 1A is formed, impurities are not ion-implanted in the semiconductor layer 4 of the SOI region 1A. Therefore, before forming the gate electrodes GE1, GE2, and GE3, impurities are not ion-implanted into the semiconductor layer 4 in the SOI region 1A. On the other hand, in the bulk region 1B, a step of forming well regions (here, p-type wells PW1, PW2) in the semiconductor substrate 2 by ion implantation is performed before the gate electrodes GE1, GE2, GE3 are formed. A step of performing channel doping ion implantation (here, channel doping ion implantation P2, P3) for adjusting the threshold value of the MISFET formed in 1B to the semiconductor substrate 2 in the bulk region 1B is performed, and gate electrodes GE1, GE2, GE3 are formed. Before you do.

  Further, after the gate electrode GE1 is formed, the gate electrode GE1 exists even if ion implantation (ion implantation P4 for forming an extension region EX1 described later and ion implantation for forming the source / drain region SD1) is performed. Therefore, it is possible to prevent impurities from being ion-implanted into the channel region formed under the gate electrode GE1. The ion implantation P1 needs to be performed before the gate electrode GE1 is formed so that the gate electrode GE1 does not interfere with the ion implantation. However, as described above, in the ion implantation P1, impurity ions are introduced into the semiconductor substrate 2 of the SOI substrate 1 in the SOI region 1A, but impurity ions are not introduced into the semiconductor layer 4 of the SOI substrate 1. To do.

  Next, an extension region EX1 is formed in the semiconductor layer 4 in the SOI region 1A by ion implantation, and the extension region EX2 is formed in the semiconductor substrate 2 (p-type well PW1) in the high breakdown voltage MIS formation region 1BH in the bulk region 1B by ion implantation. The extension region EX3 is formed by ion implantation in the semiconductor substrate 2 (p-type well PW2) in the low breakdown voltage MIS formation region 1BL in the bulk region 1B. Here, an example is described in which n-channel MISFETs are formed in the high breakdown voltage MIS formation region 1BH of the SOI region 1A, the bulk region 1B, and the low breakdown voltage MIS formation region 1BL of the bulk region 1B. Each extension region EX1, EX2, EX3 is an n-type semiconductor region.

  The process for forming the extension regions EX1, EX2, and EX3 will be specifically described.

  First, as shown in FIG. 11, a photoresist pattern PR5 is formed on the main surface of the substrate 1C by using a photolithography technique. The photoresist pattern PR5 is formed so as to cover the bulk region 1B and expose the SOI region 1A. Then, an extension region EX1 is formed in the semiconductor layer 4 in the SOI region 1A by performing ion implantation on the semiconductor layer 4 in the SOI region 1A. In the SOI region 1A, the extension region EX1 is formed in a region on both sides of the gate electrode GE1 of the semiconductor layer 4 in alignment with the gate electrode GE1. In FIG. 11, ion implantation for forming the extension region EX1 is schematically indicated by an arrow, and hereinafter referred to as ion implantation P4.

  At the time of ion implantation P4 for forming the extension region EX1, the gate electrode GE1 can function as a mask for preventing impurity ions from being implanted into the semiconductor layer 4, so that the extension region EX1 is formed by the gate electrode GE1. Impurities are not introduced (ion-implanted) directly below the gate electrode GE1. In addition, during the ion implantation P4 for forming the extension region EX1, the photoresist pattern PR5 functions as an ion implantation blocking mask for the bulk region 1B, so that impurities are introduced into the semiconductor substrate 2 in the bulk region 1B ( Ion implantation is not performed.

  After the extension region EX1 is formed, the photoresist pattern PR5 is removed.

  Next, as shown in FIG. 12, a photoresist pattern PR6 is formed on the main surface of the substrate 1C using a photolithography technique. The photoresist pattern PR6 is formed so as to cover the SOI region 1A and the low breakdown voltage MIS formation region 1BL of the bulk region 1B and to expose the high breakdown voltage MIS formation region 1BH of the bulk region 1B. Then, by performing ion implantation on the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B, the extension region EX2 is formed in the semiconductor substrate 2 (p-type well PW1) in the high breakdown voltage MIS formation region 1BH in the bulk region 1B. Form. In the high breakdown voltage MIS formation region 1BH of the bulk region 1B, the extension region EX2 is formed in alignment with the gate electrode GE2 in regions on both sides of the gate electrode GE2 of the semiconductor substrate 2 (p-type well PW1). In FIG. 12, ion implantation for forming the extension region EX2 is schematically indicated by an arrow, and hereinafter referred to as ion implantation P5.

  In the ion implantation P5 for forming the extension region EX2, the gate electrode GE2 can function as a mask for preventing impurity ions from being implanted into the semiconductor substrate 2 (p-type well PW1). EX2 is formed in alignment with the gate electrode GE2 (side wall thereof), and no impurity is introduced (ion implantation) immediately below the gate electrode GE2. Further, during the ion implantation P5 for forming the extension region EX2, the photoresist pattern PR6 functions as an ion implantation blocking mask to the low breakdown voltage MIS formation region 1BL of the SOI region 1A and the bulk region 1B. Impurities are not introduced (ion implantation) into the semiconductor layer 4 and the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL of the bulk region 1B.

  After ion implantation P5 for forming the extension region EX2, as shown in FIG. 13, ions for forming a halo region are formed in the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B. Implantation (halo ion implantation) is performed. This halo ion implantation is schematically indicated by an arrow in FIG. 13, and is hereinafter referred to as a halo ion implantation P5a.

The halo ion implantation is an ion implantation for forming a halo region. The halo region has a conductivity type opposite to that of an extension region for LDD (here, the extension region EX2) and wraps around the extension region. Is a semiconductor region like
It is formed to suppress short channel characteristics (punch through).

  The impurity implanted by the halo ion implantation P5a has a conductivity type opposite to that of the impurity implanted by the ion implantation P5 for forming the extension region EX2. When forming an n-channel type MISFET, an n-type impurity (such as arsenic or phosphorus) is ion-implanted by ion implantation P5, and a p-type impurity (such as boron) is ion-implanted by halo ion implantation P5a. The halo ion implantation P5a is performed for suppressing short channel characteristics. During the halo ion implantation P5a, the gate electrode GE2 can also function as a mask (ion implantation blocking mask).

  By the halo ion implantation P5a, the halo region HO2 is formed in the semiconductor substrate 2 (p-type well PW1) in the high breakdown voltage MIS formation region 1BH of the bulk region 1B so as to wrap (cover) the extension region EX2. The halo region HO2 is a semiconductor region having a conductivity type opposite to that of the extension region EX2 and the same conductivity type as the well region (here, the p-type well PW1). The halo region HO2 has a higher impurity concentration (p-type impurity concentration) than the p-type well PW1. In addition, during the halo ion implantation P5a, the photoresist pattern PR6 functions as an ion implantation blocking mask. Therefore, the semiconductor layer 4 in the SOI region 1A and the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL in the bulk region 1B have impurities. Is not introduced (ion implantation).

  The halo ion implantation P5a is more preferably an oblique ion implantation (gradient ion implantation), whereby the halo region HO2 can be accurately formed so as to wrap (cover) the extension region EX2. In general ion implantation, impurity ions are accelerated and implanted in a direction perpendicular to the main surface of the substrate. In oblique ion implantation, a predetermined angle (inclination angle) from the direction perpendicular to the main surface of the substrate is used. ) Impurity ions are implanted in an inclined direction.

  The ion implantation P5 for forming the extension region EX2 and the halo ion implantation P5a for forming the halo region HO2 do not necessarily have to be formed in this order, but the ion implantation P5 and the halo ion implantation P5a are at least It is necessary to carry out after forming the gate electrode GE2 and before forming a later-described side wall SW on the side wall of the gate electrode GE2.

  After the ion implantation P5 and the halo ion implantation P5a, the photoresist pattern PR6 is removed.

  Next, as shown in FIG. 14, a photoresist pattern PR7 is formed on the main surface of the substrate 1C by using a photolithography technique. The photoresist pattern PR7 is formed so as to cover the SOI region 1A and the high breakdown voltage MIS formation region 1BH of the bulk region 1B and to expose the low breakdown voltage MIS formation region 1BL of the bulk region 1B. Then, by performing ion implantation on the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL in the bulk region 1B, the extension region EX3 is formed in the semiconductor substrate 2 (p-type well PW2) in the low breakdown voltage MIS formation region 1BL in the bulk region 1B. Form. In the low breakdown voltage MIS formation region 1BL of the bulk region 1B, the extension region EX3 is formed in alignment with the gate electrode GE3 in regions on both sides of the gate electrode GE3 of the semiconductor substrate 2 (p-type well PW2). In FIG. 14, ion implantation for forming the extension region EX3 is schematically indicated by an arrow, and hereinafter referred to as ion implantation P6.

  At the time of ion implantation P6 for forming the extension region EX3, the gate electrode GE3 can function as a mask for preventing impurity ions from being implanted into the semiconductor substrate 2 (p-type well PW2). EX3 is formed in alignment with (a side wall of) the gate electrode GE3, and no impurity is introduced (ion-implanted) immediately below the gate electrode GE3. Further, during the ion implantation P6 for forming the extension region EX3, the photoresist pattern PR7 functions as an ion implantation blocking mask for the high breakdown voltage MIS formation region 1BH of the SOI region 1A and the bulk region 1B, and therefore the SOI region 1A. Impurities are not introduced (ion-implanted) into the semiconductor layer 4 and the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH of the bulk region 1B.

  After ion implantation P6 for forming the extension region EX3, as shown in FIG. 15, ions for forming a halo region are formed in the semiconductor substrate 2 in the low breakdown voltage MIS formation region 1BL of the bulk region 1B. Implantation (halo ion implantation) is performed. This halo ion implantation is schematically indicated by an arrow in FIG. 15, and hereinafter referred to as halo ion implantation P6a. The impurity implanted by the halo ion implantation P6a has a conductivity type opposite to that of the impurity implanted by the ion implantation P6 for forming the extension region EX3. When forming an n-channel type MISFET, an n-type impurity (such as arsenic or phosphorus) is ion-implanted by ion implantation P6, and a p-type impurity (such as boron) is ion-implanted by halo ion implantation P6a. The halo ion implantation P6a is performed to suppress short channel characteristics. During the halo ion implantation P6a, the gate electrode GE3 can also function as a mask (ion implantation blocking mask).

  By the halo ion implantation P6a, the halo region HO3 is formed in the semiconductor substrate 2 (p-type well PW2) in the low breakdown voltage MIS formation region 1BL of the bulk region 1B so as to wrap (cover) the extension region EX3. The halo region HO3 is a semiconductor region having a conductivity type opposite to that of the extension region EX3 and the same conductivity type as the well region (here, the p-type well PW1). The halo region HO3 has a higher impurity concentration (p-type impurity concentration) than the p-type well PW2. Further, during the halo ion implantation P6a, the photoresist pattern PR7 functions as an ion implantation blocking mask. Therefore, the semiconductor layer 4 in the SOI region 1A and the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH in the bulk region 1B have impurities. Is not introduced (ion implantation).

  The halo ion implantation P6a is more preferably oblique ion implantation (gradient ion implantation), whereby the halo region HO3 can be accurately formed so as to wrap (cover) the extension region EX3.

  The ion implantation P6 for forming the extension region EX3 and the halo ion implantation P6a for forming the halo region HO3 do not necessarily have to be formed in this order, but the ion implantation P6 and the halo ion implantation P6a are at least It is necessary to carry out after forming the gate electrode GE3 and before forming a later-described side wall SW on the side wall of the gate electrode GE3.

  After the ion implantation P6 and the halo ion implantation P6a, the photoresist pattern PR7 is removed.

  As another form, the extension region EX2 of the high breakdown voltage MIS formation region 1BH and the extension region EX3 of the low breakdown voltage MIS formation region 1BL can be formed by the same ion implantation process, and the high breakdown voltage MIS formation region It is also possible to form the 1BH halo region HO2 and the halo region HO3 of the low breakdown voltage MIS formation region 1BL in the same halo ion implantation process. In this case, instead of the photoresist patterns PR6 and PR7, a photoresist pattern that covers the SOI region 1A and exposes the high breakdown voltage MIS formation region 1BH and the low breakdown voltage MIS formation region 1BL of the bulk region 1B is formed. Then, using this photoresist pattern as an ion implantation blocking mask, extension regions EX2 and EX3 are formed in the same ion implantation process on the semiconductor substrate 2 in the high breakdown voltage MIS formation region 1BH and the low breakdown voltage MIS formation region 1BL in the bulk region 1B. In addition, the halo regions HO2 and HO3 are formed by the same halo ion implantation process.

  The extension region EX1 in the SOI region 1A may be formed before or after the extension regions EX2 and EX3 and the halo regions HO2 and HO3 in the bulk region 1B are formed, but after the gate electrodes GE1, GE2, and GE3 are formed. Extension regions EX1, EX2, EX3 and halo regions HO2, HO3 are formed before the formation of a sidewall insulating film SW described later.

  In the present embodiment, one of the main features is that halo ion implantation (ion implantation for forming a halo region in the extension region EX1) is not performed on the semiconductor layer 4 in the SOI region 1A. Therefore, when performing halo ion implantation (here, halo ion implantations P5a, P6a) on the semiconductor substrate 2 in the bulk region 1B, the SOI region 1A has an ion implantation blocking mask (here, photoresist patterns PR6, PR7). ).

  Next, as shown in FIG. 16, sidewall spacers or sidewalls (sidewall insulating films, sidewall spacers) SW are formed as insulating films (sidewall insulating films) on the sidewalls of the gate electrodes GE1, GE2, and GE3. . For example, the sidewall SW is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 2 (entire main surface thereof), and depositing the silicon oxide film, the silicon nitride film, or the laminated film on the RIE. Reactive Ion Etching (reactive ion etching) can be formed by anisotropic etching.

  Next, the semiconductor layer 4 in the SOI region 1A and the semiconductor substrate 2 in the bulk region 1B are covered with the gate electrodes GE1, GE2, GE3 and the sidewall SW by a cleaning process using, for example, a hydrofluoric acid (HF) aqueous solution. After the unexposed region is exposed and cleaned, as shown in FIG. 17, an epitaxial growth layer 10 is formed as a semiconductor layer by epitaxial growth of silicon. The epitaxial growth layer 10 is a semiconductor layer and is made of epitaxially grown silicon (single crystal silicon). Epitaxial growth layer 10 is formed on an exposed silicon region (semiconductor layer 4 in SOI region 1A, semiconductor substrate 2 in bulk region 1B, and gate electrodes GE1, GE2, and GE3 correspond to this).

  Specifically, the epitaxial growth layer 10 is formed on the semiconductor layer 4 in the region not covered with the gate electrode GE1 and the sidewall SW in the SOI region 1A and on the gate electrode GE1, and in the bulk region 1B, It is formed on the semiconductor substrate 2 in a region not covered with the electrodes GE2 and GE3 and the sidewall SW, and on the gate electrodes GE2 and GE3. Since epitaxially grown layer 10 is not formed on the insulating film, epitaxially grown layer 10 is not formed on element isolation regions 5 and 5b and sidewall SW. By utilizing this, the portion of the epitaxial growth layer 10 formed on the gate electrodes GE 1, GE 2, GE 3 is prevented from contacting the portion of the epitaxial growth layer 10 formed on the semiconductor layer 4 and the semiconductor substrate 2.

  The formation of the epitaxial growth layer 10 is not essential, but it is more preferable if the epitaxial growth layer 10 is formed. In the case where the epitaxial growth layer 10 is not formed, the thickness of a source / drain region SD1 described later formed in the SOI region 1A is limited to the thickness of the semiconductor layer 4, but if the epitaxial growth layer 10 is formed, it is formed in the SOI region 1A. It is possible to increase the thickness of a source / drain region SD1 to be described later by an amount corresponding to the epitaxial growth layer 10, thereby reducing the resistance of the source / drain region SD1.

Next, as shown in FIG. 18, a source / drain region SD1 is formed in the semiconductor layer 4 and the epitaxial growth layer 10 in the SOI region 1A by ion implantation. A source / drain region SD2 is formed by ion implantation in the semiconductor substrate 2 (p-type well PW1) and the epitaxial growth layer 10 in the high breakdown voltage MIS formation region 1BH of the bulk region 1B. A source / drain region SD3 is formed by ion implantation in the semiconductor substrate 2 (p-type well PW2) and the epitaxial growth layer 10 in the low breakdown voltage MIS formation region 1BL of the bulk region 1B. Here, a case where an n-channel MISFET is formed in each of the SOI region 1A, the high breakdown voltage MIS formation region 1BH in the bulk region 1B, and the low breakdown voltage MIS formation region 1BL in the bulk region 1B has been described as an example. The source / drain regions SD1, SD2, and SD3 are n ⁺ type semiconductor regions.

  When the source / drain region SD1 is formed in the SOI region 1A, a photoresist film (not shown) that covers the bulk region 1B may be used as an ion implantation blocking mask. When the source / drain region SD2 is formed in the high breakdown voltage MIS formation region 1BH in the bulk region 1B, a photoresist film (not shown) that covers the SOI region 1A and the low breakdown voltage MIS formation region 1BL in the bulk region 1B. May be used as an ion implantation blocking mask. When the source / drain region SD3 is formed in the low breakdown voltage MIS formation region 1BL in the bulk region 1B, a photoresist film (not shown) that covers the SOI region 1A and the high breakdown voltage MIS formation region 1BH in the bulk region 1B. May be used as an ion implantation blocking mask. Further, the source / drain region SD2 of the high breakdown voltage MIS formation region 1BH and the source / drain region SD3 of the low breakdown voltage MIS formation region 1BL can be formed by the same ion implantation process. In this case, the SOI region 1A A photoresist film covering the film may be used as an ion implantation blocking mask.

  In the SOI region 1A, the source / drain region SD1 is formed across the regions on both sides of the gate electrode GE1 of the semiconductor layer 4 and the epitaxial growth layer 10 thereon. In the high breakdown voltage MIS formation region 1BH of the bulk region 1B, the source / drain region SD2 is formed across the regions on both sides of the gate electrode GE2 of the semiconductor substrate 2 (p-type well PW1) and the epitaxial growth layer 10 thereon. . In the low breakdown voltage MIS formation region 1BL of the bulk region 1B, the source / drain region SD3 is formed across the regions on both sides of the gate electrode GE3 of the semiconductor substrate 2 (p-type well PW2) and the epitaxial growth layer 10 thereon. .

  In the ion implantation for forming the source / drain region SD1, the gate electrode GE1 and the sidewall SW on the sidewall thereof can function as a mask for preventing the impurity ions from being implanted into the semiconductor layer 4. The drain region SD1 is formed in alignment with the sidewall SW on the sidewall of the gate electrode GE1, and no impurity ions are implanted immediately below the gate electrode GE1 and the sidewall SW on the sidewall. Further, at the time of ion implantation for forming the source / drain region SD2, the gate electrode GE2 and the sidewall SW on the sidewall thereof can function as a mask for preventing impurity ions from being implanted into the semiconductor substrate 2. The source / drain region SD2 is formed in alignment with the sidewall SW on the sidewall of the gate electrode GE2, and no impurity ions are implanted immediately below the gate electrode GE2 and the sidewall SW on the sidewall. Further, at the time of ion implantation for forming the source / drain region SD3, the gate electrode GE3 and the sidewall SW on the sidewall thereof can function as a mask for preventing impurity ions from being implanted into the semiconductor substrate 2. The source / drain region SD3 is formed in alignment with the sidewall SW on the sidewall of the gate electrode GE3, and no impurity ions are implanted immediately below the gate electrode GE3 and the sidewall SW on the sidewall.

  The source / drain region SD1 and the extension region EX1 formed in the SOI region 1A have the same conductivity type, but the source / drain region SD1 has a higher impurity concentration (n-type impurity concentration) than the extension region EX1. Thereby, in the SOI region 1A, a semiconductor region (impurity diffusion layer) having an LDD (Lightly doped Drain) structure that functions as a source or drain of the MISFET is formed by the source / drain region SD1 and the extension region EX1. In other words, the extension region EX1 and the source / drain region SD1 having a higher impurity concentration function as a semiconductor region for the source or drain of the MISFET. Therefore, the extension region EX1 can be regarded as a part of the semiconductor region for source or drain.

  In addition, the source / drain region SD2 and the extension region EX2 formed in the high breakdown voltage MIS formation region 1BH of the bulk region 1B have the same conductivity type, but the source / drain region SD2 has an impurity concentration higher than that of the extension region EX2 ( n-type impurity concentration) is high. Thus, in the high breakdown voltage MIS formation region 1BH of the bulk region 1B, a semiconductor region (impurity diffusion layer) having an LDD structure that functions as a source or drain of the MISFET is formed by the source / drain region SD2 and the extension region EX2. In other words, the extension region EX2 and the source / drain region SD2 having a higher impurity concentration than that function as a semiconductor region for the source or drain of the MISFET. Therefore, the extension region EX2 can be regarded as a part of the semiconductor region for source or drain.

  The source / drain region SD3 and the extension region EX3 formed in the low breakdown voltage MIS formation region 1BL of the bulk region 1B have the same conductivity type, but the source / drain region SD3 has an impurity concentration (more than the extension region EX3). n-type impurity concentration) is high. Thereby, in the low breakdown voltage MIS formation region 1BL of the bulk region 1B, a semiconductor region (impurity diffusion layer) having an LDD structure that functions as the source or drain of the MISFET is formed by the source / drain region SD3 and the extension region EX3. In other words, the extension region EX3 and the source / drain region SD3 having a higher impurity concentration function as a semiconductor region for the source or drain of the MISFET. Therefore, the extension region EX3 can be regarded as a part of the semiconductor region for source or drain.

  Next, annealing treatment (heat treatment) for activating the impurities introduced by the conventional ion implantation is performed. This annealing process can be performed, for example, by a spike annealing process at about 1050 ° C. In this manner, MISFETs are formed as field effect transistors in the SOI region 1A and the high breakdown voltage MIS formation region 1BH and the low breakdown voltage MIS formation region 1BL of the bulk region 1B, respectively.

  Next, as shown in FIG. 19, by using salicide technology, the upper layer (surface layer) portion of the source / drain regions SD1, SD2, SD3 and the upper layer of the epitaxial growth layer 10 above the gate electrodes GE1, GE2, GE3 ( A metal silicide layer 12 is formed on the surface layer portion. The metal silicide layer 12 is made of, for example, nickel silicide or cobalt silicide. In order to form the metal silicide layer 12, for example, a metal film such as a nickel (Ni) film or a cobalt (Co) film is deposited on the substrate 1C and subjected to heat treatment, and then the metal silicide layer 12 is formed. Unreacted metal film is removed. By forming the metal silicide layer 12, diffusion resistance, contact resistance, and the like can be reduced.

  Next, as shown in FIG. 20, an insulating film (interlayer insulating film) 21 is formed on the main surface of the substrate 1C. That is, the insulating film 21 is formed on the substrate 1C including the metal silicide layer 12 so as to cover the gate electrodes GE1, GE2, GE3 and the sidewall SW. The insulating film 21 is made of, for example, a single film of a silicon oxide film or a laminated film of a silicon nitride film and a thicker silicon oxide film. Thereafter, the upper surface of the insulating film 21 is planarized by polishing the surface (upper surface) of the insulating film 21 by CMP (CMP: Chemical Mechanical Polishing). Even if unevenness is formed on the surface of the insulating film 21 due to the base step, by polishing the surface of the insulating film 21 by the CMP method, an interlayer insulating film having a flattened surface can be obtained. .

  Next, as shown in FIG. 21, the insulating film 21 is dry-etched using a photoresist pattern (not shown) formed on the insulating film 21 as an etching mask, so that a contact hole ( (Through hole, hole) 22 is formed. At the bottom of the contact hole 22, part of the main surface of the substrate 1C, for example, part of the metal silicide layer 12 on the surface of the source / drain regions SD1, SD2, SD3, and metal silicide on the gate electrodes GE1, GE2, GE3. A part of the layer 12 is exposed.

  Next, a conductive plug (connecting conductor portion) 23 made of tungsten (W) or the like is formed in the contact hole 22. In order to form the plug 23, for example, a barrier conductor film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is formed on the insulating film 21 including the inside (on the bottom and side walls) of the contact hole 22 by plasma CVD. ). Then, a main conductor film made of a tungsten film or the like is formed by CVD or the like so as to fill the contact hole 22 on the barrier conductor film, and unnecessary main conductor films and barrier conductor films on the insulating film 21 are formed by CMP or etch back. By removing by a method or the like, the plug 23 can be formed. For simplification of the drawing, the plug 23 is shown by integrating the main conductor film and the barrier conductor film. The plug 23 is in contact with the metal silicide layer 12 on the surface of the source / drain regions SD1, SD2, SD3, the metal silicide layer 12 on the gate electrodes GE1, GE2, GE3, and the like at the bottom thereof, and is electrically connected. .

  Next, as shown in FIG. 22, an insulating film 24 is formed on the insulating film 21 in which the plugs 23 are embedded. The insulating film 24 can also be formed of a stacked film of a plurality of insulating films.

  Next, the wiring M1 which is the first layer wiring is formed by a single damascene method. Specifically, the wiring M1 can be formed as follows. First, after a wiring groove is formed in a predetermined region of the insulating film 24 by dry etching using a photoresist pattern (not shown) as a mask, a barrier conductor film (on the insulating film 24 including the bottom and side walls of the wiring groove is formed. For example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like is formed. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by using an electrolytic plating method. Embed the inside. Then, the main conductor film (copper plating film and seed layer) and the barrier metal film in a region other than the wiring groove are removed by CMP, and the first layer wiring M1 embedded in the wiring groove and using copper as the main conductive material. Form. For simplification of the drawing, the wiring M1 is shown by integrating a barrier conductor film, a seed layer, and a copper plating film.

  The wiring M1 is connected to the MISFET (source / drain region SD1 or gate electrode GE1) formed in the SOI region 1A and the MISFET (source / drain region) formed in the high breakdown voltage MIS formation region 1BH in the bulk region 1B via the plug 23. SD2 or gate electrode GE2), or a MISFET (source / drain region SD3 or gate electrode GE3) formed in the low breakdown voltage MIS formation region 1BL of the bulk region 1B. Thereafter, a second layer wiring is formed by a dual damascene method, but illustration and description thereof are omitted here.

  As described above, the semiconductor device of the present embodiment is manufactured.

  The semiconductor device of the present embodiment has an SOI region 1A and a bulk region 1B, and a plurality of MISFETs are formed in each of the SOI region 1A and the bulk region 1B. The SOI region 1A is a region having an SOI structure in which a semiconductor substrate 2 (single crystal semiconductor region), an insulating layer 3, and a semiconductor layer 4 (single crystal semiconductor region) are stacked in order from the bottom. A MISFET is formed in the semiconductor layer 4 (single crystal semiconductor region) located. For this reason, the channel region of each MISFET formed in the SOI region 1 </ b> A is formed in the semiconductor layer 4 on the insulating layer 3. On the other hand, the bulk region 1B is a region in which the entire thickness direction of the substrate (excluding the element isolation regions 5 and 5b) is constituted by the semiconductor substrate 2 (single crystal semiconductor region), and this semiconductor substrate 2 (single crystal semiconductor region). In addition, a MISFET is formed. Therefore, the channel region of each MISFET formed in the bulk region 1B is formed in the semiconductor substrate 2, and an insulating layer such as the insulating layer 3 is located below the channel region (in the middle of the thickness direction of the semiconductor substrate 2). There is no (buried insulating layer).

  One of the main features of the semiconductor device of the present embodiment and its manufacturing process is that no impurity is introduced into the channel region of the MISFET formed in the SOI region 1A in the manufactured semiconductor device, and the bulk The impurity is introduced into the channel region of the MISFET formed in the region 1B. Therefore, one of the main features is that the manufacturing process of the semiconductor device of the present embodiment is performed so that impurities are not ion-implanted into the channel region of the MISFET formed in the SOI region 1A. Another main feature is that the manufacturing process of the semiconductor device of the present embodiment is performed such that impurities are ion-implanted into the channel region of the MISFET formed in the bulk region 1B. This is due to the following reasons.

  When impurities are ion-implanted into a semiconductor substrate, even if the implanted impurities are randomly arranged to some extent, if the impurities diffuse (move) in various subsequent heating processes, the random arrangement of the impurities It collapses and the distribution of impurities is biased compared to immediately after implantation. That is, in the stage immediately after ion implantation, even if the randomness of the implanted impurity is high, if the impurity is diffused (moved) in the subsequent various heating processes, the randomness of the impurity is degraded. This is the same even when the ion implantation is channel doping ion implantation for adjusting the threshold value of the MISFET or ion implantation for forming the well region.

  In addition, in a state where the randomness of the arrangement of impurities is high, the impurities are not arranged uniformly (regularly) microscopically (at the level of atomic arrangement) but are present in a random (random) manner. However, since they are microscopically random, the impurities are distributed equally in a macroscopic manner (channel region level). For this reason, in a state where the randomness of the impurity arrangement is high, the difference in impurity distribution (difference between the impurity distribution in the channel region of one MISFET and the impurity distribution in the channel region of another MISFET) when the channel regions are compared with each other. Small, variation in threshold of MISFET is small.

  However, if the randomness of the impurity arrangement decreases, this state collapses, and the macroscopic impurity distribution (impurity distribution at the channel region level) is biased. For this reason, after the channel doping ion implantation, in the state where the randomness of the channel doping impurities is reduced by thermal diffusion, the difference in the impurity distribution when comparing the channel regions (impurity distribution in the channel region of a certain MISFET and others) (Difference from the impurity distribution in the channel region of the MISFET) increases, and the variation in threshold value of the MISFET increases. That is, the state of the channel region (arrangement state of impurities in the channel region) varies for each MISFET, and the threshold voltage varies for each MISFET. In order to improve the performance of the semiconductor device, it is desired to suppress variations in threshold voltage for each MISFET. Note that the difference (variation) in the impurity distribution when the channel regions are compared corresponds to the random variation.

  For this reason, if channel doping ion implantation is not performed and impurities are not introduced into the channel region, the state of the channel region (arrangement of impurities in the channel region) does not vary for each MISFET. It becomes possible to suppress variations in value voltage.

  However, when forming a plurality of MISFETs on a semiconductor substrate, it is difficult to adjust the threshold voltage of the MISFET unless channel doping ion implantation is performed for all MISFETs. It becomes difficult to improve. Even when channel doping ion implantation is not performed, impurities are also introduced into the channel region during ion implantation for forming the well region. For this reason, if impurities are diffused (moved) in various subsequent heating processes, the randomness of the arrangement of impurities introduced into the channel region for the formation of the well region is reduced, and the state of the channel region (channel The impurity arrangement state in the region) varies, and the threshold voltage varies for each MISFET. In addition, if all the MISFETs formed on the semiconductor substrate are uniformly treated, the same countermeasures are applied to elements that are likely to cause random variations and elements that are unlikely to occur. A change is necessary, and the time, labor, and cost associated with the design change increase.

  Therefore, in the present embodiment, a plurality of MISFETs are formed on the substrate 1C having the SOI region 1A having the SOI structure and the bulk region 1B not having the SOI structure. Then, the semiconductor device manufacturing process (MISFET forming process) is performed so that impurities are not ion-implanted into the channel region of the MISFET formed in the SOI region 1A. As a result, in the manufactured semiconductor device, no impurity is introduced into the channel region of the MISFET formed in the SOI region 1A.

  In the MISFET formed in the SOI region 1A, since no impurity is introduced into the channel region, the state of the channel region (arrangement state of impurities in the channel region) does not vary for each MISFET, and the threshold voltage for each MISFET Can be prevented from fluctuating.

  In the SOI region 1A, since impurities are not introduced into the channel region of the MISFET, channel doping ion implantation is not performed in the SOI region 1A, and ion implantation for forming a well region is not performed. In the bulk region 1B, a well region is formed in the semiconductor substrate 2 and a MISFET is formed there. The SOI region 1A has an SOI structure, and a MISFET is formed in the semiconductor layer 4 on the insulating layer 3. It is not necessary to form a well region in the layer 4. That is, even if the well region is not formed, the semiconductor layer 4 in the SOI region 1A is provided with a region partitioned (enclosed) by the element isolation region 5 and the insulating layer 3, and a MISFET can be formed there. Therefore, in the SOI region 1A, it is not necessary to perform ion implantation for forming a well region in the semiconductor layer 4.

  In addition, channel doping ion implantation is not performed in the SOI region 1A. However, since the SOI region 1A has an SOI structure, the threshold voltage of the MISFET can be adjusted without performing channel doping ion implantation. It is. For example, in the present embodiment, the threshold voltage of the MISFET in the SOI region 1A is adjusted as follows.

  In the SOI region 1A, the semiconductor layer 4 is capacitively coupled to the semiconductor substrate 2 via the insulating layer 3, but when this capacitive coupling state changes, the MISFET formed in the semiconductor layer 4 is affected, The threshold voltage changes. By utilizing this fact, in the present embodiment, impurity ions are introduced into the semiconductor substrate 2 in the SOI region 1A by the ion implantation P1 in FIG. 3 above, whereby the substrate region (under the insulating layer 3 in the SOI region 1A ( By adjusting the impurity concentration of the semiconductor region 6) and thereby controlling the state of the capacitive coupling (capacitive coupling between the semiconductor layer 4 and the semiconductor substrate 2 via the insulating layer 3), the MISFET of the SOI region 1 A is controlled. The threshold voltage is adjusted. For example, a p-type impurity such as boron (B) is introduced into the semiconductor region 6 by the ion implantation P1 in FIG. 3, and the semiconductor layer 4 above the semiconductor region 6 increases as the p-type impurity concentration in the semiconductor region 6 increases. The absolute value of the threshold voltage of the n-channel type MISFET formed in (1) can be increased. Thus, in the SOI region 1A, the threshold voltage of the MISFET can be adjusted without performing channel dope ion implantation.

  Therefore, in the SOI region 1A, it is possible to prevent impurities from being introduced into the channel region of the MISFET, thereby preventing the threshold voltage from fluctuating for each MISFET.

  However, unlike the present embodiment, in a semiconductor device having a structure in which all MISFETs are formed on an SOI substrate having an SOI structure as a whole, the threshold for each MISFET is prevented by preventing impurities from being introduced into the channel region of the MISFET. Although the fluctuation of the value voltage can be prevented, a MISFET that can tolerate the fluctuation of the threshold voltage to some extent is formed on the SOI substrate. Even if the randomness of the impurity arrangement is reduced, the threshold voltage may not change so much as in a MISFET having a large gate area, but such a MISFET is also formed on the SOI substrate. In this case, even in a MISFET that can tolerate a change in threshold voltage to some extent (or a MISFET in which the threshold voltage does not change so much even if the randomness of the impurity arrangement is lowered), the characteristics of the MISFET formed on the SOI substrate. Will be added. For example, by limiting the thickness of the source / drain region, the resistance of the source / drain region is increased, and the on-current is likely to be decreased. Further, if the semiconductor substrate constituting the semiconductor device is replaced with an SOI substrate, all MISFETs to be formed are formed on this SOI substrate, and impurities are not introduced into the channel regions of all MISFETs, the entire semiconductor device is greatly reduced. Design change is required, and the time, labor, and cost associated with the design change increase.

  On the other hand, in this embodiment, a substrate 1C having an SOI region 1A and a bulk region 1B is used, and a plurality of MISFETs are formed in the SOI region 1A and the bulk region 1B of the substrate 1C, respectively. At this time, a MISFET in which it is important to suppress the fluctuation (variation) of the threshold voltage is formed in the SOI region 1A, and the fluctuation (variation) of the threshold voltage can be allowed as compared with the MISFET formed in the SOI region 1A. The design concept is to form the MISFET in the bulk region 1B. Further, when the randomness of the impurity arrangement is lowered, a MISFET whose threshold voltage is likely to fluctuate (variable) is formed in the SOI region 1A, and the randomness of the impurity arrangement is lowered as compared with the MISFET formed in the SOI region 1A. However, the design philosophy is to form a MISFET in the bulk region 1B in which the threshold voltage does not easily change (is likely to vary).

  In the semiconductor device of the present embodiment, impurities are introduced into the channel region of the MISFET formed in the bulk region 1B. That is, the manufacturing process of the semiconductor device of this embodiment is performed so that impurities are ion-implanted into the channel region of the MISFET formed in the bulk region 1B.

  The reason why the impurities are introduced into the channel region of the MISFET in the bulk region 1B is that channel doping ion implantation is performed and ion implantation for forming a well region is performed. If the MISFET is formed in the semiconductor substrate 2 in the bulk region 1B without performing either the ion implantation for forming the well region or the channel dope ion implantation, the characteristics of the formed MISFET may be deteriorated. However, in the present embodiment, impurities are introduced into the channel region of the MISFET formed in the bulk region 1B, and channel doping ion implantation or ion implantation for forming a well region is performed in the bulk region 1B. Therefore, the MISFET can be accurately formed on the semiconductor substrate 2 in the bulk region 1B. In addition, the characteristics of the formed MISFET can be improved. Further, the threshold voltage of the MISFET can be easily controlled to a desired value.

  In addition, since the MISFET formed in the bulk region 1B is not limited by the characteristics due to being formed in the SOI region 1A, the characteristics (characteristics other than the characteristics affected by random variations in channel impurities) Can be improved. For example, it is easy to increase the thickness of the source / drain region, and it is possible to reduce the resistance of the source / drain region and improve the on-current.

  However, in the MISFET formed in the bulk region 1B, since impurities are introduced into the channel region, the state of the channel region (arrangement state of impurities in the channel region) may vary for each MISFET. However, among the MISFETs to be formed in the semiconductor device, in the bulk region 1B, a MISFET that can tolerate a threshold voltage variation to some extent is formed, and the MISFET that is important to suppress the threshold voltage variation is an SOI region. Form 1A. Alternatively, in the bulk region 1B, among the MISFETs to be formed in the semiconductor device, a MISFET whose threshold voltage does not change much even if the randomness of the impurity arrangement is lowered is formed, and the randomness of the impurity arrangement is lowered. A MISFET whose value voltage is likely to fluctuate (is likely to vary) is formed in the SOI region 1A. Thereby, in the MISFET formed in the bulk region 1B, even if the channel region state (arrangement state of impurities in the channel region) varies for each MISFET, it is possible to suppress or prevent problems caused by the channel region state.

  In this embodiment, the semiconductor substrate constituting the semiconductor device is replaced with the substrate 1C having the SOI region 1A and the bulk region 1B, and a part of all the MISFETs to be formed (threshold voltage fluctuation). Is formed in the SOI region 1A, and the rest is formed in the bulk region 1B. For this reason, the design change of the semiconductor device can be reduced, and the time, labor and cost associated with the design change can be suppressed.

  As described above, in this embodiment, the substrate 1C having the SOI region 1A and the bulk region 1B is used, and a plurality of MISFETs are formed in each of the SOI region 1A and the bulk region 1B, but the MISFET formed in the SOI region 1A. It is important that an impurity is introduced into the channel region of the MISFET and an impurity is introduced into the channel region of the MISFET formed in the bulk region 1B.

  Further, in the present embodiment, in the SOI region 1A, ion implantation for forming the extension region EX1 and ion implantation for forming the source / drain region SD1 are performed, but ion implantation for forming the halo region ( (Halo ion implantation) is not performed. On the other hand, in the bulk region 1B, ion implantation (halo ion implantation P5a, P6a) for forming a halo region is performed.

  By the halo ion implantation, the halo region is formed near the channel region (the region immediately below the gate electrode). For this reason, in the SOI region 1A, when ion implantation for forming a halo region (halo ion implantation) is performed, even if channel doping ion implantation and ion implantation for forming a well region are not performed, Due to impurities introduced by halo ion implantation, the state of the channel region (arrangement state of impurities in the channel region) may vary for each MISFET. This may cause a variation in threshold voltage for each MISFET.

  On the other hand, in this embodiment, since the halo ion implantation is not performed in the SOI region 1A, the channel region state (arrangement state of impurities in the channel region) is more accurately prevented for each MISFET. it can. Thereby, fluctuations in the threshold voltage of the MISFET formed in the SOI region 1A can be prevented more accurately.

  In the SOI region 1A, since the extension region EX1 is formed in the semiconductor layer 4 on the insulating layer 3, the MISFET formed in the SOI region 1A is punch-through (shorter) than the MISFET formed in the bulk region 1B. Channel effect) is less likely to occur. For this reason, in the SOI region 1A, without performing ion implantation for forming the halo region (halo ion implantation), the extension region EX1 is formed in the semiconductor layer 4 on the insulating layer 3, so that punch-through ( (Short channel effect) can be suppressed or prevented. On the other hand, in the bulk region 1B, since the extension regions EX2 and EX3 are formed in the semiconductor substrate 2, the MISFET formed in the bulk region 1B is punch-through (short channel effect) compared to the MISFET formed in the SOI region 1A. Is likely to occur. Therefore, when forming the MISFET in the bulk region 1B, the punch-through (short channel effect) can be suppressed or prevented by forming the halo regions HO2 and HO3.

  As described above, in this embodiment, the substrate 1C having the SOI region 1A and the bulk region 1B is used, and the MISFET to be formed in the semiconductor device is divided into the SOI region 1A and the bulk region 1B. In the SOI region 1A, In order to prevent the channel region state (impurity arrangement state) from changing for each MISFET, only the minimum necessary ion implantation (extension region forming ion implantation and source / drain region forming ion implantation) is performed. . On the other hand, in the bulk region 1B, although there is a possibility that the state of the channel region (arrangement state of impurities) may fluctuate, priority is given to the improvement of other characteristics, and ion implantation and source / drain regions for extension region formation are given priority. In addition to ion implantation for forming, ion implantation necessary for improving characteristics (channel dope ion implantation, ion implantation for forming a well region and halo ion implantation) is also performed. Then, a MISFET in which it is important to suppress fluctuations in threshold voltage is arranged in the SOI region 1A, and a MISFET capable of allowing fluctuations in threshold voltage is arranged in the bulk region 1B as compared with the MISFET formed in the SOI region 1A. As a result, the performance of the entire semiconductor device can be improved.

  Although no impurity is introduced into the channel region of the MISFET formed in the SOI region 1A, this means that impurities are not intentionally introduced (added or doped). For this reason, the case where the trace amount impurity which is not intended is contained is not excluded. On the other hand, impurities are introduced into the channel region of the MISFET formed in the bulk region 1B, which means that impurities are intentionally introduced (added or doped). For this reason, the impurity concentration of the channel region of the MISFET formed in the bulk region 1B is sufficiently higher than the impurity concentration of the channel region of the MISFET formed in the SOI region 1A.

(Embodiment 2)
This embodiment corresponds to a modification of the first embodiment. 23 to 28 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  In the second embodiment, a silicon film 8 such as a polycrystalline silicon film (doped polysilicon film) and an insulating film 9 such as a silicon nitride film are formed, and the same as in FIG. 9 in the first embodiment. Until the structure shown in FIG. 23 is obtained, the same steps as those in the first embodiment are performed. However, in the first embodiment, impurity ions are introduced into the semiconductor substrate 2 of the SOI substrate 1 by the ion implantation P1 in order to control the threshold value of the MISFET formed in the SOI region 1A. In the embodiment, this ion implantation P1 may not be performed. For this reason, the manufacturing process of the present embodiment is that the process of forming the photoresist pattern PR1 and the ion implantation P1 are not performed until the process of forming the silicon film 8 and the insulating film 9 thereon. It is different from the manufacturing process of the first embodiment, and the rest is the same.

  After the silicon film 8 and the insulating film 9 thereon are formed, in this embodiment, as shown in FIG. 24, a photoresist pattern PR11 is formed on the main surface of the substrate 1C using a photolithography technique. The photoresist pattern PR11 is formed so as to cover the bulk region 1B and expose the SOI region 1A.

  Next, using the photoresist pattern PR11 as an etching mask, the entire insulating film 9 and a part (upper part) of the silicon film 8 are removed in the SOI region 1A. At this time, in the SOI region 1A, the insulating film 9 is completely removed, but the silicon film 8 is partially removed in the thickness direction (upper part) so that the silicon film 8 remains in a layer shape after the etching. In the region 1B, since the photoresist pattern PR11 functions as an etching mask, the insulating film 9 and the silicon film 8 remain without being removed. The silicon film 8 remaining in the SOI region 1A is hereinafter referred to as a silicon film 8a. FIG. 24 shows this stage.

  Comparing before and after etching, the thickness of the silicon film 8 is reduced in the SOI region 1A, and the thickness of the silicon film 8 is not changed in the bulk region 1B. Therefore, before the etching, the thickness of the silicon film 8 in the SOI region 1A and the thickness of the silicon film 8 in the bulk region 1B are substantially the same, but after the etching, the thickness of the silicon film 8a in the SOI region 1A is equal to the bulk region. It becomes thinner than the thickness of the silicon film 8 of 1B. After the etching, the thickness of the silicon film 8a in the SOI region 1A can be about 10 to 20 nm, for example, and the thickness of the silicon film 8 in the bulk region 1B can be about 100 to 120 nm, for example. Thereafter, the photoresist pattern PR11 is removed.

  Next, as shown in FIG. 25, a metal film 31 for a metal gate electrode is formed on the substrate 1C. The metal film 31 is formed on the silicon film 8a in the SOI region 1A, and is formed on the insulating film 9 in the bulk region 1B.

  The metal film 31 used here is a conductive film showing metal conduction, and not only a single metal film (pure metal film) or alloy film, but also a metal compound film (metal nitride film, metal carbide film, etc.) showing metal conduction. ) Can also be used, and these are collectively referred to as the metal film 31. For this reason, the metal film 31 has a low resistivity to the metal grade. As the metal film 31, for example, a titanium (Ti) film, a titanium nitride (TiN) film, a tungsten (W) film, or a tungsten nitride (WN) film can be used.

  Next, as shown in FIG. 26, a photoresist pattern PR12 is formed on the main surface of the substrate 1C (that is, on the metal film 31) using a photolithography technique. This photoresist pattern PR12 is formed so as to cover SOI region 1A and expose bulk region 1B.

  Next, the metal film 31 in the bulk region 1B is removed using the photoresist pattern PR12 as an etching mask. As a result, the insulating film 9 is exposed in the bulk region 1B, but since the photoresist pattern PR12 functions as an etching mask in the SOI region 1A, the metal film 31 remains without being removed.

  Next, a photoresist pattern (not shown) having the same pattern shape as the gate electrode to be formed is photolithography on the substrate 1C (that is, on the metal film 31 in the SOI region 1A and the insulating film 9 in the bulk region 1B). Form using technology. Then, by using this photoresist pattern as an etching mask, the gate electrode GE1 is formed by dry etching and patterning the metal film 31 and the silicon film 8a in the SOI region 1A, and the insulating film 9 in the bulk region 1B. Then, the gate electrodes GE2 and GE3 are formed by patterning the silicon film 8 by dry etching. Thereafter, the photoresist pattern is removed. FIG. 27 shows this stage.

  In the present embodiment, as shown in FIG. 27, the gate electrode GE1 formed in the SOI region 1A has a laminated structure (laminated film) of a patterned silicon film 8a (lower layer side) and a metal film 31 (upper layer side). The gate electrodes GE2 and GE3 formed in the bulk region 1B are formed by the patterned silicon film 8.

  Similar to the first embodiment, also in the present embodiment, the gate electrode GE1 is formed on the semiconductor layer 4 via the gate insulating film 7a in the SOI region 1A. Similarly, the gate electrode GE2 is formed on the semiconductor substrate 2 (p-type well PW1) via the gate insulating film 7b in the high breakdown voltage MIS formation region 1BH of the bulk region 1B. Similarly, the gate electrode GE3 is formed on the semiconductor substrate 2 (p-type well PW2) via the gate insulating film 7c in the low breakdown voltage MIS formation region 1BL of the bulk region 1B.

  When the silicon films 8 and 8a are dry-etched to form the gate electrodes GE1, GE2 and GE3, the etching is stopped when the gate insulating film in each region (SOI region 1A and bulk region 1B) is exposed. It is preferable that the substrate 1C (the semiconductor layer 4 in the SOI region 1A and the semiconductor substrate 2 in the bulk region 1B) is not excessively etched. The film thickness of the metal film 31 is optimized so as to satisfy this condition. It is preferable to keep it. Thereafter, the insulating film 9 is removed by etching or the like.

  As another form, when forming the gate electrodes GE1, GE2, GE3, the metal film 31 and the insulating film 9 are first patterned (dry etching) using the photoresist pattern PR13 as an etching mask, and then patterned. The silicon films 8 and 8a can be patterned (dry etching) using the insulating film 9 and the metal film 31 as a mask.

  The process after forming the gate electrodes GE1, GE2, and GE3 is the same as that in the first embodiment. That is, the extension regions EX1, EX2, and EX3 are formed, the halo regions HO2 and HO3 are formed, the sidewall SW is formed, the epitaxial growth layer 10 is formed, and the source / drain regions SD1, SD2, and SD3 are formed. And the metal silicide layer 12 is formed. Then, the insulating film 21 is formed, the contact hole 22 is formed, the plug 23 is formed, the insulating film 24 is formed, and the wiring M1 is formed. FIG. 28 is a cross-sectional view of a main part at the stage where the wiring M1 formation process is performed in the present embodiment, and corresponds to FIG. 22 of the first embodiment. However, in the present embodiment, since the gate electrode GE1 has a laminated structure of the silicon film 8a and the metal film 31 on the silicon film 8a, the epitaxial growth layer 10 and the metal are formed on the gate electrode GE1. The silicide layer 12 is not formed.

  This embodiment is different from the first embodiment in that the gate electrode GE1 formed in the SOI region 1A has a laminated structure of the silicon film 8a and the metal film 31 on the silicon film 8a. Yes.

  In the first embodiment, the threshold voltage of the MISFET in the SOI region 1A is adjusted by adjusting the impurity concentration in the substrate region (the semiconductor region 6) below the insulating layer 3 in the SOI region 1A. On the other hand, in the present embodiment, the gate electrode GE1 has a laminated structure of the silicon film 8a and the metal film 31 on the silicon film 8a, and the material of the metal film 31 is selected from various metal materials. Since the work function can be adjusted, the threshold voltage of the MISFET having the gate electrode GE1 can be controlled.

  As described above, in the present embodiment as well, in the present embodiment, the threshold voltage of the MISFET can be adjusted without performing channel doping ion implantation in the SOI region 1A. In addition, since the threshold voltage of the MISFET in the SOI region 1A can be adjusted by the material type of the metal film 31, the semiconductor region 6 does not have to be formed by the ion implantation P1 in the present embodiment.

(Embodiment 3)
29 to 32 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  In the present embodiment, as shown in FIG. 29, first, a semiconductor substrate 2 made of single crystal silicon or the like is prepared. Then, a surface protection insulating film 41 such as a silicon oxide film is formed on the main surface (front surface) of the semiconductor substrate 2, and then a hard mask insulating film 42 such as a silicon nitride film is formed on the insulating film 41. To do.

  Next, as shown in FIG. 30, a photoresist pattern PR21 that covers the bulk region 1B and exposes the SOI region 1A is formed on the insulating film 42 by using a photolithography technique. The insulating film 42 in the SOI region 1A is removed by etching using the pattern PR21 as an etching mask.

  Next, oxygen ions are ion-implanted into the semiconductor substrate 2 in the SOI region 1A using the photoresist pattern PR21 as an ion implantation blocking mask. This ion implantation of oxygen ions is schematically indicated by an arrow in FIG. 30, and is hereinafter referred to as ion implantation P11. In FIG. 30, oxygen ions introduced by the ion implantation P11 are schematically indicated by “x” marks and denoted by reference numeral 43. During the ion implantation P11, the photoresist pattern PR21 functions as an ion implantation blocking mask for the bulk region 1B. Therefore, oxygen ions are not introduced (ion implantation) into the semiconductor substrate 2 in the bulk region 1B. After the ion implantation P11, the photoresist pattern PR21 is removed.

In the ion implantation P11, the ion implantation energy is adjusted so that oxygen ions are locally implanted (introduced) at a predetermined depth from the surface of the semiconductor substrate 2 (interface between the semiconductor substrate 2 and the insulating film 41). . For example, oxygen ions are implanted with an implantation energy of 100 keV and an implantation amount of 1 × 10 ¹⁶ cm ⁻² . Thereby, oxygen ions can be prevented from being implanted from the surface of the semiconductor substrate 2 to a predetermined depth position (for example, about 50 nm).

  Next, the semiconductor substrate 2 is subjected to heat treatment to cause the oxygen ions 43 introduced by the ion implantation P11 to react with the semiconductor substrate 2, and as shown in FIG. 31, the insulating layer 3a made of silicon oxide. Form. For example, the heat treatment can be performed at about 1100 ° C. for about 6 hours. In the ion implantation P11, oxygen ions 43 are implanted into the semiconductor substrate 2 in the SOI region 1A, but are not implanted into the semiconductor substrate 2 in the bulk region 1B. Therefore, the insulating layer 3a is formed in the semiconductor substrate 2 in the SOI region 1A. Although formed, it is not formed on the semiconductor substrate 2 in the bulk region 1B.

  In the SOI region 1A, the insulating layer 3a is formed not at the surface of the semiconductor substrate 2 but at a predetermined depth from the surface of the semiconductor substrate 2. That is, in the SOI region 1A, the insulating layer 3a is formed inside (in the middle) of the semiconductor substrate 2 in the thickness direction. For this reason, the semiconductor substrate 2 having a predetermined thickness remains above the insulating layer 3 a, and the semiconductor substrate 2 also remains below the insulating layer 3 a, and the main surface (front surface) of the insulating layer 3 a is the surface of the semiconductor substrate 2. It is substantially parallel to the main surface (surface).

  In the SOI region 1A, the semiconductor substrate 2 above the insulating layer 3a is hereinafter referred to as a semiconductor layer 4a. The semiconductor layer 4a has the same configuration as that of the semiconductor substrate 2, and when the semiconductor substrate 2 is made of single crystal silicon, the semiconductor layer 4a is also made of single crystal silicon. The thickness of the semiconductor layer 4a can be preferably about 10 to 30 nm. Moreover, the thickness of the insulating layer 3a can be about 20-60 nm, for example, and the thickness of the semiconductor substrate 2 under the insulating layer 3a can be about 300-750 micrometers, for example.

  Hereinafter, the entire semiconductor substrate 2 in which the insulating layer 3a is formed is referred to as a substrate 1C1. In the SOI region 1A, the substrate 1C1 has a stacked structure (SOI structure) of the semiconductor substrate 2, the insulating layer 3a thereon, and the semiconductor layer 4a thereon. In the bulk region 1B, the substrate 1C1 is made of SOI. The semiconductor substrate 2 is configured without having a structure.

  Next, as shown in FIG. 32, after the insulating film 42 in the bulk region 1B is removed, an element isolation region (element isolation structure) 5 is formed on the substrate 1C1 in the same manner as in the first embodiment. The element isolation region 5 is formed of an insulator (for example, silicon oxide) embedded in the element isolation groove 5a.

  In the SOI region 1A, the element isolation trench 5a and the element isolation region 5 filling the element isolation groove 5A penetrate the semiconductor layer 4a and the insulating layer 3a, and the bottom thereof reaches the semiconductor substrate 2, and the lower part of the element isolation region 5 Is located in the semiconductor substrate 2. In the bulk region 1B, the element isolation trench 5a and the element isolation region 5 filling the element isolation trench 5a are formed in the semiconductor substrate 2.

  The subsequent steps (steps after the element isolation region 5 forming step) are basically the same as those in the first embodiment or the second embodiment. For this reason, the structure of the manufactured semiconductor device is basically the same as that of the first embodiment or the second embodiment. However, in this embodiment, since the insulating layer 3a is not formed in the bulk region 1B, the step of FIG. 4 (the step of removing the semiconductor layer 4 and the insulating layer 3 in the bulk region 1B) is performed in this embodiment. This is not done in the form. That is, the substrate 1C1 corresponds to the substrate 1C, the insulating layer 3a corresponds to the insulating layer 3, and the semiconductor layer 4a corresponds to the semiconductor layer 4.

  When the manufacturing process of the first embodiment is performed using the substrate 1C1 of the present embodiment, the substrate 1C is read as the substrate 1C1 in the description of the manufacturing process of the first embodiment, and the insulating layer 3 is insulated. The semiconductor layer 4 may be read as the semiconductor layer 4a. The ion implantation P1 is performed on the semiconductor substrate 2 (the semiconductor substrate 2 below the insulating layer 3a) in the SOI region 1A of the substrate 1C1, and the semiconductor layer 4a (the semiconductor layer 4a above the insulating layer 3a) in the SOI region 1A. In this case, impurity ions are prevented from being implanted. When the manufacturing process of the second embodiment is performed using the substrate 1C1 of the present embodiment, the substrate 1C is read as the substrate 1C1 and the insulating layer 3 is insulated in the description of the manufacturing process of the second embodiment. The semiconductor layer 4 may be read as the semiconductor layer 4a.

  In this embodiment, the substrate 1C1 having the SOI region 1A and the bulk region 1B can be prepared without using an expensive SOI substrate. For this reason, in addition to the effects obtained in the first and second embodiments, the manufacturing cost of the semiconductor device can be further reduced.

(Embodiment 4)
33 to 37 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.

  In the present embodiment, as shown in FIG. 33, first, a semiconductor substrate 2 made of single crystal silicon or the like is prepared. Then, a surface protecting insulating film 51 such as a silicon oxide film is formed on the main surface (front surface) of the semiconductor substrate 2.

  Next, a photoresist pattern (not shown) that covers the bulk region 1B and exposes the SOI region 1A is formed on the insulating film 51 by using a photolithography technique, and then the photoresist pattern is etched into an etching mask. As shown in FIG. 34, the insulating film 51 in the SOI region 1A is removed by etching. Thereafter, the photoresist pattern is removed.

  As a result, the surface (single crystal silicon surface) of the semiconductor substrate 2 is exposed in the SOI region 1A, and the insulating film 51 is present on the surface of the semiconductor substrate 2 in the bulk region 1B.

  Next, the semiconductor layer 4b is formed by epitaxial growth on the surface (single crystal silicon surface) of the semiconductor substrate 2 in the SOI region 1A. The semiconductor layer 4b is made of a semiconductor material (single crystal) different from that of the semiconductor substrate 2, and is made of, for example, silicon germanium mixed crystal, silicon carbide mixed crystal, or gallium arsenide. Since the semiconductor layer 4b is not formed on the insulating film 51, it is not formed in the bulk region 1B. FIG. 34 shows this stage.

  Next, as shown in FIG. 35, a photoresist pattern PR31 that covers the bulk region 1B and exposes the SOI region 1A is formed on the insulating film 51 in the bulk region 1B by using a photolithography technique. Then, oxygen ions are implanted into the semiconductor substrate 2 in the SOI region 1A using the photoresist pattern PR31 as an ion implantation blocking mask. This ion implantation of oxygen ions is schematically indicated by an arrow in FIG. 35, and is hereinafter referred to as ion implantation P11a. Further, in FIG. 35, oxygen ions introduced by the ion implantation P11a are schematically indicated by X marks and denoted by reference numeral 43a. Prior to the ion implantation P11a, an ion-implanting P11a may be performed after an insulating film (not shown) for surface protection is formed on the surface of the semiconductor layer 4b in the SOI region 1A. During the ion implantation P11a, the photoresist pattern PR31 functions as an ion implantation blocking mask for the bulk region 1B, so that oxygen ions are not introduced (ion implantation) into the semiconductor substrate 2 in the bulk region 1B. After the ion implantation P11a, the photoresist pattern PR31 is removed.

In the ion implantation P11a, oxygen ions are prevented from being implanted into at least the upper layer portion of the semiconductor layer 4b. That is, in the SOI region 1A, the ion implantation energy is adjusted so that oxygen ions are locally implanted (introduced) at a predetermined depth from the surface of the semiconductor layer 4b. For example, oxygen ions are implanted with an implantation energy of 100 keV and an implantation amount of 1 × 10 ¹⁶ cm ⁻² . Thereby, oxygen ions can be prevented from being implanted from the surface of the semiconductor layer 4b to a predetermined depth position (for example, about 50 nm).

  Next, the semiconductor substrate 2 is subjected to a heat treatment to cause the oxygen ions 43a introduced by the ion implantation P11a to react with the semiconductor substrate 2 and the semiconductor layer 4b, and from the oxide as shown in FIG. An insulating layer 3b is formed. For example, the heat treatment can be performed at about 1100 ° C. for about 6 hours. In the ion implantation P11a, the oxygen ions 43a are implanted into the semiconductor substrate 2 in the SOI region 1A (in some cases, the lower layer portion of the semiconductor layer 4b), but are not implanted into the semiconductor substrate 2 in the bulk region 1B. 3b is formed on the semiconductor substrate 2 in the SOI region 1A, but is not formed on the semiconductor substrate 2 in the bulk region 1B.

  In the SOI region 1A, the insulating layer 3b is formed not at the surface of the semiconductor layer 4b but at a predetermined depth from the surface of the semiconductor layer 4b. That is, in the SOI region 1A, the insulating layer 3b is formed inside (in the middle) of the stacked structure of the semiconductor substrate 2 and the semiconductor layer 4b in the thickness direction. At this time, the semiconductor layer 4b having a predetermined thickness remains above the insulating layer 3b, the semiconductor substrate 2 also remains below the insulating layer 3b, and the main surface (surface) of the insulating layer 3b is the surface of the semiconductor substrate 2. It is substantially parallel to the main surface (surface).

  The thickness of the semiconductor layer 4b on the insulating layer 3b is preferably about 20 to 40 nm. Moreover, the thickness of the insulating layer 3b can be about 10-50 nm, for example, and the thickness of the semiconductor substrate 2 under the insulating layer 3b can be about 300-750 micrometers, for example.

  Hereinafter, the entire semiconductor substrate 2 on which the semiconductor layer 4b and the insulating layer 3b are formed is referred to as a substrate 1C2. In the SOI region 1A, the substrate 1C2 has a stacked structure (SOI structure) of the semiconductor substrate 2, the insulating layer 3b thereon, and the semiconductor layer 4b thereon, and in the bulk region 1B, the substrate 1C2 The semiconductor substrate 2 is configured without having a structure.

  Next, as shown in FIG. 37, after removing the insulating film 51 in the bulk region 1B, an element isolation region (element isolation structure) 5 is formed on the substrate 1C2 in the same manner as in the first embodiment. The element isolation region 5 is formed of an insulator (for example, silicon oxide) embedded in the element isolation groove 5a.

  In the SOI region 1A, the element isolation trench 5a and the element isolation region 5 filling the element isolation trench 5a penetrate the semiconductor layer 4b and the insulating layer 3b, and the bottom thereof reaches the semiconductor substrate 2, and the lower part of the element isolation region 5 Is located in the semiconductor substrate 2. In the bulk region 1B, the element isolation trench 5a and the element isolation region 5 filling the element isolation trench 5a are formed in the semiconductor substrate 2.

  The subsequent steps (steps after the element isolation region 5 forming step) are basically the same as those in the first embodiment or the second embodiment. For this reason, the structure of the manufactured semiconductor device is basically the same as that of the first embodiment or the second embodiment. However, in this embodiment, since the insulating layer 3b is not formed in the bulk region 1B, the step of FIG. 4 (the step of removing the semiconductor layer 4 and the insulating layer 3 in the bulk region 1B) is performed in this embodiment. This is not done in the form. That is, the substrate 1C2 corresponds to the substrate 1C, the insulating layer 3b corresponds to the insulating layer 3, and the semiconductor layer 4b corresponds to the semiconductor layer 4.

  When the manufacturing process of the first embodiment is performed using the substrate 1C2 of the present embodiment, the substrate 1C is replaced with the substrate 1C2 in the description of the manufacturing process of the first embodiment, and the insulating layer 3 is insulated. The semiconductor layer 4 may be read as the semiconductor layer 4b. The ion implantation P1 is performed on the semiconductor substrate 2 in the SOI region 1A of the substrate 1C2 (the semiconductor substrate 2 below the insulating layer 3b), and the semiconductor layer 4b in the SOI region 1A (the semiconductor layer 4b above the insulating layer 3b). In this case, impurity ions are prevented from being implanted. When the manufacturing process of the second embodiment is performed using the substrate 1C2 of the present embodiment, the substrate 1C is read as the substrate 1C2 and the insulating layer 3 is insulated in the description of the manufacturing process of the second embodiment. The semiconductor layer 4 may be read as the semiconductor layer 4b.

  In this embodiment, a substrate 1C2 having an SOI region 1A and a bulk region 1B can be prepared without using an expensive SOI substrate. For this reason, in addition to the effects obtained in the first and second embodiments, the manufacturing cost of the semiconductor device can be further reduced.

  In the present embodiment, the semiconductor layer 4b in the SOI region 1A is formed of a semiconductor material (single crystal) different from that of the semiconductor substrate 2, for example, a silicon germanium mixed crystal, a silicon carbide mixed crystal, or gallium arsenide. As a result, the characteristics of the circuit formed in the SOI region 1A can be further improved. Further, if the semiconductor layer 4b in the SOI region 1A is formed of a direct transition type semiconductor material or a semiconductor superlattice structure such as GaAs, InP, GaN, AlGaAs, GaP, Si / Ge superlattice, etc., the SOI region 1A A circuit to be formed can have an optical communication function, a light emission function, a light reception function, or the like.

(Embodiment 5)
FIG. 38 is a plan view showing an overall configuration of a semiconductor chip (semiconductor device) CP1 of the present embodiment to which the first to fourth embodiments are applied.

  The semiconductor chip (semiconductor device) CP1 of the present embodiment shown in FIG. 38 has a memory area (memory circuit area, memory cell array area, SRAM area) MRY in which a memory cell array such as SRAM (Static Random Access Memory) is formed. And a peripheral circuit region PCR in which circuits (peripheral circuits) other than the memory are formed. The peripheral circuit region PCR includes, for example, an analog circuit region in which an analog circuit is formed, a CPU region in which a control circuit (logic circuit) is formed, and the like. The memory region MRY and the peripheral circuit region PCR or between the peripheral circuit regions PCR are electrically connected as necessary via the internal wiring layer of the semiconductor chip CP1. In addition, a plurality of pad electrodes PD are formed along the four sides of the main surface of the semiconductor chip CP1 at the periphery of the main surface (front surface) of the semiconductor chip CP1. Each pad electrode PD is electrically connected to the memory region MRY, the peripheral circuit region PCR, etc. via the internal wiring layer of the semiconductor chip CP1. FIG. 38 is a plan view, but for easy understanding, the SOI region 1A having the SOI structure is hatched.

  When the first to fourth embodiments are applied to the semiconductor chip (semiconductor device) CP1 of the present embodiment, the memory region MRY is formed (placed) in the SOI region 1A, and the peripheral circuit region PCR is formed in the bulk region 1B. Form (arrange). That is, a substrate constituting the semiconductor chip CP1 having the memory region MRY and the peripheral circuit region PCR in which circuits other than the memory are formed is a substrate having the SOI region 1A and the bulk region 1B (the substrates 1C, 1C1, 1C2). The memory region MRY is formed in the semiconductor layer of the SOI region 1A (corresponding to one of the semiconductor layers 4, 4a and 4b), and the peripheral circuit region PCR is formed on the semiconductor substrate 2 in the bulk region 1B. Form. That is, in the first to fourth embodiments, among the plurality of MISFETs included in the semiconductor chip CP1, any of the MISFETs constituting the memory (memory area MRY) is replaced with any one of the semiconductor layers in the SOI area 1A (the semiconductor layers 4, 4a, 4b). MISFETs that form a circuit other than the memory (peripheral circuit region PCR) are formed on the semiconductor substrate 2 in the bulk region 1B. Therefore, in the first to fourth embodiments, the MISFET formed in the SOI region 1A is a MISFET constituting the memory region MRY, and the MISFET formed in the bulk region 1B is a MISFET constituting the peripheral circuit region PCR. is there.

  In the memory region MRY, if the threshold voltage fluctuates for each MISFET, an accurate operation of the memory cannot be performed. Therefore, it is desirable to suppress the fluctuation of the threshold voltage as much as possible. Further, MISFETs constituting memory cells (particularly MISFETs constituting SRAMs) are miniaturized as compared to MISFETs constituting circuits other than the memory. When the state of the channel region (impurity arrangement state of the impurity in the channel region) varies for each MISFET, the variation in threshold voltage increases as the MISFET (MISFET having a smaller gate area) is miniaturized. For this reason, in the MISFET in the memory region MRY, the threshold voltage fluctuates easily due to the variation (random variation) in the arrangement state of the impurities in the channel region, compared to the MISFET in the peripheral circuit region PCR.

  As described in the first embodiment, the MISFET in which it is important to suppress the fluctuation of the threshold voltage is arranged in the SOI region 1A, and the fluctuation of the threshold voltage is reduced as compared with the MISFET formed in the SOI region 1A. Although an allowable MISFET is arranged in the bulk region 1B, in the present embodiment, the former MISFET corresponds to the MISFET in the memory region MRY, and the latter MISFET corresponds to the MISFET in the peripheral circuit region PCR.

  That is, since the MISFET in which it is important to suppress the fluctuation of the threshold voltage is the MISFET in the memory region MRY, the memory region MRY is arranged (formed) in the SOI region 1A, and the peripheral circuit region PCR is compared with the memory region MRY. Therefore, the fluctuation of the threshold voltage of the MISFET can be tolerated or the fluctuation of the threshold voltage hardly occurs, so the peripheral circuit region PCR is arranged (formed) in the bulk region 1B.

  The configuration and manufacturing process of the MISFET in the memory region MRY are the same as those of the MISFET formed in the SOI region 1A in the first to fourth embodiments, and the configuration and manufacturing process of the MISFET in the peripheral circuit region PCR are the same as those in the first embodiment. The same as the MISFET formed in the bulk region 1B in .about.4. Therefore, impurities are introduced into the channel region of the MISFET in the peripheral circuit region PCR, but no impurities are introduced into the channel region of the MISFET in the memory region MRY. That is, the MISFET of the memory region MRY is formed in the SOI region 1A and the MISFET of the peripheral circuit region PCR is formed in the bulk region 1B. When forming the MISFET of the memory region MRY in the SOI region 1A, channel doping ion implantation is performed. When the MISFET of the peripheral circuit region PCR is formed in the bulk region 1B, channel dope ion implantation is performed (well formation ion implantation is also performed). This prevents impurities from being ion-implanted in the channel region of the MISFET in the memory region MRY formed in the SOI region 1A, while impurities are present in the channel region of the MISFET in the peripheral circuit region PCR formed in the bulk region 1B. Ion implanted. Further, when forming the MISFET of the memory region MRY in the SOI region 1A, halo ion implantation is not performed, and when forming the MISFET of the peripheral circuit region PCR in the bulk region 1B, halo ion implantation is performed.

  Therefore, the effects as described in the first embodiment, such as the variation in the threshold voltage of the MISFET in the memory region MRY, can be obtained even in the semiconductor chip CP1 having the memory region MRY and the peripheral circuit region PCR.

  For example, the variation in the threshold voltage of the MISFET in the memory region MRY can be prevented, so that the reliability and performance of the memory formed in the memory region MRY can be improved, and the memory formed in the memory region MRY. Cell writing and reading margins are better than the design standard, and the incidence of product defects can be greatly reduced. Further, since the MISFET in the peripheral circuit region PCR is formed on the semiconductor substrate 2 in the bulk region 1B, there is no additional limitation on the properties due to the formation in the SOI region 1A. It is possible to improve characteristics other than the characteristics affected by the variation. Since the peripheral circuit region PCR is formed in the semiconductor substrate 2 in the bulk region 1B, it is not necessary to redesign by forming it in the SOI region 1A, and only the memory region MRY needs to be redesigned. And cost can be reduced.

  In addition to the SRAM, other types of memory cell arrays such as a flash memory can be formed in the memory area MRY. However, in the case of SRAM, the element is particularly miniaturized and the allowable amount of variation in threshold voltage is small, so that the effect is particularly great when the memory formed in the memory region MRY is SRAM.

(Embodiment 6)
FIG. 39 is a plan view showing an overall configuration of a semiconductor chip (semiconductor device) CP2 of the present embodiment to which the first to fourth embodiments are applied.

  A semiconductor chip (semiconductor device) CP2 of the present embodiment shown in FIG. 39 includes a memory region MRY in which a memory cell array such as SRAM is formed, and a peripheral circuit region PCR in which circuits (peripheral circuits) other than the memory are formed. have. The semiconductor region (semiconductor device) CP2 is mainly formed with a memory region MRY. The semiconductor device (semiconductor device) CP2 is a so-called memory chip, and the analog circuit region as in the semiconductor device CP1 of the fifth embodiment. And no CPU area. The memory region MRY and the peripheral circuit region PCR are electrically connected as necessary via the internal wiring layer of the semiconductor chip CP2. In addition, a plurality of pad electrodes PD are formed along the two sides of the main surface of the semiconductor chip CP2 in the peripheral portion of the main surface (front surface) of the semiconductor chip CP2. Each pad electrode PD is electrically connected to the memory region MRY, the peripheral circuit region PCR, etc. via the internal wiring layer of the semiconductor chip CP2. FIG. 39 is a plan view, but in order to facilitate understanding, the SOI region 1A having the SOI structure is hatched.

  Also in the semiconductor chip (semiconductor device) CP2 of the present embodiment, similarly to the semiconductor chip CP1 of the fifth embodiment, the memory region MRY is formed (placed) in the SOI region 1A, and the peripheral circuit region PCR is formed in the bulk. It is formed (arranged) in the region 1B. That is, a substrate constituting the semiconductor chip CP2 having the memory region MRY and the peripheral circuit region PCR in which circuits other than the memory are formed is a substrate having the SOI region 1A and the bulk region 1B (the substrates 1C, 1C1, 1C2). The memory region MRY is formed in the semiconductor layer of the SOI region 1A (corresponding to one of the semiconductor layers 4, 4a and 4b), and the peripheral circuit region PCR is formed on the semiconductor substrate 2 in the bulk region 1B. Form. In other words, in the first to fourth embodiments, among the plurality of MISFETs included in the semiconductor chip CP2, the MISFET constituting the memory (memory area MRY) is changed to the semiconductor layer in the SOI area 1A (any one of the semiconductor layers 4, 4a, 4b). MISFETs that form a circuit other than the memory (peripheral circuit region PCR) are formed on the semiconductor substrate 2 in the bulk region 1B. Therefore, in the first to fourth embodiments, the MISFET formed in the SOI region 1A is a MISFET constituting the memory region MRY, and the MISFET formed in the bulk region 1B is a MISFET constituting the peripheral circuit region PCR. is there. The configuration and manufacturing process of the MISFET in the memory region MRY are the same as those of the MISFET formed in the SOI region 1A in the first to fourth embodiments, and the configuration and manufacturing process of the MISFET in the peripheral circuit region PCR are the same as those in the first embodiment. The same as the MISFET formed in the bulk region 1B in .about.4.

  Also in the present embodiment, the memory region MRY in which it is important to suppress the variation in the threshold voltage of the MISFET is arranged (formed) in the SOI region 1A, and the variation in the threshold voltage of the MISFET as compared with the memory region MRY. Peripheral circuit region PCR in which the threshold voltage is less likely to change or is not easily generated is arranged (formed) in bulk region 1B. Impurities are introduced into the channel region of the MISFET in the peripheral circuit region PCR arranged (formed) in the bulk region 1B, but impurities are introduced into the channel region of the MISFET in the memory region MRY arranged (formed) in the SOI region 1A. Since it is not introduced, the effects as described in the first embodiment can be obtained in this embodiment, such as preventing the fluctuation of the threshold voltage of the MISFET in the memory region MRY. Therefore, the same effect as in the fifth embodiment can be obtained.

(Embodiment 7)
40 to 57 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process.

  In the present embodiment, as shown in FIG. 40, first, a semiconductor substrate 2 made of single crystal silicon (for example, p-type single crystal silicon) or the like is prepared. Then, a surface protection insulating film 61 such as a silicon oxide film is formed on the main surface (front surface) of the semiconductor substrate 2.

  Next, as shown in FIG. 41, a photoresist pattern PR41 is formed on the insulating film 61 using a photolithography technique. This photoresist pattern PR41 covers the entire bulk region 1B, and of the SON (SON: Silicon On Nothing) region 1D, a cavity formation scheduled area (a area where a cavity CAV is formed later is referred to as a cavity formation scheduled area). ) Are exposed, and other regions (regions other than the cavity formation planned region) are covered. 40 to 57, in the SON region 1D, the cross-sectional region indicated by reference numeral 1D1 shows a cross section parallel to the gate length direction of the gate electrode GE1 to be formed later, and is indicated by reference numeral 1D2. In the cross-sectional area, a cross section parallel to the gate width direction of the gate electrode GE1 to be formed later is shown.

  Next, the insulating film 61 in the SON region 1D is removed by etching using the photoresist pattern PR41 as an etching mask. Thereafter, the photoresist pattern PR41 is removed.

  Thus, in the SON region 1D, the insulating film 61 is removed in the cavity formation scheduled region, the surface (single crystal silicon surface) of the semiconductor substrate 2 is exposed, and the other regions (regions other than the cavity formation scheduled region) are semiconductors. The insulating film 61 is present on the surface of the substrate 2, while the bulk region 1 </ b> B is entirely in the state where the insulating film 61 is present on the surface of the semiconductor substrate 2. The cavity formation scheduled area corresponds to an area where a cavity CAV will be formed later.

  Next, as shown in FIG. 42, the semiconductor layer 62 is selectively grown by epitaxial growth on the exposed portion of the semiconductor substrate 2 in the SOI region 1A (the portion where the single crystal silicon is exposed). The semiconductor layer 62 is made of a semiconductor material (single crystal thereof) different from that of the semiconductor substrate 2, for example, silicon germanium. The semiconductor layer 62 is formed on a portion where the semiconductor substrate 2 is exposed (portion where the single crystal silicon is exposed), but is not formed on the insulating film 61. For this reason, the semiconductor layer 62 is not formed in the entire bulk region 1B, and also in the SON region 1D, the semiconductor layer 62 is not formed in any region other than the cavity formation scheduled region, and the semiconductor is not formed in the cavity formation scheduled region in the SON region 1D. Layer 62 is selectively formed.

  Next, as shown in FIG. 43, after removing the insulating film 61 in the SON region 1D and the bulk region 1B, a semiconductor layer 63 is formed by epitaxial growth of silicon. The semiconductor layer 63 is made of a silicon layer (single crystal silicon layer). In the bulk region 1B, the semiconductor layer 63 is formed on the surface of the semiconductor substrate 2, and in the SON region 1D, in the cavity formation scheduled region, the semiconductor layer 63 is formed on the semiconductor layer 62, and regions other than the cavity formation scheduled region Then, the semiconductor layer 63 is formed on the surface of the semiconductor substrate 2.

  Next, as shown in FIG. 44, an element isolation region (element isolation structure) 5 is formed. The element isolation region 5 is formed of an insulator (for example, silicon oxide) embedded in the element isolation groove 5a. The element isolation trench 5a and the element isolation region 5 filling the element isolation groove 5a penetrate the semiconductor layer 63, and the bottom thereof reaches the semiconductor substrate 2. The lower part of the element isolation region 5 is located in the semiconductor substrate 2. ing.

  In the element isolation region 5, an element isolation groove 5 a penetrating the semiconductor layer 63 and having a bottom portion located in the semiconductor substrate 2 is formed by using a photolithography technique, a dry etching technique, or the like. It can be formed by embedding an insulating film using a film technique, a CMP technique, or the like.

  At this stage, the active region defined (partitioned) in the element isolation region 5 in the bulk region 1B has a stacked structure of the semiconductor substrate 2 and the semiconductor layer 63, and is defined in the element isolation region 5 in the SON region 1D. The (divided) active region includes a portion having a stacked structure of the semiconductor substrate 2 and the semiconductor layer 63 and a portion having a stacked structure of the semiconductor substrate 2, the semiconductor layer 62, and the semiconductor layer 63. A portion having a laminated structure of the semiconductor substrate 2, the semiconductor layer 62, and the semiconductor layer 63 corresponds to a cavity formation scheduled region.

  Next, as shown in FIG. 45, the upper surface of the element isolation region 5 is etched by etching the upper portion of the element isolation region 5 (that is, the height position of the upper surface of the element isolation region 5 is lowered). This etching is performed under such a condition that the insulating material constituting the element isolation region 5 can be selectively etched, so that the semiconductor layers 62 and 63 are not etched as much as possible. Thereby, in the bulk region 1 </ b> B, the upper surface of the element isolation region 5 is lower than the surface of the semiconductor layer 63. In the SON region 1D, the upper surface of the element isolation region 5 is lower than the surfaces of the semiconductor layers 62 and 63, and the side surface of the semiconductor layer 62 is exposed in the region where the upper surface of the element isolation region 5 is recessed.

  Next, as shown in FIG. 46, the semiconductor layer 62 is selectively etched and removed. This etching is performed under conditions that allow the insulating material constituting the semiconductor layer 62 to be selectively etched, so that the semiconductor layer 63 and the semiconductor substrate 2 are not etched as much as possible. As described above, since the upper surface of the element isolation region 5 is retracted to expose the side surface of the semiconductor layer 62, the semiconductor layer 62 is etched from the exposed side surface (the side surface shown in the cross-sectional region 1D2). Can do. Therefore, the semiconductor layer 62 is etched by isotropic etching, for example, wet etching using an etchant that can selectively etch the semiconductor layer 62.

  Since the semiconductor layer 62 is removed by etching, the region where the semiconductor layer 62 was present becomes a cavity CAV. Since the semiconductor layer 62 is not formed in the bulk region 1B and is formed only in the cavity formation scheduled region of the SON region 1D, the cavity CAV is not formed in the bulk region 1B and is scheduled to be formed in the SON region 1D. Only formed in the region.

  The semiconductor substrate 2 at this stage, that is, the semiconductor substrate 2 in which the cavity CAV, the semiconductor layer 63, and the element isolation region 5 are formed is referred to as a substrate 1E. The SON region 1D is a region where a MISFET having a cavity CAV is formed below the channel region, and the cavity CAV is formed in accordance with the formation position of the MISFET. The bulk region 1B is a region where a MISFET having no cavity CAV is formed below the channel region, and no cavity CAV is formed. In the bulk region 1B, on the semiconductor substrate 2 except on the element isolation region 5 A semiconductor layer 63 is formed. As in the first and second embodiments, the bulk region 1B has the high breakdown voltage MIS formation region 1BH and the low breakdown voltage MIS formation region 1BL. Although the region 1BH and the low breakdown voltage MIS formation region 1BL can be provided, for simplicity, the illustration and description of the high breakdown voltage MIS formation region 1BH are omitted, and the bulk region 1B is illustrated as the low breakdown voltage MIS formation region 1BL. explain.

  Next, after forming a thin insulating film (through film, not shown here) on the surface of the substrate 1E (that is, the surface of the semiconductor layer 63 in the SON region 1D and the bulk region 1B) for preventing surface contamination, As shown in FIG. 47, a photoresist pattern PR3a is formed on the main surface of the substrate 1E using a photolithography technique. The photoresist pattern PR3a is formed so as to cover the SON region 1D and expose the bulk region 1B. The photoresist pattern PR3a can function as an ion implantation blocking mask for the SON region 1D.

  Next, in the bulk region 1B, ion implantation (that is, channel dope ion implantation) P2a for adjusting a threshold value of a MISFET to be formed later is performed on the semiconductor layer 63. Impurities are introduced (doped) into the channel region of the MISFET formed in the bulk region 1B by the channel dope ion implantation P2a. In FIG. 47, the channel dope ion implantation P2a is schematically indicated by an arrow. Since the semiconductor layer 63 in the SON region 1D is covered with the photoresist pattern PR3a, impurity ions are not implanted during the channel dope ion implantation P2a. Thereafter, the photoresist pattern PR3a is removed.

  Next, as shown in FIG. 48, a p-type well PW1 is formed in the semiconductor layer 63 and the semiconductor substrate 2 in the bulk region 1B, as in the first embodiment.

  In the present embodiment, ion implantation for forming a well region can be performed on the semiconductor layer 63 and the semiconductor substrate 2 in the bulk region 1B, but the well region is formed on the semiconductor layer 63 in the SON region 1D. Ion implantation for forming is not performed. Therefore, at the time of ion implantation for forming the p-type well PW1, the SON region 1D is covered with a photoresist pattern (not shown) as an ion implantation blocking mask, and the semiconductor layer 63 in the SON region 1D. In this case, impurity ions are not implanted.

  Next, after cleaning the surface (main surface) of the substrate 1E by, for example, wet etching using a hydrofluoric acid (HF) aqueous solution (removing unnecessary oxide film, etc.), as shown in FIG. A gate insulating film 7a is formed on the semiconductor layer 63 in the region 1D, and a gate insulating film 7b is formed on the semiconductor layer 63 (p-type well PW1) in the bulk region 1B. The thickness relationship and formation method of the gate insulating films 7a and 7b can be the same as those in the first embodiment.

  Next, as shown in FIG. 50, a polycrystalline silicon film (doped polysilicon) is formed on the entire main surface of the substrate 1E (that is, on the gate insulating films 7a and 7b) as a conductor film for forming a gate electrode. A silicon film 8 such as a film is formed. Then, by patterning the silicon film 8 by dry etching using a photoresist pattern (not shown) formed on the silicon film 8, gate electrodes GE1 and GE2 are formed as shown in FIG. The gate electrodes GE1 and GE2 are made of a patterned silicon film 8, the gate electrode GE1 is formed on the semiconductor layer 63 in the SON region 1D via the gate insulating film 7a, and the gate electrode GE2 is a semiconductor in the bulk region 1B. Over the layer 63 (p-type well PW1), a gate insulating film 7b is formed.

  At this time, the gate electrode GE1 is formed in the SON region 1D, and the gate electrode GE2 is formed in the bulk region 1B. In this embodiment, the gate insulating layer 1D is formed immediately below the gate electrode GE1 formed in the SON region 1D. A cavity CAV exists through the film 7 a and the semiconductor layer 63. That is, the cavity CAV is present immediately below the channel region of the MISFET formed in the SON region 1D (that is, the channel region formed under the gate electrode GE1). Therefore, in the step of forming the semiconductor layer 62 (epitaxial growth step), the semiconductor layer 62 is formed so that a cavity CAV is formed immediately below the gate electrode GE1 to be formed later. On the other hand, since the cavity CAV is not formed in the bulk region 1B, there is no cavity CAV immediately below the gate electrode GE2 formed in the bulk region 1B.

  As can be seen by referring to FIG. 55 and the like described later, in the SON region 1D, from the region immediately below the gate electrode GE1 (that is, directly below the channel region), directly below the sidewall SW formed on the side wall of the gate electrode GE1. The cavity CAV can be extended over the region. Further, the cavity CAV can be extended directly below the source / drain region SD1, but if the cavity CAV is not extended immediately below the source / drain region SD1, the semiconductor layer on the cavity CAV can be extended. 63 becomes easy to hold, and the cavity CAV can be formed more accurately.

  The process after forming the gate electrodes GE1, GE2, and GE3 is basically the same as that in the first embodiment.

  That is, as in the first embodiment, the extension regions EX1 and EX2 are formed as shown in FIG. At this time, the extension region EX1 is formed in the semiconductor layer 63 of the SON region 1D, and the extension region EX2 is formed in the p-type well PW1 of the bulk region 1B.

  Before or after the ion implantation P5 for forming the extension region EX2, the halo ion implantation P5a is performed on the p-type well PW1 in the bulk region 1B to form the halo region HO2. On the other hand, halo ion implantation (ion implantation for forming the halo region of the extension region EX1) is not performed on the semiconductor layer 63 in the SON region 1D.

  Next, as in the first embodiment, as shown in FIG. 53, a sidewall SW is formed on the sidewalls of the gate electrodes GE1 and GE2.

  Next, in the same manner as in the first embodiment, an epitaxial growth layer 10 is formed as shown in FIG. In the SON region 1D, the epitaxial growth layer 10 is formed on the semiconductor layer 63 (extension region EX1) in a region not covered with the gate electrode GE1 and the sidewall SW, and on the gate electrode GE1, and in the bulk region 1B, the gate is formed. It is formed on the semiconductor layer 63 (extension region EX2) in the region not covered with the electrode GE2 and the sidewall SW, and on the gate electrode GE2.

  Next, as in the first embodiment, as shown in FIG. 55, source / drain regions SD1 and SD2 are formed.

  In the SON region 1D, the source / drain region SD1 is formed across the regions on both sides of the gate electrode GE1 of the semiconductor layer 63 and the epitaxial growth layer 10 thereon. In the bulk region 1B, the source / drain region SD2 is formed across the regions on both sides of the gate electrode GE2 of the semiconductor layer 63 and the epitaxial growth layer 10 thereon. The bottoms of the source / drain region SD2, extension region EX2, and halo region HO2 formed in the bulk region 1B may be located in the semiconductor substrate 2 (p-type well PW1) below the semiconductor layer 63.

  Next, as shown in FIG. 56, the metal silicide layer 12 is formed in the same manner as in the first embodiment. The metal silicide layer 12 is formed in the upper layer (surface layer) portion of the source / drain regions SD1 and SD2 and the upper layer (surface layer) portion of the epitaxial growth layer 10 above the gate electrodes GE1 and GE2.

  Thereafter, in the same manner as in the first embodiment, an insulating film (interlayer insulating film) 21 is formed on the main surface of the substrate 1E, a contact hole 22 is formed in the insulating film 21, and a plug 23 is formed in the contact hole 22. Then, the insulating film 24 is formed on the insulating film 21 in which the plug 23 is embedded, and the wiring M 1 is formed in the insulating film 24. FIG. 57 is a main-portion cross-sectional view of the stage where the wiring M1 forming process is performed in the present embodiment, and corresponds to FIG. 22 of the first embodiment.

  In the first to fourth embodiments, the substrate 1C (or the substrates 1C1 and 1C2) having the SOI region 1A and the bulk region 1B is used, and the MISFET to be formed in the semiconductor device is distributed to the SOI region 1A and the bulk region 1B. Was placed. On the other hand, in this embodiment, an SON structure is applied instead of an SOI structure.

  That is, in the semiconductor device of the present embodiment, a plurality of MISFETs in which a cavity CAV is formed below the channel region and a plurality of MISFETs in which the cavity CAV is not formed below the channel region are formed on the substrate 1E (semiconductor substrate). 2) The semiconductor device formed on the main surface. The MISFET formed in the SON region 1D of the substrate 1E corresponds to the MISFET in which the cavity CAV is formed below the channel region, and the MISFET formed in the bulk region 1B of the substrate 1E is the cavity CAV below the channel region. This corresponds to a MISFET in which is not formed.

  In the first to fourth embodiments, impurities are not introduced into the channel region of the MISFET formed in the SOI region 1A, and impurities are introduced into the channel region of the MISFET formed in the bulk region 1B. It was. With the same concept, in this embodiment, impurities are not introduced into the channel region of the MISFET having a cavity CAV formed in the lower portion of the channel region (that is, the MISFET formed in the SON region 1D). Impurities are introduced into the channel region of the MISFET in which the cavity CAV is not formed below the region (that is, the MISFET formed in the bulk region 1B). That is, when a cavity CAV exists under the channel region of the MISFET, no impurity is introduced into the channel region of the MISFET, and when no cavity CAV exists under the channel region of the MISFET, Impurities are introduced into the channel region.

  Therefore, in the manufacturing process of the present embodiment, when forming a MISFET having a cavity CAV formed in the lower part of the channel region (that is, a MISFET formed in the SON region 1D), impurities are present in the channel of the MISFET. Avoid ion implantation. Therefore, as described above, for the MISFET in the SON region 1D (that is, the MISFET in which the cavity CAV is formed in the lower portion of the channel region), channel doping ion implantation is not performed, and ion implantation for forming the well region is performed. Also do not. Thereby, in the manufactured semiconductor device, the channel region of the MISFET in which the cavity CAV is formed in the lower portion is in a state in which no impurity is introduced.

  Further, in the manufacturing process of the present embodiment, when forming a MISFET in which the cavity CAV is not formed in the lower part of the channel region (that is, a MISFET formed in the bulk region 1B), impurities are formed in the channel region of the MISFET. Are ion-implanted. Therefore, as described above, for the MISFET in the bulk region 1B (that is, the MISFET in which the cavity CAV is not formed under the channel region), channel doping ion implantation is performed, and ion implantation for forming the well region is also performed. Do. Thereby, in the manufactured semiconductor device, the channel region of the MISFET in which the cavity CAV is formed below is in a state in which impurities are introduced.

  In the first to fourth embodiments, halo regions (HO2, HO3) are formed in the MISFET formed in the bulk region 1B, but no halo region is formed in the MISFET formed in the SOI region 1A. . In this embodiment, a halo region (HO2) is formed in the MISFET formed in the bulk region 1B, but no halo region is formed in the MISFET formed in the SON region 1D.

  In this embodiment, the SON region 1D is applied instead of the SOI region 1A. In this case, the threshold of the MISFET in the SON region 1D is not introduced by introducing impurities into the channel region of the MISFET in the SON region 1D. The fluctuation of the value voltage can be prevented. On the other hand, in the bulk region 1B, impurities are introduced into the channel region, but ion implantation (channel dope ion implantation, ion implantation for forming a well region and halo ion implantation) necessary for improving characteristics can be performed. Then, a MISFET in which it is important to suppress fluctuations in threshold voltage is arranged in the SOI region 1A, and a MISFET capable of allowing fluctuations in threshold voltage is arranged in the bulk region 1B as compared with the MISFET formed in the SOI region 1A. As a result, the performance of the entire semiconductor device can be improved.

  Further, when the present embodiment is applied to the semiconductor chips CP1 and CP2 of the fifth and sixth embodiments, the memory region MRY is the SON region 1D and the peripheral circuit region PCR is the bulk region 1B. That is, the substrate constituting the semiconductor chip CP1 (or the semiconductor chip CP2) having the memory region MRY and the peripheral circuit region PCR in which circuits other than the memory are formed is defined as a substrate 1E having the SON region 1D and the bulk region 1B. The memory region MRY is formed in the SON region 1D, and the peripheral circuit region PCR is formed in the bulk region 1B. That is, among the plurality of MISFETs included in the semiconductor chip CP1 (or the semiconductor chip CP2), the MISFET constituting the memory (memory area MRY) is replaced with the MISFET (that is, the SON area 1D) in which the cavity CAV is formed below the channel area. MISFET formed in the above). The MISFET constituting the circuit other than the memory (peripheral circuit region PCR) is a MISFET in which the cavity CAV is not formed below the channel region (that is, the MISFET formed in the bulk region 1B).

  Thereby, fluctuations in the threshold voltage of the MISFET in the memory region MRY can be prevented, so that the reliability and performance of the memory formed in the memory region MRY can be improved and the memory region MRY is formed in the memory region MRY. The margin of writing and reading of the memory cell becomes better than the design standard, and the occurrence rate of product defects can be greatly reduced. Further, since the MISFET in the peripheral circuit region PCR is formed in the bulk region 1B having no cavity CAV, there is no additional limitation on the characteristics due to the formation on the cavity CAV. It is possible to improve characteristics other than the characteristics affected by the variation. Since the peripheral circuit region PCR is formed in the bulk region 1B, it is not necessary to redesign by forming it in the SON region 1D, and only the memory region MRY needs to be redesigned, and the time, labor and cost associated with the design change are suppressed. can do.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1 SOI substrate 1A SOI region 1B Bulk region 1BH High breakdown voltage MIS formation region 1BL Low breakdown voltage MIS formation region 1C, 1C1, 1C2, 1E Substrate 1D SON region 1D1, 1D2 Cross sectional region 2 Semiconductor substrates 3, 3a, 3b Insulating layers 4, 4a , 4b Semiconductor layer 5, 5b Element isolation region 5a Element isolation trench 6 Semiconductor region 7a, 7b, 7c Gate insulating film 8, 8a Silicon film 9 Insulating film 10 Epitaxial growth layer 12 Metal silicide layer 15, 16 Impurity 21 Insulating film 22 Contact hole 23 Plug 24 Insulating film 31 Metal film 41, 42 Insulating film 43, 43a Oxygen ion 51 Insulating film 61 Insulating film 62 Semiconductor layer CAV Cavity CP1, CP2 Semiconductor chip (semiconductor device)
EX1, EX2, EX3 Extension region GE1, GE2, GE3 Gate electrode HO2, HO3 Halo region M1 Wiring MRY Memory region P1, P2, P2a, P3, P4, P5, P5a, P6, P6a Ion implantation P11, P11a Ion implantation PCR Circuit region PD Pad electrode PR1, PR2, PR3, PR3a Photoresist pattern PR4, PR5, PR6, PR7 Photoresist pattern PR11, PR12, PR21, PR31, PR41 Photoresist pattern PW1, PW2 p-type wells SD1, SD2, SD3 Source Drain region SW Side wall

Claims (20)

A semiconductor device in which a plurality of MISFETs are formed on a semiconductor substrate having a first region having an SOI structure in which an insulating layer is embedded and a second region in which the insulating layer is not embedded and does not have an SOI structure. There,
Of the plurality of MISFETs, no impurity is introduced into the channel region of the MISFET formed in the first region, and impurities are introduced into the channel region of the MISFET formed in the second region. A semiconductor device characterized by the above. The semiconductor device according to claim 1,
A memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed;
The semiconductor device, wherein the memory region is formed in the first region of the semiconductor substrate, and the peripheral circuit region is formed in the second region. The semiconductor device according to claim 2,
In the first region, the semiconductor substrate has an SOI structure in which the semiconductor substrate, the insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer are stacked.
Of the plurality of MISFETs, a channel region of the MISFET formed in the first region is formed in the semiconductor layer,
Of the plurality of MISFETs, a channel region of the MISFET formed in the second region is formed in the semiconductor substrate. The semiconductor device according to claim 3.
An SRAM is formed in the memory region. The semiconductor device according to claim 4.
An impurity is introduced into a region adjacent to the insulating layer in the semiconductor substrate under the insulating layer in the first region. A semiconductor device in which a plurality of first MISFETs having cavities formed in a lower portion of a channel region and a plurality of second MISFETs having no cavities formed in a lower portion of the channel region are formed on a main surface of a semiconductor substrate,
Impurities are not introduced into the channel regions of the plurality of first MISFETs,
A semiconductor device, wherein impurities are introduced into channel regions of the plurality of second MISFETs. (A) preparing a semiconductor substrate having a first region having an SOI structure embedded with an insulating layer and a second region not having the insulating layer embedded and having an SOI structure; Forming a first MISFET in the first region and forming a second MISFET in the second region of the semiconductor substrate;
A method of manufacturing a semiconductor device having
The step (a) is performed so that impurities are not ion-implanted into the channel region of the first MISFET formed in the first region. The method of manufacturing a semiconductor device according to claim 7.
The step (a) is performed so that impurities are ion-implanted into the channel region of the second MISFET formed in the second region. The method of manufacturing a semiconductor device according to claim 8.
The semiconductor substrate prepared in the step (a) has an SOI structure in which the semiconductor substrate, the insulating layer on the semiconductor substrate, and the semiconductor layer on the insulating layer are stacked in the first region. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 9,
The step (a)
(A1) A first gate electrode of the first MISFET is formed on the semiconductor layer in the first region via a first gate insulating film, and a second gate insulating film is formed on the semiconductor substrate in the second region. Forming a second gate electrode of the second MISFET,
Including
Prior to the step (a1), impurities are not ion-implanted into the semiconductor layer in the first region. The method of manufacturing a semiconductor device according to claim 10.
The step (a)
(A2) a step of forming a well region in the semiconductor substrate of the second region by ion implantation before the step (a1);
Further including
In the step (a1), the second gate electrode of the second MISFET is formed on the well region via the second gate insulating film. The method of manufacturing a semiconductor device according to claim 11.
The step (a)
(A3) before the step (a1), performing channel doping ion implantation for adjusting the threshold value of the second MISFET into the semiconductor substrate in the second region;
A method for manufacturing a semiconductor device, further comprising: In the manufacturing method of the semiconductor device according to claim 12,
The step (a)
(A4) After the step (a1), in the first region, ion implantation is performed on the semiconductor layer using the first gate electrode as a mask, and one semiconductor region for the source or drain of the first MISFET is formed in the semiconductor layer Forming a first semiconductor region functioning as a portion;
(A5) After the step (a1), in the second region, ion implantation is performed on the semiconductor substrate using the second gate electrode as a mask, and one semiconductor region for the source or drain of the second MISFET is formed on the semiconductor substrate Forming a second semiconductor region functioning as a portion;
(A6) After the step (a1), in the second region, ion implantation is performed on the semiconductor substrate using the second gate electrode as a mask, and the second semiconductor has a conductivity type opposite to that of the second semiconductor region. Forming a first halo region that envelops the region;
(A7) After the steps (a4), (a5), and (a6), forming a sidewall insulating film on the sidewalls of the first gate electrode and the second gate electrode;
A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 13,
A method of manufacturing a semiconductor device, wherein halo ion implantation is not performed on the semiconductor layer in the first region after the step (a1) and before the step (a7). 15. The method of manufacturing a semiconductor device according to claim 14,
The method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
The method of manufacturing a semiconductor device, wherein the memory region is formed in the first region of the semiconductor substrate, and the peripheral circuit region is formed in the second region. The method of manufacturing a semiconductor device according to claim 8.
The step (a)
(A8) a step of ion-implanting impurities into the semiconductor substrate under the insulating layer in the first region before the step (a1);
Further including
In the step (a8), impurities are introduced into the semiconductor substrate under the insulating layer in the first region, but ion implantation is performed so that impurities are not introduced into the semiconductor layer in the first region. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device having a memory region in which a memory is formed and a peripheral circuit region in which a circuit other than the memory is formed,
(B) preparing a semiconductor substrate having a first region having an SOI structure embedded with an insulating layer and a second region not embedded with the insulating layer and having no SOI structure;
Have
After the step (b), a MISFET in the memory region is formed in the first region of the semiconductor substrate, a MISFET in the peripheral circuit region is formed in the second region of the semiconductor substrate,
When forming the MISFET of the memory region in the first region, channel doping ion implantation is not performed,
A method for manufacturing a semiconductor device, wherein channel doping ion implantation is performed when forming a MISFET in the peripheral circuit region in the second region. The method of manufacturing a semiconductor device according to claim 17.
Impurity ions are not implanted into the channel region of the MISFET in the memory region formed in the first region. The method of manufacturing a semiconductor device according to claim 18.
When forming the MISFET of the memory region in the first region, halo ion implantation is not performed,
A method of manufacturing a semiconductor device, wherein halo ion implantation is performed when forming the MISFET of the peripheral circuit region in the second region. A method of manufacturing a semiconductor device in which a plurality of first MISFETs each having a cavity formed below a channel region and a plurality of second MISFETs each having a cavity not formed below the channel region are formed on a main surface of a semiconductor substrate. There,
When forming the plurality of first MISFETs, impurities are prevented from being ion-implanted into the channel regions of the plurality of first MISFETs,
In forming the plurality of second MISFETs, impurities are ion-implanted into channel regions of the plurality of second MISFETs.

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