JP2011517006A - Analog read / write paths in solid state memory devices - Google Patents

Abstract

The memory array in the memory device is connected to an analog I / O data interface that allows analog voltage levels to be written to the memory array. The I / 0 interface is configured to include a plurality of analog data paths, each of which includes a capacitor for storing a charge corresponding to a target voltage, in which selected memory cells connected to each of the data paths are programmed. The A plurality of comparators may be included in an I / O interface comprising each such comparator connected to each bit line. These comparators compare the threshold voltage of the selected memory cell with its target voltage and suppress further programming if the threshold voltage is greater than or equal to the target voltage.
[Selection figure] None

Description

  The present disclosure relates generally to semiconductor memory, and more particularly to non-volatile memory devices in one or more embodiments.

  Electronic devices typically have several types of mass storage devices available for them. A common example of this is a hard disk drive (HDD). HDDs are relatively inexpensive and can store a large capacity, and currently, HDDs with a capacity exceeding 1 terabyte are commercially available for consumers.

  The HDD generally stores data on a rotating magnetic medium or platter. Data is generally stored in the platter as a magnetic flux reversal pattern. In general data writing to the HDD, a write head floating above the platter generates a series of magnetic pulses to arrange magnetic particles indicating data on the platter while the platter rotates at high speed. In reading data from a general HDD, the resistance value of the read head having a magnetic resistance changes when the read head floats on a platter that rotates at high speed. The data signal that is actually obtained is an analog signal in which peaks and valleys are the result of a magnetic flux reversal data pattern. A digital signal processing technique called partial response maximum likelihood (PRML) is then used to sample the analog data signal to determine the similar data patterns involved in generating the data signal.

  HDDs have certain drawbacks due to mechanical characteristics. HDDs are sensitive to damage or excessive read / write errors due to shock, vibration or strong magnetic fields. In addition, HDD uses relatively large power among portable electronic devices.

  Another example of a mass storage device is a solid state drive (SSD). Instead of storing data on spinning media, SSDs use semiconductor storage devices to store their data, and an interface that makes them appear to their host system as if they were typical HDDs. Including form factors. Usually, the SSD memory device is a non-volatile flash memory device.

  Flash memory devices have evolved as a source of non-volatile memory being widely used in electronic equipment. Flash memory devices typically use one-transistor memory cells that allow high storage density, high reliability, and low power consumption. Variations in the cell's threshold voltage through charge storage or trapping layer programming or other physical phenomena determine the data value of each cell. Typical applications for flash memory and other non-volatile memory are personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable Including non-volatile memory and the use of non-volatile memory continues to expand.

  SSD operations, unlike HDDs, are generally not affected by vibrations, shocks or magnetic fields due to their solid state nature. Similarly, since there are no moving parts, the SSD requires less power than the HDD. However, SSDs are currently much smaller in capacity than HDDs of the same form factor, and the price per bit is very expensive.

  For the reasons described above and other reasons which will become apparent to those skilled in the art upon reading and understanding this specification, new mass storage options are needed in the art.

FIG. 1 is a simplified block diagram illustrating a memory device according to one embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating a portion of an exemplary NAND memory array used in the memory device shown in FIG. FIG. 3 is a schematic block diagram illustrating a solid state mass storage system according to one embodiment of the present disclosure. FIG. 4 is a waveform diagram illustrating a conceptual data signal received from a memory device over a read / write channel according to one embodiment of the present disclosure. FIG. 5 is a schematic block diagram illustrating an electronic system according to one embodiment of the present disclosure. FIG. 6 is a block diagram illustrating a memory device in one embodiment according to the mass storage system shown in FIG. 3 having an input / output interface for reading / writing analog voltage levels. FIG. 7 is a block diagram illustrating an analog I / O data path in one embodiment according to the memory device shown in FIG. FIG. 8 is a block diagram illustrating a data cache circuit in one embodiment according to the memory device shown in FIG. FIG. 9 is a flowchart of a method in one embodiment of programming the memory device shown in FIG. 6 having an analog data path.

  In the following detailed description of the embodiments, reference is made to the drawings that form a part hereof, and in which are shown by way of illustration specific embodiments that specifically implement the embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and other embodiments may be utilized, and may be processed, electrically, and without departing from the scope of the present disclosure. Or it should be understood that changes are made mechanically. The following detailed description is, therefore, not to be taken in a limiting sense.

Conventional solid state memory devices pass data in the form of binary signals. The normal ground potential indicates a first logic level of a data bit, for example a data value of “0”, while the supply potential indicates a second logic level of the data bit, for example a data value of “1”. In a multi-level cell (MLC), for example, four different threshold voltage (V _t ) ranges, each in the range of 200 mV, are assigned to each range with a different data state, resulting in four data values or bit patterns. Indicates. To prevent the distribution of V _t overlap, between each range, there usually is 0.4V dead space or margin from 0.2V. If the cell's V _t is in the first range, the cell may be considered to preserve the logical 11 state and is usually considered to be in the cell's erased state. If V _t is in the second range, it may be considered that the cell preserves a logical 10 state. If there is a V _t in the third range, the cell may be considered to save the state of the logical 00. Then, if V _t is in the fourth range, the cell may be considered to store the state of 01 logically.

When programming a conventional MLC device as described above, the cells are typically erased first as a block to accommodate the erased state. Following erasure of a block of cells, the least significant bit (LSB) of each cell is first programmed as needed. For example, if LSB is 1, no programming is required, but if LSB is 0, V _{t of the} target memory cell is changed from a range of V _t corresponding to 11 logic states to 10 logic states. Moved to the corresponding V _t range. Following programming LSB, the most significant bit of each cell (MSB) is likewise programmed to move the V _t where needed. When reading from the MLC of the conventional memory device, generally, which range the cell voltage V _t falls into is determined by one or more reading processes. For example, the first read process may determine whether V _{t of the} target memory cell indicates that the MSB is 1 or 0, while the second read process is: V _t of the target cell, LSB can determine whether indicates that either indicate a 1, or 0. However, no matter how many bits are held in each cell, a single bit is returned each time for one read operation to the target memory cell. This problem in multiple program and read processing becomes very troublesome when each MLC holds more bits. Each such program or read process is a binary process, i.e., each program or responds with a single bit of information per cell, so each MLC holding more bits results in increased processing time.

The memory device of the present embodiment stores data as a range of V _{t in} the memory cell. However, in contrast to conventional memory devices, programming and reading processes utilize the data signal as a complete representation of the MLC data value, such as its overall bit pattern, rather than as individual bits of the MLC data value. For example, in a 2-bit MLC device, instead of programming the LSB of one cell and then programming the MSB of that cell, the target threshold voltage is programmed to show those 2-bit bit patterns. Also good. That is, rather than programming the first threshold voltage for the first bit, shifting to the second threshold voltage for the second bit, etc., until the memory cell has achieved the target threshold voltage, The program and verify process are applied to the memory cell. Similarly, instead of using multiple read processing to determine each bit stored in a cell, the cell's threshold voltage is a single signal that indicates the complete data value of the cell or the bit pattern of the cell. May be confirmed and passed. The various memory devices of this embodiment simply do not recognize whether the memory cell is above or below some nominal threshold voltage, as conventional memory devices do. Instead, a voltage signal is generated that indicates the actual threshold voltage in that memory cell over successive possible threshold voltages. The advantage of this approach becomes more important as the number of bits per cell increases. For example, if the memory cell stores 8-bit information, one analog data signal indicating 8-bit information is returned in one read process.

  FIG. 1 is a simplified block diagram illustrating a memory device 101 according to an embodiment of the present disclosure. Memory device 101 includes an array 104 of memory cells arranged in rows and columns. Although various embodiments primarily refer to NAND memory arrays, the various embodiments are not limited to a particular configuration of memory array 104. Other array structures applicable to this embodiment include a NOR array, an AND array, and a virtual ground array. However, in general, the embodiments described herein are applicable to any array structure capable of generating a data signal indicative of the threshold voltage of each memory cell.

  The row decoding circuit 108 and the column decoding circuit 110 are provided for decoding an address signal supplied to the memory device 101. Address signals are received and decoded to access the memory array 104. The memory device 101 also includes an input / output (I / O) control circuit 112 that manages not only the output of data and status information from the memory device 101 but also the input of commands, addresses, and data to the memory device 101. . Address register 114 is connected between I / O control circuit 112 and row decode circuit 108 and column decode circuit 110, and latches the address signal before decoding. The command register 124 is connected between the I / O control circuit 112 and the control logic 116 and latches an incoming command. The control logic 116 controls access to the memory array 104 in response to the command and generates status information for the external processor 130. Control logic 116 is connected to row decode circuit 108 and column decode circuit 110, and controls row decode circuit 108 and column decode circuit 110 in response to an address.

  Control logic 116 is also connected to sample and hold circuit 118. Sample and hold circuit 118 latches data in the form of analog voltage levels, either incoming or outgoing. For example, the sample and hold circuit is for sampling an incoming voltage signal that indicates data to be written to the memory cell or an outgoing voltage signal that indicates a threshold voltage sent from the memory cell. Includes capacitors or other analog holding devices. The sample and hold circuit 118 may further amplify and / or buffer the sampled voltage to provide a stronger data signal to an external device.

  The analog voltage signal is handled in the same manner as a method known in the technical field of a CMOS imaging device in which a charge level generated in response to illumination incident on a pixel of the imaging device is stored on a capacitor. You may take These charge levels are then converted to voltage signals by using a differential amplifier with the reference capacitor as the second input. The output of the differential amplifier is then sent to an analog / digital conversion (ADC) device to obtain a digital value indicative of illumination intensity. In this embodiment, the charge is held in the capacitor according to the actual voltage level of the memory cell that the capacitor follows to read the memory cell or the target threshold voltage of the memory cell that the capacitor follows to program the memory cell. May be. This charge can be converted to an analog voltage through the use of a differential amplifier whose second input is a ground input or other reference signal. The output of the differential amplifier is sent to the I / O control circuit 112 for subsequent output from the memory device in a read process, or for comparison during one or more verify processes when programming the memory device. Used. The I / O control circuit 112 converts the read data from the analog signal into a digital bit pattern and converts the write data from the digital bit pattern so that the memory device 101 can communicate with either the analog or digital data interface. Optionally, an analog / digital conversion function and a digital / analog conversion (DAC) function may also be included for conversion to an analog signal.

During the writing process, target memory cells of the memory array 104, a voltage indicating their V _t level is programmed to match the levels held in the sample and hold circuit 118. This is accomplished by comparing the holding voltage with the threshold voltage of the target memory cell using a differential sensing device as an example. As in conventional memory programming, programming pulses are applied to the target memory cell until the threshold voltage of the memory cell increases to reach or exceed the desired value. In the read process, the V _t level of the target memory cell is directly converted to an analog signal depending on whether the ADC / DAC function is provided outside or inside the memory device for passing to an external processor (not shown in FIG. 1). Alternatively, the analog signal is digitized and sent to the sample and hold circuit 118.

  The threshold voltage of the cell may be determined by various methods. For example, the voltage on the word line may be sampled when the target memory cell becomes active. Alternatively, a boost voltage can be applied to the first source / drain side of the target memory cell, and the threshold voltage can be the difference between the control gate voltage and the other source / drain side voltage. By coupling the voltage with the capacitor, the charge is shared with the capacitor to hold its sample voltage. Note that the sample voltage need not be equal to the threshold voltage, but merely indicates that voltage. For example, when a boost voltage is supplied to the first source / drain side of the memory cell and a known voltage is supplied to its control gate, the voltage generated on the second source / drain side of the memory cell is Since the threshold voltage of the cell is shown, it can be obtained as a data signal.

  The sample and hold circuit 118 may include caching, i.e., multiple storage locations for each data value, so that the memory device 101 receives the next data value while sending the first data value to an external processor. While reading or writing the first data value to the memory array 104, the next data value is received. Status register 122 is coupled between I / O control circuit 112 and control logic 116 to latch status information for output to an external processor.

  Memory device 101 receives control signals at control logic 116 via control link 132. The control signal may include a chip enable CE #, a command latch enable CLE, an address latch enable ALE, and a write enable WE #. The memory device 101 receives commands (in the form of command signals), addresses (in the form of address signals), and data (in the form of data signals) from an external processor via a multiple input / output (I / O) bus 134. Data may be received, and data may be output to an external processor through the I / O bus 134.

  In a specific example, commands are received at the I / O control circuit 112 via input / output (I / O) pins [7: 0] of the I / O bus 134 and written to the command register 124. The address is received at the I / O control circuit 112 via the input / output (I / O) pins [7: 0] of the bus 134 and written to the address register 114. Data is input via input / output (I / O) pins [7: 0] so that the device can receive 8 parallel signals or input / output (I) so that the device can receive 16 parallel signals. / O) received by the I / O control circuit 112 via pins [15: 0] and transferred to the sample and hold circuit 118. Data may be output via input / output (I / O) pins [7: 0] so that the device can transfer 8 parallel signals, or input so that the device can transfer 16 parallel signals. / Output (I / O) pins [15: 0] may be used for output. It will be apparent to those skilled in the art that circuitry and signals can be added, and the memory device of FIG. 1 has been simplified to help focus on the embodiments of the present disclosure. In addition, although the memory device of FIG. 1 represents the reception and output of various signals in accordance with common conventions, various embodiments will be described unless explicitly stated herein. It is not limited to detailed signal and I / O configurations. For example, command and address signals can be received as an input separate from the input that receives the data signal. Further, a data signal can be transmitted serially via only one I / O line of the I / O bus 134. Since the data signal represents a bit pattern instead of individual bits, serial communication of an 8-bit data signal is as efficient as parallel communication of 8 signals representing individual bits.

FIG. 2 is a schematic diagram illustrating a portion of an exemplary NAND memory array 200 used as the memory array 104 shown in FIG. In FIG. 2, the memory array 200 includes word lines 202 ₁ to 202 _N and bit lines 204 ₁ to 204 _M intersecting them. For ease of addressing in the digital environment, the number of word lines 202 and the number of bit lines 204 are almost always powers of two.

Memory array 200 includes a NAND string 206 ₁ 206 _M. Each NAND string, the transistor 208 ₁ disposed respectively at the position of intersection between the word lines 202 and bit lines 204 including 208 _N. The transistor 208 represents a nonvolatile memory cell that holds data, and is shown as a floating gate transistor in FIG. The floating gate transistor 208 of each NAND string 206 has a source and drain connected in series between one or more source select gates 210, eg, field effect transistors (FETs), and one or more drain select gates 212, eg, FETs. Is done. Each source selection gate 210 is disposed at the intersection of the local bit line 204 and the source selection line 214, while each drain selection gate 212 is disposed at the intersection of the local bit line 204 and the drain selection line 215.

The source of each source selection gate 210 is connected to the common source line 216. The drain of each source select gate 210 is connected to the source of the first floating gate transistor 208 of the corresponding NAND string 206. For example, the drain of the source select gate 210 ₁ is connected to the source of the floating gate transistor 208 ₁ of the corresponding NAND string 206 ₁ . The control gate of each source selection gate 210 is connected to the source selection line 214. If multiple source select gates 210 are utilized for a given NAND string 206, they are connected in series between the common source line 216 and the first floating gate transistor 208 of that NAND string 206. The

The drain of each drain select gate 212 is connected to the local bit line 204 at the drain contact for the corresponding NAND string. For example, the drain of the drain select gate 212 ₁ is connected at the drain contact with the local bit line 204 ₁ for the corresponding NAND string 206 ₁ . The source of each drain select gate 212 is connected to the drain of the last floating gate transistor 208 of the corresponding NAND string 206. For example, the source of the drain select gate 212 ₁ is connected to the drain of the floating gate transistor 208 _N of the corresponding NAND string 206 ₁ . A plurality of drain select gate 212 is, when utilized for a given NAND string 206, they are in series between the corresponding bit line 204 and the last floating-gate transistor 208 _N of the NAND string 206 Connected.

  A typical floating gate transistor 208 includes a source 230 and a drain 232, a floating gate 234, and a control gate 236, as shown in FIG. Floating gate transistor 208 has their control gates 236 connected to word line 202. The columns of floating gate transistors 208 are those NAND strings 206 connected to a given local bit line 204. The row of floating gate transistors 208 is those transistors commonly connected to a predetermined word line 202. Also, other types of transistors 208 can be programmed to assume one of two or more threshold voltage ranges, such as NROM, magnetic or ferroelectric transistors, and others Of the transistors may be utilized with the disclosed embodiments.

  Memory devices in various embodiments may be used effectively in mass storage devices. These mass storage devices, according to various embodiments, may have the same form factor and communication bus interface as conventional HDDs, so that they can be used as such drives in various applications. Can be replaced. Some common form factors for HDDs are not only the 3.5 ", 2.5" and PCMCIA (PC Memory Card International Association) form factors commonly used in current personal computers and larger digital media recorders. Also included are 1.8 "and 1" form factors commonly used in smaller personal devices such as mobile phones, personal digital assistants (PDAs), and digital media players. Some common bus interfaces are Universal Serial Bus (USB), AT Attachment Interface (ATA), also known as Integrated Drive Electronics or IDE, Serial ATA (SATA), Small Computer System Interface (SCSI), And the American Institute of Electrical and Electronics Engineers (IEEE) 1394 standard. Although various form factors and communication interfaces have been described, the present embodiments are not limited to a particular form factor or communication standard. Furthermore, the present embodiment may not conform to the HDD form factor or the communication interface. FIG. 3 is a schematic block diagram of a solid state mass storage device 300 according to an embodiment of the present disclosure.

  Mass storage device 300 includes a memory device 301, a read / write channel 305, and a controller 310 according to an embodiment of the present disclosure. The read / write channel 305 is provided not only for A / D conversion of the data signal received from the memory device 301 but also for D / A conversion of the data signal received from the controller 310. The controller 310 is provided for communicating between the mass storage device 300 and an external processor (not shown in FIG. 3) via the bus interface 315. Read / write channel 305 can service one or more additional memory devices, as indicated by the dotted line as memory device 301 '. Selection of a single memory device 301 for communication can be handled through a multi-bit chip enable signal or other multiplexing scheme.

  Memory device 301 is coupled to read / write channel 305 via analog interface 320 and digital interface 325. The analog interface 320 is provided as a path for analog data signals between the memory device 301 and the read / write channel 305, and the digital interface 325 is a control signal or command from the read / write channel 305 to the memory device 301. It is provided as a path for signals and address signals. The digital interface 325 is also provided as a status signal path from the memory device 301 to the read / write channel 305. The analog interface 320 and the digital interface 325 can share signal lines as described in connection with the memory device 101 of FIG. The embodiment of FIG. 3 describes both an analog / digital interface to a memory device, but uses only the digital interface as the path for control, command, status, address, and data signals, The functionality of the read / write channel 305 can optionally be incorporated into the memory device 301 as described in connection with FIG. 1 so that the memory device 301 communicates directly with the controller 310.

  Read / write channel 305 is connected to controller 310 via one or more interfaces, such as data interface 330 and control interface 335. The data interface 330 is provided as a path for digital data signals between the read / write channel 305 and the controller 310. The control interface 335 is provided as a path for control signals, command signals, and address signals from the controller 310 to the read / write channel 305. The control interface 335 is further provided as a status signal path from the read / write channel 305 to the controller 310. Status and command / control signals may be sent directly between the controller 310 and the memory device 301 as depicted by the dotted lines connecting the control interface 335 and the digital interface 325.

  Although depicted as two different devices in FIG. 3, the functions of read / write channel 305 and controller 310 may alternatively be performed by a single integrated circuit device. While the individual devices maintain the memory device 301 to be more flexible so that this embodiment adapts to different form factors and communication interfaces, the memory device 301 is also an IC device, so The large-capacity storage device 300 can be manufactured as one IC device.

  Read / write channel 305 is a single processor configured to convert at least a digital data stream to an analog data stream and vice versa. The digital data stream has a data signal in the form of a binary voltage level, i.e. a first voltage level indicating a first binary data value, e.g. one bit with 0, and a second binary data value, e.g. Supply at a second voltage level suggesting one bit. The analog data stream provides a data signal in the form of an analog voltage having two or more levels with different voltage levels or ranges corresponding to different bit patterns of two or more bits. For example, in a system that holds 2 bits per memory cell, the first voltage level or range of the voltage level of the analog data stream can correspond to the bit pattern 11 and the second voltage of the voltage level of the analog data stream. The level or range can correspond to the bit pattern 10 and the third voltage level or range of the voltage level of the analog data stream can correspond to the bit pattern 00 and the fourth of the voltage level of the analog data stream. Can correspond to the bit pattern 01. Therefore, an analog data signal in various embodiments is converted to two or more digital data signals and vice versa.

  In fact, control signals and command signals are received at the bus interface 315 to access the memory device 301 via the controller 310. Address values and data values may also be received at the bus interface 315 depending on what type of access is desired, eg, read, write, format, etc. In a shared bus system, the bus interface 315 is connected to the bus along with various other devices. In order to communicate directly with a particular device, an identification value may be placed on that bus that suggests which device on the bus will operate according to the following command. If the identification value matches the value that the mass storage device 300 has, the controller 310 takes over the subsequent command in the bus interface 315. If the identification values do not match, the controller 310 ignores the subsequent command. Similarly, to avoid collisions on the bus, various devices on the shared bus may instruct other devices to interrupt out-of-band communication while individually controlling the bus. The bus sharing and collision avoidance protocols are well known and will not be described in detail here. Next, the controller 310 sends command, address and data signals to the read / write channel 305 for processing. Command, address, and data signals passed from the controller 310 to the read / write channel 305 need not be the same signals received at the bus interface 315. For example, the communication standard of the bus interface 315 may be different from the communication standard of the read / write channel 305 or the memory device 301. In this situation, the controller 310 may convert the command and / or address scheme prior to accessing the memory device 301. In addition, the controller 310 may provide load leveling within one or more memory devices 301, in which case the physical address of the memory device 301 may change over time to a predetermined logical address. Therefore, the controller 310 maps the logical address from the external device to the physical address of the target memory device 301.

  For write requests, in addition to command and address signals, the controller 310 sends digital data signals to the read / write channel 305. For example, in a 16-bit data word, the controller 310 sends 16 individual signals having a first or second binary logic level. The read / write channel 305 then converts the digital data signal into an analog data signal that indicates the bit pattern of the digital data signal. Following the example above, the read / write channel 305 performs D / A conversion to convert 16 individual digital data signals into a single analog signal having a potential level indicative of the desired 16-bit data pattern. Use. In one embodiment, the analog data signal indicating the bit pattern of the digital data signal is indicative of the desired threshold voltage of the target memory cell. However, in programming one-transistor memory cells, programming of adjacent memory cells often increases the threshold voltage of already programmed memory cells. Thus, in another embodiment, the read / write channel 305 can take into account these types of expected variations in threshold voltage, and is lower than the final desired threshold voltage. The analog data signal can be adjusted to indicate a threshold voltage. After conversion of the digital data signal from the controller 310, the read / write channel 305 then sends write commands and address signals to the memory device 301 along with analog data signals used to program individual memory cells. Although programming can be performed on a cell-by-cell basis, it is generally performed on one page of data per operation. In a typical memory array structure, a page of data includes every other memory cell connected to a word line.

  For read requests, the controller sends command and address signals to the read / write channel 305. The read / write channel 305 sends a read command and an address signal to the memory device 301. After the read process, the memory device 301 returns an address signal and an analog data signal indicating the threshold voltage of the memory cell defined by the read command as a response. The memory device 301 can transfer these analog data signals in a parallel or serial manner.

  The analog data signal can also be transferred as a substantially continuous stream of analog signals rather than as separate voltage pulses. In this state, the read / write channel 305 uses signal processing similar to the signal processing called PRML used for accessing the HDD, that is, the maximum likelihood of partial response. In the conventional HDD PRML processing, the HDD read head outputs a stream of analog signals indicating magnetic flux reversal that occurs during the read processing for the HDD platter. Rather than trying to capture the exact peaks and valleys of this analog signal caused by the flux reversal caused by the read head, the signal is periodically sampled to produce a digital representation of the signal pattern. This digital representation is then analyzed to determine the patterns that are likely to cause magnetic flux reversals that are involved in the generation of the analog signal pattern. This same type of processing can be utilized with embodiments of the present disclosure. By sampling an analog signal from the memory device 301, PRML processing can be used to determine the likely pattern of threshold voltages involved in generating the analog signal.

  FIG. 4 is a diagram conceptually illustrating a waveform of a data signal 450 as received from the memory device 301 by the read / write channel 305 according to an embodiment of the present disclosure. Data signal 450 is periodically sampled and a digital representation of data signal 450 is generated by the amplitude of the sampled voltage level. In one embodiment, the sampling may be synchronized with the data output so that sampling occurs during the steady state portion of the data signal 450. Such an embodiment is depicted by sampling as indicated by the dotted lines at times t1, t2, t3, and t4. However, if the synchronized sampling is not correctly placed, the value of the data sample can be quite different from the steady state value. In an alternative embodiment, the sampling rate can be increased to determine where a steady state is likely to occur, such as by observing slope variations suggested by the data samples. Such an embodiment is depicted by sampling indicated by dotted lines at times t5, t6, t7, and t8, where the slope between the data sample at time t6 and the data sample at t7 is steady state. Show. In such an embodiment, a trade-off is made between sampling rate and representation accuracy. A higher sampling rate provides a more accurate representation but increases processing time. And regardless of whether the sampling is synchronized to the data output or more frequently, the digital representation then determines how much of the incoming voltage level is in the analog signal pattern. Can be used to predict if it was probably involved in the generation. In other words, from this expected pattern of incoming voltage levels, the likely data values of the individual memory cells being read can be predicted.

  Upon recognizing that an error will occur when reading a data value from memory device 301, read / write channel 305 may include error correction. Error correction is commonly used in memory devices as well as HDDs to recover from expected errors. In general, the memory device stores user data in a first set location and an error correction code (ECC) in a second set location. In the read processing period, both the user data and the ECC are read as a response to the user data read request. Using known algorithms, the user data returned from the read process is compared with the ECC. If the error is within its ECC, the error is corrected.

  FIG. 5 is a block schematic diagram illustrating an electronic system according to an embodiment of the present disclosure. Exemplary electronic systems may include personal computers, PDAs, digital cameras, digital media players, digital recorders, electronic games, appliances, vehicles, wireless devices, mobile phones, and the like.

  The electronic system includes a host processor 500 that may include a cache memory 502 that increases the efficiency of the host processor 500. The processor 500 is connected to the communication bus 504. Various other devices may be connected to the communication bus 504 based on the control of the processor 500. For example, the electronic system may include a random access memory (RAM) 506, one or more input devices 508 such as a keyboard, touchpad, pointing device, an audio controller 510, a video controller 512, and one or more mass storage devices 514. May be included. The at least one mass storage device 514 has a digital bus interface 515 for communicating with the bus 504 and an analog interface for passing data signals indicating a data pattern of two or more bits of data according to an embodiment of the present disclosure. One or more memory devices and a signal processor that performs D / A conversion of digital data signals received from the bus interface 515 and A / D conversion of analog signals received from the memory device (s).

  6 is a block diagram illustrating one embodiment of a memory device 600 in the mass storage device system illustrated in FIG. 3 having an analog input / output data interface for reading / writing analog signals. The block diagram shown in FIG. 6 shows only a simplified memory device that highlights the components associated with the analog I / O data interface of the present disclosure. Other components of the memory device 600 are shown and described in the embodiments described above or are known to those skilled in the art.

  Memory device 600 is comprised of a memory array 601 having non-volatile memory cells organized in a matrix. Rows are connected to word lines and columns are connected to bit lines. The array format may be configured as a NAND structure, a NOR structure, or other types of structures. The non-volatile memory cell is a floating gate memory cell in one embodiment.

  The memory array 601 is connected to a plurality of analog data paths 602. In one embodiment, there is one data path for each bit line of memory array 601. Each analog data path 602 connected to a bit line shares all of the memory cells on that particular bit line. By selecting a specific word line with the verify voltage, that word line is connected to its respective analog data path.

  Analog data path 602 functions as both a data cache for storing data and an input path for accessing memory cells in array 601. Data path 602 is disposed between analog I / O pad 610 of memory device 600 and memory array 601. Data path 602 is connected to 8 or 16 analog I / O pad 610 by an 8 or 16 bit wide bus. In alternate embodiments, other bus widths may be used. One embodiment of the analog data path 605 is shown in FIG.

  The analog I / O data path 605 shown in FIG. 7 includes an I / 0 pad 701 including a unity gain amplifier 703. The amplifier 703 provides one amplification constant for improving the signal strength of the input analog voltage. In one embodiment, amplifier block 703 is bi-directional with respect to the enable voltage from the memory array to output I / O pad 701.

  FIG. 8 shows an analog data cache circuit connected to the analog I / O path 605 shown in FIG. In one embodiment, the data cache circuit is considered to be part of the analog data path 605 shown in FIG.

  The analog data cache circuit includes a read circuit 800, a verify circuit 801, and a reference circuit 802. The circuit shown in FIG. 8 is illustrated as the data cache function being achieved in many different ways.

The readout circuit is configured to include a voltage storage device 806 that constitutes the sample and hold portion of the circuit. In the illustrated embodiment, a capacitor 806 that stores a voltage is used. In alternative embodiments, other types of capacitive elements, or some other voltage storage means can be used. Capacitor 806 is connected to the selected word line ramp voltage via switch 804. The switch is controlled by a control signal from a sense amplifier circuit. During processing, the selected word line ramp voltage increases until it reaches V _t which turns on the selected memory cell. While the voltage is being ramped, the switch is normally closed so that the voltage stored in capacitor 806 increases with the input voltage. When the lamp voltage reaches V _t in the selected memory cell, current begins to flow through the bit line. A sense amplifier detects the current and generates a control signal to open switch 804. Opening the switch 804 causes the capacitor 806 to store the V _t level at which current flow has started. This is the threshold voltage at which the selected memory cell is programmed at that time.

The stored threshold voltage is output via the NMOS transistor 805 connected to the power source 807 via the source connection of the transistor 805. The drain connection of transistor 805 is connected to supply voltage _Vcc .

NMOS transistor 805 is connected to the I / 0 node of the memory device (ie, the I / 0 line) via output switch 808 in a source follower configuration to drive the stored threshold voltage. The output switch 808 is normally opened to disconnect the connection from the I / 0 line to the readout circuit 800. During this period, the I / 0 switch 820 is closed to discharge the I / 0 line to ground so that any voltage applied to the line is started at 0V. After V _t of the selected cell is stored in capacitor 806, output switch 808 is closed and I / O switch 820 is opened to connect NMOS transistor 805 to the I / 0 line. A power supply 821 in the I / 0 line increases the drive current in the line.

The output of read circuit 800 cannot be equal to V _t stored in capacitor 804. Since the V _t is applied to the gate of the NMOS transistor 805, the source of the transistor 805, 1.30 V is the gate of the transistor 805 - if the source voltage drop _{V t} is increased to 1.30 V. That is, when V _t is 1.0 V, the readout circuit next outputs 0.30 V as the readout V _t .

In one embodiment shown in FIG. 8, a reference circuit 802 is used. The reference circuit 802 includes a switch, a storage capacitor 826, and the source follower configuration with the power supply 827 in the source-connected NMOS transistors 825, _{V t} is the input switch 824 are stored in the capacitor 826 is controlled by the sense amplifier control signal It is substantially similar to readout circuit 800 in that it includes an output switch 828 that is open until it is opened.

Reference circuit 802 operates by the memory controller sending a command to the voltage source to store the target V _t of the selected memory cell in capacitor 826 of reference circuit 802. Input switch 824 is then opened by the controller to include target V _t at capacitor 826. Reference circuit 802 then sends this value to the I / 0 line via output switch 828. As described above, the I / 0 line is first discharged by the discharge switch 820 so that the output voltage starts at 0V. The memory controller now senses the actual V _t stored in the reference circuit 802 even if the same voltage drop is present across the transistor 825 as in the readout circuit 800. When the output of the reference circuit 802 is read from the I / 0 line by the memory controller, the controller detects the value of V _t corresponding to the voltage read from the I / 0 line. Therefore, when the controller reads this same voltage during the period that the read circuit 800 is driving that voltage on the I / 0 line, it senses V _t stored in the read circuit capacitor 806. .

  The output of the read circuit 800 and the output of the reference circuit 802 may be alternately connected to the I / 0 line by the memory controller during each read cycle. The controller alternately performs a closing operation on the output switch 808 of the circuit 800 and the output switch 828 of the circuit 802 to add the desired output to the I / 0 line. The I / 0 line is connected to the unity gain amplifier 703 shown in FIG.

Reference circuit have the added advantage of correcting the readout circuit V _t to temperature changes. Since it is known that the output voltage of the reference circuit changes in a manner similar to the readout circuit output and the value of V _t stored in the reference circuit, the memory controller reads out by a conversion table stored in the memory. The actual V _t stored in the circuit can be determined.

  The verify circuit 801 includes a comparator function 815 comprising an operational amplifier configured as a comparator 815 in one embodiment. The comparator circuit 815 compares the output voltage from the reading circuit 800 with the output voltage from the verify circuit 801. Comparator circuit 815 then outputs an INHIBIT signal when the two signals are substantially equal. The INHIBIT signal is used to suppress programming of the memory cell that has reached its own threshold voltage.

  During processing in the circuit, the analog voltage programmed into the cell is read in the sample / hold circuit. This is accomplished by closing switch S1 810 so that the received data is sampled by C1 811. Next, S1 810 is opened and C1 811 now holds the target data.

The selected cell is then programmed as described below. Each programming pulse to accommodate the selected cell changes the V _t to a predetermined threshold voltage interval. A read and verify process is performed during each programming pulse to determine if V _t has reached the target voltage.

The verify process includes storing the target V _t in a data storage device, such as the capacitor 811 of the verify circuit 801. This is during the verify process, or a capacitor 826 in the reference circuit 802 can be achieved at the same time as when programmed to the target V _t. After verify capacitor 811 is programmed, input switch 810 is opened to store the voltage at capacitor 811. Next, a read process is executed.

As described above, until V _t reaches a predetermined value and is stored in capacitor 806, the readout process includes representing a ramp voltage that adapts to the input of readout circuit 800. The output of the source follower transistor 805 is then used as the input of the comparator circuit 815. If the cell V _t is smaller than the target V _t is INHIBIT signal suggests that the cell requires additional programming pulse (e.g., a logic low signal). The programming sequence described above is then repeated. If cell V _t is greater than or substantially equal to target V _t , the INHIBIT signal indicates that the cell does not require further program pulses (eg, a logic high signal). The cell is then “inhibited”.

  A “suppressed” state is indicated when the output of the source follower transistor 805 of the read circuit is at least equal to the output of the source follower transistor 812 of the verify circuit 801. At this point, the comparator circuit 815 outputs an INHIBIT signal. In one embodiment, the INHIBIT signal is logically 1. The INHIBIT signal is used to activate the suppression function.

The suppression function is accomplished using a variety of methods that respond to circuitry that receives the INHIBIT signal. For example, the bias of a bit line can be changed from a program enable voltage of 0V to V _cc that is used during the programming process to inhibit programming of memory cells connected to that particular bit line. The bit line voltage can also be varied between 0V and _Vcc to slow down programming instead of completely suppressing programming.

  The representation of the analog ramp voltage for the above-described embodiments can be an adjusted version of the selected word line ramp voltage. The adjustment process reduces the voltage range (eg, divides the selected word line ramp voltage by 5), level shifting (eg, shifts the selected word line ramp voltage displacement from -2V to + 3V from + 2V to + 3V). Including) and buffering.

  One embodiment of the processing in the circuit shown in FIG. 6 is shown in the flowchart of FIG. At 900 where programming is initiated, an address is received by the memory device and the method begins. The controller then stores the analog voltage 901 in the analog data path associated with the start address. This analog voltage is the voltage that is written to the memory cell that is currently associated with the analog data path. The associated memory cell is indicated by the selected memory cell at the intersection of the word line and the associated bit line.

  As described above, the analog voltage written in the selected memory cell indicates a multiple bit pattern stored in the selected memory cell. This bit pattern can be two or more bits, each bit pattern being represented by a different threshold voltage. In another embodiment, only a single bit in each memory cell is stored.

  The data path currently associated with the current memory cell address is then checked to see if it is the last data path for programming 902. The final data path is determined by the memory controller in the length command (measured from the starting address), in the final address command indicating the last data path for the programmed memory page or block, or in the final for programming Can be shown in some other means of determining the analog data path.

  If the programmed data path is not the final data path (902), programming is clocked or incremented (920) to the next data path in the page or block. Next, the next data path is programmed to an analog voltage and the process is repeated until the final data path arrives (902).

  Since all of the desired analog data paths are programmed into their respective memory cells, once read at the appropriate analog voltage (ie, data), the voltage is then transferred to each memory cell. This is achieved through a memory cell programming / verify process.

  A target voltage indicating a desired analog voltage (ie, target data) to be programmed into the selected memory cell is stored in a part of the verify circuit of the sample / hold circuit (903). In an alternative embodiment, a reference circuit is also programmed into this data. Next, an initial programming pulse is generated to bias the word line connected to the control gate of the selected memory cell 904.

During a normal programming process, selected cells are biased by a series of increasing programming pulses. The memory cell typically starts the programming process in an erased state with a negative threshold voltage. Each programming pulse increases the threshold voltage V _t of the memory cell, a predetermined voltage corresponding to the programming voltage pulse level.

  The verify process described above is then performed on the selected memory cell (905) to determine whether the target threshold voltage has been programmed (911). The verify process determines whether the threshold voltage of the selected cell is greater than or equal to the stored target voltage.

  As described above, the verify process includes biasing the word line at the ramp voltage until the memory cell begins to conduct and generate current in the bit line. Once the current detection circuit detects the current in the bit line, it stores the current ramped read voltage, a control signal that instructs the sample / hold circuit, or the current ramped read voltage that turns the cell on. Generate a display of. The stored target analog voltage is compared with the sample and hold voltage from the ramped read voltage to determine whether the selected memory cell has been programmed with a target threshold voltage (911). In other words, the selected cell is verified to determine whether the target data has been programmed.

  If the selected memory cell is programmed (911), further programming in the selected cell is suppressed (915). Bit line suppression is accomplished using the method described above or some other suppression method.

  If the selected memory cell has not yet reached the target threshold voltage (911), the programming voltage is increased (913). Next, another programming pulse at the increased programming voltage is generated and the process is repeated until the threshold voltage of the selected cell is substantially equal to the programmed stored analog voltage. In order to determine that the selected cell has reached the programmed voltage, the threshold voltage of the selected cell may not be exactly equal to the desired analog voltage. The cell may be above or below the programmed voltage by hundreds or thousands of volts, and still be determined to be the programmed voltage.

CONCLUSION One or more embodiments in the present disclosure provide an analog I / O data interface with a memory device adapted to store an analog voltage indicative of a digital bit pattern. One such analog I / O data interface consists of a plurality of analog data paths with storage and comparison functions, stores a target voltage for each bit line, and in each programmed cell The threshold voltage is compared with the stored target voltage. The data path then suppresses further programming once the target voltage reaches a predetermined value.

  Although specific embodiments have been illustrated and described herein, it is understood by those skilled in the art that any arrangement calculated to achieve the same purpose may be substituted for that particular embodiment shown. Understood. Many adaptations in this disclosure will be apparent to those skilled in the art. This adaptation is therefore intended to cover any application or variation in this disclosure.

Claims (19)

An analog input / output data interface that interfaces between a controller circuit (310) and a memory device (301) having a memory array (200), the interface comprising:
An analog interface (305) for connecting the memory device and the controller circuit;
An analog data cache (602) for connecting the analog interface and the memory array to store an analog signal (450) indicating data, the analog interface and the analog data cache comprising: An interface for receiving the analog signal from the controller circuit for storage in the memory array;   The interface according to claim 1, wherein the analog signal is a voltage indicating a digital bit pattern.   The interface of claim 1, wherein the analog data cache comprises a capacitive element (806) for storing the analog signal.   The interface of claim 1, wherein the analog interface comprises an amplifier (703) having unity gain.   The amplifier is a bidirectional amplifier for enabling output of an amplified output signal from the memory array, and the amplified output signal is an analog voltage indicating a digital bit pattern stored in a selected memory cell. The interface according to claim 4. A plurality of memory cells (2) organized in a column (206) connected to a bit line (204)
00) a memory array (104),
A memory device (101) comprising an analog input / output data interface (305) connected to the memory array,
The interface comprises a plurality of storage elements (806) for storing analog signals (450) input to the memory device, each programmed into a selected memory cell in the memory array. A memory device (101) comprising an analog data path (602).   The analog input / output data interface further includes a comparator circuit (815) for connecting the storage element and the selected memory cell, the comparator circuit including the stored analog signal input and the selection The device of claim 6, wherein the device is configured to compare (915) a programmed voltage in a programmed memory cell and generate a programmed indication.   The device of claim 7, further comprising a memory controller (310) configured to control programming of the selected memory cell in response to the analog signal input.   Each analog data path is connected to a different bit line, and each analog data path stores a first capacitive element (806) for storing an analog input signal input to the memory device and a target voltage. The device of claim 6, further comprising a second capacitive element (811) for performing.   The device of claim 9, wherein each analog data path further comprises a unity gain amplifier (703) for amplifying the target voltage before being stored in the second capacitive element.   The device of claim 8, wherein when the selected memory cell is programmed with a target voltage, the programmed indication includes a suppression signal used to suppress programming of the selected memory cell. . The memory controller suppresses programming of the selected memory cell in response to the suppression signal by biasing a bit line connected to the selected memory cell having V _cc (915). The device of claim 11, wherein the device is adapted to: A method for operating a memory device (101) having a plurality of analog data paths (602) connected to a memory array (104), the method comprising:
Storing an analog data signal (450) in at least one analog data path of the plurality of data paths (901);
Biasing a word line (202) of the memory array with a bias voltage to program a memory cell selected by the analog data signal;
Biasing the bit line (204) to enable programming of the selected memory cell;
Verifying a program voltage at which the selected memory cell is programmed (905);
Suppressing programming when the program voltage is greater than or equal to a target voltage indicative of the analog data signal (915).   The step of suppressing programming includes the step of comparing the program voltage with a target voltage (911) and the step of generating a suppression signal when the program voltage is equal to or higher than the target voltage (915). The method according to claim 13.   Increasing the bias voltage in the selected memory cell if the program voltage is less than the target voltage (913), and the selected until the program voltage is greater than or equal to the target voltage; 15. The method of claim 14, further comprising continuing (904) programming of the memory cell.   The step of storing the analog data signal amplifies the analog data signal by an amplifier (703) having a unity gain prior to the step of storing the analog data signal in the capacitive element (806) of the analog data path. 14. The method of claim 13, comprising the step of:   Storing the analog data signal includes receiving a start address in a first analog data path of the plurality of data paths (900), and increasing through the plurality of analog data paths (920); Storing the analog data signal in each of the plurality of analog data paths (901).   The method of claim 13, wherein the plurality of analog data paths are connected to the bit lines in a page of memory cells.   The method of claim 13, wherein the plurality of analog data paths are connected to the bit lines in a block of memory cells.