JP2011517003A5 - - Google Patents

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Publication number
JP2011517003A5
JP2011517003A5 JP2011505052A JP2011505052A JP2011517003A5 JP 2011517003 A5 JP2011517003 A5 JP 2011517003A5 JP 2011505052 A JP2011505052 A JP 2011505052A JP 2011505052 A JP2011505052 A JP 2011505052A JP 2011517003 A5 JP2011517003 A5 JP 2011517003A5
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JP
Japan
Prior art keywords
processor core
packet
information
partition
consistency
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Application number
JP2011505052A
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English (en)
Japanese (ja)
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JP2011517003A (ja
JP5419107B2 (ja
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Priority claimed from US12/103,250 external-priority patent/US7941637B2/en
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Publication of JP2011517003A publication Critical patent/JP2011517003A/ja
Publication of JP2011517003A5 publication Critical patent/JP2011517003A5/ja
Application granted granted Critical
Publication of JP5419107B2 publication Critical patent/JP5419107B2/ja
Active legal-status Critical Current
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JP2011505052A 2008-04-15 2009-02-16 マルチコア処理システム Active JP5419107B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/103,250 US7941637B2 (en) 2008-04-15 2008-04-15 Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
US12/103,250 2008-04-15
PCT/US2009/034189 WO2009128981A1 (en) 2008-04-15 2009-02-16 Multi-core processing system

Publications (3)

Publication Number Publication Date
JP2011517003A JP2011517003A (ja) 2011-05-26
JP2011517003A5 true JP2011517003A5 (enExample) 2012-04-05
JP5419107B2 JP5419107B2 (ja) 2014-02-19

Family

ID=41164943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011505052A Active JP5419107B2 (ja) 2008-04-15 2009-02-16 マルチコア処理システム

Country Status (6)

Country Link
US (2) US7941637B2 (enExample)
JP (1) JP5419107B2 (enExample)
KR (1) KR20110000741A (enExample)
CN (1) CN101999115B (enExample)
TW (1) TW200945048A (enExample)
WO (1) WO2009128981A1 (enExample)

Families Citing this family (15)

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US8547971B1 (en) 2009-01-07 2013-10-01 Marvell Israel (M.I.S.L) Ltd. Multi-stage switching system
US8358651B1 (en) 2009-09-21 2013-01-22 Marvell International Ltd. Switch device having a plurality of processing cores
US9460038B2 (en) * 2010-12-22 2016-10-04 Via Technologies, Inc. Multi-core microprocessor internal bypass bus
US9172659B1 (en) 2011-07-12 2015-10-27 Marvell Israel (M.I.S.L.) Ltd. Network traffic routing in a modular switching device
US9372724B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9372723B2 (en) * 2014-04-01 2016-06-21 Freescale Semiconductor, Inc. System and method for conditional task switching during ordering scope transitions
US9733981B2 (en) 2014-06-10 2017-08-15 Nxp Usa, Inc. System and method for conditional task switching during ordering scope transitions
US9448741B2 (en) 2014-09-24 2016-09-20 Freescale Semiconductor, Inc. Piggy-back snoops for non-coherent memory transactions within distributed processing systems
US11449452B2 (en) 2015-05-21 2022-09-20 Goldman Sachs & Co. LLC General-purpose parallel computing architecture
EP3298486B1 (en) * 2015-05-21 2022-08-24 Goldman, Sachs & Co. LLC General-purpose parallel computing architecture
US10904150B1 (en) 2016-02-02 2021-01-26 Marvell Israel (M.I.S.L) Ltd. Distributed dynamic load balancing in network systems
US10866753B2 (en) * 2018-04-03 2020-12-15 Xilinx, Inc. Data processing engine arrangement in a device
CN112948282A (zh) * 2019-12-31 2021-06-11 北京忆芯科技有限公司 用于数据快速查找的计算加速系统
WO2022047403A1 (en) * 2020-08-31 2022-03-03 Zidan Mohammed Memory processing unit architectures and configurations
US12086066B1 (en) * 2023-03-15 2024-09-10 Cornami, Inc. Cache architecture for a massively parallel processing array

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JPH07104923B2 (ja) * 1988-12-28 1995-11-13 工業技術院長 並列画像表示処理方法
US6678773B2 (en) 2000-01-13 2004-01-13 Motorola, Inc. Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system
US7106742B1 (en) 2000-01-13 2006-09-12 Mercury Computer Systems, Inc. Method and system for link fabric error detection and message flow control
US6754752B2 (en) 2000-01-13 2004-06-22 Freescale Semiconductor, Inc. Multiple memory coherence groups in a single system and method therefor
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US6862283B2 (en) 2000-01-13 2005-03-01 Freescale Semiconductor, Inc. Method and apparatus for maintaining packet ordering with error recovery among multiple outstanding packets between two devices
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CN1320464C (zh) * 2003-10-23 2007-06-06 英特尔公司 用于维持共享高速缓存一致性的方法和设备
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