JP2011259622A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce surge and noise in a semiconductor device having a semiconductor element that penetrates a substrate to be fixed to the substrate.SOLUTION: On the surface of a substrate B, capacitors C1, C2 and Ca and switching elements S1 and S2 are mounted, and a wiring W1 for connecting a drain terminal Td1 of the switching element S1 and the one-ends of the capacitors C1 and Ca with an output terminal To, and a wiring W2 for connecting a source terminal Ts2 of the switching element S2 and the other ends of the capacitors C1, C2 and Ca with a ground terminal GND, are formed. In the wiring W2, a via VA1 that penetrates from the surface to the rear surface of the substrate B to electrically connect the surface and the rear surface of the substrate B with each other is formed in the vicinity of the other end of the capacitor Ca. On the rear surface of the substrate B, a wiring W5 that includes the formation point of the via VA1 as one end and the source terminal Ts2 of the switching element S2 as the other end, is formed so as to bypass an insulating region formed around the terminals of the switching elements S1 and S2.

Description

  The present invention relates to a semiconductor device in which a semiconductor element is provided on a substrate.

  Conventionally, as shown in FIG. 9A, a boost chopper device 101 including a reactor L1, a capacitor C1, and switch elements S1 and S2 is known. Reactor L1 has one end connected to DC power supply V1, the other end connected to output terminal To via switch element S1, and grounded via switch element S2. The capacitor C1 has one end connected to the output terminal To and the other end grounded. The switch elements S1 and S2 are constituted by MOSFETs.

  In the step-up chopper device 101 configured as described above, the switch element S1 and the switch element S2 can be alternately turned on / off to generate a voltage higher than the power supply voltage at the output terminal To. That is, when the switch element S2 is first turned on, magnetic energy is accumulated in the reactor L1. Thereafter, when the switch element S2 is turned off, the magnetic energy stored in the reactor L1 increases the voltage at the connection point between the reactor L1 and the switch element S2, and charges are stored in the capacitor C1. By repeating this operation, the voltage at the output terminal To (hereinafter also referred to as output voltage) increases.

  The capacitor C1 has a large capacitance in order to sufficiently suppress the ripple of the output voltage. Thereby, since the physique of capacitor C1 becomes large, capacitor C1 is arranged away from switch elements S1 and S2. For this reason, the inductance component La parasitic on the wiring between the switch element S1 and the capacitor C1 increases.

  By the way, a film capacitor or an electrolytic capacitor is generally used as a capacitor having a large capacitance. It is known that these capacitors have a larger inductance component Lc parasitic to the capacitor terminal and the capacitor internal electrode as the capacitance increases. That is, if the smoothing ability of the output voltage is emphasized and a capacitor having a large capacitance is used as the smoothing capacitor, the parasitic inductance components La and Lc increase.

The following two problems occur due to the increase of the parasitic inductance components La and Lc.
The first problem is that a surge voltage exceeding the voltage rating of the switch elements S1 and S2 is generated when the switch element S2 is turned off and on, and the switch elements S1 and S2 are destroyed.

That is, when the switch element S2 is turned off, the reactor current I _L flowing in the switch element S2 when the switch element S2 is turned on is instantaneously commutated to the switch element S1. For this reason, as shown in FIG. 9B, the time gradient (dI / dt) _{1 of the} current I flowing through the parallel diode D1 of the switch element S1 (hereinafter referred to as current gradient (dI / dt) ₁ ) becomes larger. FIG. 9B is a diagram illustrating a current flowing through the connection point T1 between the switch element S2 and the parasitic inductance component La in FIG. 9A when the switch element S2 is turned off and turned on.

Since the fluctuation component Irip of the current I flowing through the parallel diode Da flows through the capacitor C1, the fluctuation component Irip of the current I passes through the parasitic inductance components La and Lc. Therefore, a large current gradient (dI / dt) ₁ generated when the switch element S2 is turned off is applied to the parasitic inductance components La and Lc. Thereby, resonance occurs between the parasitic capacitance of the switching element S2 and the parasitic inductance components La and Lc. For this reason, as shown in FIG. 10A, a voltage fluctuation occurs at the connection point T1, and a surge voltage V _S1 represented by the following expression (1) is generated as a maximum value of the voltage fluctuation. FIG. 10A is a diagram showing fluctuations in voltage and current at the connection point T1 due to turn-off of the switch element S2.

The same problem occurs when the switch element S2 is turned on. Since the time gradient (dI / dt) ₂ (hereinafter referred to as current gradient (dI / dt) ₂ ) of the current I flowing through the parallel diode D1 of the switch element S1 at the time of turn-on becomes a negative value (see FIG. 9B). As shown in FIG. 10B, at the moment of turn-on, the voltage at the connection point T1 swings to the negative side with the amplitude V ′ _S2 expressed by the following equation (2), and then the parasitic of the switch element S2 Resonance occurs between the capacitance and the parasitic inductance component La. For this reason, voltage fluctuation occurs at the connection point T1, and a surge voltage V _S2 represented by the following equation (2) is generated as the maximum value of the voltage fluctuation. FIG. 10B is a diagram showing changes in voltage and current at the connection point T1 due to turn-on of the switch element S2.

The second problem is that the voltage fluctuation generated at the connection point T1 due to the current gradient (dI / dt) ₁ and the current gradient (dI / dt) ₂ appears at the output terminal To, and noise is generated in the output voltage. The quality of the voltage is reduced.

Even if a capacitor having a capacitance capable of sufficiently smoothing the surge at the connection point T1 is used as the capacitor C1, voltage fluctuations at the connection point T1 are divided by the parasitic inductance components La and Lc. The maximum values V _n1 and V _n2 of the noise voltage appearing at To are expressed by the following equations (3) and (4).

That is, the maximum values V _n1 and V _{n2 of the} noise voltage appearing at the output terminal To increase due to the increase of the parasitic inductance component Lc, and the quality of the output voltage decreases.

  As described above, when the capacitance of the capacitor C1 is increased in order to ensure the smoothing ability of the output voltage, there arises a problem that the surge voltage appearing at the connection point T1 and the noise voltage appearing at the output terminal To increase.

  In order to solve such a problem, as shown in FIG. 11A, a surface mount capacitor Ca having a capacitance smaller than that of the capacitor C1 is arranged in parallel so as to be closer to the switch element S1 than the capacitor C1. A technique is known in which a loop line RL11 formed of switch elements S1, S2 and a capacitor Ca is arranged to face each other through an insulating layer (see, for example, Patent Document 1).

Since the current gradients (dI / dt) ₁ and (dI / dt) ₂ at the time of turn-off and turn-on of the switch element S2 are instantaneously generated, the electric current flowing through the current at this moment is small. For this reason, even if the capacitance of the capacitor Ca is small, the surge current can be absorbed. Since the output current ripple other than this moment is absorbed by the capacitor C1, the voltage smoothing capability of the output voltage can be ensured by using a capacitor having a capacitance that can sufficiently absorb the current ripple as the capacitor C1. .

Furthermore, the parasitic inductance component Lc is reduced by using a surface-mounted capacitor (for example, a multilayer ceramic capacitor) having a small parasitic inductance as the capacitor Ca. Further, the parasitic inductance component La is reduced by the lines opposed via the insulating layer. Since the surge voltages V _S1 and V _S2 generated at the connection point T1 when the switch element S2 is turned off and turned on are expressed by the above equations (1) and (2), the parasitic inductance components La and Lc are reduced. Surge voltage can be reduced.

In addition to the parasitic inductance components La and Lc, the voltage generated at the connection point T1 is divided by the inductance component Lb parasitic on the wiring between the capacitor Ca and the capacitor C1 and the parasitic inductance component Ld of the capacitor C1. Therefore, the maximum values V _n1 and V _n2 of the noise voltage appearing at the output terminal To at turn-on and turn-off are expressed by the following equations (5) and (6).

In addition, the symbol “//” in the equations (5) and (6) is a symbol representing the parallel connection of impedance, and is defined by the following equation (7).

Here, when the factor g commonly applied to the equations (5) and (6) is defined by the following equation (8), the equations (5) and (6) are represented by the following equations (9) and (10).

Then, when the factor g represented by the equation (8) is expanded, the following equation (11) is obtained.

Here, since the capacitance of the capacitor C1 is large, the parasitic inductance components Lb and Ld are sufficiently larger than the parasitic inductance components La and Lc for the above-described reason, and the relationship expressed by the following expression (12) is established.

Then, when the above equation (12) is applied to the above equation (11), the following equation (13) is obtained.

Therefore, the maximum values V _n1 and V _n2 of the noise voltage appearing at the output terminal To at turn-on and turn-off are expressed by the following equations (14) and (15).

As shown in the above equations (14) and (15), the noise voltage can be reduced by reducing the parasitic inductance component Lc, and the noise voltage can be reduced by making the parasitic inductance component Lb sufficiently larger than the parasitic inductance component Ld. It can be further reduced.

  And in the technique of the said patent document 1, while arrange | positioning the circuit shown to Fig.11 (a) on a metal base board through an insulating layer, loop line RL11 as shown to Fig.11 (a) is metal. The parasitic inductance component La is reduced by forming the loop line RL11 so as to face the circuit through the base plate. Further, the parasitic inductance component Lc is reduced by using a surface mount component for the capacitor Ca. Further, the parasitic inductance component Lb is increased by disposing the capacitor C1 outside the metal base plate. As a result, a great reduction effect can be obtained for both the surge voltage and the noise voltage.

JP 2007-318911 A

  By the way, in the technique described in Patent Document 1, it is necessary to form the loop line RL11 so as to face the circuit with the insulating layer interposed therebetween. For this reason, the semiconductor elements used as the switch elements S1 and S2 must be mounted on the substrate surface.

  However, in a semiconductor element for a chopper circuit that converts relatively large electric power, it is necessary to dissipate heat generated in the element using a heat sink. For this reason, it is difficult to use a surface-mount package in which it is difficult to attach a heat sink.

  That is, as shown in FIG. 11B, as the semiconductor element SD for bonding to the heat sink HS, a package is used that is fixed in a form standing upright on the substrate surface by a leg that penetrates the substrate B. In this way, in the semiconductor element SD having the legs penetrating the substrate, it is necessary to ensure the insulation around the legs connected to the substrate surface, and therefore it is not possible to form the opposing line directly under the semiconductor element SD. There was a problem that surge and noise could not be reduced.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a technique for reducing surge and noise in a semiconductor device including a semiconductor element that penetrates and is fixed to a substrate.

  The semiconductor device according to claim 1, which has been made to achieve the above object, is a semiconductor device in which a semiconductor element is provided on a substrate, and includes a first terminal installed through the substrate, a first terminal, Having a second terminal different from each other, and a first semiconductor switching element that switches between the first terminal and the second terminal in an electrically insulated state or an electrically conductive state, A third terminal that is electrically connected to the two terminals, and a fourth terminal that is connected to the ground and that is installed through the substrate, and is electrically connected between the third terminal and the fourth terminal. A second semiconductor switching element that switches to one of an insulated state and an electrically conductive state, and a first capacitor having one end connected to the first terminal and the other end connected to the fourth terminal. .

  And about the surface mount type 2nd capacitor whose electrostatic capacity is smaller than the 1st capacitor, the one end is connected to the 1st terminal, and the other end is connected to the 4th terminal. Furthermore, the first current path from the first terminal to the fourth terminal through the second capacitor is more than the second current path from the first terminal to the fourth terminal through the first capacitor. And it forms so that it may become near from the 2nd semiconductor switch element.

  A current gradient is instantaneously generated by the switching operation of the first semiconductor switch element and the second semiconductor switch element. However, since the electric current that flows at this moment is small, the surge current can be absorbed by the surface mount type second capacitor having a small capacitance. Furthermore, since the output current ripple other than this moment is absorbed by the first capacitor, the voltage smoothing capability can be ensured by using a capacitor having a capacitance that can sufficiently absorb the current ripple as the first capacitor.

  Further, since the surface mount type capacitor having a small parasitic inductance is used as the second capacitor, the parasitic inductance component of the second capacitor can be reduced, and the surge current and noise can be reduced.

  On the first current path, vias that penetrate the substrate and electrically connect the front surface side and the back surface side of the substrate are provided, and the substrate has a side opposite to the surface on which the first current path is formed. A third current path from the via to the first terminal or the fourth terminal is formed on the surface so as to surround the insulating regions around the first semiconductor switch element and the second semiconductor switch element.

  Thereby, in the current path from the first terminal to the fourth terminal, a parallel wiring constituted by the first current path and the third current path is obtained. For this reason, for example, if the wiring inductance by the first current path is equal to the wiring inductance by the third current path, the second capacitor passes through the second capacitor as compared with the case of only the first current path without the third current path. The wiring inductance of the current path can be halved.

  Therefore, the wiring inductance of the current path passing through the second capacitor can be reduced without mounting the first semiconductor switch element and the second semiconductor switch element on the substrate surface, and the surge current can be further reduced.

  Further, in the semiconductor device according to claim 1, as described in claim 2, at least a part of the third current path is opposed to the first current path with the substrate interposed therebetween, and is also opposed to the third current path. In the above, it is preferable that the first current path and the third current path are formed in opposite directions in which the current flows.

  According to the semiconductor device configured as described above, in the region where the first current path and the third current path face each other, the current flows so as to cancel the magnetic field. Therefore, the current passing through the second capacitor in the facing region The wiring inductance of the path can be reduced.

  Also, in the semiconductor device according to claim 1 or 2, as described in claim 3, the semiconductor device is surrounded by a first loop wiring formed through the first capacitor and the second capacitor on the surface of the substrate. The area of the region to be formed is larger than the area of the region surrounded by the second loop wiring formed through the first current path and the third current path on the surface of the substrate, and the surface on which the first loop wiring is formed In the wiring layers arranged above and below, it is preferable that no ground wiring exists in a region facing the first loop wiring.

  According to the semiconductor device configured as described above, the wiring inductance between the first capacitor and the second capacitor is sufficiently smaller than the wiring inductance of the current path passing through the second capacitor, so that the noise voltage can be reduced. Can do.

  Further, in the semiconductor device according to any one of claims 1 to 3, as described in claim 4, the first current path and the third current path are the first current path and the third current path. Are preferably formed so that there is a portion that is line-symmetric with respect to a straight line connecting the first terminal and the fourth terminal.

  According to the semiconductor device configured as described above, the first current path is increased as the number of portions in which the first current path and the third current path are symmetrical with respect to the straight line connecting the first terminal and the fourth terminal increases. And the third current path have a similar degree of wiring shape, and the difference between the wiring inductance by the first current path and the wiring inductance by the third current path can be reduced. If the wiring inductance due to the first current path and the wiring inductance due to the third current path can be made equal, the current path passing through the second capacitor compared to the case where there is no third current path and only the first current path is present. The wiring inductance can be halved.

  Further, in the semiconductor device according to any one of claims 1 to 4, as described in claim 5, the voltage at the third terminal associated with turn-off and turn-on of the second semiconductor switch element is a maximum voltage. The longer time of the time varying from 10% to 90% is Δt, the maximum current flowing through the first semiconductor switch element and the second semiconductor switch element during the operation of the second semiconductor switch element is Ip, and the first semiconductor switch element and Of the maximum ratings of the second semiconductor switch element, Vabs is the lower voltage, Vm is the maximum voltage applied to the first semiconductor switch element during operation of the second semiconductor switch element, and Ca is the capacitance of the second capacitor. The capacitance of the two capacitors may satisfy the following formula (36).

According to the semiconductor device configured as described above, the second capacitor can be charged with the electric charge caused by the instantaneous current due to the switching operation of the first semiconductor switch element and the second semiconductor switch element, and the voltage due to the instantaneous current can be sufficiently increased. It can be smoothed.

FIG. 2 is a circuit diagram including a wiring inductance of the boost chopper device 1 and a parasitic inductance of a capacitor, and a diagram showing a front surface wiring and a back surface wiring. It is a figure which shows the surface wiring and back surface wiring of the pressure | voltage rise chopper apparatus. It is a figure which shows typically the electric current path from terminal Td1 to terminal Ts2, and a figure which shows the equivalent structure of an electric current path. It is a figure which shows the electric current which flows through the connection point T1 at the time of turn-off and turn-on of switch element S2. It is a circuit diagram of the step-down chopper device 11, and a diagram showing a front surface wiring and a back surface wiring. FIG. 2 is a circuit diagram of a step-up / down converter device 21 and a diagram showing a front surface wiring and a back surface wiring. FIG. 4 is a circuit diagram of a motor inverter device 31 and a diagram showing a front surface wiring and a back surface wiring. It is a figure which shows the back surface wiring of another embodiment. It is a circuit diagram including the wiring inductance of the boost chopper device 101 and the parasitic inductance of the capacitor, and a diagram showing the current flowing through the connection point T1 when the switch element S2 is turned off and turned on. It is a figure which shows the fluctuation | variation of the voltage and electric current in the connection point T1 by the turn-off and turn-on of switch element S2. FIG. 6 is a circuit diagram showing a technique described in Patent Document 1, and a diagram showing a semiconductor element SD bonded to a heat sink HS.

(First embodiment)
A first embodiment of the present invention will be described below with reference to the drawings.
FIG. 1A is a circuit diagram showing a configuration of a boost chopper device 1 of the present embodiment. FIG. 1B is a diagram showing the surface wiring of the step-up chopper device 1. FIG. 1C is a diagram illustrating the backside wiring of the boost chopper device 1.

As shown in FIG. 1A, the boost chopper device 1 includes a reactor L1, capacitors C1, C2, Ca, and switch elements S1, S2.
The capacitor C1 has a large capacitance so that the power supply can be sufficiently smoothed. The capacitor Ca is a surface mount capacitor having a smaller capacitance than the capacitor C1. The switch elements S1 and S2 are N-channel field effect transistors.

  Among these, the switch element S1 has a drain connected to the output terminal To and a source connected to the drain of the switch element S2. The switch element S2 has a drain connected to the source of the switch element S1 and a source grounded.

  The capacitor Ca has one end connected to a connection point between the capacitor C1 and the switch element S1, and the other end grounded. The capacitor C1 has one end connected to a connection point between the output terminal To and the capacitor Ca and the other end grounded.

Reactor L1 has one end connected to DC power supply V1 and the other end connected to a connection point between switch element S1 and switch element S2.
Capacitor C2 has one end connected to the connection point between DC power supply V1 and reactor L1, and the other end grounded.

  In the step-up chopper device 1 configured as described above, the switch element S1 and the switch element S2 can be alternately turned on / off to generate a voltage higher than the power supply voltage at the output terminal To. That is, when the switch element S2 is first turned on, magnetic energy is accumulated in the reactor L1. Thereafter, when the switch element S2 is turned off, the magnetic energy stored in the reactor L1 increases the voltage at the connection point between the reactor L1 and the switch element S2, and charges are stored in the capacitor C1. By repeating this operation, the voltage at the output terminal To (hereinafter also referred to as output voltage) increases.

  As shown in FIG. 1B, capacitors C1, C2, Ca and switch elements S1, S2 are mounted on the surface of the substrate B on which components of the boost chopper device 1 are mounted, and input terminals Ti and outputs are mounted. A terminal To and a ground terminal GND are provided.

  Further, on the surface of the substrate B, the drain terminal Td1 of the switch element S1 and the wiring W1 for connecting one end of the capacitors C1 and Ca to the output terminal To, the source terminal Ts2 of the switch element S2 and the capacitors C1, C2, A wiring W2 for connecting the other end of Ca to the ground terminal GND, a wiring W3 for connecting the source terminal Ts1 of the switch element S1 to the drain terminal Td2 of the switch element S2, an input terminal Ti and one end of the capacitor C2 And a wiring W4 for connecting the two. The switch elements S1, S2 are turned on / off by applying a voltage to the gate terminals Tg1, Tg2, respectively.

  Further, in the wiring W2, a via VA1 that penetrates from the front surface to the back surface of the substrate B and electrically connects the front surface and the back surface of the substrate B is formed near the other end of the capacitor Ca. In addition, a connection terminal TL for connecting to the end of the reactor L1 is provided in the wirings W3 and W4. That is, by connecting one end of the reactor L1 to the connection terminal TL of the wiring W3 and connecting the other end of the reactor L1 to the connection terminal TL of the wiring W4, the wiring W3 and the wiring W4 are electrically connected via the reactor L1. Connected.

  Then, as shown in FIG. 1C, on the back surface of the substrate B, the via VA1 is formed at one end and the source terminal Ts2 of the switch element S2 is formed at the other end around the terminals of the switch elements S1 and S2. Wiring W5 provided so as to bypass the insulating region to be formed is formed. A heat sink HS is disposed so as to face the switch elements S1 and S2.

The following lines F1, F2, and F3 are formed by the wirings W1, W2, W3, and W5.
FIG. 2A is a diagram showing the surface wiring of the step-up chopper device 1 excluding the reactor L1, the capacitor C2, and the DC power source V1. FIG. 2B is a diagram showing the backside wiring of the boost chopper device 1 shown in FIG.

  First, the line F1 is a path on the wiring W1 from the drain terminal Td1 of the switch element S1 to one end of the capacitor Ca, as shown in FIG. In order to make the line F1 as short as possible, one end of the capacitor Ca is arranged in the vicinity of the drain terminal Td1 of the switch element S1.

  The line F2 is a path on the wiring W2 from the other end of the capacitor Ca to the source terminal Ts2 of the switch element S2. The shape of the wiring W2 is determined so that the line F2 is the shortest within a range in which the insulation between the wiring W2 and the switch elements S1 and S2 can be ensured.

  The line F3 is a path on the wiring W5 from the via VA1 to the source terminal Ts2 of the switch element S2. The shapes of the wirings W1, W2, and W5 are determined so that the line F1 and the line F3 are substantially symmetric with respect to the insulating region formed around the terminals of the switch elements S1 and S2.

  By forming the lines F1, F2, and F3 as described above, the instantaneous current formed by the current gradient generated at the drain terminal Td1 flows through the path of the drain terminal Td1, the line F1, the capacitor Ca, and the via VA1. , Flows from the via VA1 divided into the line F2 and the line F3.

FIG. 3A is a diagram schematically showing a current path from the drain terminal Td1 to the source terminal Ts2. FIG. 3B is a diagram showing an equivalent structure of the current path of FIG.
As shown in FIG. 3A, a route from the drain terminal Td1 to the via VA1 is a route R1, and a portion of the route from the via VA1 through the line F3 to the source terminal Ts2 that is opposed to the route R1 is a route R2, via VA1. A path from the line F2 to the source terminal Ts2 is defined as a path R3, and a path from the via VA1 through the line F3 to the source terminal Ts2 that does not face the path R1 is defined as a path R4.

Further, the current flowing clockwise is positive, the current value flowing through the path R1 is I ₁ (= I), the current value flowing through the path R2 is I ₂ , the current value flowing through the path R3 is I ₃ , and the path R4 is The value of the flowing current is I ₄ .

  Here, considering the current flowing through the wiring when an instantaneous current time gradient (hereinafter referred to as current gradient) is applied when the switch element S2 is turned on / off, such instantaneous current passes through the capacitor C1. Almost no flow in the path. This is because the wiring inductance Lb (see FIG. 1) between the capacitor C1 and the capacitor Ca is large.

  Therefore, when it is approximated that all instantaneous currents flow through the paths R1, R2, R3, R4 and the path passing through the capacitor Ca, the relationship expressed by the following equation (16) is established.

Next, the vector potential A _{n (n} = 1,2,3,4) to create the current flowing through the line Rn (n = 1, 2, 3, 4), the current value I _{n (n} = 1 flowing through the line Rn , 2, 3, 4) and is represented by the following formula (17).

Further, the line is approximated by a line, and a line length parameter taken clockwise along the line from the drain terminal Td1 is x. Then, when the unit vector e (x) is taken clockwise along the line Rn at the point x on each line Rn, the current vector I _n (x) of the line Rn is expressed by the following equation (18). .

The energy E _n to be stored in the line due to the inductance parasitic on line Rn Rn has the formula (17), represented by the following formula (19) using (18).

Here, the line R1 and the line R2 are opposed to each other in a direction perpendicular to the substrate surface via an insulating layer. For this reason, the vector potentials cancel each other because currents having the same amount of current flow in opposite directions. Since A ₁ + A ₂ = 0 when I ₁ = −I ₂ , the coefficients α ₁ and α ₂ of the vector potential between the line R1 and the line R2 are expressed by the following equation (20).

Then, substituting equation (20) into equation (19) yields the following equation (21).

Here, since the line R1 and the line R2 are close to each other in the direction perpendicular to the substrate surface, the ranges of the line length parameters x of the line R1 and the line R2 are equal to each other.

  And the energy E in all the lines of line R1-R4 is represented by the following Formula (22) using Formula (21).

Here, if it is assumed that a current I ₃ flows through the line R13 obtained by connecting the line R1 and the line R3 and α ₁₃ is generated as a coefficient of the vector potential, the vector potential is a potential generated by each internal line Rn. Since it is the sum, the following equation (23) is established.

Then, substituting equation (23) into equation (22) yields the following equation (24).

At this time, when the self-inductance of the line R13 is L ₁₃ , the self-inductance of the line R4 is L ₄ , and the mutual inductance of the line R13 and the line R4 is M, the relationship expressed by the following equation (25) is established.

Then, substituting equation (25) into equation (24) yields the following equation (26).

Here, the line R13 and the line R4 are formed so as to be substantially symmetrical with each other so as to bypass the insulating regions formed around the terminals of the switch elements S1 and S2. For this reason, when the self-inductance L13 and the self-inductance L4 are substantially equal and the value of both is L, the following equation (27) is obtained.

Here, the currents I ₃ and I ₄ flow so as to minimize the energy E of all lines while satisfying the equation (16). For this reason, the currents I ₃ and I ₄ at which the energy E represented by the equation (27) is minimized are represented by the following equation (28).

Accordingly, the current paths shown in FIG. 3A are equivalently, as shown in FIG. 3B, a line R13 extending from the drain terminal Td1 to the source terminal Ts2, and a line R4 extending from the drain terminal Td1 to the source terminal Ts2. And a structure composed of That is, compared to the current path of only the conventional line R13 that is connected from the drain terminal Td1 to the source terminal Ts2 through the capacitor Ca in the shortest, the current is equally divided between the line R13 and the line R4. The induced voltage is reduced.

The wiring inductance La1 is a self-inductance L _13, the wiring inductance La2 is a self-inductance L _4. Since the line R13 and the line R4 are separated by the insulating region, it can be approximated that the mutual inductance M between the line R13 and the line R4 is sufficiently small. For this reason, as described above, the self-inductance L13 and the self-inductance L4 are substantially equal, and both values are L. Therefore, the combined inductance La of the wiring inductance La1 and the wiring inductance La2 is (L / 2).

Here, when the line R2 does not oppose the line R1 in the vertical direction, the line R4 becomes larger than the line R13 by the self-inductance of the line R1 and the line R2. However, by shortening the line R1 and the line R2, the self-inductance L ₁₃ and self-inductance L ₄ is equal substantially approximately. However, in order to further reduce the combined inductance of the wiring inductance La1 and the wiring inductance La2, it is desirable that the line R1 and the line R2 face each other in the vertical direction.

  Next, as shown in FIG. 2A, an area SL1 of a region surrounded by the loop line RL1 formed by the capacitors C1 and Ca and the wiring between the capacitors C1 and Ca is formed by the lines F2 and F3. Is larger than the area SL2 of the region surrounded by the loop line RL2. Further, no ground wiring layer is disposed above and below the loop line RL1.

  Here, it is generally known that the self-inductance of the loop line is proportional to the area of the region surrounded by the loop line. Therefore, the impedance (La1 + La2≈2L) of the line connecting the line 13 and the line R4 in series is proportional to the area SL2 of the loop line RL2. Therefore, the following equation (29) is obtained using the proportionality constant κ.

Here, as described above, since the combined inductance La of the wiring inductance La1 and the wiring inductance La2 can be approximated to (L / 2), the combined inductance La is expressed by the following equation (30).

Furthermore, as described above, since there is no ground wiring layer below the loop line RL1, the inductance Lb of the loop line RL1 is expressed by the following equation (31) using the same proportionality constant κ as the loop line RL2. The

Here, when Expression (30) is compared with Expression (31), even when the area SL1 of the loop line RL1 is equal to the area SL2 of the loop line RL2, the inductance Lb is four times the value of the inductance La. be able to. As described above, since the area SL1 is larger than the area SL2, Lb >> La can be realized, that is, the inductance Lb can be made sufficiently larger than the inductance La.

  Next, a method for setting the capacitance of the capacitor Ca will be described. FIG. 4 is a diagram illustrating a current flowing through a connection point T1 (see FIG. 1) between the switch element S1 and the parasitic inductances La1 and La2 when the switch element S2 is turned off and turned on.

  As shown in FIG. 4, when the switch element S2 is turned off and turned on, a high current gradient is instantaneously generated at the connection point T1. Such an instantaneous current flows to the capacitor Ca as described above, and the capacitor Ca is charged. Therefore, the capacitor Ca is required to sufficiently smooth the voltage when the charges Q1 and Q2 through which an instantaneous current flows when the switch element S2 is turned off and turned on are charged. That is, when the allowable value of the surge voltage is Vs, the capacitance of the capacitor Ca needs to satisfy the following expression (32).

Further, in order that the voltage that rises when the capacitor Ca is charged with the charges Q1 and Q2 is 10% or less of the allowable value of the surge voltage, the capacitance of the capacitor Ca needs to satisfy the following equation (33). .

Here, if the longer time of the turn-off or turn-on switching time is Δt, the maximum current flowing through the reactor L1 is Ip, the breakdown voltage of the element is Vabs, and the maximum voltage applied to the switch element S1 is Vm, The relationship represented by (34), (35) is obtained.

Then, when Expressions (34) and (35) are substituted into Expression (33), the following Expression (36) is obtained as a desirable capacitance condition for the capacitor Ca.

As a result, the capacitor Ca can be charged with the electric charge caused by the instantaneous current due to the switching operation of the switch elements S1 and S2, and the voltage due to the instantaneous current can be sufficiently smoothed.

  Table 1 shows the operating conditions of the boost chopper device 1 of the present embodiment and the capacitance value of the capacitor Ca.

The step-up chopper device 1 configured as described above has a drain terminal Td1 and a source terminal Ts1 installed through the substrate B, and electrically insulates between the drain terminal Td1 and the source terminal Ts1. A switching element S1 that switches to one of a state and an electrically conductive state, a drain terminal Td2 that is electrically connected to the source terminal Ts1, and a grounding and penetrating the substrate B. A switching element S2 having a source terminal Ts2 and switching between the drain terminal Td2 and the source terminal Ts2 to one of an electrically insulated state and an electrically conductive state, and one end of which is a drain terminal Td1 And a capacitor C1 having the other end connected to the source terminal Ts2.

  And about the surface mount type capacitor | condenser Ca whose electrostatic capacitance is smaller than the capacitor | condenser C1, the one end is connected to the drain terminal Td1, and the other end is connected to the source terminal Ts2. Furthermore, a current path from the drain terminal Td1 through the capacitor Ca to the source terminal Ts2 (hereinafter referred to as a first current path; the line F1 + line F2 corresponds to the first current path) connects the capacitor C1 from the drain terminal Td1. It is formed so as to be closer to the switch elements S1 and S2 than a current path (hereinafter referred to as a second current path) passing through to the source terminal Ts2.

  A current gradient is instantaneously generated by the switching operation of the switch elements S1 and S2. However, since the electric current flowing at this moment is small, the surge current can be absorbed by the surface mount type capacitor Ca having a small capacitance. Further, the output current ripple other than this moment is absorbed by the capacitor C1.

  Furthermore, since the surface mount type capacitor Ca having a small parasitic inductance is used, the parasitic inductance component of the capacitor Ca can be reduced, and the surge current and noise can be reduced.

  On the first current path, a via VA1 that penetrates the substrate B and electrically connects the front surface side and the back surface side of the substrate B is provided, and the surface of the substrate B on which the first current path is formed. A current path (hereinafter referred to as a third current path) from the via VA1 to the source terminal Ts2 so as to surround an insulating region around the switch elements S1 and S2 on the surface opposite to the line F3. Corresponding) is formed.

  Thereby, in the current path from the drain terminal Td1 to the source terminal Ts2, a parallel wiring constituted by the first current path and the third current path is obtained. For this reason, for example, if the wiring inductance by the first current path is equal to the wiring inductance by the third current path, the current passing through the capacitor Ca is smaller than the case where there is no third current path and only the first current path. The wiring inductance of the path can be halved.

  Therefore, it is possible to reduce the wiring inductance of the current path passing through the capacitor Ca without mounting the switch elements S1 and S2 on the substrate surface, and the surge current can be further reduced.

  In addition, the line R1 and the line R2 are opposed to each other with the substrate B interposed therebetween, and the direction in which the current flows is opposite to the opposite part. As a result, the current flows so as to cancel the magnetic fields in the line R1 and the line R2, so that the wiring inductance of the current path passing through the capacitor Ca can be reduced.

  Further, the area SL1 of the region surrounded by the loop line RL1 formed through the capacitor C1 and the capacitor Ca on the surface of the substrate B passes through the first current path and the third current path on the surface of the substrate B. There is no ground wiring in a region facing the loop line RL1 on the substrate surface that is larger than the area SL2 of the region surrounded by the formed loop line RL2 and opposite to the surface on which the loop line RL1 is formed. .

  Thereby, since the wiring inductance Lb between the capacitor C1 and the capacitor Ca is sufficiently smaller than the wiring inductance La of the current path passing through the capacitor Ca, the noise voltage can be reduced.

  The line R13 and the line R4 are formed so as to be substantially symmetrical with respect to a straight line connecting the drain terminal Td1 and the source terminal Ts2. As a result, the wiring inductance by the first current path and the wiring inductance by the third current path can be made substantially equal, and the current passing through the capacitor Ca can be compared to the case where there is no third current path and only the first current path. The wiring inductance of the path can be substantially halved.

  In the embodiment described above, the step-up chopper device 1 is the semiconductor device according to the present invention, the drain terminal Td1 is the first terminal according to the present invention, the source terminal Ts1 is the second terminal according to the present invention, and the switch element S1 is the first semiconductor according to the present invention. The switch element and drain terminal Td2 are the third terminal in the present invention, the source terminal Ts2 is the fourth terminal in the present invention, the switch element S2 is the second semiconductor switch element in the present invention, and the capacitor C1 is the first capacitor and capacitor Ca in the present invention. Is the second capacitor in the present invention, the loop line RL1 is the first loop wiring in the present invention, and the loop line RL2 is the second loop wiring in the present invention.

(Second Embodiment)
A second embodiment of the present invention will be described below with reference to the drawings.
FIG. 5A is a circuit diagram showing a configuration of the step-down chopper device 11 of the present embodiment. FIG. 5B is a diagram illustrating the surface wiring of the step-down chopper device 11. FIG. 5C is a diagram showing the back surface wiring of the step-down chopper device 11.

As shown in FIG. 5A, the step-down chopper device 11 includes a reactor L11, capacitors C11, C12, and Cb, and switch elements S11 and S12.
Capacitors C11 and C12 are smoothing capacitors, and capacitor Cb is a surface mount capacitor. The switch elements S11 and S12 are N-channel field effect transistors.

Among these, the reactor L11 has one end connected to the output terminal To and the other end connected to a connection point between the switch element S11 and the switch element S12.
Capacitor C11 has one end connected to the connection point between reactor L11 and output terminal To, and the other end grounded.

  The switch element S11 has a drain terminal Td11 connected to the DC power source V11 and a source terminal Ts11 connected to the drain terminal Td12 of the switch element S2. In the switch element S12, the drain terminal Td12 is connected to the source terminal Ts11 of the switch element S11, and the source terminal Ts12 is grounded.

The capacitor Cb has one end connected to a connection point between the DC power source V11 and the switch element S11 and the other end grounded.
The capacitor C12 has one end connected to a connection point between the DC power supply V11 and the capacitor Cb and the other end grounded.

  In the step-down chopper device 11 configured as described above, the switch element S11 and the switch element S12 can be alternately turned on / off to generate a voltage lower than the power supply voltage at the output terminal To. That is, a period during which the switch element S11 is in an on state (hereinafter referred to as a switch on time) with respect to a period from when the switch element S11 is changed from off to on until the next change from off to on (hereinafter referred to as switching cycle) ) And the voltage at the output terminal To (output voltage) can be lowered as the switch-on time is shortened with respect to the switching period. Reactor L11 and capacitor C11 constitute a smoothing circuit for smoothing the output voltage.

  As shown in FIG. 5B, capacitors C11, C12, Cb and switch elements S11, S12 are mounted on the surface of the substrate B on which the components of the step-down chopper device 11 are mounted, and the input terminal Ti and the output are output. A terminal To and a ground terminal GND are provided.

  Furthermore, on the surface of the substrate B, the drain terminal Td11 of the switch element S11 and one end of the capacitors C12, Cb are connected to the input terminal Ti, the source terminal Ts12 of the switch element S12, the capacitors C11, C12, A wiring W12 for connecting the other end of Cb to the ground terminal GND, a wiring W13 for connecting the source terminal Ts11 of the switch element S11 to the drain terminal Td12 of the switch element S12, an output terminal To, and one end of the capacitor C11 And a wiring W14 for connecting the two.

  Further, in the wiring W12, a via VA11 that penetrates from the front surface to the back surface of the substrate B and electrically connects the front surface and the back surface of the substrate B is formed near the other end of the capacitor Ca. In addition, a connection terminal TL for connecting to the end of the reactor L11 is provided in the wirings W13 and W14. That is, by connecting one end of the reactor L11 to the connection terminal TL of the wiring W13 and connecting the other end of the reactor L11 to the connection terminal TL of the wiring W14, the wiring W13 and the wiring W14 are electrically connected via the reactor L11. Connected.

  Then, as shown in FIG. 5C, on the back surface of the substrate B, the via VA11 is formed at one end and the source terminal Ts12 of the switch element S12 is formed at the other end around the terminals of the switch elements S11 and S12. Wiring W15 provided so as to bypass the insulating region to be formed is formed.

  The step-down chopper device 11 configured as described above has a drain terminal Td11 and a source terminal Ts11 installed through the substrate B, and electrically insulates between the drain terminal Td11 and the source terminal Ts11. A switching element S11 that switches to one of a state and an electrically conductive state; a drain terminal Td12 that is electrically connected to the source terminal Ts11; A switching element S12 having a source terminal Ts12 and switching between the drain terminal Td12 and the source terminal Ts12 to one of an electrically insulated state and an electrically conductive state, and one end of the drain terminal Td11. And a capacitor C12 having the other end connected to the source terminal Ts12.

  And about the surface mount type capacitor | condenser Cb whose electrostatic capacitance is smaller than the capacitor | condenser C12, the one end is connected to the drain terminal Td11, and the other end is connected to the source terminal Ts12. Furthermore, a current path (hereinafter referred to as a first current path) from the drain terminal Td11 through the capacitor Cb to the source terminal Ts12 is a current path (hereinafter referred to as a second current path) from the drain terminal Td11 through the capacitor C12 to the source terminal Ts12. It is formed so as to be closer to the switch elements S11 and S12 than the current path).

  A current gradient is instantaneously generated by the switching operation of the switch elements S11 and S12. However, since the electric current that flows at this moment is small, the surge current can be absorbed by the surface mount capacitor Cb having a small capacitance. Further, the output current ripple other than this moment is absorbed by the capacitor C12.

  Furthermore, since the surface-mounted capacitor Cb having a small parasitic inductance is used, the parasitic inductance component of the capacitor Cb can be reduced, and the surge current and noise can be reduced.

  On the first current path, a via VA11 that penetrates the substrate B and electrically connects the front surface side and the back surface side of the substrate B is provided, and the surface of the substrate B on which the first current path is formed. A current path from the via VA11 to the source terminal Ts12 (hereinafter referred to as a third current path) is formed on the opposite surface to surround the insulating region around the switch elements S11 and S12.

  Thereby, in the current path from the drain terminal Td11 to the source terminal Ts12, a parallel wiring constituted by the first current path and the third current path is obtained. For this reason, for example, if the wiring inductance by the first current path and the wiring inductance by the third current path are made equal, the current passing through the capacitor Cb compared to the case where there is no third current path and only the first current path is present. The wiring inductance of the path can be halved.

  Therefore, it is possible to reduce the wiring inductance of the current path passing through the capacitor Cb without mounting the switch elements S11 and S12 on the substrate surface, and the surge current can be further reduced.

  In the embodiment described above, the step-down chopper device 11 is the semiconductor device according to the present invention, the drain terminal Td11 is the first terminal according to the present invention, the source terminal Ts11 is the second terminal according to the present invention, and the switch element S11 is the first semiconductor according to the present invention. The switch element and drain terminal Td12 are the third terminal in the present invention, the source terminal Ts12 is the fourth terminal in the present invention, the switch element S12 is the second semiconductor switch element in the present invention, and the capacitor C12 is the first capacitor and capacitor Cb in the present invention. Is a second capacitor in the present invention.

(Third embodiment)
A third embodiment of the present invention will be described below with reference to the drawings.
FIG. 6A is a circuit diagram showing a configuration of the buck-boost converter device 21 of the present embodiment. FIG. 6B is a diagram showing the surface wiring of the buck-boost converter device 21. FIG. 6C is a diagram showing the backside wiring of the buck-boost converter device 21.

  As shown in FIG. 6A, the step-up / step-down converter device 21 includes a reactor L21, capacitors C21, C22, Cc, Cd, and switch elements S21, S22, S23, S24.

  Capacitors C21 and C22 are smoothing capacitors, and capacitors Cc and Cd are surface mount capacitors. The switch elements S21, S22, S23, and S24 are N-channel field effect transistors.

  Among these, the switch element S21 has a drain terminal Td21 connected to the DC power source V21 and a source terminal Ts21 connected to the drain terminal Td22 of the switch element S22. In the switch element S22, the drain terminal Td22 is connected to the source terminal Ts21 of the switch element S21, and the source terminal Ts22 is grounded.

  The switch element S23 has a drain terminal Td23 connected to the output terminal To and a source terminal Ts23 connected to the drain terminal Td24 of the switch element S24. In the switch element S24, the drain terminal Td24 is connected to the source terminal Ts23 of the switch element S23, and the source terminal Ts24 is grounded.

  Reactor L11 has one end connected to a connection point between switch elements S21 and S22, and the other end connected to a connection point between switch elements S23 and S24.

  The capacitor Cc has one end connected to a connection point between the DC power supply V21 and the switch element S21 and the other end grounded. The capacitor C21 has one end connected to a connection point between the DC power source V21 and the capacitor Cc, and the other end grounded.

  The capacitor Cd has one end connected to the connection point between the output terminal To and the switch element S23 and the other end grounded. The capacitor C22 has one end connected to a connection point between the output terminal To and the capacitor Cd and the other end grounded.

  In the step-up / step-down converter device 21 configured as described above, at the time of boosting, the switch element S21 is turned on, the switch element S22 is turned off, the switch element S23 and the switch element S24 are alternately turned on / off, and the output terminal A voltage higher than the power supply voltage can be generated at To. At the time of step-down, the switch element S23 is turned on and the switch element S24 is turned off, and the switch element S21 and the switch element S22 are alternately turned on / off to generate a voltage lower than the power supply voltage at the output terminal To. .

  As shown in FIG. 6B, capacitors C21, C22, Cc, Cd and switch elements S21, S22, S23, S24 are mounted on the surface of the substrate B on which the components of the buck-boost converter device 21 are mounted. In addition, an input terminal Ti, an output terminal To, and a ground terminal GND are provided.

  Further, on the surface of the substrate B, the drain terminal Td21 of the switch element S21 and one end of the capacitors C21 and Cc are connected to the input terminal Ti, and the drain terminal Td23 of the switch element S23 and the capacitors C22 and Cd are connected. A wiring W22 for connecting one end to the output terminal To, a wiring W23 for connecting the other ends of the source terminals Ts22, 24 of the switch elements S22, S24 and the capacitors C21, C22, Cc, Cd to the ground terminal GND, A wiring W24 for connecting the source terminal Ts21 of the switch element S21 to the drain terminal Td22 of the switch element S22 and a wiring W25 for connecting the source terminal Ts23 of the switch element S23 to the drain terminal Td24 of the switch element S24 are formed. The

  Further, in the wirings W21 and W22, vias VA21 and VA22 that penetrate from the front surface to the back surface of the substrate B and electrically connect the front surface and the back surface of the substrate B are formed near one end of the capacitors Cc and Cd. . In addition, a connection terminal TL for connecting to the end of the reactor L21 is provided in the wirings W24 and W25. That is, by connecting one end of the reactor L21 to the connection terminal TL of the wiring W24 and connecting the other end of the reactor L21 to the connection terminal TL of the wiring W25, the wiring W24 and the wiring W25 are electrically connected via the reactor L21. Connected.

  Then, as shown in FIG. 6C, on the back surface of the substrate B, the via VA21 is formed at one end and the source terminal Ts22 of the switch element S22 is formed at the other end around the terminals of the switch elements S21 and S22. Insulation formed around the terminals of the switch elements S23 and S24, with the wiring W26 provided so as to bypass the insulation region to be formed and the formation point of the via VA22 as one end and the source terminal Ts24 of the switch element S24 as the other end A wiring W27 provided so as to bypass the region is formed.

  The buck-boost converter device 21 configured as described above has a drain terminal Td21 (Td23) and a source terminal Ts21 (Ts23) installed through the substrate, and the drain terminal Td21 (Td23) and the source terminal Ts21 ( Switch element S21 (S23) that switches between the electrically insulated state and the electrically conductive state, and the drain terminal electrically connected to the source terminal Ts21 (Ts23). It has Td22 (Td24) and a source terminal Ts22 (Ts24) that is connected to the ground and installed through the substrate, and between the drain terminal Td22 (Td24) and the source terminal Ts22 (Ts24) Switch element S22 that switches between the electrically insulated state and the electrically conductive state Comprises a S24), a capacitor C21 (C22) that the other end connected to a source terminal Ts22 (TS24) with one end connected to the drain terminal Td21 (Td23).

  And about the surface mount type capacitor Cc (Cd) whose electrostatic capacity is smaller than the capacitor C21 (C22), one end is connected to the drain terminal Td21 (Td23) and the other end is connected to the source terminal Ts22 (Ts24). Is done. Furthermore, a current path (hereinafter referred to as a first current path) from the drain terminal Td21 (Td23) to the source terminal Ts22 (Ts24) through the capacitor Cc (Cd) is connected from the drain terminal Td21 (Td23) to the capacitor C21 (C22). It is formed so as to be closer to the switch elements S21 (S23) and S22 (S24) than a current path (hereinafter referred to as a second current path) passing through the source terminal Ts22 (Ts24).

  A current gradient is instantaneously generated by the switching operation of the switch elements S21 (S23) and S22 (S24). However, since the electric current that flows at this moment is small, the surge current can be absorbed by the surface mount type capacitor Cc (Cd) having a small capacitance. Further, the output current ripple other than this moment is absorbed by the capacitor C21 (C22).

  Furthermore, since the surface-mounted capacitor Cc (Cd) having a small parasitic inductance is used, the parasitic inductance component of the capacitor Cc (Cd) can be reduced, and the surge current and noise can be reduced.

  Then, a via VA21 (VA22) that penetrates the substrate B and electrically connects the front side and the back side of the substrate B is provided on the first current path, and the first current path is formed in the substrate B. A current path (hereinafter, referred to as “source path”) from the VA21 (VA22) to the source terminal Ts22 (Ts24) so as to surround the insulating region around the switch elements S21 (S23) and S22 (S24) on the surface opposite to the surface being A third current path) is formed.

  Thereby, in the current path from the drain terminal Td21 (Td23) to the source terminal Ts22 (Ts24), a parallel wiring composed of the first current path and the third current path is obtained. Therefore, for example, if the wiring inductance by the first current path is equal to the wiring inductance by the third current path, the capacitor Cc (Cd) is compared with the case where there is no third current path and only the first current path. The wiring inductance of the current path passing through can be halved.

  Therefore, the wiring inductance of the current path passing through the capacitor Cc (Cd) can be reduced without mounting the switch elements S21 (S23) and S22 (S24) on the substrate surface, and the surge current can be further reduced. it can.

  In the embodiment described above, the buck-boost converter device 21 is the semiconductor device according to the present invention, the drain terminals Td21 and Td23 are the first terminals according to the present invention, the source terminals Ts21 and Ts23 are the second terminals according to the present invention, and the switch elements S21 and S23. Is a first semiconductor switch element according to the present invention, drain terminals Td22 and Td24 are a third terminal according to the present invention, source terminals Ts22 and Ts24 are a fourth terminal according to the present invention, and switch elements S22 and S24 are a second semiconductor switch element according to the present invention. The capacitors C21 and C22 are the first capacitors in the present invention, and the capacitors Cc and Cd are the second capacitors in the present invention.

(Fourth embodiment)
A fourth embodiment of the present invention will be described below with reference to the drawings.
FIG. 7A is a circuit diagram showing a configuration of the motor inverter device 31 of the present embodiment. FIG. 7B is a diagram showing surface wiring of the motor inverter device 31. FIG. 7C is a diagram showing the backside wiring of the motor inverter device 31.

  As shown in FIG. 7A, the motor inverter device 31 includes capacitors C31, Ce, Cf, and Cg, and switch elements S31, S32, S33, S34, S35, and S36.

  The capacitor C31 is a smoothing capacitor, and the capacitors Ce, Cf, and Cg are surface mount capacitors. The switch elements S31, S32, S33, S34, S35, and S36 are N-channel field effect transistors.

  Among these, the switch elements S31, S33, and S35 have the drain terminals Td31, Td33, and Td35 connected to the DC power source V31, and the source terminals Ts31, Ts33, and Ts35 connected to the drains of the switch elements S32, S34, and S36. Yes. The switch elements S32, S34, and S36 have drain terminals Td32, Td34, and Td36 connected to the source terminals Ts31, Ts33, and Ts35 of the switch elements S31, S33, and S35, and the source terminals Ts32, Ts34, and Ts36 are grounded. Yes.

  The capacitor Ce has one end connected to a connection point between the DC power source V31 and the switch element S31 and the other end grounded. The capacitor C31 has one end connected to a connection point between the DC power supply V31 and the capacitor Ce and the other end grounded.

  The capacitor Cf has one end connected to a connection point between the switch element S31 and the switch element S33, and the other end grounded. The capacitor Cg has one end connected to a connection point between the switch element S33 and the switch element S35 and the other end grounded.

  A connection point between the switch element S31 and the switch element S32, a connection point between the switch element S33 and the switch element S34, and a connection point between the switch element S35 and the switch element S36 are connected to the motor MT. Motor MT is a three-phase AC motor.

  In the motor inverter device 31 configured as described above, the switch element S31 and the switch element S32 are alternately turned on / off to control the U-phase voltage, and the switch element S33 and the switch element S34 are alternately turned on / off. The motor MT is rotated by controlling the V-phase voltage and controlling the W-phase voltage by alternately turning on / off the switch element S35 and the switch element S36.

  As shown in FIG. 7B, capacitors C31, Ce, Cf, Cg and switch elements S31, S32, S33, S34, S35, S36 are provided on the surface of the substrate B on which the components of the motor inverter device 31 are mounted. While being mounted, an input terminal Ti, a motor connection terminal TM, and a ground terminal GND are provided.

  Further, on the surface of the substrate B, the drain terminals Td31, Td33, Td35 of the switch elements S31, S33, S35 and the wiring W31 for connecting one end of the capacitors C31, Ce, Cf, Cg to the input terminal Ti, and the switch The source terminals Ts32, Ts34, Ts36 of the elements S32, S34, S36 and the wiring W32 for connecting the other ends of the capacitors C31, Ce, Cf, Cg to the ground terminal GND, and the source terminal Ts31 of the switch element S31 are connected to the switch element S32. A wiring W33 for connecting to the drain terminal Td32, a wiring W34 for connecting the source terminal Ts33 of the switching element S33 to the drain terminal Td34 of the switching element S34, and a source terminal Ts35 of the switching element S35 as the drain of the switching element S36. Connect to terminal Td36 Because of the wiring W35 and is formed.

  Further, in the wiring W32, vias VA31, VA32, and VA33 are formed in the vicinity of one end of the capacitors Ce, Cf, and Cg so as to penetrate from the front surface to the back surface of the substrate B and to electrically connect the front surface and the back surface of the substrate B. Is done. In addition, a motor connection terminal TM for connecting to the motor MT is provided in the wirings W33, W34, and W35.

  Then, as shown in FIG. 7C, on the back surface of the substrate B, the via VA31 is formed at one end and the source terminal Ts32 of the switch element S32 is formed at the other end around the terminals of the switch elements S31 and S32. Insulation formed around the terminals of the switch elements S33 and S34, with the wiring W36 provided so as to bypass the insulation region to be formed and the formation point of the via VA32 as one end and the source terminal Ts34 of the switch element S34 as the other end The wiring W37 provided so as to bypass the region and the formation region of the via VA33 as one end and the source terminal Ts36 of the switch element S36 as the other end, bypass the insulating region formed around the terminals of the switch elements S35 and S36. In this way, the wiring W38 provided is formed.

  The motor inverter device 31 configured in this way has a drain terminal Td31 (Td33, Td35) and a source terminal Ts31 (Ts33, Ts35) installed through the substrate B, and has a drain terminal Td31 (Td33, Td35). ) And the source terminal Ts31 (Ts33, Ts35), the switch element S31 (S33, S35) for switching between the electrically insulated state and the electrically conductive state, and the source terminal Ts31 (Ts33). , Ts35) and a drain terminal Td32 (Td34, Td36) electrically connected to the ground, and a source terminal Ts32 (Ts34, Ts36) connected to the ground and installed through the substrate B. Td32 (Td34, Td36) and source terminal Ts32 (Ts34, Ts36) Switch element S32 (S34, S36) that switches between the electrically insulated state and the electrically conductive state, and one end connected to drain terminal Td31 (Td33, Td35). The other end includes a capacitor C31 connected to the source terminal Ts32 (Ts34, Ts36).

  And about the surface mount type capacitor | condenser Ce (Cf, Cg) whose electrostatic capacitance is smaller than the capacitor | condenser C31, the one end is connected to drain terminal Td31 (Td33, Td35), and the other end is source terminal Ts32 (Ts34, Ts36). ). Further, a current path (hereinafter referred to as a first current path) from the drain terminal Td31 (Td33, Td35) through the capacitor Ce (Cf, Cg) to the source terminal Ts32 (Ts34, Ts36) is the drain terminal Td31 (Td33, It is closer to the switch elements S31 (S33, S35) and S32 (S34, S36) than a current path (hereinafter referred to as a second current path) from Td35) through the capacitor C31 to the source terminal Ts32 (Ts34, Ts36). Formed as follows.

  A current gradient is instantaneously generated by the switching operation of the switch elements S31 (S33, S35) and S32 (S34, S36). However, since the electric current that flows at this moment is small, the surge current can be absorbed by the surface mount type capacitor Ce (Cf, Cg) having a small capacitance. Further, the output current ripple other than this moment is absorbed by the capacitor C31.

  Furthermore, since the surface-mounted capacitor Ce (Cf, Cg) having a small parasitic inductance is used, the parasitic inductance component of the capacitor Ce (Cf, Cg) can be reduced, and the surge current and noise can be reduced. Can do.

  On the first current path, vias VA31 (VA32, VA33) that penetrate the substrate B and electrically connect the front surface side and the back surface side of the substrate B are provided. In the substrate B, the first current path is A source terminal Ts32 (from the via VA31 (VA32, VA33) to the surrounding area of the switch elements S31 (S33, S35), S32 (S34, S36) is surrounded on the surface opposite to the formed surface. A current path (hereinafter referred to as a third current path) reaching Ts34, Ts36) is formed.

  Thereby, in the current path from the drain terminal Td31 (Td33, Td35) to the source terminal Ts32 (Ts34, Ts36), a parallel wiring constituted by the first current path and the third current path is obtained. For this reason, for example, if the wiring inductance by the first current path and the wiring inductance by the third current path are made equal, the capacitor Ce (Cf, The wiring inductance of the current path passing through Cg) can be halved.

  Therefore, the wiring inductance of the current path passing through the capacitor Ce (Cf, Cg) can be reduced without mounting the switch elements S31 (S33, S35), S32 (S34, S36) on the board surface, and the surge current Can be further reduced.

  In the embodiment described above, the motor inverter device 31 is the semiconductor device according to the present invention, the drain terminals Td31, Td33, and Td35 are the first terminals according to the present invention, and the source terminals Ts31, Ts33, and Ts35 are the second terminals according to the present invention. S31, S33, S35 are the first semiconductor switch elements in the present invention, drain terminals Td32, Td34, Td36 are the third terminals in the present invention, and source terminals Ts32, Ts34, Ts36 are the fourth terminals in the present invention, the switch elements S32, S34. , S36 are the second semiconductor switch element in the present invention, the capacitor C31 is the first capacitor in the present invention, and the capacitors Ce, Cf, Cg are the second capacitors in the present invention.

As mentioned above, although one Example of this invention was described, this invention is not limited to the said Example, As long as it belongs to the technical scope of this invention, a various form can be taken.
For example, in the above embodiment, as shown in FIG. 1C, the wiring W5 bypasses the gate terminal Tg1 from the via VA1 and reaches the source terminal Ts2, that is, the shortest path from the via VA1 to the source terminal Ts2 exists. Shown not formed. However, as shown in FIG. 8A, the wiring W5 may be formed so as to surround the entire periphery of the insulating region formed around the terminals of the switch elements S1 and S2, or as shown in FIG. As described above, a current path may be formed between the source terminal Ts1 and the gate terminal Tg2.

  DESCRIPTION OF SYMBOLS 1 ... Boost chopper device, 11 ... Buck chopper device, 21 ... Buck-boost converter device, 31 ... Motor inverter device, B ... Substrate, C1, C11, C12, C21, C22, C31, Ca, Cb, Cc, Cd, Ce , Cf, Cg: capacitors, F1, F2, F3 ... lines, L1, L11, L21 ... reactors, RL1, RL2 ... loop lines, S1, S2, S11, S12, S21, S22, S23, S24, S31, S32, S33, S34, S35, S36 ... switch elements, Td1, Td2, Td11, Td12, Td21, Td22, Td23, Td24, Td31, Td32, Td33, Td34, Td35, Td36 ... drain terminals, Ts1, Ts2, Ts11, Ts12, Ts21, Ts22, Ts23, Ts24, Ts31, Ts32, s33, Ts34, Ts35, Ts36 ... source terminal, VA1, VA11, VA21, VA22, VA31, VA32, VA33 ... via

Claims (5)

A semiconductor device in which a semiconductor element is provided on a substrate,
A first terminal installed through the substrate and a second terminal different from the first terminal, wherein the first terminal and the second terminal are electrically insulated; And a first semiconductor switch element that switches to either one of the electrically conductive states;
A third terminal that is electrically connected to the second terminal; and a fourth terminal that is connected to the ground and that is installed through the substrate; and the third terminal and the fourth terminal A second semiconductor switch element that switches between the electrically insulated state and the electrically conductive state,
A first capacitor having one end connected to the first terminal and the other end connected to the fourth terminal;
A surface mount type second capacitor having one end connected to the first terminal and the other end connected to the fourth terminal and having a smaller capacitance than the first capacitor;
The first current path from the first terminal through the second capacitor to the fourth terminal is more than the second current path from the first terminal through the first capacitor to the fourth terminal. Formed close to the first semiconductor switch element and the second semiconductor switch element;
On the first current path, vias that penetrate the substrate and electrically connect the front surface side and the back surface side of the substrate are provided,
In the substrate, on the surface opposite to the surface on which the first current path is formed, the insulating region around the first semiconductor switch element and the second semiconductor switch element is surrounded by the via from the via. 3. A semiconductor device, wherein a third current path reaching the first terminal or the fourth terminal is formed. The third current path is
At least a part of the first current path is opposed to the substrate across the substrate,
2. The semiconductor device according to claim 1, wherein in a portion facing each other, a direction in which a current flows is formed to be opposite in the first current path and the third current path. The area of the region surrounded by the first loop wiring formed through the first capacitor and the second capacitor on the surface of the substrate is the first current path and the third current on the surface of the substrate. Larger than the area of the region surrounded by the second loop wiring formed through the path,
3. The ground wiring does not exist in a region facing the first loop wiring in a wiring layer arranged above and below the surface on which the first loop wiring is formed. A semiconductor device according to 1. The first current path and the third current path are:
The first current path and the third current path are formed so as to have a line-symmetric portion with respect to a straight line connecting the first terminal and the fourth terminal. The semiconductor device according to claim 3. Δt, which is the longer of the time during which the voltage at the third terminal changes from 10% to 90% of the maximum voltage due to turn-off and turn-on of the second semiconductor switch element.
The maximum current flowing through the first semiconductor switch element and the second semiconductor switch element during the operation of the second semiconductor switch element is Ip,
Of the maximum ratings of the first semiconductor switch element and the second semiconductor switch element, the lower voltage is expressed as Vabs,
The maximum voltage applied to the first semiconductor switch element during the operation of the second semiconductor switch element is Vm,
The capacitance of the second capacitor is Ca,
5. The semiconductor device according to claim 1, wherein the capacitance of the second capacitor satisfies the following expression (36).