JP2011258691A - Light-receiving element array - Google Patents

Light-receiving element array Download PDF

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JP2011258691A
JP2011258691A JP2010130919A JP2010130919A JP2011258691A JP 2011258691 A JP2011258691 A JP 2011258691A JP 2010130919 A JP2010130919 A JP 2010130919A JP 2010130919 A JP2010130919 A JP 2010130919A JP 2011258691 A JP2011258691 A JP 2011258691A
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light receiving
light
receiving element
element array
layer
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Etsuji Omura
悦司 大村
Ei Sawada
映 澤田
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Kyosemi Corp
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Kyosemi Corp
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Priority to PCT/JP2011/052165 priority patent/WO2011155230A1/en
Priority to TW100117396A priority patent/TW201203530A/en
Publication of JP2011258691A publication Critical patent/JP2011258691A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • H01L27/14629Reflectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1463Pixel isolation structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1464Back illuminated imager structures

Abstract

PROBLEM TO BE SOLVED: To provide a light-receiving element array in which optical crosstalk can be minimized by additionally forming an isolation trench having a V-shaped cross-section in a conventional epitaxial structure.SOLUTION: The light-receiving element array 1 has a first conductivity type semiconductor substrate 2, a first conductivity type light-receiving layer 4 formed on the surface side of the semiconductor substrate 2, a first conductivity type window layer 5 formed on the surface side of the light-receiving layer, a plurality of second conductivity type regions 6 formed in a state of penetrating the window layer and plunging into the surface side of the light-receiving layer and formed separately as one-dimensional or two-dimensional arrangement, and a plurality of first electrodes 7 provided at least partially on the surface of the plurality of second conductivity type regions 6, respectively. In a plurality of regions between the arrays formed by a plurality of arrays consisting of the plurality of second conductivity type regions 6, first isolation trenches 10 having a V-shaped cross-section open to the surface side are provided to penetrate at least the window layer 5 and the light-receiving layer 4.

Description

本発明は受光素子アレイに関し、光学的クロストークを抑制可能な光通信用又は1次元,2次元センサ用の受光素子アレイに関する。   The present invention relates to a light receiving element array, and relates to a light receiving element array for optical communication or one-dimensional or two-dimensional sensor capable of suppressing optical crosstalk.

従来から、光通信用又は1次元、2次元センサ用の種々の受光素子アレイが実用に供されている。受光素子アレイには、例えば、光がアレイ上面側から入射される上面入射型や、光がアレイ下面側から入射される下面入射型などがある。
ここで、図8には、上面入射型受光素子アレイの一般的な構造が示され、図9には、下面入射型受光素子アレイの一般的な構造が示されている。
Conventionally, various light receiving element arrays for optical communication or one-dimensional and two-dimensional sensors have been put to practical use. The light receiving element array includes, for example, an upper surface incident type in which light is incident from the upper surface side of the array, and a lower surface incident type in which light is incident from the lower surface side of the array.
Here, FIG. 8 shows a general structure of a top-illuminated light receiving element array, and FIG. 9 shows a general structure of a bottom-illuminated light receiving element array.

上記の図8,図9の受光素子アレイ21,21Aを製造する為に、先ずは、n型InP半導体基板22上に、n型InPバッファ層23、n型InGaAs受光層24、n型InP窓層25の順にエピタキシャル成長させて積層する。次に、フォトリソグラフィにより、n型InP窓層25上に1次元的又は2次元的になるように一定ピッチで複数の開口部を設け、これら複数の開口部にZnを夫々拡散してp型領域26を形成する。これにより、これら複数のp型領域26とn型InGaAs受光層24とからpn接合31が夫々形成され、pn構造フォトダイオードが1次元的又は2次元的に配設される。   In order to manufacture the light receiving element arrays 21 and 21A shown in FIGS. 8 and 9, the n type InP buffer layer 23, the n type InGaAs light receiving layer 24, and the n type InP window are first formed on the n type InP semiconductor substrate 22. Layers 25 are epitaxially grown in this order. Next, by photolithography, a plurality of openings are provided on the n-type InP window layer 25 at a constant pitch so as to be one-dimensional or two-dimensional, and Zn is diffused into each of the plurality of openings to form p-type. Region 26 is formed. Thereby, a pn junction 31 is formed from each of the plurality of p-type regions 26 and the n-type InGaAs light receiving layer 24, and the pn structure photodiodes are arranged one-dimensionally or two-dimensionally.

次に、例えば、図8に示す上面入射型受光素子アレイ21の場合は、各p型領域26の上面に部分的にp型電極27を夫々設け、p型領域26のp型電極27を除く上面残部と窓層25の上面に反射防止膜32を設け、n型InP基板22の裏面全域に共通のn型電極28を形成する。
図9に示す下面入射型受光素子アレイ21Aの場合は、各p型領域26の上面に部分的にp型電極27Aを夫々設け、窓層25の上面に前記p型領域26を囲うように平面視C型で且つスリット状の複数のn型電極28Aを夫々設け、n型InP基板22の裏面に反射防止膜33を形成する。
Next, for example, in the case of the top-illuminated light receiving element array 21 shown in FIG. 8, a p-type electrode 27 is partially provided on the upper surface of each p-type region 26, and the p-type electrode 27 in the p-type region 26 is excluded. An antireflection film 32 is provided on the remaining upper surface and the upper surface of the window layer 25, and a common n-type electrode 28 is formed over the entire back surface of the n-type InP substrate 22.
In the case of the bottom-illuminated light receiving element array 21A shown in FIG. 9, a p-type electrode 27A is partially provided on the upper surface of each p-type region 26, and the p-type region 26 is surrounded by the upper surface of the window layer 25. A plurality of n-type electrodes 28 </ b> A that are C-type and slit-shaped are provided, and an antireflection film 33 is formed on the back surface of the n-type InP substrate 22.

ところで、図8の従来の受光素子アレイ21では、受光素子間は分離されていない。このため、受光素子のpn接合31近傍(空乏層)に入射した光が、電子正孔対のキャリアを発生させた場合、その発生した一部のキャリアが、横方向拡散により受光層24を介して隣接する受光素子のpn接合31近傍に移動する可能性がある。このとき、この移動したキャリアにより隣接する受光素子に光電流が流れて、電気的クロストークが発生するため、受光素子アレイの特性が劣化するという問題がある。   Incidentally, in the conventional light receiving element array 21 of FIG. 8, the light receiving elements are not separated. For this reason, when light incident on the vicinity of the pn junction 31 (depletion layer) of the light receiving element generates carriers of electron-hole pairs, some of the generated carriers pass through the light receiving layer 24 by lateral diffusion. There is a possibility of moving to the vicinity of the pn junction 31 of the adjacent light receiving element. At this time, there is a problem that the characteristics of the light receiving element array are deteriorated because a photocurrent flows to an adjacent light receiving element due to the moved carrier and electrical crosstalk occurs.

上記電気的クロストークの問題を解決する手段として、特許文献1では、受光素子間に、窓層上面からn型InP基板近傍に達する深さのトレンチ溝を夫々設けている。このトレンチ溝により、受光素子間は物理的に分離されるので、キャリアの移動を防止して電気的クロストークを抑制することができる。尚、各トレンチ溝には、pn接合の劣化を防止する為に半導体材料が埋め込まれている場合がある。   As means for solving the electrical crosstalk problem, in Patent Document 1, trench grooves each having a depth reaching the vicinity of the n-type InP substrate from the upper surface of the window layer are provided between the light receiving elements. Since the light receiving elements are physically separated by the trench, carrier movement can be prevented and electrical crosstalk can be suppressed. Each trench groove may be embedded with a semiconductor material in order to prevent deterioration of the pn junction.

ここで、光学的クロストークについて、図10の受光素子アレイ21Bに基づいて説明する。光は光ファイバに導かれレンズで集光されて受光素子アレイ21Bに垂直に入射されるが、光の一部は、受光面に対して垂直に入射されずに斜めに入射される場合がある。この斜め入射光は、仮に受光層24に吸収されずに透過すると漏れ光となり、受光素子の下面に反射して隣接する受光素子のpn接合近傍に入射する場合、或いは、受光素子の上面と下面との間で多重反射を繰り返して隣接する受光素子のpn接合31の近傍に入射する場合がある。このように隣接するpn接合近傍に入射した漏れ光は、そこで電子正孔対のキャリアを形成し光電流を発生させてしまう。これを光学的クロストークという。   Here, the optical crosstalk will be described based on the light receiving element array 21B of FIG. The light is guided to the optical fiber, condensed by the lens, and vertically incident on the light receiving element array 21B. However, a part of the light may be incident obliquely without being perpendicularly incident on the light receiving surface. . This obliquely incident light becomes leakage light if it is transmitted without being absorbed by the light receiving layer 24, and is reflected on the lower surface of the light receiving element and incident near the pn junction of the adjacent light receiving element, or the upper surface and the lower surface of the light receiving element. May be incident near the pn junction 31 of the adjacent light receiving element. Thus, the leaked light incident near the adjacent pn junction forms carriers of electron-hole pairs and generates a photocurrent. This is called optical crosstalk.

このため、上記の受光素子間にトレンチ溝を設ける構造では、電気的クロストークを低減させることが可能であっても、光学的クロストークの抑制は十分とは言えない。つまり、漏れ光が、受光素子の上面と下面との間で多重反射を繰り返す場合、トレンチ溝が縦に細長い形状のため、漏れ光がトレンチ溝に当たらずに、隣接するpn接合近傍に入射されてしまう可能性がある。尚、光が受光面に垂直に入射されても、その一部が受光層を透過して、半導体基板と電極の境界面で乱反射され、その光が多重反射することで隣接する受光素子のpn接合近傍に入射する場合もある。   For this reason, in the structure in which the trench groove is provided between the light receiving elements, even if the electrical crosstalk can be reduced, it cannot be said that the optical crosstalk is sufficiently suppressed. That is, when the leakage light repeats multiple reflections between the upper surface and the lower surface of the light receiving element, the trench groove is vertically elongated, so that the leakage light does not strike the trench groove but is incident on the adjacent pn junction. There is a possibility that. Even if light is incident perpendicularly to the light receiving surface, a part of the light is transmitted through the light receiving layer, is irregularly reflected at the boundary surface between the semiconductor substrate and the electrode, and the light is subjected to multiple reflections so that the pn of the adjacent light receiving element is obtained. In some cases, the light enters the vicinity of the junction.

上記の光学的クロストークを解決する手段として、特許文献2,3のような受光素子アレイが開示されている。即ち、特許文献2では、受光層と受光素子底部との間に光吸収層を設け、特許文献3では、受光層と受光素子上面との間に光吸収層を設けている。この光吸収層は、入射する光のエネルギーより小さいバンドギャップエネルギを有する物質から形成されるため、受光層を透過した漏れ光を吸収減衰させることができ、光学的クロストークを抑制することができる。   As means for solving the above optical crosstalk, a light receiving element array as disclosed in Patent Documents 2 and 3 is disclosed. That is, in Patent Document 2, a light absorbing layer is provided between the light receiving layer and the bottom of the light receiving element, and in Patent Document 3, a light absorbing layer is provided between the light receiving layer and the upper surface of the light receiving element. Since this light absorption layer is formed of a material having a band gap energy smaller than that of incident light, leakage light transmitted through the light receiving layer can be absorbed and attenuated, and optical crosstalk can be suppressed. .

特開2001−144278号公報JP 2001-144278 A 特開2005−251890号公報JP 2005-251890 A 特開2005−259829号公報JP 2005-259829 A

しかし、上記の特許文献2,3の光学的クロストークの抑制手段では、受光素子アレイの製造時に、図8,図9に示す従来のエピ構造に追加して、光吸収層を成長させるプロセスが必要となる。従って、受光素子アレイの製造コストが増加してしまう。さらに、受光層を透過して光吸収層に入射した光は、熱や光電流に変換されるので、暗電流の増加や応答速度の低下など受光素子の特性の劣化が伴うという問題が生じる。   However, in the optical crosstalk suppressing means described in Patent Documents 2 and 3, a process for growing a light absorption layer in addition to the conventional epistructure shown in FIGS. Necessary. Therefore, the manufacturing cost of the light receiving element array increases. Furthermore, since the light transmitted through the light receiving layer and incident on the light absorbing layer is converted into heat and photocurrent, there arises a problem that the characteristics of the light receiving element are deteriorated such as an increase in dark current and a decrease in response speed.

また、特許文献3の受光素子アレイは、InP窓層に光吸収層を成長させた構造であるが、一般的なZn拡散によりp型領域を形成するプロセスを行う場合、特許文献3のプロセスでは、従来よりも拡散領域を深くする必要がある。このため、p型領域が横方向に拡大してしまう。このp型領域の拡大は、上記の問題と同様に、暗電流の増加や応答速度の低下など受光素子の特性の劣化を招くという問題が生じる。   The light receiving element array of Patent Document 3 has a structure in which a light absorption layer is grown on an InP window layer. However, when performing a process of forming a p-type region by general Zn diffusion, It is necessary to make the diffusion region deeper than before. For this reason, the p-type region expands in the horizontal direction. The enlargement of the p-type region causes a problem that the characteristics of the light receiving element are deteriorated, such as an increase in dark current and a decrease in response speed, as in the above problem.

本発明の目的は、従来のエピ構造に断面V型の分離溝を追加形成することで光学的クロストークを抑制可能な受光素子アレイを提供することである。   An object of the present invention is to provide a light receiving element array capable of suppressing optical crosstalk by additionally forming a V-shaped separation groove in a conventional epi structure.

請求項1の受光素子アレイは、第1導電型の半導体基板と、この半導体基板の表面側に形成した第1導電型の受光層と、この受光層の表面側に形成した第1導電型の窓層と、この窓層を貫通して受光層の表面側に突入する状態に形成され且つ1次元的または2次元的な配列として離隔状に形成された複数の第2導電型領域と、これら複数の第2導電領域の表面の少なくとも一部に夫々設けた複数の第1電極とを有する受光素子アレイにおいて、前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも前記窓層と受光層を貫通する深さの表面側に開放された断面V型の第1分離溝を夫々設けた、ことを特徴としている。   The light receiving element array according to claim 1 includes a first conductive type semiconductor substrate, a first conductive type light receiving layer formed on the surface side of the semiconductor substrate, and a first conductive type light receiving layer formed on the surface side of the light receiving layer. A plurality of second conductivity type regions formed in a state of penetrating to the surface side of the light receiving layer through the window layer and spaced apart as a one-dimensional or two-dimensional array, and A plurality of inter-array regions formed by a plurality of arrays of the plurality of second conductivity type regions in a light receiving element array having a plurality of first electrodes respectively provided on at least a part of the surface of the plurality of second conductive regions. In addition, a first separation groove having a V-shaped cross section opened at least on the surface side having a depth penetrating the window layer and the light receiving layer is provided.

請求項6の受光素子アレイは、第1導電型の半導体基板と、この半導体基板の表面側に形成した第1導電型の受光層と、この受光層の表面側に形成した第1導電型の窓層と、この窓層を貫通して受光層の表面側に突入する状態に形成され且つ1次元的または2次元的な配列として離隔状に形成された複数の第2導電型領域と、これら複数の第2導電領域の表面の少なくとも一部に夫々設けた複数の第1電極とを有する受光素子アレイにおいて、 前記半導体基板の裏面側に解放された断面倒立V型の複数の第1分離溝を夫々設けた、ことを特徴としている。   The light receiving element array according to claim 6 is a first conductive type semiconductor substrate, a first conductive type light receiving layer formed on the surface side of the semiconductor substrate, and a first conductive type light receiving layer formed on the surface side of the light receiving layer. A plurality of second conductivity type regions formed in a state of penetrating to the surface side of the light receiving layer through the window layer and spaced apart as a one-dimensional or two-dimensional array, and In a light receiving element array having a plurality of first electrodes respectively provided on at least a part of the surfaces of the plurality of second conductive regions, the plurality of first separation grooves having an inverted V-section opened to the back side of the semiconductor substrate It is characterized by providing each.

請求項1の発明によれば、受光素子アレイにおいて、複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも前記窓層と受光層を貫通する深さの表面側に開放された断面V型の第1分離溝を夫々設けたので、斜め入射された光、多重反射を繰り返す漏れ光や乱反射された漏れ光が発生した場合でも、断面V型の第1分離溝により、隣接するp型領域から離隔する水平方向又は水平に近い横方向へ効率よく反射させて、漏れ光が隣接するpn接合へ入射するのを低減させることができ、光学的クロストークを抑制することができる。   According to the first aspect of the present invention, in the light receiving element array, a surface having a depth penetrating at least the window layer and the light receiving layer in a plurality of inter-array regions formed by the plurality of arrays of the plurality of second conductivity type regions. Since the first separation groove having a V-shaped cross section that is open on the side is provided, the first separation groove having the V-shaped cross section can be obtained even when obliquely incident light, leaked light that repeats multiple reflections, or irregularly reflected light is generated. The groove can efficiently reflect in the horizontal direction or the horizontal direction separated from the adjacent p-type region to reduce the incidence of leaked light to the adjacent pn junction, thereby suppressing optical crosstalk. can do.

請求項6の発明によれば、受光素子アレイにおいて、半導体基板の裏面側に開放された断面倒立V型の複数の第1分離溝を夫々設けたので、断面倒立V型の第1分離溝により、斜め入射された光、多重反射を繰り返す漏れ光や乱反射された漏れ光が発生した場合でも、隣接するp型領域から離隔する水平方向又は水平に近い横方向へ効率よく反射させて、隣接するpn接合へ入射する光を低減させることで、光学的クロストークを抑制することができる。   According to the sixth aspect of the present invention, in the light receiving element array, since the plurality of first V-shaped first separation grooves opened on the back surface side of the semiconductor substrate are provided, Even when obliquely incident light, leaky light that repeats multiple reflections, or diffused leaked light occurs, the light is efficiently reflected in the horizontal direction or the horizontal direction that is separated from the adjacent p-type region, and is adjacent. By reducing the light incident on the pn junction, optical crosstalk can be suppressed.

請求項1の上記の構成に加えて、次のような種々の構成を採用してもよい。
(1)前記半導体基板と前記受光層の間に、第1導電型のバッファ層を設ける。
(2)前記半導体基板の裏面に1又は複数の第2電極を設ける。
(3)前記各第1分離溝の表面に第2電極を設ける。
(4)前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも前記窓層と受光層を貫通する深さのスリット状の第2分離溝を夫々設け、これらの第2分離溝の表面に第2電極を形成する。
In addition to the above configuration of claim 1, the following various configurations may be adopted.
(1) A buffer layer of a first conductivity type is provided between the semiconductor substrate and the light receiving layer.
(2) One or more second electrodes are provided on the back surface of the semiconductor substrate.
(3) A second electrode is provided on the surface of each first separation groove.
(4) A slit-shaped second separation groove having a depth penetrating at least the window layer and the light-receiving layer is provided in a plurality of inter-array regions formed by a plurality of arrays composed of the plurality of second conductivity type regions, A second electrode is formed on the surface of these second separation grooves.

請求項6の上記の構成に加えて、次のような種々の構成を採用してもよい。
(5)前記半導体基板と前記受光層の間に、第1導電型のバッファ層を設ける。
(6)前記半導体基板の裏面に第2電極を形成する。
(7)前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、前記窓層と受光層を貫通する深さのスリット状の第2分離溝を夫々設け、これらの第2分離溝の表面に第2電極を形成する。
In addition to the above-described configuration of the sixth aspect, the following various configurations may be employed.
(5) A buffer layer of a first conductivity type is provided between the semiconductor substrate and the light receiving layer.
(6) A second electrode is formed on the back surface of the semiconductor substrate.
(7) Slit-like second separation grooves each having a depth penetrating the window layer and the light receiving layer are provided in a plurality of inter-array regions formed by a plurality of arrays composed of the plurality of second conductivity type regions. A second electrode is formed on the surface of the second separation groove.

実施例1に係る受光素子アレイの要部拡大断面図である。3 is an enlarged cross-sectional view of a main part of the light receiving element array according to Embodiment 1. FIG. 実施例2に係る受光素子アレイの要部拡大断面図である。6 is an enlarged cross-sectional view of a main part of a light receiving element array according to Embodiment 2. FIG. 実施例3に係る受光素子アレイの要部拡大断面図である。6 is an enlarged cross-sectional view of a main part of a light receiving element array according to Example 3. FIG. 実施例4に係る受光素子アレイの要部拡大断面図である。10 is an enlarged cross-sectional view of a main part of a light receiving element array according to Example 4. FIG. 実施例5に係る受光素子アレイの要部拡大断面図である。FIG. 10 is an enlarged cross-sectional view of a main part of a light receiving element array according to Example 5. 実施例6に係る受光素子アレイの要部拡大断面図である。10 is an enlarged cross-sectional view of a main part of a light receiving element array according to Example 6. FIG. 実施例7に係る受光素子アレイの要部拡大断面図である。10 is an enlarged cross-sectional view of a main part of a light receiving element array according to Example 7. FIG. 従来例に係る受光素子アレイの要部拡大断面図である。It is a principal part expanded sectional view of the light receiving element array which concerns on a prior art example. 従来例に係る受光素子アレイの要部拡大断面図である。It is a principal part expanded sectional view of the light receiving element array which concerns on a prior art example. 光学的クロストークの説明図である。It is explanatory drawing of optical crosstalk.

以下、本発明を実施するための形態について実施例に基づいて説明する。   Hereinafter, modes for carrying out the present invention will be described based on examples.

先ず、受光素子アレイ1の全体構造について説明する。
図1に示すように、受光素子アレイ1は、光多重通信用の光ファイバから投射される複数波長の光を受光する用途などに適用するものである。この受光素子アレイ1は上面入射型の受光素子アレイである。この受光素子アレイ1は、n型InP半導体基板2(第1導電型の半導体基板)と、この半導体基板2の表面側に形成されたn型InPバッファ層3(第1導電型のバッファ層)と、このバッファ層3の表面側に形成されたn型InGaAs受光層4(第1導電型の受光層)と、この受光層4の表面側に形成されたn型InP窓層5(第1導電型の窓層)とを順次積層して構成され、複数のp型領域6(第2導電型領域)と、複数のp型電極7(第1電極)と、共通のn型電極8(第2電極)と、複数の断面V型の第1分離溝10なども備えている。
First, the overall structure of the light receiving element array 1 will be described.
As shown in FIG. 1, the light receiving element array 1 is applied to an application for receiving light of a plurality of wavelengths projected from an optical fiber for optical multiplex communication. This light receiving element array 1 is a top-incident type light receiving element array. The light receiving element array 1 includes an n-type InP semiconductor substrate 2 (first conductivity type semiconductor substrate) and an n-type InP buffer layer 3 (first conductivity type buffer layer) formed on the surface side of the semiconductor substrate 2. An n-type InGaAs light-receiving layer 4 (first-conductivity-type light-receiving layer) formed on the surface side of the buffer layer 3, and an n-type InP window layer 5 (first first-layer) formed on the surface side of the light-receiving layer 4. A plurality of p-type regions 6 (second conductivity type regions), a plurality of p-type electrodes 7 (first electrodes), and a common n-type electrode 8 ( A second electrode), a plurality of V-shaped first separation grooves 10 and the like.

尚、図1の受光素子アレイ1は、その全体構成の一部分を示しているに過ぎず、複数の受光素子が1次元的に配設された1次元受光素子アレイであっても良いし、複数の受光素子がマトリックス状に配設された2次元受光素子アレイであっても良い。受光素子の数は、4、8、16・・・などの2の累乗個が望ましいが、特に限定する必要はない。本実施例では、「n型」が第1導電型に相当し、「p型」が第2導電型に相当する。尚、図2以降に示されている受光素子アレイ1A〜1Fも、図1と同様に、その全体構成の一部分を示しているに過ぎない。   Note that the light receiving element array 1 in FIG. 1 only shows a part of the entire configuration, and may be a one-dimensional light receiving element array in which a plurality of light receiving elements are arranged one-dimensionally. A two-dimensional light receiving element array in which the light receiving elements are arranged in a matrix may be used. The number of light receiving elements is preferably a power of 2, such as 4, 8, 16,..., But is not particularly limited. In this embodiment, “n-type” corresponds to the first conductivity type, and “p-type” corresponds to the second conductivity type. Note that the light receiving element arrays 1A to 1F shown in FIG. 2 and subsequent figures also show only a part of the entire configuration, as in FIG.

図1に示すように、複数のp型領域6は、窓層5を貫通して受光層4の表面側部分に突入する状態に形成され且つ1次元的又は2次元的なアレイ状配列として離隔状に形成されている。複数のp型領域6は、平面視にて円形に夫々形成されているが、特に円形に限定する必要はなく、平面視正方形や平面視矩形に形成しても良い。   As shown in FIG. 1, the plurality of p-type regions 6 are formed so as to penetrate the window layer 5 and enter the surface side portion of the light receiving layer 4 and are separated as a one-dimensional or two-dimensional array arrangement. It is formed in a shape. The plurality of p-type regions 6 are each formed in a circular shape in plan view, but are not particularly limited to a circular shape, and may be formed in a square shape in plan view or a rectangular shape in plan view.

p型領域6と受光層4との境界部およびp型領域6と窓層5との境界部には、pn接合11が形成されている。このpn接合11の近傍部には空乏層が形成され、この空乏層に光が入射されることで、電子正孔対のキャリアを発生させる。   A pn junction 11 is formed at the boundary between the p-type region 6 and the light receiving layer 4 and at the boundary between the p-type region 6 and the window layer 5. A depletion layer is formed in the vicinity of the pn junction 11, and light is incident on the depletion layer to generate carriers of electron-hole pairs.

各p型電極7は、p型領域6の表面の一部分に形成されている。各p型電極7は、反射防止膜12により窓層5との間で絶縁されている。n型電極8は、半導体基板2の裏面全域に設けられている。   Each p-type electrode 7 is formed on a part of the surface of the p-type region 6. Each p-type electrode 7 is insulated from the window layer 5 by an antireflection film 12. The n-type electrode 8 is provided over the entire back surface of the semiconductor substrate 2.

反射防止膜12は、受光素子アレイ1の表面反射を軽減させて透過率を増加させる為に、複数のp型領域6の表面のうち複数のp型電極7を除く表面残部と、窓層5の表面と、複数の第1分離溝10の表面を覆うように設けられている。   In order to reduce the surface reflection of the light receiving element array 1 and increase the transmittance, the antireflection film 12 and the window layer 5 and the remaining surface of the plurality of p-type regions 6 except for the plurality of p-type electrodes 7. And the surfaces of the plurality of first separation grooves 10 are provided.

図1に示すように、第1分離溝10は、断面V型に形成され、複数のp型領域6からなる複数のアレイが形成する複数のアレイ間領域に、表面側に開放状に設けられている。この第1分離溝10は、窓層5と受光層4とバッファ層3を貫通して半導体基板2に達する深さ(受光素子アレイ1の全厚の約1/2の深さ)に設けられている。第1分離溝10の頂角は、約70度程度に形成される。尚、第1分離溝10が、少なくとも窓層5と受光層4を貫通する深さであることが望ましく、その場合、光クロストークを十分に抑制可能である。また、第1分離溝10に半導体材料を埋め込むように形成しても良い。   As shown in FIG. 1, the first separation groove 10 is formed in a V-shaped cross section, and is provided open on the surface side in a plurality of inter-array regions formed by a plurality of arrays composed of a plurality of p-type regions 6. ing. The first separation groove 10 is provided at a depth that reaches the semiconductor substrate 2 through the window layer 5, the light receiving layer 4, and the buffer layer 3 (a depth that is about ½ of the total thickness of the light receiving element array 1). ing. The apex angle of the first separation groove 10 is formed to be about 70 degrees. It is desirable that the first separation groove 10 has a depth that penetrates at least the window layer 5 and the light receiving layer 4, and in this case, optical crosstalk can be sufficiently suppressed. Further, the first separation groove 10 may be formed so as to be embedded with a semiconductor material.

次に、受光素子アレイ1の製造方法について説明する。
先ず、MOCVD法などにより、n型InP半導体基板2上に、n型InPバッファ層3、n型InGaAs受光層4、n型InP窓層5の順に連続してエピタキシャル成長させる。次に、n型InP窓層5上に、フォトリソグラフィにより1次元的又は2次元的に一定ピッチで複数の開口部を形成する。そして、これら複数の開口部に対してZnを夫々拡散して、複数のp型領域6を形成する。このとき、複数の開口部は、窓層5の半導体結晶の(01−1)面に対して垂直方向に配列されるように形成する。
Next, a method for manufacturing the light receiving element array 1 will be described.
First, the n-type InP buffer layer 3, the n-type InGaAs light receiving layer 4, and the n-type InP window layer 5 are successively grown on the n-type InP semiconductor substrate 2 in this order by MOCVD or the like. Next, a plurality of openings are formed on the n-type InP window layer 5 at a constant pitch one-dimensionally or two-dimensionally by photolithography. Then, Zn is diffused into each of the plurality of openings to form a plurality of p-type regions 6. At this time, the plurality of openings are formed so as to be arranged in a direction perpendicular to the (01-1) plane of the semiconductor crystal of the window layer 5.

次に、断面V型の第1分離溝10を形成する為に、CVD法等により、SiN等の絶縁膜を窓層の上面に成膜し、フォトリソグラフィとエッチングにより第1分離溝10を形成する部分の絶縁膜を除去する。その後、メタノールに臭素を数パーセント程度含有させた溶液にて異方性ウエットエッチングを行い、断面V型の第1分離溝10を形成する。   Next, in order to form the first separation groove 10 having a V-shaped cross section, an insulating film such as SiN is formed on the upper surface of the window layer by CVD or the like, and the first separation groove 10 is formed by photolithography and etching. The portion of the insulating film to be removed is removed. Thereafter, anisotropic wet etching is performed with a solution containing about several percent of bromine in methanol to form a first separation groove 10 having a V-shaped cross section.

次に、受光面上の絶縁膜をエッチングにより除去して、SiN等の絶縁膜をCVD等により、膜厚が無反射条件になるように成膜して反射防止膜12を設ける。そして、p型領域6の上面の少なくとも一部に反射防止膜12を貫通するように、例えばAuZnからなるp型電極7を形成し、n型InP半導体基板2の裏面全域に、例えばAuGeNiからなる共通のn型電極8を形成する。   Next, the insulating film on the light receiving surface is removed by etching, and an insulating film such as SiN is formed by CVD or the like so that the film thickness becomes a non-reflective condition, and the antireflection film 12 is provided. Then, a p-type electrode 7 made of, for example, AuZn is formed so as to penetrate the antireflection film 12 on at least a part of the upper surface of the p-type region 6, and the entire back surface of the n-type InP semiconductor substrate 2 is made of, for example, AuGeNi. A common n-type electrode 8 is formed.

このように、受光素子アレイ1の上部の窓層5はn型InP層であるので、メタノールに臭素を数パーセント程度含有させた溶液を用いて、異方性ウエットエッチングを行うことで、断面V型の第1分離溝10を形成することができる。尚、臭酸或いは臭酸に過酸化水素水を混合した溶液でも上記のような異方性ウエットエッチングを行うことは可能であるが、ここで、特に限定する必要はない。   Thus, since the window layer 5 on the upper side of the light receiving element array 1 is an n-type InP layer, the cross section V can be obtained by performing anisotropic wet etching using a solution containing about several percent of bromine in methanol. A first separation groove 10 of the mold can be formed. It is possible to perform the anisotropic wet etching as described above even with odorous acid or a solution in which hydrogen peroxide is mixed with odorous acid, but there is no particular limitation here.

上記異方性ウエットエッチングを行う場合、半導体基板2の面指数や使用するエッチング液によって結晶面ファセットが異なる。(100)面のInP層に対して、メタノールに臭素数パーセント程度含有させたエッチング液を使用する場合、(01−1)面に垂直方向に対しては、深さ方向に溝幅が小さくなるような順メサ面が形成され、(0−1−1)面に垂直方向に対しては、深さ方向に溝幅が大きくなるような逆メサ面が形成される。   When the anisotropic wet etching is performed, the crystal facet differs depending on the plane index of the semiconductor substrate 2 and the etching solution used. When an etching solution containing about several percent bromine in methanol is used for the (100) plane InP layer, the groove width decreases in the depth direction with respect to the direction perpendicular to the (01-1) plane. Such a forward mesa surface is formed, and with respect to the direction perpendicular to the (0-1-1) plane, a reverse mesa surface is formed such that the groove width increases in the depth direction.

次に、本発明の受光素子アレイ1の作用及び効果について説明する。
先ず、この受光素子アレイ1において、共通のn型電極8を正極に接続し、複数のp型電極7は対応する負極に夫々接続し、受光素子アレイ1を逆バイアス状態になるように接続する。このときのpn接合11の近傍の状態は、そのp型領域6側ではp側空乏層が形成され、その受光層4側にはn側空乏層が形成される。
Next, the operation and effect of the light receiving element array 1 of the present invention will be described.
First, in this light receiving element array 1, a common n-type electrode 8 is connected to a positive electrode, a plurality of p-type electrodes 7 are connected to corresponding negative electrodes, and the light receiving element array 1 is connected so as to be in a reverse bias state. . In this state, a p-side depletion layer is formed on the p-type region 6 side, and an n-side depletion layer is formed on the light receiving layer 4 side.

次に、光が受光素子アレイ1の上面側に入射されると、この光は、反射防止膜12とp型領域6を通りpn接合11の空乏層に入射されて、この空乏層にて電子正孔対のキャリアが発生する。そして、主にn側空乏層で発生した正孔がp型領域6に移動することで、光電流が発生する。   Next, when light is incident on the upper surface side of the light receiving element array 1, the light is incident on the depletion layer of the pn junction 11 through the antireflection film 12 and the p-type region 6. Hole pair carriers are generated. Then, a photocurrent is generated when holes generated mainly in the n-side depletion layer move to the p-type region 6.

しかし、pn接合11に入射する光の大部分は、受光面(上面)に対して垂直に近い角度で入射されるが、その一部は斜めに入射される場合がある。この斜め入射光が、受光層4を透過して漏れ光となると、受光素子アレイ1の上面と下面との間で多重反射を繰り返しながら、隣接するpn接合11の方向に移動してしまう。このとき、断面V型の第1分離溝10は、受光素子アレイ1のpn接合11間に受光層4を貫通するように設けられているので、第1分離溝10の傾斜面により、図1に示す実線のような軌跡で、漏れ光を隣接するp型領域6から離隔する水平方向又は水平に近い横方向へ反射し、pn接合11の近傍部へ再入射させる。   However, most of the light incident on the pn junction 11 is incident at an angle close to perpendicular to the light receiving surface (upper surface), but a part of the light may be incident obliquely. When this obliquely incident light passes through the light receiving layer 4 and becomes leakage light, it moves in the direction of the adjacent pn junction 11 while repeating multiple reflections between the upper surface and the lower surface of the light receiving element array 1. At this time, the first separation groove 10 having a V-shaped cross section is provided so as to penetrate the light receiving layer 4 between the pn junctions 11 of the light receiving element array 1. Is reflected in a horizontal direction or a horizontal direction that is separated from the adjacent p-type region 6 and re-enters the vicinity of the pn junction 11.

また、光が受光面に対して垂直に入射された場合であっても、その一部が受光層4に吸収されずに透過して漏れ光となり、この漏れ光が、受光素子アレイ1の下面で乱反射してしまう可能性がある。このとき、漏れ光は、受光素子アレイ1の上面と下面との間で多重反射を繰り返しながら、隣接するpn接合11の方向に移動してしまうが、第1分離溝10の傾斜面により、漏れ光を入射方向に対してほぼ水平方向に反射し、pn接合11の近傍部へ再入射させる。   Even if the light is incident perpendicular to the light receiving surface, a part of the light is transmitted without being absorbed by the light receiving layer 4 and becomes leaked light. This leaked light is the lower surface of the light receiving element array 1. May cause irregular reflection. At this time, the leaked light moves in the direction of the adjacent pn junction 11 while repeating multiple reflections between the upper surface and the lower surface of the light receiving element array 1, but the leaked light is leaked by the inclined surface of the first separation groove 10. The light is reflected substantially in the horizontal direction with respect to the incident direction, and is incident again on the vicinity of the pn junction 11.

このように、受光素子アレイ1において、複数のp型領域6からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも窓層5と受光層4を貫通する深さの表面側に開放された断面V型の第1分離溝10を夫々設けたので、断面V型の第1分離溝10により、斜め入射された光、多重反射を繰り返す漏れ光や乱反射された漏れ光が発生した場合でも、隣接するp型領域6から離隔する水平方向又は水平に近い横方向へ効率よく反射させて、漏れ光が隣接するpn接合11へ入射するのを低減させることで、光学的クロストークを抑制することができる。   In this manner, in the light receiving element array 1, at least the surface side having a depth penetrating the window layer 5 and the light receiving layer 4 is opened to a plurality of inter-array regions formed by a plurality of p-type regions 6. Since the first V-shaped first separation grooves 10 are provided, even if the first V-shaped first separation grooves 10 generate obliquely incident light, multiple reflection leaked light, or irregularly reflected leak light. The optical crosstalk is suppressed by efficiently reflecting in the horizontal direction separated from the adjacent p-type region 6 in the horizontal direction or the horizontal direction close to the horizontal and reducing the incident of the leaked light to the adjacent pn junction 11. be able to.

また、第1分離溝10が受光層4を貫通する深さに形成されているので、空乏層で発生したキャリアが横方向拡散により隣接するpn接合11へ移動するのを防止して、隣接するpn接合11との間の電気的クロストークを抑制することができる。複数のp型電極7と共通のn型電極8が対向面上に形成され且つ上面側に断面V型の第1分離溝10が形成された上面入射型受光素子アレイ1を提供することができる。   Further, since the first separation groove 10 is formed to a depth penetrating the light receiving layer 4, carriers generated in the depletion layer are prevented from moving to the adjacent pn junction 11 due to lateral diffusion, and are adjacent to each other. Electrical crosstalk with the pn junction 11 can be suppressed. A top-illuminated type light-receiving element array 1 in which a plurality of p-type electrodes 7 and a common n-type electrode 8 are formed on the opposing surface and a first separation groove 10 having a V-shaped cross section is formed on the top surface side can be provided. .

以下では、上記受光素子アレイ1を部分的に変更した種々の実施例及びこれらの実施例を部分的に変更した種々の実施例について説明するが、先行する実施例と同様の構成要素には同様の参照符号を付して説明を省略し、異なる構成要素についてのみ説明する。   In the following, various embodiments in which the light receiving element array 1 is partially changed and various embodiments in which these embodiments are partially changed will be described, but the same components as those in the preceding embodiments are described. The description will be omitted, and only different components will be described.

図2に示すように、本実施例の受光素子アレイ1Aは、前記実施例1の半導体基板2の裏面全域に設けられたn型電極8に代えて、半導体基板2の裏面に部分的に複数のn型電極8Aが設けられ、これら複数のn型電極8Aを除く半導体基板2の裏面残部には、絶縁膜13が形成されている。このため、上面から光が入射され、受光層4を透過した漏れ光は、図2に示す実線の軌跡で、隣接するp型領域6から離隔する水平方向又は水平に近い横方向に反射される。この場合、複数のp型電極7と複数のn型電極8Aが表裏の対向面上に形成され且つ上面側に断面V型の第1分離溝10が形成された上面入射型受光素子アレイ1を提供することができる。   As shown in FIG. 2, the light receiving element array 1 </ b> A of the present example is partially formed on the back surface of the semiconductor substrate 2 in place of the n-type electrode 8 provided on the entire back surface of the semiconductor substrate 2 of the first embodiment. An n-type electrode 8A is provided, and an insulating film 13 is formed on the remaining back surface of the semiconductor substrate 2 excluding the plurality of n-type electrodes 8A. Therefore, the leaked light that is incident from the upper surface and transmitted through the light receiving layer 4 is reflected in a horizontal direction or a horizontal direction that is separated from the adjacent p-type region 6 along the locus of the solid line shown in FIG. . In this case, the top-illuminated light-receiving element array 1 in which a plurality of p-type electrodes 7 and a plurality of n-type electrodes 8A are formed on the front and back facing surfaces and the first separation groove 10 having a V-shaped cross section is formed on the upper surface side. Can be provided.

尚、この受光素子アレイ1において、p型領域6と窓層5の上面の反射防止膜12に代えて絶縁膜を形成し、半導体基板2の裏面の絶縁膜13に代えて反射防止膜を形成することで、下面側から入射可能な受光素子アレイを構成しても良い。このとき、下面から光が入射されて、受光層4で吸収されなかった漏れ光は、図2に示す2点鎖線の軌跡で隣接するp型領域6から離隔する水平方向又は水平方向に近い横方向に反射される。この場合、上面側に断面V型の第1分離溝10が形成された下面入射型受光素子アレイを提供することができる。   In this light receiving element array 1, an insulating film is formed instead of the antireflection film 12 on the upper surface of the p-type region 6 and the window layer 5, and an antireflection film is formed instead of the insulating film 13 on the back surface of the semiconductor substrate 2. By doing so, you may comprise the light receiving element array which can inject from a lower surface side. At this time, the leaked light that is incident from the lower surface and is not absorbed by the light receiving layer 4 is a horizontal direction or a horizontal direction that is separated from the adjacent p-type region 6 along the locus of the two-dot chain line shown in FIG. Reflected in the direction. In this case, it is possible to provide a bottom-illuminated type light receiving element array in which a first separation groove 10 having a V-shaped cross section is formed on the top surface side.

図3に示すように、本実施例の受光素子アレイ1Bにおいては、前記実施例1の各第1分離溝10の表面の反射防止膜12に代えて、断面V字状のn型電極8B(第2電極)が夫々設けられている。p型電極7を除くp型領域6の表面とn型電極8Bを除く窓層5の表面には、反射防止膜12Bが形成されている。半導体基板2の裏面全域には、前記実施例1と同様にn型電極8が形成されている。このため、複数のp型電極7と複数のn型電極8Bが同じ表面側に形成され且つ上面側に断面V型の第1分離溝10が形成された上面入射型受光素子アレイ1Bを提供することができる。   As shown in FIG. 3, in the light receiving element array 1B of this embodiment, instead of the antireflection film 12 on the surface of each first separation groove 10 of the first embodiment, an n-type electrode 8B (V-shaped cross section) A second electrode) is provided. An antireflection film 12B is formed on the surface of the p-type region 6 excluding the p-type electrode 7 and on the surface of the window layer 5 excluding the n-type electrode 8B. An n-type electrode 8 is formed over the entire back surface of the semiconductor substrate 2 as in the first embodiment. Therefore, a top-surface incident type light receiving element array 1B is provided in which a plurality of p-type electrodes 7 and a plurality of n-type electrodes 8B are formed on the same surface side, and a first separation groove 10 having a V-shaped cross section is formed on the top surface side. be able to.

尚、この受光素子アレイ1Bにおいて、p型領域6と窓層5の上面の反射防止膜12Bに代えて絶縁膜を形成し、半導体基板2の裏面全域のn型電極8に代えて又はp型領域6に対応する部分のn型電極8に代えて反射防止膜を形成することで、裏面側から入射可能な受光素子アレイを構成しても良い。この場合、上面側に断面V型の第1分離溝10が形成された下面入射型受光素子アレイを提供することができる。   In this light receiving element array 1B, an insulating film is formed in place of the antireflection film 12B on the upper surface of the p-type region 6 and the window layer 5, and the n-type electrode 8 on the entire back surface of the semiconductor substrate 2 is replaced or p-type. A light receiving element array that can be incident from the back surface side may be formed by forming an antireflection film instead of the n-type electrode 8 corresponding to the region 6. In this case, it is possible to provide a bottom-illuminated type light receiving element array in which a first separation groove 10 having a V-shaped cross section is formed on the top surface side.

図4に示すように、本実施例の受光素子アレイ1Cにおいては、複数のp型領域6に対応する窓層5と受光層4とバッファ層3を貫通する深さのスリット状の第2分離溝15が形成され、このスリット状の第2分離溝15の表面にn型電極8Cが形成されている。このスリット状の第2分離溝15は、p型領域を囲むように平面視C型又は円形に形成されている。p型電極7を除くp型領域6とn型電極8Cを除く窓層と第1分離溝10の表面には、反射防止膜12Cが形成されている。半導体基板2の裏面全域には、前記実施例1と同様にn型電極8が形成されている。このため、複数のp型電極7と複数のn型電極8Cが同じ表面側に形成され且つ上面側に断面V型の第1分離溝10とスリット状の第2分離溝15が形成された上面入射型受光素子アレイ1Cを提供することができる。   As shown in FIG. 4, in the light receiving element array 1 </ b> C of the present embodiment, the slit-shaped second separation having a depth penetrating the window layer 5, the light receiving layer 4, and the buffer layer 3 corresponding to the plurality of p-type regions 6. A groove 15 is formed, and an n-type electrode 8 </ b> C is formed on the surface of the slit-shaped second separation groove 15. The slit-shaped second separation groove 15 is formed in a C shape or a circular shape in plan view so as to surround the p-type region. An antireflection film 12C is formed on the surface of the first separation groove 10 and the window layer excluding the p-type region 6 and the n-type electrode 8C excluding the p-type electrode 7. An n-type electrode 8 is formed over the entire back surface of the semiconductor substrate 2 as in the first embodiment. Therefore, an upper surface in which a plurality of p-type electrodes 7 and a plurality of n-type electrodes 8C are formed on the same surface side, and a V-shaped first separation groove 10 and a slit-shaped second separation groove 15 are formed on the upper surface side. An incident type light receiving element array 1C can be provided.

尚、この受光素子アレイ1Cにおいて、p型領域6と窓層5と第1分離溝10の表面の反射防止膜12Cに代えて絶縁膜を形成し、半導体基板2の裏面全域のn型電極8に代えて又はp型領域6に対応する部分のn型電極8に代えて反射防止膜を形成することで、下面側から入射可能な下面側受光素子アレイを構成しても良い。この場合、上面側に断面V型の第1分離溝10とスリット状の第2分離溝15が形成された下面入射型受光素子アレイを提供することができる。   In this light receiving element array 1C, an insulating film is formed instead of the antireflection film 12C on the surface of the p-type region 6, the window layer 5 and the first separation groove 10, and the n-type electrode 8 on the entire back surface of the semiconductor substrate 2 is formed. Alternatively, an antireflection film may be formed instead of the n-type electrode 8 corresponding to the p-type region 6 to form a lower surface side light receiving element array that can enter from the lower surface side. In this case, it is possible to provide a bottom-illuminated type light receiving element array in which the first separation groove 10 having a V-shaped cross section and the second separation groove 15 having a slit shape are formed on the upper surface side.

先ず、受光素子アレイ1Dの全体構成について説明する。
図5に示すように、受光素子アレイ1Dは、下面入射型の受光素子アレイである。この 受光素子アレイ1Dは、n型InP半導体基板2と、この半導体基板2の表面側に形成されたn型InPバッファ層3と、このバッファ層3の表面側に形成されたn型InGaAs受光層4と、この受光層4の表面側に形成されたn型InP窓層5とを順次積層して構成されている。複数のp型領域6と、複数のp型電極7と、複数のn型電極8Dと、断面倒立V型の複数の第1分離溝14と、スリット状の複数の第2分離溝15なども設けられている。
First, the overall configuration of the light receiving element array 1D will be described.
As shown in FIG. 5, the light receiving element array 1D is a bottom surface incident type light receiving element array. The light receiving element array 1D includes an n-type InP semiconductor substrate 2, an n-type InP buffer layer 3 formed on the surface side of the semiconductor substrate 2, and an n-type InGaAs light-receiving layer formed on the surface side of the buffer layer 3. 4 and an n-type InP window layer 5 formed on the surface side of the light receiving layer 4 are sequentially laminated. A plurality of p-type regions 6, a plurality of p-type electrodes 7, a plurality of n-type electrodes 8 </ b> D, a plurality of inverted V-shaped first separation grooves 14, a plurality of slit-shaped second separation grooves 15, etc. Is provided.

複数のp型領域6は、窓層5を貫通して受光層4の表面側部分に突入する状態に形成され且つ1次元的又は2次元的な配列として離隔状に形成されている。複数のp型電極7は、これら複数のp型領域6の表面の少なくとも一部に夫々設けられている。このp型電極7は、絶縁膜13Dにより窓層5と絶縁されている。複数のp型領域6と受光層4との各境界部には、pn接合11が形成されている。尚、p型電極7は、本実施例ではp型領域に部分的に設けられているが、窓層5と電気的に接触しない程度にp型領域6の表面全域に設けても良い。   The plurality of p-type regions 6 are formed in a state of penetrating the window layer 5 and entering the surface side portion of the light receiving layer 4 and are formed in a spaced manner as a one-dimensional or two-dimensional array. The plurality of p-type electrodes 7 are respectively provided on at least a part of the surfaces of the plurality of p-type regions 6. The p-type electrode 7 is insulated from the window layer 5 by the insulating film 13D. A pn junction 11 is formed at each boundary between the plurality of p-type regions 6 and the light receiving layer 4. In this embodiment, the p-type electrode 7 is partially provided in the p-type region. However, the p-type electrode 7 may be provided over the entire surface of the p-type region 6 so as not to be in electrical contact with the window layer 5.

第1分離溝14は、複数のp型領域6からなる複数のアレイが形成する複数のアレイ間領域の裏面側に断面倒立V型に形成され、半導体基板2の裏面側に開放状に設けられている。第1分離溝14の頂角は、約70度程度に形成される。反射防止膜12Dは、複数の第1分離溝14の裏面を含む半導体基板2の裏面全域に設けられている。   The first separation groove 14 is formed in an inverted V-shaped cross section on the back side of a plurality of inter-array regions formed by a plurality of arrays composed of a plurality of p-type regions 6, and is provided open on the back side of the semiconductor substrate 2. ing. The apex angle of the first separation groove 14 is formed to be about 70 degrees. The antireflection film 12 </ b> D is provided over the entire back surface of the semiconductor substrate 2 including the back surfaces of the plurality of first separation grooves 14.

第2分離溝15は、スリット状に形成されている。第2分離溝15は、複数のp型領域6からなる複数のアレイが形成する複数のアレイ間領域に、p型領域6を囲むように平面視C型又は円形に形成されている。この第2分離溝15は、窓層5と受光層4とバッファ層3を貫通する深さに設けられている。n型電極8Dは、これら各第2分離溝15の表面に断面U形に形成されている。p型電極7を除くp型領域6の上面とn型電極8Dを除く窓層5の上面には、絶縁膜13Dが形成されている。尚、第2分離溝15は、少なくとも窓層5と受光層4を貫通することが望ましい。第1,第2分離溝14,15に半導体材料を埋め込んだ構造にしても良い。   The second separation groove 15 is formed in a slit shape. The second separation groove 15 is formed in a C-shape or a circular shape in plan view so as to surround the p-type region 6 in a plurality of inter-array regions formed by a plurality of arrays composed of the plurality of p-type regions 6. The second separation groove 15 is provided at a depth that penetrates the window layer 5, the light receiving layer 4, and the buffer layer 3. The n-type electrode 8D is formed in a U-shaped cross section on the surface of each second separation groove 15. An insulating film 13D is formed on the upper surface of the p-type region 6 excluding the p-type electrode 7 and the upper surface of the window layer 5 excluding the n-type electrode 8D. The second separation groove 15 desirably penetrates at least the window layer 5 and the light receiving layer 4. A structure in which a semiconductor material is embedded in the first and second separation grooves 14 and 15 may be employed.

次に、本発明の受光素子アレイ1Dの作用及び効果について説明する。
先ず、逆バイアス状態の受光素子アレイ1Dの下面側に、光が入射されると、この光は、反射防止膜12Dと半導体基板2とバッファ層3を透過してpn接合11の空乏層に入射されて、この空乏層にて電子正孔対のキャリアが発生する。そして、主にn側空乏層で発生した正孔がp型領域6に移動することで、光電流が発生する。
Next, functions and effects of the light receiving element array 1D of the present invention will be described.
First, when light is incident on the lower surface side of the light receiving element array 1D in the reverse bias state, this light is transmitted through the antireflection film 12D, the semiconductor substrate 2, and the buffer layer 3, and is incident on the depletion layer of the pn junction 11. Then, carriers of electron-hole pairs are generated in this depletion layer. Then, a photocurrent is generated when holes generated mainly in the n-side depletion layer move to the p-type region 6.

しかし、pn接合11に入射する光の大部分は、受光面(下面)に対して垂直に近い角度で入射されるが、その一部は斜めに入射される場合がある。この斜め入射光が、受光層4に吸収されずに漏れ光となると、受光素子アレイ1Dの上面と下面との間で多重反射を繰り返しながら、隣接するpn接合11の方向に移動する。断面倒立V型の第1分離溝14は、受光素子アレイ1Dのpn接合11間に設けられているので、第1分離溝14の傾斜面により、図5に示す2点鎖線の軌跡で、漏れ光を隣接するp型領域6から離隔する水平方向又は水平方向に近い横方向に反射する。   However, most of the light incident on the pn junction 11 is incident at an angle close to perpendicular to the light receiving surface (lower surface), but some of the light may be incident obliquely. When this obliquely incident light becomes leaked light without being absorbed by the light receiving layer 4, it moves in the direction of the adjacent pn junction 11 while repeating multiple reflections between the upper surface and the lower surface of the light receiving element array 1D. Since the first separation groove 14 having an inverted V-shaped cross section is provided between the pn junctions 11 of the light receiving element array 1D, the inclined surface of the first separation groove 14 causes a leak along a two-dot chain line shown in FIG. The light is reflected in the horizontal direction that is separated from the adjacent p-type region 6 or in the lateral direction close to the horizontal direction.

また、光が受光面に対して垂直に入射された場合であっても、その一部が受光層に吸収されずに透過して漏れ光となり、この漏れ光が、受光素子アレイ1Dの上面で乱反射してしまう可能性がある。このとき、漏れ光は、受光素子アレイ1Dの上面と下面との間で多重反射を繰り返しながら、隣接するpn接合11の方向に移動してしまうが、第1分離溝14の傾斜面により、漏れ光を隣接するp型領域6から離隔する水平方向又は水平方向に近い横方向に反射する。   Even when light is incident perpendicular to the light receiving surface, a part of the light is transmitted without being absorbed by the light receiving layer and becomes leaked light. This leaked light is reflected on the upper surface of the light receiving element array 1D. There is a possibility of irregular reflection. At this time, the leaked light moves in the direction of the adjacent pn junction 11 while repeating multiple reflection between the upper surface and the lower surface of the light receiving element array 1D. However, the leaked light is leaked by the inclined surface of the first separation groove 14. The light is reflected in the horizontal direction that is separated from the adjacent p-type region 6 or in the lateral direction close to the horizontal direction.

このように、受光素子アレイ1Dにおいて、半導体基板2の裏面に開放された断面倒立V型の複数の第1分離溝14を夫々設けたので、この第1分離溝14により、斜め入射された光、垂直方向に多重反射を繰り返す光や乱反射された漏れ光を、隣接するp型領域6から離隔する水平方向又は水平に近い横方向へ効率よく反射させ、隣接するpn接合11へ入射する光を低減させることで、光学的クロストークを抑制することができる。   As described above, in the light receiving element array 1D, the plurality of first V-shaped first separation grooves 14 opened on the back surface of the semiconductor substrate 2 are provided, so that light incident obliquely by the first separation grooves 14 is provided. The light that repeats multiple reflections in the vertical direction and the irregularly reflected leakage light are efficiently reflected in the horizontal direction or the horizontal direction that is separated from the adjacent p-type region 6, and the light incident on the adjacent pn junction 11 is reflected. By reducing it, optical crosstalk can be suppressed.

また、スリット状の第2分離溝15により、空乏層で発生したキャリアが横方向拡散により隣接するpn接合11へ移動するのを防止し、隣接するpn接合11との間の電気的クロストークを抑制することができる。さらに、断面倒立V型の第1分離溝14が下面側に形成された下面入射型受光素子アレイ1Dを提供することができる。   In addition, the slit-shaped second separation groove 15 prevents carriers generated in the depletion layer from moving to the adjacent pn junction 11 due to lateral diffusion, thereby preventing electrical crosstalk between the adjacent pn junctions 11. Can be suppressed. Furthermore, it is possible to provide a bottom-illuminated light-receiving element array 1D in which the inverted V-shaped first separation groove 14 is formed on the bottom surface side.

次に、前記実施例5を部分的に変更した変更例について説明する。
図5に示す受光素子アレイ1Dにおいて、半導体基板2の裏面全域の反射防止膜12Dに代えてn型電極を形成し、p型領域6と窓層5の上面の絶縁膜13Dに代えて反射防止膜を形成することで、上面側から入射可能な上面入射型受光素子アレイを構成しても良い。このとき、上面から光が入射されて、受光層4を透過した漏れ光は、図5に示す実線の軌跡で水平方向に反射される。この場合、断面倒立V型の第1分離溝14が下面側にスリット状の第2分離溝15が上面側に形成された上面入射型受光素子アレイを提供することができる。
Next, a modified example in which the fifth embodiment is partially modified will be described.
In the light receiving element array 1 </ b> D shown in FIG. 5, an n-type electrode is formed instead of the antireflection film 12 </ b> D on the entire back surface of the semiconductor substrate 2, and an antireflection film is substituted for the p-type region 6 and the insulating film 13 </ b> D on the upper surface of the window layer 5. By forming a film, a top-illuminated light-receiving element array that can be incident from the top surface side may be configured. At this time, the leaked light that is incident from the upper surface and transmitted through the light receiving layer 4 is reflected in the horizontal direction along the locus of the solid line shown in FIG. In this case, it is possible to provide a top-illuminated type light receiving element array in which the inverted first V-shaped separation groove 14 is formed on the lower surface side and the slit-shaped second separation groove 15 is formed on the upper surface side.

図6に示すように、本実施例の受光素子アレイ1Eにおいて、複数の第1分離溝14Eは、各pn接合11の下側に位置するように且つ半導体基板2の裏面側に開放するように夫々設けられている。第1分離溝14Eの裏面を含む半導体基板2の裏面全域にはn型電極18が形成され、p型電極7を除くp型領域6の上面残部とn型電極8Dを除く窓層5の上面残部には、反射防止膜12Eが形成されている。それ以外の構成は、前記実施例5と同様である。このため、断面倒立V型の第1分離溝14Eがpn接合11の下側に夫々形成された上面入射型受光素子アレイ1Eを提供することができる。尚、複数の第1分離溝14Eが各pn接合11の下側に位置するように形成される構成は、以下の実施例の構成にも適用可能であるが、上面入射型の受光素子アレイに限定される。   As shown in FIG. 6, in the light receiving element array 1 </ b> E of the present embodiment, the plurality of first separation grooves 14 </ b> E are located below each pn junction 11 and open to the back side of the semiconductor substrate 2. Each is provided. An n-type electrode 18 is formed over the entire back surface of the semiconductor substrate 2 including the back surface of the first separation groove 14E, and the upper surface remaining of the p-type region 6 excluding the p-type electrode 7 and the upper surface of the window layer 5 excluding the n-type electrode 8D. An antireflection film 12E is formed in the remaining part. Other configurations are the same as those in the fifth embodiment. Therefore, it is possible to provide the top-illuminated type light receiving element array 1E in which the inverted V-shaped first separation grooves 14E are formed below the pn junction 11, respectively. The configuration in which the plurality of first separation grooves 14E are formed below the pn junctions 11 can be applied to the configurations of the following embodiments. Limited.

図7に示すように、本実施例の受光素子アレイ1Fにおいては、半導体基板2の裏面の各p型領域6に対応する部分に反射防止膜12Fが部分的に形成され、前記実施例5の第2分離溝15の表面に形成されたn型電極8Dに代えて、複数の第1分離溝14の裏面を含む半導体基板2の反射防止膜12Fを除く裏面残部にn型電極8Fが設けられている。絶縁膜13Fは、p型電極7を除くp型領域6の表面と窓層5の表面と第2分離溝15の表面に形成されている。このため、複数のp型電極7とn型電極8Fが対向面上に形成され且つ第1分離溝14が下面側に第2分離溝15が上面側に形成された下面入射型受光素子アレイ1Fを提供することができる。   As shown in FIG. 7, in the light receiving element array 1 </ b> F of the present embodiment, an antireflection film 12 </ b> F is partially formed in a portion corresponding to each p-type region 6 on the back surface of the semiconductor substrate 2. Instead of the n-type electrode 8D formed on the surface of the second separation groove 15, an n-type electrode 8F is provided on the remaining back surface of the semiconductor substrate 2 including the back surface of the plurality of first separation grooves 14 except for the antireflection film 12F. ing. The insulating film 13F is formed on the surface of the p-type region 6 excluding the p-type electrode 7, the surface of the window layer 5, and the surface of the second separation groove 15. Therefore, the bottom-illuminated light receiving element array 1F in which a plurality of p-type electrodes 7 and n-type electrodes 8F are formed on the opposing surface, the first separation groove 14 is formed on the lower surface side, and the second separation groove 15 is formed on the upper surface side. Can be provided.

尚、この受光素子アレイ1Fにおいて、半導体基板2の裏面側の反射防止膜12Fに代えてn型電極を形成し、p型領域6と窓層5と第2分離溝15の表面の絶縁膜13Fに代えて反射防止膜を形成することで、上面側から入射可能な受光素子アレイを構成するようにしても良い。この場合、第1分離溝14が下面側に第2分離溝15が上面側に形成された上面入射型受光素子アレイを提供することができる。   In this light receiving element array 1F, an n-type electrode is formed instead of the antireflection film 12F on the back surface side of the semiconductor substrate 2, and an insulating film 13F on the surface of the p-type region 6, the window layer 5, and the second separation groove 15 is formed. Alternatively, an antireflection film may be formed to constitute a light receiving element array that can be incident from the upper surface side. In this case, it is possible to provide an upper surface incident type light receiving element array in which the first separation groove 14 is formed on the lower surface side and the second separation groove 15 is formed on the upper surface side.

ここで、前記実施例を部分的に変更する例について説明する。
[1]前記実施例において、n側InP半導体基板に代えて、半絶縁性基板(Si−InP基板)を採用することも可能である。この場合、n側InPバッファ層の代わりにn+型InP層を形成する。
[2]前記実施例において、第1導電型を「n型」に、第2導電型を「p型」にしているが、これとは逆に、第1導電型を「p型」に、第2導電型を「n型」となるように受光素子アレイを製造しても良い。
[3]その他、当業者であれば、本発明の趣旨を逸脱することなく、前記実施例の種々の変更を付加した形態で実施可能で、本発明はそのような変更形態を包含するものである。
Here, the example which changes the said Example partially is demonstrated.
[1] In the above embodiment, a semi-insulating substrate (Si-InP substrate) can be adopted instead of the n-side InP semiconductor substrate. In this case, an n + type InP layer is formed instead of the n-side InP buffer layer.
[2] In the above embodiment, the first conductivity type is “n-type” and the second conductivity type is “p-type”. Conversely, the first conductivity type is “p-type”. The light receiving element array may be manufactured so that the second conductivity type is “n-type”.
[3] In addition, those skilled in the art can implement the present invention in various forms added with various modifications without departing from the spirit of the present invention, and the present invention includes such modifications. is there.

本発明は、光通信用、1次元又は2次元センサ用の種々の受光素子アレイや、他の用途に用いられる種々の受光素子アレイに利用することができる。   The present invention can be used for various light receiving element arrays for optical communication, one-dimensional or two-dimensional sensors, and various light receiving element arrays used for other applications.

1,1A〜1F 受光素子アレイ
2 半導体基板
3 バッファ層
4 受光層
5 窓層
6 p型領域
7 p型電極
8,8A〜8D n型電極
10,14,14E 第1分離溝
11 pn接合
15 第2分離溝
1, 1A to 1F Light receiving element array 2 Semiconductor substrate 3 Buffer layer 4 Light receiving layer 5 Window layer 6 p-type region 7 p-type electrode 8, 8A to 8D n-type electrode 10, 14, 14E First separation groove 11 pn junction 15 1st 2 separation grooves

Claims (9)

第1導電型の半導体基板と、この半導体基板の表面側に形成した第1導電型の受光層と、この受光層の表面側に形成した第1導電型の窓層と、この窓層を貫通して受光層の表面側に突入する状態に形成され且つ1次元的または2次元的な配列として離隔状に形成された複数の第2導電型領域と、これら複数の第2導電領域の表面の少なくとも一部に夫々設けた複数の第1電極とを有する受光素子アレイにおいて、
前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも前記窓層と受光層を貫通する深さの表面側に開放された断面V型の第1分離溝を夫々設けた、
ことを特徴とする受光素子アレイ。
A first conductivity type semiconductor substrate, a first conductivity type light-receiving layer formed on the surface side of the semiconductor substrate, a first conductivity type window layer formed on the surface side of the light-receiving layer, and penetrating through the window layer A plurality of second conductivity type regions formed so as to protrude into the surface side of the light receiving layer and spaced apart as a one-dimensional or two-dimensional array, and the surfaces of the plurality of second conductive regions In a light receiving element array having a plurality of first electrodes provided at least in part,
A first separation groove having a V-shaped cross section opened to a surface side having a depth penetrating at least the window layer and the light receiving layer in a plurality of inter-array regions formed by a plurality of arrays of the plurality of second conductivity type regions. Respectively,
A light receiving element array.
前記半導体基板と前記受光層の間に、第1導電型のバッファ層を設けたことを特徴とする請求項1に記載の受光素子アレイ。   The light receiving element array according to claim 1, wherein a buffer layer of a first conductivity type is provided between the semiconductor substrate and the light receiving layer. 前記半導体基板の裏面に1又は複数の第2電極を設けたことを特徴とする請求項1又は2に記載の受光素子アレイ。   The light receiving element array according to claim 1, wherein one or a plurality of second electrodes are provided on a back surface of the semiconductor substrate. 前記各第1分離溝の表面に第2電極を設けたことを特徴とする請求項1又は2に記載の受光素子アレイ。   The light receiving element array according to claim 1, wherein a second electrode is provided on a surface of each of the first separation grooves. 前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、少なくとも前記窓層と受光層を貫通する深さのスリット状の第2分離溝を夫々設け、これらの第2分離溝の表面に第2電極を形成したことを特徴とする請求項1又は2に記載の受光素子アレイ。   A plurality of inter-array regions formed by the plurality of arrays of the plurality of second conductivity type regions are provided with slit-shaped second separation grooves each having a depth penetrating at least the window layer and the light-receiving layer. The light receiving element array according to claim 1, wherein a second electrode is formed on a surface of the two separation grooves. 第1導電型の半導体基板と、この半導体基板の表面側に形成した第1導電型の受光層と、この受光層の表面側に形成した第1導電型の窓層と、この窓層を貫通して受光層の表面側に突入する状態に形成され且つ1次元的または2次元的な配列として離隔状に形成された複数の第2導電型領域と、これら複数の第2導電領域の表面の少なくとも一部に夫々設けた複数の第1電極とを有する受光素子アレイにおいて、
前記半導体基板の裏面側に解放された断面倒立V型の複数の第1分離溝を夫々設けた、
ことを特徴とする受光素子アレイ。
A first conductivity type semiconductor substrate, a first conductivity type light-receiving layer formed on the surface side of the semiconductor substrate, a first conductivity type window layer formed on the surface side of the light-receiving layer, and penetrating through the window layer A plurality of second conductivity type regions formed so as to protrude into the surface side of the light receiving layer and spaced apart as a one-dimensional or two-dimensional array, and the surfaces of the plurality of second conductive regions In a light receiving element array having a plurality of first electrodes provided at least in part,
A plurality of first V-shaped first separation grooves opened on the back side of the semiconductor substrate,
A light receiving element array.
前記半導体基板と前記受光層の間に、第1導電型のバッファ層を設けたことを特徴とする請求項6に記載の受光素子アレイ。   The light receiving element array according to claim 6, wherein a buffer layer of a first conductivity type is provided between the semiconductor substrate and the light receiving layer. 前記半導体基板の裏面に第2電極を形成したことを特徴とする請求項6又は7に記載の受光素子アレイ。   The light receiving element array according to claim 6 or 7, wherein a second electrode is formed on a back surface of the semiconductor substrate. 前記複数の第2導電型領域からなる複数のアレイが形成する複数のアレイ間領域に、前記窓層と受光層を貫通する深さのスリット状の第2分離溝を夫々設け、これらの第2分離溝の表面に第2電極を形成したことを特徴とする請求項6又は7に記載の受光素子アレイ。   Slit-like second separation grooves each having a depth penetrating the window layer and the light-receiving layer are provided in a plurality of inter-array regions formed by a plurality of arrays of the plurality of second conductivity type regions, respectively. The light receiving element array according to claim 6 or 7, wherein a second electrode is formed on a surface of the separation groove.
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