JP2011257924A - Testing device and test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate detection of a path which has not been passed through by tracing a jump result of a conditional instruction of a program while writing the result in RAM.SOLUTION: The following improvements have been made on the basis of the conventional micro program tracer disclosed in Patent Application Publication No. H5-224990: For a RAM1, a 1c of the RAM1 has been added, which stores flag information indicating that a jump has been performed to a branch destination of a branch instruction if a branch has been established in the branch instruction. A signal 20 indicating that a branch has been established and an address for a branch destination has been determined is output from a branch control 5 to a buffer register 7 and is also connected to the 1c of the RAM1 as a write enable signal. A signal line 21 is output from the buffer register 7 and connected to the 1c of the RAM1. The 1c added to the RAM1 can be read from a signal line 18 which reads contents of the RAM1. Furthermore, detection of a path which has not been passed through is performed from RAM1 information including a RAM which has been added to the RAM1.

Description

  The present invention relates to a program test apparatus and a test method in microcomputer program development.

  In recent years, various quality assurances have been required in microcomputer program development. Therefore, when a program is tested, an index of how much the test is being performed is required. As one of them, C0 coverage is used. C0 coverage is an index indicating whether or not a program instruction or branch has been executed at least once during a test.

  As a method of realizing C0 coverage, there is a method of acquiring C0 coverage by acquiring an address (address) of an executed instruction as trace information and analyzing the information.

  However, when performing parallel processing with a high-speed clock found in current high-performance microcomputers, if trace acquisition is performed in real time, address information to be traced increases, and the transfer speed also increases. However, even if it is attempted to increase the number of terminals that output trace information, there are many cases where the number of terminals cannot be increased due to the reduction in the chip size of the microcomputer and the cost reduction. Therefore, the executed address information may not be output as trace information. Therefore, a method of measuring the C0 coverage by reducing the trace information using a branch trace that traces only the branch instruction has been proposed.

  As a method for acquiring C0 coverage without leaving trace information as it is, a method as disclosed in Japanese Patent Application Laid-Open No. 5-224990 has been proposed.

  FIG. 1 shows the configuration of a conventional microprogram tracer. The conventional microprogram tracer includes RAM1, RAM2, MIR3, instruction decoder 4, branch control module 5, MAR6, buffer register 7, STR8, and logic gate 19.

  The RAM 1 is a RAM (Random Access Memory) for storing information indicating whether a branch instruction of a program is taken or not taken. The RAM 2 is a RAM for storing a program to be traced. The MIR3 is a macro instruction register that holds an instruction to be executed. The instruction decoder 4 decodes the instruction of the MIR 3 and determines whether it is a branch instruction. The branch control module 5 determines whether or not a branch is taken when the instruction to be executed is a branch instruction, and determines an address to be executed next. MAR 6 is a macro instruction address register that holds the address of the instruction currently being executed. The buffer register 7 holds information on whether or not the branch instruction is established. The STR 8 is a status register that holds an operation result and the like necessary for determining the condition of the branch instruction. The logic gate 19 is a logic gate.

  The MAR 6 that stores the execution address of the program gives an address to the RAM 2. The MIR 3 reads the contents (execution address). The instruction decoder 4 decodes the instruction (execution address) read to the MIR 3. When the decoding result is a branch instruction, the branch control module 5 compares the branch condition of the branch instruction with the status of the operation result of STR8, and when the branch is established, sends the branch destination address to MAR6. When the branch is established, the branch control module 5 sends a branch establishment signal to the buffer register 7 holding the information on the failure of establishment of the branch through the signal line 14 and the logic gate 19 of the RAM 1. The branch establishment signal is a signal indicating that a branch has been established.

  FIG. 2 is a diagram for explaining the contents of the RAM 1 and RAM 2. In FIG. 2, (a) shows the contents of the RAM 1 after execution of tracing. (B) is a coding list of programs in the RAM 2. A conventional microprogram tracer inputs a program address from the MAR 6 to the RAM 2 via the signal line 9 and reads a program from the RAM 2 via the signal line 10. The conventional microprogram tracer stores the read program in the MIR 3 and sends it to the decoder 4. The decoder 4 decodes the program and gives an instruction to each module in the processor according to the contents of the program. If the decoded instruction is not a branch instruction, the branch control module 5 generates an address obtained by adding 1 to the address of the MAR 6 and sets (sets) it in the MAR 6.

  When the decoded program is a branch instruction, the decoder 4 sends a branch instruction detection signal to the RAM 1 via the signal line 11 and sends a branch condition of the branch instruction to the branch control module 5 via the signal line 12. .

  The branch control module 5 compares the branch condition with the contents of the STR 8 and determines whether or not the branch is established.

  When the branch is established, the branch control module 5 outputs a branch establishment signal via the signal line 14 and sends it to the buffer register 7 and the gate 19 of the RAM 1. A signal output via the signal line 11 and the signal line 14 turns on (enables) a write enable (WE: Write Enable) on the signal line 17a via the gate 19. The contents of the buffer register 7 are written via the signal line 15 into the bit position of 1a of the RAM 1 corresponding to the address set in the MAR 6 via the signal line 13. Thereafter, the branch control module 5 sets the branch destination address in the MAR 6 via the signal line 13. Thereby, the operation when the branch is established is completed.

  If the branch is not established, the branch control module 5 does not output a branch establishment signal via the signal line 14. Therefore, the write enable (WE) on the signal line 17b is turned on via the gate 19, and the inversion of the contents of the buffer register 7 is written into the bit position 1b of the RAM 1. Thereafter, the branch control module 5 generates an address obtained by adding 1 to the address of the MAR 6 and sets it in the MAR 6. Thereby, the operation when the branch is not established is completed.

  As described above, each time a branch instruction is executed, writing to the RAM 1 is performed. When the branch is established, the bit 1a of the RAM 1 is turned on, and when the branch is not established, Bit 1b of RAM1 is turned on.

  Next, an operation in which the microcomputer or other processor actually reads the contents of the RAM 1 and detects a non-passing path will be described. The contents of the RAM 1 can be read out of the processor via the signal line 18. FIG. 2A shows an example in which the contents of the RAM 1 are read out. In the RAM 1, 1a is a J system (branch establishment flag) and 1b is an NJ system (branch establishment failure flag).

  The meaning of this flag is that when the branch establishment flag (1a) is 1, the instruction executed next to this branch instruction is interpreted as a branch destination instruction, not an instruction at the next address.

  If the branch incomplete flag (1b) is 1, the instruction executed next to this branch instruction is interpreted as an instruction at the next address.

  If both the branch established (1a) and branch unestablished (1b) flags are 1, the next executed instruction is the instruction at the next address of the branch instruction and the branch destination instruction. After that, it interprets both execution instructions. By repeating this until the end, the instructions executed and not executed in the program become clear, and the C0 coverage can be calculated.

  FIG. 2B is a list of programs executed at that time. It is assumed that there are no other branch instructions between addresses A to B and addresses B to C.

  First, in the jump instruction (branch instruction) at address A, it can be seen from FIG. 2A that both the branch establishment and non-establishment operations were performed because both the branch establishment flag and the branch establishment failure flag are set. Similarly, it can be seen that the jump instruction at address B only operated for branch establishment, and the jump instruction at address C only operated for branch failure.

  If a non-passing path is detected based on this information, first, since the branch of A address may not be established, it is determined that the instruction next to A address is executed and executed up to B address. Further, the branch destination of address A branches to address B when the program is analyzed. In this case, analysis up to address B is omitted because it can be seen that it has already been executed.

  Next, since address B is operating only for branch establishment, the branch destination of the branch instruction at address B is determined to be address C by analyzing the program list, and the instructions from address B to address C are: Judge that it is not executed.

  Next, since the address C operates only when the branch is not established, it is determined that the instruction after the address C has been executed.

  In this way, a method is proposed in which a static analysis of the program list (RAM2) and the information on whether or not the branch is taken (RAM1) is repeated to detect a non-passing path.

  Further, in Patent Document 2 (Japanese Patent Laid-Open No. 7-262047), a storage device that holds the address of a branch instruction and the branch destination address of the instruction is prepared instead of the flag indicating whether a branch is taken or not taken. A method is proposed in which a non-passed path can be detected by reading and tracing the information in order.

  In Patent Document 1, whether or not a branch is taken is dynamically analyzed (recorded), and the branch destination address is obtained by statically analyzing the program. However, the branch instruction of the microcomputer may use a branch instruction whose branch destination is determined by the value of the register when the branch instruction is executed, such as a jump to the address stored in the register. In some cases, the branch destination address is not known even after analysis.

  FIG. 3 shows an example of the program. In this example, the branch destination address of the branch instruction at address C changes depending on the result of instruction execution, that is, whether it branches to address D or E.

  In a conventional example such as Patent Document 1, a method for detecting a non-passing path when a program as shown in FIG. 3 is used is not described. If an attempt is made to detect a non-passing path of this program, it may not be possible to determine whether the branch instruction at address C has branched to either address D or E, the instruction execution cannot be traced, and there is a non-passing path. May not be detected.

  Further, Patent Document 2 describes a method of acquiring a branch destination address. However, since information on the failure of branching is not obtained, when the program as shown in FIG. Although it can be seen that the branching from address A to address B, it may not be possible to determine whether addresses A to B have been executed.

  In the conventional examples such as these two patent documents, there may be a problem that the actual execution result and the acquired C0 coverage result do not match (incorrect).

JP-A-5-224990 Japanese Patent Laid-Open No. 7-262047

  The present invention is characterized in that a branch establishment / non-establishment and a branch destination are held in the processor as a branch result of a branch instruction of the microprogram, and the execution result of the microprogram is observed by reading the held branch result. .

  A test apparatus according to the present invention includes a first RAM having the same address space as a program address, a 3-bit width, a second RAM for storing a program, and a conditional branch instruction for the program The execution detection means for detecting the execution of the instruction, the buffer register for holding the result of whether or not the branch instruction has branched, and the execution status of the branch instruction of the program sent out by the execution detection means And a gate for classifying and writing to the first RAM.

  The execution detection means decodes the microinstruction read from the second RAM to the microinstruction register, outputs a signal indicating whether or not the instruction is a branch instruction and a branch condition, and obtains the output from the decoder. A branch control module for comparing the determined branch condition with the contents of the status register, determining whether or not the branch is taken, and sending the determination result to the buffer register and the gate.

  The branch control module writes a signal indicating to the buffer register that the branch has been established and the branch destination address has been established, and a signal to indicate that the branch has been established and the branch destination address has been established. Bits of the first RAM corresponding to the branch destination address set in the microinstruction register by turning on the write enable of the first RAM according to the means for sending to the first RAM as the enable signal and the write enable signal Means for writing a buffer register value to the location.

  By recording the branch destination information, it is possible to grasp all the branch destinations including the branch instruction whose branch destination is determined by the register value at the time of execution of the branch instruction.

It is a block diagram of the conventional microprogram tracer. It is a figure for demonstrating the relationship and content of RAM. It is a figure which shows the example of a program. It is a block diagram of the test apparatus of this invention. It is an example of the value of RAM acquired in this invention. It is a flowchart of a non-passing path detection process in the present invention.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 4 is a configuration example of the test apparatus of the present invention. The test apparatus of the present invention shown in FIG. 4 includes a RAM 1, a RAM 2, an MIR 3, an instruction decoder 4, a branch control module 5, a MAR 6, a buffer register 7, a STR 8, and a logic gate 19.

  The RAM 1 is a RAM (Random Access Memory) for storing information indicating whether a branch instruction of a program is taken or not taken. The RAM 2 is a RAM for storing a program to be traced. The MIR3 is a macro instruction register that holds an instruction to be executed. The instruction decoder 4 decodes the instruction of the MIR 3 and determines whether it is a branch instruction. The branch control module 5 determines whether or not a branch is taken when the instruction to be executed is a branch instruction, and determines an address to be executed next. MAR 6 is a macro instruction address register that holds the address of the instruction currently being executed. The buffer register 7 holds information on whether or not the branch instruction is established. The STR 8 is a status register that holds an operation result and the like necessary for determining the condition of the branch instruction. The logic gate 19 is a logic gate.

  The MAR 6 that stores the execution address of the program gives an address to the RAM 2. The MIR 3 reads the contents (execution address). The instruction decoder 4 decodes the instruction (execution address) read to the MIR 3. When the decoding result is a branch instruction, the branch control module 5 compares the branch condition of the branch instruction with the status of the operation result of STR8, and when the branch is established, sends the branch destination address to MAR6. When the branch is established, the branch control module 5 sends a branch establishment signal to the buffer register 7 holding the information on the failure of establishment of the branch through the signal line 14 and the logic gate 19 of the RAM 1. The branch establishment signal is a signal indicating that a branch has been established.

  The test apparatus of the present invention shown in FIG. 4 is based on the conventional microprogram tracer shown in FIG. 1 and adds a RAM 1c, a signal line 20, and a signal line 21, and connects the signal line 18 to the RAM 1 1c. It is a thing. Note that the test apparatus of the present invention shown in FIG. 4 may be a microcomputer itself or an information processing apparatus externally connected to the microcomputer. That is, the test apparatus of the present invention may be a module mounted on the microcomputer itself or a semiconductor device externally connected to the microcomputer.

  In the present invention, on the basis of the conventional microprogram tracer shown in FIG. 1, the RAM 1 is stored in the RAM 1 with flag information indicating that the jump is made as the branch destination of the instruction when the branch of the branch instruction is established. Added.

  In the present invention, based on the conventional microprogram tracer shown in FIG. 1, the branch control 5 sends a signal indicating that the branch is established and the branch destination address is determined via the signal line 20 to the buffer register 7. Further, it is sent to 1c of the RAM 1 as a write enable signal. In FIG. 4, the signal line 20 branches from a signal line (a signal line provided in parallel with the signal line 14) connecting the branch control module 5 and the buffer register 7, and is connected to 1 c of the RAM 1. The signal line 14 is a signal line for outputting a signal (branch establishment signal) indicating that the branch has been established. The signal line 20 is a signal line for outputting a signal indicating that the branch destination address has been determined. Therefore, the signal line 14 and the signal line 20 are independent of each other.

  In the present invention, based on the conventional microprogram tracer shown in FIG. 1, a signal is output from the buffer register 7 via the signal line 21 and sent to the RAM 1 1c.

  In the present invention, on the basis of the conventional microprogram tracer shown in FIG. 1, the signal line 18 is connected to 1c of the RAM 1 to read the contents of the RAM 1, and the 1c added to the RAM 1 is read via the signal line 18. I was able to put it out. For example, a microcomputer or computer connected to the test apparatus of the present invention via the signal line 18 can read 1c added to the RAM 1 via the signal line 18.

  In the present invention, based on the conventional microprogram tracer shown in FIG. 1, the non-passing path is detected from the information in the RAM 1 including 1c added to the RAM 1.

  The test apparatus of the present invention inputs a program address from the MAR 6 to the RAM 2 via the signal line 9 and reads the program from the RAM 2 via the signal line 10. The test apparatus of the present invention stores the read program in the MIR 3 and sends it to the decoder 4. The decoder 4 decodes the program and gives an instruction to each module in the processor according to the contents of the program. If the decoded instruction is not a branch instruction, the branch control module 5 generates an address obtained by adding 1 to the address of the MAR 6 and sets (sets) it in the MAR 6.

  When the decoded program is a branch instruction, the decoder 4 sends a branch instruction detection signal to the RAM 1 via the signal line 11 and sends a branch condition of the branch instruction to the branch control module 5 via the signal line 12. .

  The branch control module 5 compares the branch condition with the contents of the STR 8 and determines whether or not the branch is established.

  The following operations are unique operations of the test apparatus of the present invention.

  When the branch is established, the branch control module 5 outputs a branch establishment signal via the signal line 14 and sends it to the buffer register 7 and the gate 19. The signal output via the signal line 11 and the signal line 14 turns on the write enable (WE) on the signal line 17a via the gate 19. The contents of the buffer register 7 are written via the signal line 15 into the bit position of 1a of the RAM 1 corresponding to the address set in the MAR 6 via the signal line 13. Thereafter, the branch control module 5 sets the branch destination address in the MAR 6 via the signal line 13.

  At this time, in the present invention, the branch control module 5 outputs a signal indicating that the branch is established and the branch destination address is fixed via the signal line 20 and sends the signal to the RAM 1 1c.

  As a result, the write enable (WE) of 1c in the RAM 1 is turned on, and the buffer register 7 passes through the signal line 21 to the bit position of 1c in the RAM 1 corresponding to the branch destination address (signal line 16) set in the MAR 6. The value of is written.

  As information indicating the start address of a program, in the present invention, when starting execution of a program from a reset vector or the like, it is determined in the same manner as the branch destination of a branch instruction, and when the start address is set in MAR6, A signal indicating that the branch is established and the branch destination address is fixed is output via the line 20, and the value of the buffer register 7 is held in the RAM 1 1 c via the signal line 21.

  As an instruction placed at the end of the program, there is an infinite loop branch instruction or a HALT instruction. The HALT instruction is an instruction for stopping the processor or the like. In the present invention, the decoder 4 determines that the HALT instruction is also a branch instruction, and outputs a signal indicating the branch instruction via the signal line 11 similarly to the branch instruction. Thereby, the branch control module 5 outputs a branch establishment signal via the signal line 14 and sends it to the buffer register 7 and the gate 19. A signal output from the signal line 11 and the signal line 14 turns on the write enable (WE) on the signal line 17a via the gate 19. The contents of the buffer register 7 are written via the signal line 15 into the bit position of 1a of the RAM 1 corresponding to the address set in the MAR 6 via the signal line 13.

  In the present invention, a microcomputer or other processor uses this RAM1 value to detect a non-passing path. Specific processing will be described below. In the following, regarding the address value, “0” indicates that the enable is off (invalid), and “1” indicates that the enable is on (valid).

  The branch destination information of the instruction that started executing the program and the branch destination (jump destination) instruction is always “branch destination flag (1c) = 1”, and the instruction at the address next to the conditional branch instruction is not executed (branch) The branch destination information in the case of “only branch to the destination” is “branch established (1a) = 1” and “branch not established (1b) = 0”, so in the branch information from the beginning to the end of the program, A section starting with the first flag (1c) = 1 ”and ending with“ branch established (1a) = 1 ”and“ branch not established (1b) = 0 ”can be extracted as a section in which the program is executed.

  An example in which the present invention is applied to a program that uses a branch instruction in which the branch destination of the branch instruction is determined by the register value when the instruction is executed will be described using the program shown in FIG. To do.

  FIG. 5 shows the value of the RAM 1 obtained by using the present invention when the value n of the register that determines the branch destination of the branch instruction at the address C is branched to the address E and executed for the program shown in FIG. Is shown.

  First, the address A is a program start instruction, and a flag indicating the start position is set in 1c corresponding to the address A of the RAM1.

  Thereafter, execution is performed from address A to address B, a branch is established by the branch instruction at address B, and a flag indicating that the branch is established is set in 1a corresponding to address B of RAM1.

  Subsequently, since the branch destination is the address C, a flag indicating the branch destination is set in 1c corresponding to the address C of the RAM 1. Further, there is a branch instruction at the address C, the branch is established, and the branch establishment flag is set to 1a corresponding to the address C in the RAM 1.

  At this time, if n indicates E as the branch destination address, a value is set to 1c corresponding to the address E of the RAM1. Thereafter, execution is performed from address E to address G, and the HALT instruction at address G is executed. In the present invention, since the HALT instruction is handled in the same manner as the branch instruction, the branch establishment flag is set to 1a corresponding to the address G of the RAM1.

[Unpassed path detection processing]
Hereinafter, the non-passing path detection process will be described with reference to FIG. If the test apparatus of the present invention is a module mounted on the microcomputer itself or a semiconductor device externally connected to the microcomputer, the microcomputer performs the process (unpassed path detection process). In addition, when the test apparatus of the present invention is externally connected to a computer, the computer performs the process. Here, the microcomputer and the computer as described above are expressed as “microcomputer and other processors”.

(1) Step S101
First, the microcomputer or other processor statically analyzes the program list and holds the area where the program is arranged.

(2) Step S102
Next, the RAM1 address is set at the head of the area where the program exists.

(3) Step S103
Thereafter, the value of the RAM1 address is read.

(4) Step S104
The RAM 1 address is searched for a “branch destination flag (1c) = 1”. That is, it is confirmed whether the read RAM1 address is “branch destination flag (1c) = 1”.

(5) Step S105
If the read RAM1 address is “branch destination flag (1c) = 1”, it is determined that the program is started from the instruction of this RAM1 address, and this RAM1 address is used as the execution start address (or branch destination address). Hold. When there is a RAM1 address that is already held, the held RAM1 address may be updated (overwritten) to the newly read RAM1 address. If the read RAM1 address is not “branch destination flag (1c) = 1”, the operation (operation in step S105) is not performed.

(6) Step S106
Subsequently, it is confirmed whether the RAM1 address is “branch established (1a) = 1” and “branch not established (1b) = 0”.

(7) Step S107
If the RAM1 address is “branch established (1a) = 1” and “branch not established (1b) = 0”, the RAM1 address held as the last execution address (or branch destination address) is Up to the read RAM1 address (current RAM1 address) is held as an execution history of the program. At this time, the RAM 1 address held as the execution start address (or branch destination address) and the read RAM 1 address may be the same RAM 1 address. Note that the RAM 1 address held as the execution start address (or branch destination address) may be deleted / released after being held as the program execution history. If the RAM1 address is not “branch established (1a) = 1” and “branch not established (1b) = 0”, the operation (operation in step S107) is not performed.

(8) Step S108
It is confirmed whether this RAM1 address is the end (final address) of the area where the program is arranged.

(9) Step S109
If it is not the end of the area where the program is arranged, the address of the RAM 1 is further incremented, and the next contents of the RAM 1 are sequentially read and searched. Incrementing is a process of incrementing the value of an integer type variable by one.

(10) Step S110
If it is the end of the area in which the program is arranged, the acquired program execution history is compared with the program sequence, and a non-passing path is detected.

[Example]
A case where a non-passing path is detected by performing the non-passing path detection process according to the present invention shown in FIG. 6 using the value of the RAM 1 shown in FIG. 5 will be described.

  First, the program list is statically analyzed, and the area where the program is arranged is held (step S101). In FIG. 5, the program exists from address A to address F. Next, the RAM1 address is set at the head of the area where the program exists (step S102). Thereafter, the value of the RAM1 address is read (step S103).

  As for the value of the RAM1 address, a place where “branch destination flag (1c) = 1” is searched (step S104). In FIG. 5, since the address A is “branch destination flag (1c) = 1”, it is determined that the program is started from the instruction at the address A, and this RAM1 address is used as the execution start address (or branch destination address). (Step S105).

  Subsequently, it is confirmed whether the address A is “branch established (1a) = 1” and “branch not established (1b) = 0” (step S106).

  In FIG. 5, since the address A is “branch established (1a) = 0” and “branch not established (1b) = 0”, “branch established (1a) = 1” and “branch not established (1b) = 0”. The address of the RAM 1 is incremented until the location is found (step S108, step S109), and the next contents of the RAM 1 are read in order (step S103).

  As for the value of the next RAM1 address, the part of “branch destination flag (1c) = 1” is searched (step S104). In FIG. 5, since the address B is “branch destination flag (1c) = 0”, it is determined whether the address B is “branch established (1a) = 1” and “branch not established (1b) = 0”. Confirmation (step S106).

  In FIG. 5, since the address B is “branch established (1a) = 1” and “branch not established (1b) = 0”, the execution from the address A to the address B is indicated as the program execution history. Hold (step S107).

  Since address B is not the end of the area where the program is placed (step S108), the address of RAM1 is incremented (step S109), and the next contents of RAM1 are read in order (step S103).

  The location of “branch destination flag (1c) = 1” is searched again for the value of the next RAM1 address (step S103). In FIG. 5, since the address C is “branch destination flag (1c) = 1” (step S104), it is determined that the program is started from the instruction at the address C, and this RAM1 address is set as the execution start address (or Branch destination address) (step S105).

  Subsequently, it is confirmed whether the address C is “branch established (1a) = 1” and “branch not established (1b) = 0” (step S106).

  In FIG. 5, since the address C is “branch established (1a) = 1” and “branch not established (1b) = 0”, the fact that the address C has been executed is held as an execution history of the program ( Step S107).

  Since the address C is not the end of the area where the program is arranged (step S108), the address of the RAM 1 is incremented (step S109), and the next contents of the RAM 1 are read in order (step S103).

  As for the value of the next RAM1 address, the part of “branch destination flag (1c) = 1” is searched (step S104). In FIG. 5, since the address D is “branch destination flag (1c) = 0”, it is determined whether the address D is “branch established (1a) = 1” and “branch not established (1b) = 0”. Confirmation (step S106).

  In FIG. 5, since the address D is “branch established (1a) = 0” and “branch not established (1b) = 0”, “branch established (1a) = 1” and “branch not established (1b) = 0”. The address of the RAM 1 is incremented until the location is found (step S108, step S109), and the next contents of the RAM 1 are read in order (step S103).

  With respect to the value of the next RAM1 address, the location of “branch destination flag (1c) = 1” is searched again (step S104). In FIG. 5, since the address E is “branch destination flag (1c) = 1”, it is determined that the program is started from the instruction at the address E, and this RAM1 address is used as the execution start address (or branch destination address). (Step S105).

  Subsequently, it is confirmed whether the address E is “branch established (1a) = 1” and “branch not established (1b) = 0” (step S106). In FIG. 5, because “branch established (1a) = 0” and “branch not established (1b) = 0”, the location of “branch established (1a) = 1” and “branch not established (1b) = 0” The address of the RAM 1 is incremented until it is found (steps S108 and S109), and the next contents of the RAM 1 are read in order (step S103).

  With respect to the value of the next RAM1 address, the location of “branch destination flag (1c) = 1” is searched again (step S104). In FIG. 5, since the address F is “branch destination flag (1c) = 0”, it is determined whether the address F is “branch established (1a) = 1” and “branch not established (1b) = 0”. Confirmation (step S106).

  In FIG. 5, since the address F is “branch established (1a) = 1” and “branch not established (1b) = 0”, execution from the address E to the address F is indicated as an execution history of the program. Hold (step S107).

  Thereafter, confirmation is made to the end of the area where the program is placed (step S108). In the example of the program of FIG. 5, the area where the program is placed is up to the address F, so the program ends here.

  Therefore, addresses A to B, address C, and addresses E to F are actually executed histories. By comparing this execution history with the program sequence (areas from addresses A to F where the program is actually allocated), non-passing paths (in this case, addresses B to C and addresses D to E) are detected. (Step S110).

  From this, in the detection of the non-passing path according to the prior art, it was not possible to determine whether it was executed from the address D or from the address E. However, in the present invention, it can be seen that the address D is not executed. It can be detected that the path from D to address E is a non-passing path.

<Summary>
As described above, according to the present invention, similarly to the prior art, when a program test is performed during program development of a microcomputer, it is possible to easily detect a non-passing path.

  Furthermore, by leaving the branch destination result in addition to branch establishment and branch establishment failure, it is possible to detect a non-passing path in any program sequence, and to obtain accurate C0 coverage. .

  As mentioned above, although embodiment of this invention was explained in full detail, actually, it is not restricted to said embodiment, Even if there is a change of the range which does not deviate from the summary of this invention, it is included in this invention.

1, 2 ... RAM
3 ... Micro instruction register 4 ... Decoder 5 ... Branch control module 6 ... Micro instruction address register 7 ... Buffer register 8 ... Status register 9-18 ... Signal line 19 ... Gate 20 ... Signal line 21 ... Signal line

Claims (6)

A first RAM having the same address space as the address of the program and having a width of 3 bits;
A second RAM for storing the program;
Execution detection means for detecting that a conditional branch instruction of the program is executed;
A buffer register for holding a result of whether or not the branch instruction is branched;
Analyzing the execution status of the branch instruction of the program sent by the execution detection means, and having a gate for classifying and writing to the first RAM,
The execution detection means includes
A decoder for decoding a microinstruction read from the second RAM to the microinstruction register and outputting a signal indicating whether the instruction is a branch instruction and a branch condition;
A branch control module for comparing the branch condition obtained by the output of the decoder with the contents of the status register, determining whether or not a branch is established, and sending a determination result to the buffer register and the gate; Equipped,
The branch control module
Means for outputting to the buffer register a signal indicating that the branch has been established and the branch destination address has been determined;
Means for sending a signal indicating that the branch is established and the branch destination address is fixed to the first RAM as a write enable signal;
In response to the write enable signal, the write enable of the first RAM is turned on, and the buffer register value is written to the bit position of the first RAM corresponding to the branch destination address set in the microinstruction register. And a test apparatus. The test apparatus according to claim 1,
The first RAM is
Of the 3 bits, a first 1 bit that traces branch establishment;
Of the 3 bits, a second 1 bit that traces branch failure,
Among the 3 bits, a third 1 bit indicating a branch destination,
The gate is
Means for outputting a signal for enabling the first bit;
Means for outputting a signal for enabling the second bit,
The branch control module
Means for outputting a signal for enabling the third bit when the write enable signal is sent to the first RAM;
A test apparatus further comprising means for writing the buffer register value to the third bit when the buffer register value is written to the bit position of the first RAM. The test apparatus according to claim 2,
A test execution means for executing a test of the program;
The test execution means includes
Means for statically analyzing a program list of the program and holding an area where the program is arranged;
Means for setting an address of the first RAM at the head of an area where the program exists;
Means for reading an address value of the first RAM;
Means for checking whether the enable of the third one bit is on for the value of the read address;
When the third 1-bit enable is on, it is determined that the program is started from the instruction at the read address, and the read address is held as either the execution start address or the branch destination address When,
Means for checking whether the first one bit enable is on and the second one bit enable is off at the read address;
In the read address, when the enable of the first 1 bit is on and the enable of the second 1 bit is off, the read is performed from the address held as either the execution start address or the branch destination address. Means for holding up to a predetermined address as an execution history of the program;
Means for confirming whether the read address is the end of the area where the program is located;
Means for reading the value of the next address of the first RAM, if not the end of the area where the program is located;
A test apparatus comprising: means for comparing an execution history of the program with a program sequence and detecting a non-passing path when the program is located in an end area. Using a first RAM having the same address space as the address of the program and having a width of 3 bits;
Using a second RAM for storing the program;
Detecting that a conditional branch instruction of the program has been executed;
Using a buffer register to hold the result of whether the branch instruction has branched;
Analyzing the execution status of the branch instruction of the program and using a gate for classifying and writing to the first RAM;
Decoding a microinstruction read from the second RAM to a microinstruction register and outputting a signal indicating whether the instruction is a branch instruction and a branch condition;
Comparing the branch condition with the contents of the status register to determine whether or not a branch has been established;
If a branch is taken, a signal indicating that the branch is taken and the branch destination address is fixed is output to the buffer register and sent as a write enable signal to the first RAM;
In response to the write enable signal, the write enable of the first RAM is turned on, and the buffer register value is written to the bit position of the first RAM corresponding to the branch destination address set in the microinstruction register. And testing methods. The test method according to claim 4, comprising:
In the first RAM, among the 3 bits, the first 1 bit is a value that traces the establishment of a branch;
In the first RAM, out of the 3 bits, the second 1 bit is set to a value that traces branch failure;
In the first RAM, among the 3 bits, a third 1 bit is set as a value indicating a branch destination;
Outputting a signal enabling the first bit from the gate;
Outputting a signal enabling the second bit from the gate;
Outputting a signal for enabling the third bit when the write enable signal is sent to the first RAM;
A test method further comprising: writing the buffer register value to the third bit when writing the buffer register value to the bit position of the first RAM. The test method according to claim 5, comprising:
Statically analyzing a program list of the program and holding an area where the program is located;
Setting the address of the first RAM at the head of the area where the program exists;
Reading the value of the address of the first RAM;
Confirming whether the third 1-bit enable is on for the value of the read address;
When the third 1-bit enable is on, it is determined that the program is started from the instruction at the read address, and the read address is held as either the execution start address or the branch destination address. When,
Checking whether the first 1-bit enable is on and the second 1-bit enable is off at the read address;
In the read address, when the enable of the first 1 bit is on and the enable of the second 1 bit is off, the read is performed from the address held as either the execution start address or the branch destination address. Holding up to the specified address as the execution history of the program,
Checking whether the read address is the end of the area where the program is located;
If it is not the end of the area where the program is located, reading the value of the next address in the first RAM;
A test method further comprising: comparing an execution history of the program with a program string and detecting a non-passing path when the program is located at an end of the area where the program is arranged.

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