JP2011253992A - Semiconductor substrate, semiconductor device, and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate which makes it possible to obtain a sufficient gettering effect in a semiconductor device manufacturing process.SOLUTION: A semiconductor substrate 3 of the present invention comprises a substrate body 8 consisting of a semiconductor; an insulation layer 6 consisting of a silicon oxide film which is formed on the substrate body 8 and contains phosphor; and a semiconductor layer 7 provided on the insulation layer 6. Also, a semiconductor device of the present invention includes the semiconductor substrate 3 comprising the substrate body 8 consisting of a semiconductor, the insulation layer 6 consisting of a silicon oxide film which is formed on the substrate body 8 and contains phosphor, and the semiconductor layer 7 provided on the insulation layer 6; a gate insulation film provided on the semiconductor layer 7; a gate electrode provided on the gate insulation film; and an impurity diffusion region provided at a position inside the semiconductor layer 7 and self-aligned with the gate electrode.

Description

  The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor device.

  In general, gettering is known as a method for preventing deterioration of characteristics of a semiconductor device due to mobile ions or metal ions in the manufacturing process of the semiconductor device. For this gettering, there are methods such as IG (Intrinsic Gettering) and EG (Extrinsic Gettering) represented by PBS (Poly-Si Back Seal) for depositing polysilicon on the back surface of the wafer.

In recent years, with miniaturization of semiconductor devices, for example, both surfaces of a 300 mm wafer or the like are polished. Further, due to further demands for thinning and stacking of packages of semiconductor devices, the back surface grinding thickness in the subsequent process has been reduced, and further, it has become necessary to polish the back surface after grinding.
For this reason, when an EG having a high gettering ability is employed, the gettering ability after the back surface grinding becomes insufficient, and there is a disadvantage that characteristic deterioration due to heat treatment during assembly process or substrate mounting becomes obvious.

  Therefore, Patent Document 1 describes a method of forming an upper silicon layer using an epitaxial growth method after doping a silicon layer constituting a semiconductor substrate with impurities.

JP 2005-317735 A

  However, in the method described in Patent Document 1, it is difficult to control the impurity diffusion from the impurity layer provided below during epitaxial growth, and the impurity concentration of the silicon layer in the part where the device is formed is appropriately maintained. There was a problem that was difficult.

Therefore, the present invention employs the following configuration.
A semiconductor substrate of the present invention includes a substrate body made of a semiconductor, an insulating layer made of a silicon oxide film containing phosphorus formed on the substrate body, and a semiconductor layer provided on the insulating layer. It is characterized by.

  In the semiconductor substrate of the present invention, an insulating layer made of a silicon oxide film containing phosphorus is formed under the semiconductor layer. Thereby, by forming a device in the semiconductor layer, it is possible to suppress the influence of movable ions, metal ions, and the like on the device. In other words, mobile ions, metal ions, and the like that enter from the back surface side of the semiconductor substrate are gettered to the insulating layer made of a silicon oxide film containing phosphorus, so that the influence on the device can be suppressed.

FIG. 1 is a plan view showing a part of an example of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a sectional view showing the semiconductor substrate according to the first embodiment of the present invention. FIG. 3 is a cross-sectional process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a cross-sectional process diagram illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 9 is a cross-sectional process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a sectional view showing the semiconductor device according to the first embodiment of the present invention. FIG. 12 is a cross-sectional process diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[First Embodiment]
Hereinafter, a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.
First, a memory cell of a DRAM manufactured using the semiconductor device of this embodiment will be described. FIG. 1 is a plan view schematically showing a layout of a MOS-FET (memory cell transistor) in a memory cell region of a DRAM.

  As shown in FIG. 1, in the memory cell 1 of the DRAM device of this embodiment, a plurality of elongated strip-like active regions 2 are arranged in a diagonally upward right direction with predetermined intervals. The active region 2 is formed on the surface of a semiconductor substrate 3 (see FIG. 2 and the like), and is formed by being insulated and separated by an element isolation region 4 (see FIG. 5 and the like).

A gate electrode 5 functioning as a word line is formed in the longitudinal (Y) direction of FIG. 1, and a planar type MOS-FET is formed at the intersection of the gate electrode 5 and the active region 2. .
In FIG. 1, bit lines and capacitor elements are omitted.

<Semiconductor substrate>
Next, the semiconductor substrate of this embodiment will be described with reference to FIG. 2 to 12 are cross-sectional views taken along the line AA ′ in FIG.
As shown in FIG. 2, the semiconductor substrate 3 is roughly configured by a substrate body 8, an insulating layer 6 formed on the substrate body 8, and a semiconductor layer 7 provided on the insulating layer 6. That is, the semiconductor substrate 3 is a substrate having a structure in which the insulating layer 6 is inserted between the substrate body 8 and the semiconductor layer 7.

The insulating layer 6 is made of a silicon oxide film containing phosphorus, and even if it is a PSG film doped with only phosphorus (Phospho-Silicate Glass film), a BPSG film doped with phosphorus and boron (Boro-Phospho-Silicate). Glass film). In addition, in the case of the PSG film and the BPSG film, the phosphorus doping amount is preferably 1 × 10 ²⁰ atoms / cm ³ or more.
In addition, although the film thickness of the insulating layer 6 is not specifically limited, For example, it is preferable to set it as about 10-500 nm.

As the semiconductor layer 7, for example, a silicon substrate can be used. Also, a thin silicon oxide film (not shown) of about 3 to 10 nm, for example, may be formed on the surface 7b of the semiconductor layer 7 on the side in contact with the insulating layer 6 by a thermal oxidation method. As a material for the semiconductor layer 7, SiGe, SiC, or the like may be used in addition to pure Si.
A device can be formed in the semiconductor layer 7.

  The substrate body 8 is made of a semiconductor, and for example, a silicon substrate can be used. Further, a thin silicon oxide film (not shown) of about 3 to 10 nm, for example, may be formed on the surface 8a of the substrate body 8 on the side in contact with the insulating layer 6 by a thermal oxidation method.

In the semiconductor substrate 3 of the present embodiment having the above-described configuration, an insulating layer 6 made of a silicon oxide film containing phosphorus is formed under the semiconductor layer 7 on which a device is formed. Thereby, movable ions, metal ions, and the like entering from the back surface 3b side of the semiconductor substrate 3 are gettered to the insulating layer 6 and can be prevented from affecting the device.
Thereby, a high-performance semiconductor device can be formed. Further, when applied to the formation of a DRAM element as in the present embodiment, an element excellent in data retention characteristics (refresh characteristics) can be formed while suppressing leakage current.

<Semiconductor device>
Next, the semiconductor device 10 using the semiconductor substrate 3 of this embodiment will be described.
As shown in FIG. 11, the semiconductor device 10 of the present embodiment is formed on the semiconductor substrate 3, the element isolation region 4 made of a buried insulating film provided in the semiconductor layer 7 of the semiconductor substrate 3, and the semiconductor substrate 3. Source / drain regions provided in positions that are self-aligned with the gate electrode 12 in the semiconductor layer 7 of the semiconductor substrate 3 and the gate electrode 5 provided on the gate insulating film 11. (Impurity diffusion layer) 13 is provided.

  A contact plug 14 is formed on each source / drain region 13, and a bit wiring 15, a capacitor element 16, an upper metal wiring layer 17, and a surface protection film 18 are connected to the contact plug 14. Is formed.

  The semiconductor substrate 3 described above is used in the semiconductor device 10 of the present embodiment. That is, the insulating layer 6 is formed under the semiconductor layer 7 where the device is formed. Thereby, mobile ions, metal ions, and the like from the back surface 3b side of the semiconductor substrate 3 are gettered to the insulating layer 6, and it is possible to suppress the mobile ions, metal ions, and the like from affecting the semiconductor device. it can.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of this embodiment will be described. The manufacturing method of the semiconductor device 10 according to the present embodiment includes a step of forming the semiconductor substrate 3, a step of forming the element isolation region 4 in the semiconductor substrate 3, a step of forming the gate insulating film 11 on the semiconductor substrate 3, A step of forming the gate electrode 5 on the gate insulating film 11, a step of forming the source region 13 and the drain region 13 at positions that are self-aligned with the gate electrode 5, and a sidewall 30 that covers the sidewall of the gate electrode 5 Forming the interlayer insulating film 41 so as to cover the gate electrode 5, forming the contact plug 14 penetrating the interlayer insulating film 41, and forming the upper metal wiring layer 17 and the like And having. Details will be described below.

<< Semiconductor substrate formation process >>
First, as shown in FIG. 2, a silicon oxide film (not shown) is formed on the surface 8a of, for example, a P-type silicon substrate to be the substrate body 8 by a thermal oxidation method.
Thereafter, an insulating layer 6 made of a silicon oxide film containing phosphorus is formed on a silicon substrate to be the substrate body 8. Specifically, a silicon oxide film having a thickness of about 200 nm is deposited using, for example, a CVD method.

The silicon oxide film constituting the insulating layer 6 is preferably a PSG film containing only phosphorus or a BPSG film containing phosphorus and boron, and the doping amount of phosphorus is, for example, 1 × 10 ²⁰ atoms / cm. It is preferably ³ or more.
In addition, for doping with phosphorus, for example, PH ₃ (phosphine) gas may be added to the material gases SiH ₄ and O ₂ when the film is formed by the CVD method, or phosphorus is added to the silicon oxide film deposited without doping. The introduction implantation may be performed by an ion implantation method.

  Next, separately from the above steps, another silicon substrate to be the semiconductor layer 7 is prepared, and a silicon oxide film (not shown) is formed on the surface 7b of the silicon substrate by using a thermal oxidation method. And the silicon substrate used as the board | substrate body 8 and another silicon substrate used as the semiconductor layer 7 are bonded together using a well-known wafer bonding technique.

Thereafter, another silicon substrate is polished to form the semiconductor layer 7. During polishing, so that the film thickness which is suitable for device formation, adjusting the thickness T ₁ of the semiconductor layer 7. Incidentally, the semiconductor layer 7, because it is used as a device formation region, the thickness T ₁ of the semiconductor layer 7 after polishing is too thin, will affect the electrical characteristics of the devices that form. On the other hand, if the thickness T ₁ of the semiconductor layer 7 is too thick, the insulating layer 6 is placed in the semiconductor substrate 3 during back grinding (back surface grinding) of the semiconductor substrate 3 in the assembly process (post process) after device formation. It is difficult to remain in the surface.

Therefore, when back grinding is finally performed until the thickness T ₂ of the semiconductor substrate 3 is 50 μm, the thickness T ₁ of the semiconductor layer 7 after polishing is preferably in the range of 10 to 40 μm. Note that the upper limit of the thickness T _1, can be changed according to the thickness T ₂ of the final semiconductor substrate 3 to form the back-grinding.
Through the above steps, the semiconductor substrate 3 is formed.

  In this embodiment, the semiconductor layer is not directly doped with impurities, but the silicon oxide film, which is the insulating layer 6, is doped with phosphorus, which is an impurity, and the semiconductor layer 7 is bonded onto the insulating layer 6 to form a semiconductor substrate. 3 is formed. Thereby, it can suppress that an impurity introduce | transduces into a device formation area compared with the past. That is, when a semiconductor layer for forming a device is epitaxially grown on a semiconductor layer doped with impurities, there is a disadvantage that the impurities penetrate into the device formation region. On the other hand, in this embodiment, since the bonding technique is used, it is possible to prevent impurities contained in the insulating layer 6 from entering the semiconductor layer 7 which is a device formation region.

<< Element isolation region formation process >>
Next, after forming the semiconductor substrate 3, as shown in FIG. 3, a silicon oxide film 23 having a thickness of about 10 nm is formed on the semiconductor substrate 3 by using, for example, a thermal oxidation method. Thereafter, a silicon nitride film 24 having a thickness of about 150 nm is deposited by using, for example, LP-CVD, and the silicon nitride film 24 and the silicon oxide film 23 are patterned by using a well-known lithography technique and dry etching technique.

  Next, as shown in FIG. 4, using the silicon nitride film 24 as a mask, the semiconductor layer 7 is etched by, for example, about 200 nm to form a trench 25 for element isolation using an STI (Shallow Trench Isolation) structure.

  Next, as shown in FIG. 5, a silicon oxide film 26 of about 400 nm is deposited on the semiconductor substrate 3 by, for example, HDP-CVD (High Density Plasma) method. Thereafter, the deposited silicon oxide film 26 is polished and removed by CMP (Chemical Mechanical Polishing) using the silicon nitride film 24 as a stopper to form an STI buried oxide film. As described above, the element isolation region 4 is formed in the semiconductor substrate 3.

  Thereafter, the silicon nitride film 24 is removed by wet etching using a chemical solution such as hot phosphoric acid, and the silicon oxide film 23 is removed by wet etching using a chemical solution such as hydrofluoric acid. The surface 7a of the semiconductor layer 7 is exposed.

<< Gate insulating film and gate electrode formation process >>
Next, as shown in FIG. 6, a gate insulating film 11 having a thickness of about 6 nm is formed on the semiconductor layer 7 by, for example, thermal oxidation.
A silicon oxide film is preferably used as the gate insulating film 11. Further, when forming the gate insulating film 11, it is preferable to use an ISSG (In-Situ Steam Generation) oxidation method. By using the ISSG oxidation method, it is possible to suppress the generation of stress due to diffusion of oxidized species as compared with thermal oxidation using a normal heating furnace, so that leakage current at the end of the STI buried oxide film or the like Can be reduced.

Thereafter, a polysilicon film 27 having a thickness of about 80 nm doped with, for example, phosphorus at a concentration of about 1 × 10 ²⁰ / cm ^{3 is} formed on the gate insulating film 11. Next, a tungsten film (WN) having a thickness of, for example, about 5 nm and a tungsten (W) film having a thickness of about 70 nm are stacked on the polysilicon film 27 to form a metal film (W / WN film) 28. .

  Thereafter, a silicon nitride film 29 having a thickness of about 140 nm is deposited by LP-CVD, for example. Then, the silicon nitride film 29 is patterned using a well-known lithography technique and dry etching technique.

  Next, as shown in FIG. 7, for example, anisotropic dry etching is performed using the silicon nitride film 29 as a mask. Through the above steps, the gate electrode 5 composed of the metal film 28 and the polysilicon film 27 is formed.

<< Source / Drain Region Formation Step >>
Next, as shown in FIG. 8, for example, phosphorus with a dose of about 1 × 10 ¹³ / cm ² is ion-implanted at an energy of 30 keV, and heat treatment is performed at 900 ° C. for 10 seconds in an inert gas such as nitrogen. . As a result, source / drain regions (impurity diffusion layers) 13 are formed in the semiconductor layer 7 at positions that are self-aligned with the gate electrode 5.

<< Sidewall formation process >>
After that, for example, a silicon nitride film having a thickness of about 10 nm deposited by LP-CVD is etched back by normal anisotropic dry etching to form a sidewall 30 that covers the sidewall of the gate electrode 5.

<< Interlayer insulating film formation process >>
Next, as shown in FIG. 9, as an interlayer insulating film 41 with a wiring layer formed as an upper layer, a BPSG film is deposited with a film thickness of about 400 nm by, for example, a CVD method, and then a reflow process at 750 ° C. for 30 minutes. I do. Note that after the reflow treatment, the surface 41a of the interlayer insulating film 41 may be further planarized by CMP.

<< Contact plug formation process >>
Next, as shown in FIG. 10, a contact hole 42 is formed in the interlayer insulating film 41 using, for example, a well-known lithography technique and dry etching technique. Thereafter, polysilicon is deposited so as to fill the contact hole 42, and the polysilicon deposited on the interlayer insulating film 41 is polished and removed by CMP to form the contact plug 14. For example, polysilicon doped with phosphorus at a concentration of about 1 × 10 ²⁰ / cm ³ may be used, and may be deposited in the contact hole 42 by LP-CVD.

<< Upper wiring layer formation process >>
Next, as shown in FIG. 11, a bit wiring 15 and a capacitor element 16 are formed so as to be connected to the contact plug 14, and then an upper metal wiring layer 17, a surface protective film 18 and the like are formed.
Thereafter, the back surface 3b side of the semiconductor substrate 3 and back grinding, the total thickness T ₃ of the semiconductor device 10, so that for example the desired size, such as 50 [mu] m.
Thereafter, the semiconductor device 10 used in the DRAM memory cell is completed by assembling into a predetermined package by a known means.

  In general, during the manufacturing process of a semiconductor device, metal ions such as Na enter mainly from the back side of the substrate. In particular, in the case of a device such as a DRAM element that has been improved in performance by suppressing the leakage current through the source / drain diffusion layer, the getter is designed so that metal ions entering during the manufacturing process do not affect the device. It is important to do the ring.

  In this embodiment, a semiconductor layer 7 is formed on the insulating layer 6 made of a silicon oxide film containing phosphorus, and a device is formed on the semiconductor layer 7. As a result, in the manufacturing process of the semiconductor device 10, even if movable ions or metal ions enter from the back surface 3 b of the semiconductor substrate 3, gettering is performed by the insulating layer 6. Etc. can be prevented.

In addition, after manufacturing the semiconductor device 10, movable ions, metal ions, and the like may enter the semiconductor device 10 in the process of incorporating the semiconductor device 10 into the package. In the present embodiment, the thickness T ₁ of the semiconductor layer 7 is set so that the insulating layer 6 that is a silicon oxide film containing phosphorus remains in the semiconductor substrate 3 even after back grinding (back surface grinding). . Thereby, the gettering effect can be maintained during the assembly process to the package, and the device characteristic deterioration can be suppressed.

[Second Embodiment]
Next, a method for manufacturing the semiconductor device of the second embodiment will be described. The present embodiment is a modification of the first embodiment, and description of similar parts is omitted.

In the first embodiment, a planar-type MOS-FET is employed. However, the present embodiment is different in that it is a MOS-FET having a groove-type gate electrode.
Specifically, the process up to the formation of the element isolation region 4 shown in FIG. 5 is performed in the same manner as in the first embodiment.

After that, as shown in FIG. 12, the semiconductor layer 7 in the region where the groove-type gate electrode 55 is to be formed is removed by etching to form a groove pattern 51 (gate trench) for the gate electrode. Then, the trench pattern 51 is covered with a gate insulating film 52.
Next, a polysilicon film 53 doped with an impurity such as phosphorus and a metal film 54 such as tungsten are deposited so as to fill the trench pattern 51 through the gate insulating film 52, and patterned to form a trench type. A gate electrode 55 is formed.

  Thereafter, impurities such as phosphorus are introduced by an ion implantation method, and annealing is performed in an inert gas such as nitrogen to form source / drain regions (impurity diffusion layers) 56. Thereafter, in the same manner as in the first embodiment, an interlayer insulating film, contact plugs connected to the source / drain regions 56 and the groove-type gate electrode 55, a wiring layer, and the like are formed, thereby forming the groove-type gate electrode. A MOS-FET with 55 is completed.

  Also in this embodiment, the insulating layer 6 made of a silicon oxide film containing phosphorus is formed under the semiconductor layer 7 where the device is formed. Thereby, mobile ions, metal ions, and the like from the back surface 3b side of the semiconductor substrate 3 are gettered to the insulating layer 6, and the influence of the mobile ions, metal ions, and the like on the device can be suppressed. .

As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention can be variously changed in the range which is not limited to the said embodiment and does not deviate from the summary.
For example, in the above embodiment, the application to the DRAM element has been described. However, this is an example, and the application to the DRAM element is not limited. The present invention can be applied to any semiconductor device that can improve device characteristics such as reduction of leakage current due to the gettering effect during the manufacturing process.

  Since the present invention relates to a method for manufacturing a semiconductor device, it can be widely used in the manufacturing industry for manufacturing semiconductor devices.

  DESCRIPTION OF SYMBOLS 3 ... Semiconductor substrate, 5,55 ... Gate electrode, 6 ... Insulating layer, 7 ... 1st semiconductor layer, 8 ... 2nd semiconductor layer, 11, 52 ... Gate insulating film 51 ... Gate trench

Claims (12)

A substrate body made of a semiconductor;
An insulating layer made of a silicon oxide film containing phosphorus formed on the substrate body;
And a semiconductor layer provided on the insulating layer.   The semiconductor substrate according to claim 1, wherein the insulating layer further contains boron. A substrate body made of a semiconductor; an insulating layer made of a silicon oxide film containing phosphorus formed on the substrate body; and a semiconductor substrate comprising a semiconductor layer provided on the insulating layer;
A gate insulating film provided on the semiconductor layer;
A gate electrode provided on the gate insulating film;
An impurity diffusion region provided in a position that is self-aligned with the gate electrode in the semiconductor layer.   The semiconductor device according to claim 3, wherein the insulating layer further contains boron. A gate trench is provided in the semiconductor layer;
The gate insulating film is provided in the gate trench;
5. The semiconductor device according to claim 3, wherein the gate electrode is provided on the gate insulating film. Forming an insulating layer made of a silicon oxide film containing phosphorus on a substrate body made of a semiconductor;
Forming a semiconductor layer on the insulating layer;
Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode on the gate insulating film;
And a step of forming an impurity diffusion layer in the semiconductor layer so as to be self-aligned with the gate electrode.   The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the semiconductor layer on the insulating layer, the semiconductor layer is bonded to the insulating layer.   The method for manufacturing a semiconductor device according to claim 6, wherein the insulating layer further contains boron.   7. A gate trench is provided in the semiconductor layer formed on the insulating layer, the gate insulating film is formed in the gate trench, and the gate electrode is formed on the gate insulating film. A method for manufacturing a semiconductor device according to claim 8. On the semiconductor layer of the semiconductor substrate comprising a substrate body made of a semiconductor, an insulating layer made of a silicon oxide film containing phosphorus formed on the substrate body, and a semiconductor layer provided on the insulating layer, Forming a gate insulating film;
Forming a gate electrode on the gate insulating film;
And a step of forming an impurity diffusion layer in the semiconductor layer so as to be self-aligned with the gate electrode.   The method for manufacturing a semiconductor device according to claim 10, wherein the insulating layer further contains boron.   11. The semiconductor layer formed on the insulating layer is provided with a gate trench, the gate insulating film is formed in the gate trench, and the gate electrode is formed on the gate insulating film. A method for manufacturing a semiconductor device according to claim 11.

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