JP2011250237A - Packet transfer device control method and controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a packet transfer device control method and its controller that can reduce the power consumption of a packet transfer device by appropriately determining a predictive input bandwidth.SOLUTION: A packet transfer device including a plurality of packet processing circuits controls operations of the packet processing circuits. This method comprises: a first step of storing an information history of packets input and output into and from the packet transfer device within a unit time; a second step of calculating an input bandwidth of packets input into the packet transfer device in each unit time on the basis of the packet information history; a third step of calculating the number of packets stored in a queue of the packet transfer device in each unit time on the basis of the packet information history; a forth step of setting up control information of processing performance for a packet processing circuit to be operated depending on the input bandwidth for a unit time and the number of packets per unit time; and a fifth step of controlling operations of the packet processing circuits on the basis of the set control information.

Description

  The present invention relates to a method for controlling a packet transfer apparatus, and more particularly to a method for controlling a packet transfer apparatus for transferring a packet in a power-saving manner.

  In order to increase the speed of packet transfer apparatuses such as routers and switches, it is necessary to increase the number of devices such as application specific integrated circuits (ASICs) and increase the operating frequency of the packet transfer apparatus. However, when the speed is increased by such a method, the power consumption of the packet transfer apparatus increases. For this reason, it is required to reduce the power consumption of the packet transfer apparatus, that is, to minimize the increase in power consumption accompanying the increase in speed.

  A method for reducing the power consumption of the packet transfer apparatus is disclosed in Patent Document 1, for example. According to the packet transfer apparatus disclosed in Patent Document 1, the power of the packet processing circuit that processes a packet can be set according to the number of lines that perform communication. That is, when the number of communication lines is small, the power consumption of the packet transfer apparatus can be reduced. Furthermore, the power of the packet processing circuit can be set according to the bandwidth of the packet to be processed. That is, when the amount of packets transmitted and received by the packet transfer apparatus is small, the power consumption of the packet transfer apparatus can be reduced.

JP 2009-111707 A

  According to the packet transfer apparatus disclosed in Patent Document 1, the number of packet processing circuits to be operated can be set to a number corresponding to the predicted input bandwidth notified by an external control terminal. That is, when the predicted input bandwidth is small, power consumption can be reduced by reducing the number of packet processing circuits to be operated. However, the method for determining the predicted input band has not been considered.

  The present invention takes the above-described problems into consideration, and provides a control method and a control device for a packet transfer device that can reduce the power consumption of the packet transfer device by appropriately determining the predicted input bandwidth. For the purpose.

  A typical example of the invention disclosed in the present application is as follows. That is, in a packet transfer apparatus including a plurality of packet processing circuits that execute packet processing based on header information of an input packet, a method for controlling operations of the plurality of packet processing circuits, and for a unit time Based on the first procedure for accumulating the packet information history including the number of packets input to and output from the packet transfer apparatus and the packet length, and during each unit time based on the accumulated packet information history Based on the second procedure for calculating the input bandwidth of the packet input to the packet transfer device and the history of the stored packet information, the packet is stored in a queue included in the packet transfer device during each unit time. In the third procedure for calculating the number of packets, the calculated packet input bandwidth per unit time, and the calculated queue per unit time Based on the set number of packets, the fourth procedure for setting the control information of the processing performance of the packet processing circuit to be operated among the plurality of packet processing circuits, and the plurality of the plurality of packet processing circuits based on the set control information. And a fifth procedure for controlling the operation of the packet processing circuit.

  According to the present invention, the power consumption of the packet transfer apparatus can be reduced by appropriately determining the predicted input bandwidth.

It is a figure which shows the example of 1 structure of the computer system of the 1st Embodiment of this invention. It is a figure which shows the hardware structural example of the control terminal of the 1st Embodiment of this invention. It is a figure which shows the example of 1 structure of the packet transfer apparatus of the 1st Embodiment of this invention. It is a figure which shows an example of the data format of the packet which the packet transmission apparatus of the 1st Embodiment of this invention transmits / receives. It is a figure which shows an example of the data format of the packet inside the packet transfer apparatus of the 1st Embodiment of this invention. It is a figure which shows the example of 1 structure of the header process part of the 1st Embodiment of this invention. It is a figure which shows the example of 1 structure of the header information storage part of the 1st Embodiment of this invention. It is a flowchart which shows the control logic of the control information setting part of the 1st Embodiment of this invention. It is a flowchart which shows the control logic of the control information setting part of the 1st Embodiment of this invention. It is a flowchart which shows the control logic of the control information setting part of the 1st Embodiment of this invention. It is a figure which shows the example of 1 structure of the control information conversion table of the 1st Embodiment of this invention. It is a figure which shows the example of 1 structure of the packet transfer apparatus of the 2nd Embodiment of this invention. It is a figure which shows the example of 1 structure of the control setting correction | amendment part of the 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Each device of the control terminal 100 and the packet transfer device 200 to be controlled by the control terminal 100 according to the first embodiment of the present invention will be described.

  FIG. 1 is a diagram illustrating a configuration example of a computer system 1 according to the first embodiment of this invention. A computer system 1 illustrated in FIG. 1 includes a control terminal 100 and a plurality of packet transfer apparatuses 200 to be controlled by the control terminal 100.

  The control terminal 100 includes a statistical information reception unit 101, a statistical information calculation unit 102, a statistical information storage unit 103, a control information setting unit 104, a control information conversion table 105, a control information transmission unit 106, and control target information. And an accumulation unit 110. The statistical information calculation unit 102 includes an input bandwidth calculation unit 107 and an input queue length calculation unit 108.

  Hereinafter, the operation of each unit of the control terminal 100 will be described. In the following description, a case where the control terminal 100 controls one packet transfer apparatus 200 will be described as an example. When the control terminal 100 controls a plurality of packet transfer apparatuses 200, each unit of the control terminal 100 operates in the same manner for each packet transfer apparatus 200.

  The statistical information receiving unit 101 receives statistical information accumulated in the packet transfer apparatus 200 from the packet transfer apparatus 200 at a predetermined frequency. The statistical information here is statistical information such as the total number of packets and the total packet length for each port of the packet transfer apparatus 200. The frequency at which the statistical information receiving unit 101 receives the statistical information is, for example, a time window interval such as one minute. The statistical information received by the statistical information receiving unit 101 is stored in the statistical information storage unit 103 via the statistical information calculation unit 102.

  Based on the statistical information accumulated in the statistical information receiving unit 103 and the control target information accumulated in the control target information storage unit 110 (details will be described later), the statistical information calculation unit 102 The input queue length calculation unit 108 performs calculations (including statistical processing) to be described later. The calculation result is transmitted to the statistical information storage unit 103.

  In the following description, the statistical information receiving unit 101 receives statistical information of one time window, and the input bandwidth calculating unit 107 and the input queue length calculating unit 108 calculate based on the statistical information of one time window. An example of executing is described. Actually, the statistical information receiving unit 101 receives the statistical information of each time window, and the input bandwidth calculating unit 107 and the input queue length calculating unit 108 execute the same calculation based on the statistical information of each time window.

  The input bandwidth calculation unit 107 calculates the input bandwidth for each port of the packet transfer apparatus 200 based on the statistical information of the predetermined time window received by the statistical information reception unit 101. Specifically, the packet processing speed (unit: packet per second (pps)) for each port is calculated by accumulating the reciprocal of the time window and the total number of packets for each port of the packet transfer apparatus 200. To do. Further, for each port of the packet transfer apparatus 200, the input bandwidth (unit: bits per second, bps) for each port is calculated by integrating the reciprocal of the time window and the total packet length. On the other hand, the input queue length calculator 108 calculates the length of the packet accumulated in the queue for each input (reception) queue of the packet transfer apparatus 200 based on the statistical information of the predetermined time window received by the statistical information receiver 101. (Queue length) is calculated.

  The statistical information accumulating unit 103 is a statistical information such as a packet processing speed for each port of the packet transfer device 200 obtained by the statistical information calculation unit 102, an input bandwidth, and a queue length for each input queue (hereinafter, the statistical information described above). In order to distinguish it from this, it is called “post-calculation statistical information”). The statistical information storage unit 103 stores the calculated statistical information in association with the time when the statistical information for obtaining the calculated statistical information is received by the statistical information receiving unit 101. As a result, the statistical information storage unit 103 stores post-calculation statistical information for each time (time window).

  In addition, the statistical information storage unit 103 calculates the average input bandwidth for each time, which is obtained when the statistical information calculation unit 102 performs statistical processing on the statistical information after calculation for each time, for example, the time of the same day on the same day It is stored as a performance prediction value (hereinafter simply referred to as “performance prediction value”) of the packet transfer apparatus 200 scheduled in the window. That is, the statistical information accumulation unit 103 accumulates performance prediction values for each time (time window). Further, the statistical information accumulating unit 103 determines the amount of change in the predicted performance value for each time, the queue length for each time, which is obtained by the statistical information calculating unit 102 performing statistical processing on the statistical information after calculation for each time. Accumulate the variance of the amount of change and the performance prediction value together.

  The control information setting unit 104 sets control information to be transmitted to the packet transfer apparatus 200 based on the post-calculation statistical information stored in the statistical information storage unit 103 and the control information conversion table 105. Specifically, first, a performance prediction value for each time stored in the statistical information storage unit 103, a change amount of the performance prediction value, and a correction amount corresponding to the change amount of the queue length are acquired from the control information conversion table 105. Next, the performance prediction value is corrected based on the acquired correction amount. The control information setting unit 104 sets the corrected performance prediction value as control information (a control amount indicating the performance of the packet processing circuit) to be transmitted to the packet transfer apparatus 200 to be controlled. The control information setting unit 104 transmits control information transmitted to the packet transfer apparatus 200 from one or both of the calculated statistical information accumulated in the statistical information accumulating unit 103 and the statistical information received by the statistical information receiving unit 101. It may be set. Further, the control information setting unit 104 may obtain a correction value of control information from the control information conversion table 105 and calculate a corrected performance prediction value. The operation of the control information setting unit 104 will be described later with reference to FIG. 8, FIG. 9, and FIG.

  The control information conversion table 105 defines the performance prediction value, the change amount of the performance prediction value, the change amount of the queue length for each time accumulated in the statistical information storage unit 103, and the correction amount of the performance prediction value in association with each other. It is a table. Details of the control information conversion table 105 will be described later with reference to FIG.

  The control information transmission unit 106 transmits the control information set by the control information setting unit 104 to the packet transfer apparatus 200.

  The control target information accumulating unit 110 accumulates setting information (for example, a queue length threshold Th and a performance prediction value threshold dev described later) of each packet transfer device 200 to be controlled by the control terminal 100 as an initial setting. Further, the control target information storage unit 110 stores an increase / decrease amount (correction amount) of control information for each packet transfer apparatus 200.

  FIG. 2 is a diagram illustrating a hardware configuration example of the control terminal 100 according to the first embodiment of this invention. The control terminal 100 shown in FIG. 2 includes a memory device 11, an arithmetic processing device 12, an interface device 13, an input device 14, an auxiliary storage device 15, and a drive device 16 that are mutually connected by a bus 20.

  The memory device 11 is a RAM (Random) that reads and stores a program such as a program (a program that executes the processing of each unit 101 to 102, 104, and 106 in FIG. 1) stored in the auxiliary storage device 15 when the control terminal 100 is activated. Access memory). The memory device 11 also stores files, data (each unit 103, 105, 110 in FIG. 1) and the like necessary for executing the program. The arithmetic processing device 12 is an arithmetic processing device such as a CPU (Central Processing Unit) that executes a program stored in the memory device 11. The interface device 13 is an interface device for connecting to an external network or the like. The input device 14 is an input device (for example, a keyboard or a mouse) that provides a user interface.

  The auxiliary storage device 15 is a storage device such as an HDD that stores programs, files, data (the units 103, 105, and 110 in FIG. 1) and the like. The drive device 16 is a device that reads a program recorded on the recording medium 17. The program read by the drive device 16 is installed in the auxiliary storage device 15. The recording medium 17 is a recording medium such as a USB (Universal Serial Bus) memory, an SD memory card, an optical disk, or a magneto-optical disk in which the above-described program is recorded.

  8, 9, and 10 are flowcharts illustrating the control logic of the control information setting unit 104 according to the first embodiment of this invention. FIG. 11 is a diagram illustrating a configuration example of the control information conversion table 105 according to the first embodiment of this invention. Here, a control logic in which the control information setting unit 104 sets control information based on the statistical information received by the statistical information receiving unit 101 at time T1 will be described.

  In step S701, the control information setting unit 104, from the statistical information storage unit 103, the performance predicted value A1 at time T1, the performance predicted value A0 at time T0 immediately before time T1 (before the time window described above), and the performance The variance (square of the standard deviation σ) of the predicted value A1 is acquired (S701).

  In step S702, the control information setting unit 104 acquires the queue length B at time T1 from the statistical information storage unit 103 (S702).

  In step S703, the control information setting unit 104 determines whether or not the variance of the predicted performance value A1 is larger than the threshold value dev (S703). The threshold value dev here is an upper limit value of the variance (variation) of the performance predicted value A1 that can guarantee the reliability of the performance predicted value A1. That is, when the variance of the performance predicted value A1 is larger than the threshold value dev (YES in S703), it is determined that the reliability of the performance predicted value A1 is low. On the other hand, when the variance of the performance predicted value A1 is smaller than the threshold dev (NO in S703), it is determined that the reliability of the performance predicted value A1 is high. This threshold value dev is set for each packet transfer apparatus 200.

  In step S704, the control information setting unit 104 determines whether or not the predicted performance value A1 is increasing (S704). Here, the control information setting unit 104 determines by comparing the performance predicted value A1 acquired in step S701 with the performance predicted value A0. When the predicted performance value A1 is increasing (YES in S704), it is predicted that the packet transfer apparatus 200 will transfer a large amount of packets in the future. On the other hand, when the performance predicted value A1 has not increased (NO in S704), it is predicted that the packet transfer apparatus 200 will transfer the same amount or a smaller amount of packets in the future.

  In step S705, the control information setting unit 104 determines whether or not the queue length B is smaller than the threshold Th (S705). The threshold value Th here is an upper limit value of the queue length that does not cause a decrease in the processing speed of the packet transfer apparatus 200. That is, when the queue length B is smaller than the threshold Th (YES in S705), it is determined that the packet transfer apparatus 200 can appropriately transfer the packet. On the other hand, when the queue length is larger than the threshold Th (NO in S705), it is determined that the processing speed of the packet transfer apparatus 200 is reduced. This threshold Th is set for each input queue of the packet transfer apparatus 200.

  If NO in step S704, the process proceeds to A (step S801 in FIG. 9) or B (step 801 in FIG. 10), and the control information setting unit 104 determines whether or not the performance predicted value A1 has changed. Determination is made (S801). If the predicted performance value A1 has not changed (YES in S801), the packet transfer apparatus 200 is predicted to transfer the same amount of packets in the future. On the other hand, when the performance prediction value A1 changes (becomes a small amount) (NO in S801), the packet transfer apparatus 200 is predicted to transfer a small amount of packets in the future.

  The control information setting unit 104 switches between steps S706 to S708, S802 to S805, and S901 to S905 according to the results of the processes of steps S703 to S705 and S801 described above.

  When the process proceeds to step S706 of FIG. 8, that is, when the variance of the predicted performance value A1 is larger than the threshold value dev, the predicted performance value A1 is increased, and the queue length B is smaller than the threshold value Th, control information setting is performed. The unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed (S706). In step S706, although it is predicted that the packet transfer apparatus 200 will transfer a large amount of packets in the future, the reliability of the performance prediction value A1 is low, and the packet transfer apparatus 200 is appropriate in the determination based on the queue length B. Is determined to be able to transfer the packet. In this case, the control information setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed in order to see the state for a while until the reliability of the performance prediction value A1 becomes high. It is case (1) of FIG.

  When the process proceeds to step S707, that is, when the variance of the predicted performance value A1 is larger than the threshold value dev, the predicted performance value A1 is increased, and the queue length B is larger than the threshold value Th, the control information setting unit 104 Then, control information for increasing the number of packet processing circuits to be operated is set (S707). Step S707 is a case where it is determined in the determination based on the queue length B that the processing speed of the packet transfer apparatus 200 decreases. In this case, it is necessary to increase the number of packet processing circuits to be operated in order to prevent a decrease in the processing speed of the packet transfer apparatus 200. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. It is case (2) of FIG.

  When the process proceeds to step S708, that is, when the variance of the performance prediction value A1 is smaller than the threshold dev and the performance prediction value A1 is increasing, the control information setting unit 104 indicates that the number of packet processing circuits is increased. Control information is set (S708). Step S708 is a case where the reliability of the performance prediction value A1 is high, and it is predicted that the packet transfer apparatus 200 will transfer a large amount of packets in the future. In this case, it is necessary to increase the number of packet processing circuits to be operated regardless of the queue length B. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. Cases (3) and (4) in FIG.

  When the process proceeds to step S802 in FIG. 9, that is, when the variance of the predicted performance value A1 is smaller than the threshold value dev, the predicted performance value A1 is not changed, and the queue length B is smaller than the threshold value Th, the control information The setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed (S802). In step S802, it is predicted that the reliability of the performance prediction value A1 is high, the packet transfer apparatus 200 will transfer the same amount of packets in the future, and the packet transfer apparatus 200 appropriately transmits the packet in the determination based on the queue length B. This is a case where it is determined that transfer is possible. In this case, there is no need to increase or decrease the number of packet processing circuits to be operated. Therefore, the control information setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed. It is case (5) of FIG.

  When the process proceeds to step S803, that is, when the variance of the predicted performance value A1 is smaller than the threshold value dev, the predicted performance value A1 is not changed, and the queue length B is larger than the threshold value Th, the control information setting unit 104 Sets control information to increase the number of packet processing circuits to be operated (S803). Step S803 is a case where it is determined in the determination based on the queue length B that the processing speed of the packet transfer apparatus 200 decreases. In this case, it is necessary to increase the number of packet processing circuits to be operated in order to prevent a decrease in the processing speed of the packet transfer apparatus 200. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. It is case (6) of FIG.

  When the process proceeds to step S804, that is, when the variance of the predicted performance value A1 is smaller than the threshold value dev, the predicted performance value A1 is decreased, and the queue length B is smaller than the threshold value Th, the control information setting unit 104 Then, control information for reducing the number of packet processing circuits to be operated is set (S804). In step S804, the reliability of the performance prediction value A1 is high, the packet transfer apparatus 200 is predicted to transfer a small amount of packets in the future, and the packet transfer apparatus 200 appropriately transmits packets in the determination based on the queue length B. This is a case where it is determined that transfer is possible. In this case, the number of packet processing circuits to be operated may be reduced. Therefore, the control information setting unit 104 sets control information for reducing the number of packet processing circuits to be operated. It is case (11) of FIG.

  When the process proceeds to step S805, that is, when the variance of the performance predicted value A1 is smaller than the threshold dev, the performance predicted value A1 is decreased, and the queue length B is larger than the threshold Th, the control information setting unit 104 Then, control information for increasing the number of packet processing circuits to be operated is set (S805). In step S805, the reliability of the performance prediction value A1 is high, and the packet transfer apparatus 200 is predicted to transfer a small amount of packets in the future. On the other hand, in the determination based on the queue length B, the processing of the packet transfer apparatus 200 is performed. In this case, it is determined that the speed is reduced. In this case, it is necessary to increase the number of packet processing circuits to be operated in order to prevent a decrease in the processing speed of the packet transfer apparatus 200. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. It is case (12) of FIG.

  When the process proceeds to step S901 in FIG. 10, that is, when the variance of the performance predicted value A1 is larger than the threshold dev, the performance predicted value A1 is not changed, and the queue length B is smaller than the threshold Th, the control information The setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed (S901). In step S901, although it is predicted that the packet transfer apparatus 200 will transfer the same amount of packets in the future, the reliability of the performance prediction value A1 is low, and the packet transfer apparatus 200 appropriately determines that the determination is based on the queue length B. In this case, it is determined that the packet can be transferred. In this case, the control information setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed in order to see the state for a while until the reliability of the performance prediction value A1 becomes high. This is the case (9) of FIG.

  When the process proceeds to step S902, that is, when the variance of the predicted performance value A1 is larger than the threshold value dev, the predicted performance value A1 is not changed, and the queue length B is larger than the threshold value Th, the control information setting unit 104 Sets control information to increase the number of packet processing circuits to be operated (S902). Step S902 is a case where it is determined in the determination based on the queue length B that the processing speed of the packet transfer apparatus 200 decreases. In this case, it is necessary to increase the number of packet processing circuits to be operated in order to prevent a decrease in the processing speed of the packet transfer apparatus 200. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. It is case (10) of FIG.

  When the process proceeds to step S903, that is, when the variance of the predicted performance value A1 is larger than the threshold value dev, the predicted performance value A1 is decreased, and the queue length B is smaller than the threshold value Th, the control information setting unit 104 Then, control information for reducing the number of packet processing circuits to be operated is set (S903). In step S903, although it is predicted that the packet transfer apparatus 200 will transfer a small amount of packets in the future, the reliability of the performance prediction value A1 is low, and the packet transfer apparatus 200 appropriately determines in the determination based on the queue length B. In this case, it is determined that the packet can be transferred. In this case, the control information setting unit 104 sets control information indicating that the number of packet processing circuits to be operated is not changed in order to see the state for a while until the reliability of the performance prediction value A1 becomes high. It is case (7) of FIG.

  When the processing proceeds to step S904, that is, when the variance of the predicted performance value A1 is larger than the threshold value dev, the predicted performance value A1 is decreased, and the queue length B is larger than the threshold value Th, the control information setting unit 104 Then, control information for increasing the number of packet processing circuits to be operated is set (S904). Step S904 is a case where it is determined in the determination based on the queue length B that the processing speed of the packet transfer apparatus 200 decreases. In this case, it is necessary to increase the number of packet processing circuits to be operated in order to prevent a decrease in the processing speed of the packet transfer apparatus 200. Therefore, the control information setting unit 104 sets control information for increasing the number of packet processing circuits to be operated. This is Case (8) in FIG.

  As described above, the control information setting unit 104 determines the performance predicted values (performance predicted values A0 and A1 and the variance of the performance predicted values A1) obtained based on the statistical information history of the packet transfer apparatus 200 received by the statistical information receiving unit 101. ) And the queue length B indicating the real-time packet arrival status, and the control information to be set is switched. Accordingly, the packet transfer apparatus 200 can be operated in consideration of both the predicted input band close to the ideal predicted input band and the real-time packet arrival status, and the power consumption of the packet transfer apparatus 200 can be reduced. The control information setting unit 104 sets the control information so that the control information to which the correction amount corresponding to the queue length B is added is limited to the range between the upper limit value and the lower limit value of the performance prediction value. It is preferable to set. This is because a setting value that exceeds the upper limit value of the predicted performance value may cause an increase in power consumption, and a setting value that falls below the lower limit value of the predicted performance value may cause a deterioration in communication quality. It is.

  FIG. 3 is a diagram illustrating a configuration example of the packet transfer apparatus 200 according to the first embodiment of this invention. The packet transfer apparatus 200 shown in FIG. 3 includes N interface units 210-i (i = 1, 2,..., N), a packet relay processing unit 250 that couples the interface units 210-i, and an external control. And a processor 290 connected to the terminal 100.

  Each interface unit 210-i includes a packet reception circuit 230 that performs packet reception processing, an input PB (Packet Buffer) 240 that accumulates packets received by the packet reception circuit 230, and a packet transmission circuit 270 that performs packet transmission processing. The packet transmission circuit 270 includes an output PB 280 that accumulates packets to be transmitted, and a header processing unit 500 that performs packet header processing.

  Each interface unit 210-i includes M input lines 201-ij (i = 1, 2,..., N, j = 1, 2,..., M) and M output lines 202-ij (i = 1, 2,..., N, j = 1, 2,. In the example of FIG. 3, the interface unit 210-1 accommodates input lines 201-11 to 14 and output lines 202-11 to 14. The interface unit 210-2 accommodates input lines 201-21 and 22 and output lines 202-21 and 22. The interface unit 210-N accommodates an input line 201-N and an output line 202-N. These input line 201-ij and output line 202-ij are connected to other communication nodes such as the client PC 2000 and the server 2100, for example.

  The processor 290 is an arithmetic processing unit that executes a program stored in a memory (not shown). The processor 290 notifies the instruction received from the control terminal 100 (including control information for increasing or decreasing the number of packet processing circuits to be operated) to the header processing unit 500 of each interface unit 210-i, or the interface unit 210- The information of i is notified to the control terminal 100.

  FIG. 4 is a diagram illustrating an example of a data format of a packet transmitted and received by the packet transfer apparatus 200 according to the first embodiment of this invention. FIG. 4 shows an example of the data format of packets input / output from the input line 201-ij and output line 202-ij in FIG.

  This data format includes a header portion 310 and a data portion 320. The header unit 310 includes a source IP address (SIP) 311, a destination IP address (DIP: Destination IP address) 312, a source port (SPORT: Source PORT) 313, and a destination port (DPORT: Destination). PORT) 314, DSCP (Differentiated Services Code Point) 315, source MAC address (SMAC) 316, destination MAC address (DMAC) 317, and ether priority (UPRI: User PRIority). ) 318. The transmission source IP address 311 is a transmission address of the network layer (transmission terminal address). The destination IP address 312 is a destination address (receiving terminal address) in the network layer. The transmission source port 313 is a port number of the transmission source. The destination port 314 is a destination port number. DSCP 315 is the transfer priority of the network layer. The source MAC address 316 is the source MAC address of the data link layer. The destination MAC address 317 is a destination MAC address of the data link layer. The ether priority 318 is a transfer priority of the data link layer. On the other hand, the data section 320 includes user data 321 that is application data.

  FIG. 5 is a diagram illustrating an example of a data format of a packet inside the packet transfer apparatus 200 according to the first embodiment of this invention. The data format shown in FIG. 5 includes an internal header portion 330 in addition to the header portion 310 and the data portion 320 of FIG.

  The internal header section 330 includes an input line number 331 that is an identification number of an input line 201-ij that has input a packet, an output line number 332 that is an identification number of an output line 202-ij that outputs a packet, and packet transmission priority. QoS information 333 indicating the degree.

  Returning to FIG. 3, the operation of each part of the packet transfer apparatus 200 will be described in random order.

  When receiving a packet having the data format shown in FIG. 4 from the input line 201-ij, the packet receiving circuit 230 adds an internal header 330 (see FIG. 5) to the input packet. Further, the number of the input line 201 -ij into which the packet is input is written in the field of the input line number 331 in the internal header 330 and stored in the input PB 240. Also, all the information of the header section 310 and the input line number 331 are transmitted to the header processing section 500 as the header information 21.

  The header processing unit 500 determines the output line number of the input packet based on the header information 21 received from the packet receiving circuit 230, the filter information of the flow to which the input packet belongs, and the flow process of determining QoS information Etc. Thereafter, the determined output line number, filter information, and QoS information are transmitted to the packet receiving circuit 230 as output information 22.

  The packet receiving circuit 230 executes the following processing based on the output information 22 received from the header processing unit 500. That is, when the filter information in the output information 22 indicates a packet transfer instruction, the output line number and QoS information in the output information 22 are converted into the output line number 332 and QoS in the internal header 330 of the packet stored in the input PB 240. Each field is written in the information 333 and transmitted to the packet relay processing unit 250. On the other hand, when the filter information in the output information 22 indicates a packet discard instruction, the packet receiving circuit 230 does not transmit the packet stored in the input PB 240 to the packet relay processing unit 250. This packet is eventually overwritten and discarded when another packet arrives.

  The packet relay processing unit 250 transmits the packet received from the packet receiving circuit 230 to the packet transmission circuit 270 of the interface unit 210-i corresponding to the output line number 332 in the internal header 330 of the received packet.

  The packet transmission circuit 270 accumulates the packet received from the packet relay processing unit 250 in the output PB 280. Also, all the information of the header part 310 and the output line number 332 are transmitted to the header processing part 500 as the header information 25.

  Based on the header information 25 received from the packet transmission circuit 270, the header processing unit 500 performs a flow process for determining filter information and QoS information of a flow to which an output packet belongs. Thereafter, the determined filter information and QoS information are transmitted to the packet transmission circuit 270 as output information 26.

  The packet transmission circuit 270 executes the following processing based on the output information 26 received from the header processing unit 500. That is, when the filter information in the output information 26 indicates a packet transmission instruction, the packet receiving circuit 270 converts the QoS information in the output information 26 into the QoS information 333 in the internal header 330 of the packet stored in the output PB 280. Write in the field. Further, based on the value of the field of the output line number 332 in the internal header 330 of this packet, the packet is transmitted to the corresponding output line 202-ij. On the other hand, when the filter information in the output information 26 indicates a packet discard instruction, the packet transmission circuit 270 does not transmit the packet stored in the output PB 280 to the output line 202-ij. This packet is finally overwritten and discarded when another packet arrives.

  In the packet transfer apparatus 200 according to the first embodiment of the present invention described above, the header processing unit 500 includes the input line 201-ij connected to the packet reception circuit 230 and the output line 202 connected to the packet transmission circuit 270. The number of packet processing circuits 510-k (see FIG. 6) to be operated in the header processing unit 500 is switched according to the number of lines ij. The pair of input lines 201-ij and output lines 202-ij make one set, and are connected or disconnected in units of this set. The header processing unit 500 receives notification of the line number information 24 indicating the number of lines of the input line 201-ij and the output line 202-ij from the packet receiving circuit 230.

  In addition, the header processing unit 500 operates the packet processing circuit 510-k (operated in the header processing unit 500 in accordance with the control information received from the control terminal 100 via the processor 290 to increase or decrease the number of operated packet processing circuits. The number is changed. That is, when the control information indicates that the number of packet processing circuits to be operated is increased, the number of packet processing circuits 510-k to be operated is increased. If the control information indicates that the number of packet processing circuits to be operated is not changed, the number of packet processing circuits 510-k to be operated is not changed. If the control information is to reduce the number of packet processing circuits to be operated, the number of packet processing circuits 510-k to be operated is decreased.

  FIG. 6 is a diagram illustrating a configuration example of the header processing unit 500 according to the first embodiment of this invention. The header processing unit 500 includes an input header processing unit 501 that executes header processing of an input packet, and an output header processing unit 502 that executes header processing of an output packet.

  Based on the header information 21, the input header processing unit 501 performs packet processing (the processing for determining the output line number of the input packet described above, the filter information of the flow to which the input packet belongs, the flow processing for determining QoS information, etc. ) And the processing result (output line number, filter information, QoS information) is transmitted to the packet receiving circuit 230 as output information 22. The input header processing unit 501 includes N (four in FIG. 6) packet processing circuits 510-k (k = 1, 2,..., N), a header information storage unit 520, an alignment circuit 540, and a circuit number determination circuit. 570. The circuit number determination circuit 570 receives the notification of the line number information 24 described above.

  Based on the header information 25, the output header processing unit 502 performs packet processing (such as the flow information for determining the flow to which the output packet belongs, the flow processing for determining QoS information, etc.), and the processing result (filter information, QoS information). Is transmitted as output information 26 to the packet transmission circuit 270. The output header processing unit 502 has the same configuration as that of the input header processing unit 501 except that the output header processing unit 502 does not include a notification unit for the line number information 24.

  Hereinafter, the operation of each unit of the input header processing unit 501 will be described. The operation of each unit of the output header processing unit 502 is the same.

  The packet processing circuit 510-k executes packet processing (the above-described output line number determination processing, flow processing, etc.).

  The header information storage unit 520 stores a plurality of input header information 21 (or header information 25), and distributes the stored head information 21 (or header information 25) to one of the packet processing circuits 510-k. To send. Details of the header information storage unit 520 will be described later with reference to FIG.

  The alignment circuit 540 inputs the processing results (output line number, filter information, QoS information) of the packet processing circuit 510-k in the order in which the header information 21 (or header information 25) corresponding to the information is input. The information is rearranged for each line 201-ij (or output line 202-ij) and output as output information 22 (or output information 25). The alignment circuit 540 is provided to prevent the packet order from being changed due to the difference in processing speed between the packet processing circuits 510-k.

  The circuit number determination circuit 570 operates based on the line number information 24 received from the packet receiving circuit 230 and the control information for increasing / decreasing the number of packet processing circuits to be operated received from the control terminal 100 via the processor 290. The number of packet processing circuits 510-k to be determined is determined. Further, the determination result is transmitted to the distribution circuit 523 (see FIG. 7) in the header information storage unit 520.

  FIG. 7 is a diagram illustrating a configuration example of the header information storage unit 520 according to the first embodiment of this invention. The header information storage unit 520 illustrated in FIG. 7 includes a queue 521, a sequence number addition circuit 522, a distribution circuit 523, and a queue counter 524.

  Hereinafter, the operation of each unit of the header information storage unit 520 will be described in random order.

  The sequence number giving circuit 522 gives a sequence number to the input header information 21. Specifically, a counter is provided for each input line 201-ij, and when the header information 21 is input, the input line 201-ij corresponding to the input line number 331 (see FIG. 5) in the input header information 21. Is given as a sequence number. The header information 21 to which the sequence number is assigned is transmitted to the queue 521. At this time, the sequence number assigning circuit 522 counts up the counter value of the input line 201-ij corresponding to the input line number 331 by one.

  The queue 521 stores the header information 21 to which the sequence number is assigned by the sequence number assigning circuit 522.

  The distribution circuit 523 transmits the header information 21 accumulated in the queue 521 to each packet processing circuit 510-k. Specifically, based on the BUSY signal received from the packet processing circuit 510-k and the number of packet processing circuits 510-k to be operated received from the circuit number determination circuit 570, the plurality of packet processing circuits 510-k. The packet processing circuit 510-k that can receive a packet during operation is determined from the inside, and is transmitted to the determined packet processing circuit 510-k. Thus, the plurality of packet processing circuits 510-k can process the packets received from the distribution circuit 523 in parallel.

  As described above, the packet transfer apparatus 200 according to the first embodiment of the present invention is based on the line number information 24 and the instruction from the control terminal 100 (control information for increasing or decreasing the number of packet processing circuits to be operated). The number of packet processing circuits 510-k to be operated can be changed. Instead of changing the number of packet processing circuits 510-k to be operated, the operating frequency of the packet processing circuit 510-k to be operated may be changed. In this case, the operation frequency of the packet processing circuit 510-k is changed in the performance control for a short period (for example, 1 minute), and the operation of the packet processing circuit 510-k is performed in the performance control for a long period (for example, 1 hour). By changing the number, the power consumption of the packet transfer apparatus 200 can be more effectively reduced. The long term assumes a period including a period in which the number of packets to be processed in the queue 521 is zero. On the contrary, the short period is a period in which a packet to be processed is always waiting for processing in the queue 521.

(Second Embodiment)
Each device of the control terminal 100 and the packet transfer device 1100 to be controlled by the control terminal 100 according to the second embodiment of the present invention will be described.

  In the above-described first embodiment (see FIG. 1), only the control terminal 100 sets the control information of the packet transfer apparatus 200. In the second embodiment (see FIG. 12), a mode in which the control terminal 100 and the control setting correction unit 1200 provided in the packet transfer apparatus 1100 set control information of the packet transfer apparatus 200 will be described. In the following description, parts that perform the same functions as those of the first embodiment described above are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate.

  FIG. 12 is a diagram illustrating a configuration example of the packet transfer apparatus 1100 according to the second embodiment of this invention. A packet transfer apparatus 1100 illustrated in FIG. 12 includes a control setting correction unit 1200 having the function of the control terminal 100 in addition to the units of the packet transfer apparatus 200 of the first embodiment.

  FIG. 13 is a diagram illustrating a configuration example of the control setting correction unit 1200 according to the second embodiment of this invention. 13 includes a statistical information calculation unit 1020, a statistical information storage unit 1030, a control information setting unit 1040, a control information conversion table 105, a control target information storage unit 110, a timer 1100, and the like. Is provided.

  The statistical information calculation unit 1020 includes an input bandwidth calculation unit 107, an input queue length calculation unit 108, and a queue length increase rate determination unit 1090.

  Based on the statistical information received from the processor 290 and the value of the timer 1100, the queue length increase rate determination unit 1090 increases the queue length increase rate of each input queue of the packet transfer apparatus 200 (increase in queue length per unit time). Amount). Thereafter, it is determined whether or not the calculated increase rate of the queue length is larger than a predetermined threshold value. Here, the threshold value is an increase rate value indicating a rapid increase in queue length to the extent that the control terminal 100 cannot perform appropriate feedback control. That is, the queue length increase rate determination unit 1090 determines whether or not the queue length is increasing rapidly. Thereafter, the determination result is transmitted to the control information setting unit 1040.

  The statistical information storage unit 1030 stores post-calculation statistical information obtained by the statistical information calculation unit 1020. Note that the amount of data stored in the statistical information storage unit 1030 is smaller than that of the statistical information storage unit 103 of the first embodiment. For example, the statistical information storage unit 1030 stores post-calculation statistical information for each time window that is several times the time window described above. This is to reduce the load on the storage area of the packet transfer apparatus 200.

  The control information setting unit 1040 sets control information to be transmitted to the packet transfer apparatus 200 based on the post-calculation statistical information stored in the statistical information storage unit 103 and the control information conversion table 105. When information indicating that the queue length is rapidly increasing is received from the queue length increase rate determining unit 1090, the control information setting unit 1040 sets control information indicating that the number of packet processing circuits to be operated is increased. To do. This is because it is necessary to increase the number of packet processing circuits to be operated in order to prevent packet discard due to insufficient processing performance of the packet transfer apparatus 200 due to a rapid increase in queue length. In this case, further, information indicating that the control information set by the control information setting unit 1040 is applied in preference to the control information set by the control terminal 100 is added to the control information and transmitted to the processor 290. After that, when receiving information indicating that the control information set by the control information setting unit 1040 is preferentially applied, the processor 290 instructs the header processing unit 500 to increase the number of packet processing circuits to be operated.

  As described above, the packet transfer apparatus 200 according to the second embodiment of the present invention receives instructions from each of the control terminal 100 and the control setting correction unit 1200 (control information indicating that the number of packet processing circuits to be operated is increased or decreased). Based on this, the number of packet processing circuits to be operated can be changed. As a result, even when the queue length increases rapidly and the control terminal 100 cannot perform appropriate feedback control, the packet transfer apparatus 200 is operated in consideration of such a rapid increase in queue length, and packet transfer is performed. The power consumption of the apparatus 200 can be reduced.

  Each embodiment of the present invention has been described above. However, each of the above embodiments shows one application example of the present invention, and the technical scope of the present invention is limited to the specific configuration of each of the above embodiments. It is not the purpose. Various modifications can be made without departing from the scope of the present invention.

1 Computer system 21, 25 Header information 22 Output line information 24 Number of lines information 100 Control terminal (control device)
200 packet transfer device 500 header processing unit

Claims (14)

In a packet transfer apparatus including a plurality of packet processing circuits that execute packet processing based on header information of input packets, a method for controlling operations of the plurality of packet processing circuits,
A first procedure for accumulating a history of packet information including the number of packets input to and output from the packet transfer device during a unit time and a packet length;
A second procedure for calculating an input bandwidth of a packet input to the packet transfer device during each unit time based on the accumulated history of the packet information;
A third procedure for calculating the number of packets accumulated in the queue of the packet transfer device during each unit time based on the accumulated history of the packet information;
According to the calculated input bandwidth of the packet per unit time and the calculated number of packets accumulated in the queue per unit time, the processing performance of the packet processing circuit to be operated among the plurality of packet processing circuits A fourth procedure for setting control information;
A fifth procedure for controlling operations of the plurality of packet processing circuits based on the set control information;
A method for controlling a packet transfer apparatus, comprising: The control information includes information for controlling at least one of the number of packet processing circuits to be operated and an operating frequency,
In the fourth procedure, using the control information conversion table in which the control information to be set is associated with the input bandwidth of the packet per unit time and the number of packets accumulated in the queue per unit time, 2. The method for controlling a packet transfer apparatus according to claim 1, wherein control information to be set associated with a time corresponding to the current time in the unit time is set as control information for the current time.   In the procedure for setting the control information, when the number of packets accumulated in the queue during a predetermined unit time is larger than a predetermined threshold, the processing performance of the packet processing circuit to be operated is improved. 2. The method of controlling a packet transfer apparatus according to claim 1, wherein the control information is set as time control information corresponding to a unit time. In the procedure for setting the control information,
When the variance of the input band during a predetermined unit time is smaller than a predetermined threshold, the predetermined unit indicates that the processing performance of the packet processing circuit to be operated is changed according to the time change of the input band. Set as time control information corresponding to time,
When the variance of the input bandwidth during a predetermined unit time is larger than a predetermined threshold, setting that the processing performance of the packet processing circuit to be operated is maintained as control information of the time corresponding to the predetermined unit time The method of controlling a packet transfer apparatus according to claim 1, wherein:   The procedure for setting the control information sets the control information within a range between an upper limit value and a lower limit value of the calculated input bandwidth of the packet per unit time. A method for controlling a packet transfer apparatus.   In the control procedure, the operation frequency of the packet processing circuit to be operated is controlled in the case of short-term control, and the number of the packet processing circuits to be operated is controlled in the case of long-term control. Item 2. A method for controlling a packet transfer apparatus according to Item 1. The packet transfer device is connected to a control device including a processor that executes a program, a memory that stores a program executed by the processor, and an interface connected to the processor,
The control device executes the first procedure, the second procedure, the third procedure, and the fourth procedure,
The method of controlling a packet transfer apparatus according to claim 1, wherein the packet transfer apparatus executes the procedure of 5. The packet transfer apparatus includes a processor that executes a program, a memory that stores a program executed by the processor, and an interface connected to the processor,
The packet transfer apparatus executes the first procedure, the second procedure, the third procedure, the fourth procedure, and the fifth procedure. Item 2. A method for controlling a packet transfer apparatus according to Item 1. A control device that controls the packet transfer device is connected to the packet transfer device,
Each of the packet transfer device and the control device includes a processor that executes a program, a memory that stores a program executed by the processor, and an interface connected to the processor,
The control device executes the first procedure, the second procedure, the third procedure, and the fourth procedure,
The packet transfer apparatus executes the first procedure, the second procedure, the third procedure, the fourth procedure, and the fifth procedure,
The method further includes a sixth procedure in which the packet transfer apparatus determines a sudden increase in the number of packets accumulated in a queue included in the packet transfer apparatus,
In the fifth procedure,
When it is determined that the number of packets accumulated in the queue is rapidly increased in the sixth procedure, the packet transfer device, based on the control information set by the packet transfer device according to the fourth procedure, Control the operation of multiple packet processing circuits,
When it is not determined that the number of packets accumulated in the queue in the sixth procedure is suddenly increased, the packet transfer device determines whether the plurality of packets are based on the control information set by the control device according to the fourth procedure. The method of controlling a packet transfer apparatus according to claim 1, wherein the operation of the packet processing circuit is controlled. A control device connected to a packet transfer apparatus including a plurality of packet processing circuits for executing packet processing based on header information of input packets, and controlling operations of the plurality of packet processing circuits;
An accumulation unit for accumulating a history of packet information including the number of packets input to and output from the packet transfer device during a unit time and a packet length;
An input bandwidth calculator for calculating an input bandwidth of a packet input to the packet transfer device during each unit time based on the accumulated history of the packet information;
An input queue length calculator that calculates the number of packets stored in the queue of the packet transfer device during each unit time based on the history of the stored packet information;
According to the calculated input bandwidth of the packet per unit time and the calculated number of packets accumulated in the queue per unit time, the processing performance of the packet processing circuit to be operated among the plurality of packet processing circuits A control information setting unit for setting control information;
A control device comprising: The control information includes information for controlling at least one of the number of packet processing circuits to be operated and an operating frequency,
The control information setting unit uses the control information conversion table in which the control information to be set is associated with the input bandwidth of the packet per unit time and the number of packets accumulated in the queue per unit time, 11. The control apparatus according to claim 10, wherein control information to be set associated with a time corresponding to the current time in the unit time is set as control information at the current time.   The control information setting unit indicates that when the number of packets accumulated in the queue during a predetermined unit time is larger than a predetermined threshold, the processing performance of the packet processing circuit to be operated is improved. The control device according to claim 10, wherein the control device is set as control information at a time corresponding to. The control information setting unit
When the variance of the input band during a predetermined unit time is smaller than a predetermined threshold, the predetermined unit indicates that the processing performance of the packet processing circuit to be operated is changed according to the time change of the input band. Set as time control information corresponding to time,
When the variance of the input bandwidth during a predetermined unit time is larger than a predetermined threshold, setting that the processing performance of the packet processing circuit to be operated is maintained as control information of the time corresponding to the predetermined unit time The control device according to claim 10.   The control device according to claim 10, wherein the control information setting unit sets the control information within a range between an upper limit value and a lower limit value of the calculated packet input bandwidth per unit time. .

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