JP2011249986A - Motion compensation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the circuit scale of a motion compensation apparatus supporting multi-codec.SOLUTION: To find an interpolation pixel, a control unit 110 controls so as to make a horizontal filter 130, which performs interpolation in a horizontal direction, output required reference pixels to an appropriate input port according to the compression standard or a target position. Then the control unit 110 controls so that the interpolation values obtained from the horizontal filter 130 is output to an appropriate input port of a vertical filter 150, which performs interpolation in a vertical direction. This allows two-dimensional linear interpolation and processing specific to the compression standard can be realized by the same horizontal filter and the vertical filter.

Description

  The present invention relates to a motion compensation technique when decoding a compressed moving image.

  As a moving image compression technique, ITU-T's H.264 standard. H.264, SMPTE VC-1, ISO MPEG2 and MPEG4 are known. These moving image compression techniques are used as standards in various fields. For example, MPEG2 is used for DVD and H.264 is used for Blu-ray Disc. H.264 is used.

  As described above, there are a plurality of standards (codecs) regarding the compression of moving images. When a compressed moving image is decoded, it is necessary to perform decoding according to the compression standard of the moving image. In recent years, it has been desired that one hardware (H / W) can cope with decoding of moving images of different compression standards.

  In general, decoding of a compressed moving image includes entropy decoding, inverse quantization, inverse transform, motion compensation, a loop filter, and the like. Among these processes, the circuit scale of the H / W part responsible for motion compensation tends to increase.

  Motion compensation at the time of compression is a process for obtaining a motion vector by detecting how a pixel moves between consecutive frames in order to compress efficiently. Motion compensation at the time of decoding is a process for obtaining a pixel value (luminance, color difference, etc.) of a pixel at a position indicated by a motion vector from pixel values of one or a plurality of reference pixels. The specifications of motion compensation differ depending on the moving image compression standard. The reference pixel means a pixel that actually exists in the reference frame.

  Here, motion compensation at the time of decoding will be described for various compression standards. For the sake of clarity, some symbols and terms used in this specification and drawings are defined.

  Unless otherwise specified, in each figure, a black rectangle indicates a reference pixel, and an uppercase alphabetic character is a code for distinguishing the reference pixel. The reference pixels are arranged at equal intervals in the vertical and horizontal directions regardless of the illustration. The position of the reference pixel is called “integer position”. The position indicated by the motion vector is referred to as a “target position”. Note that “pixel” may be used as “pixel value” under the assumption that no misunderstanding occurs.

  When the target position is an integer position, the reference pixel at the integer position is used as the pixel at the target position. On the other hand, when the target position is not an integer position, it is necessary to obtain a pixel at the target position by interpolation using a plurality of reference pixels. Pixels obtained by interpolation are called interpolation pixels. The accuracy of interpolation varies depending on the standard. When interpolation is performed up to a position where the interval between reference pixels is divided into ¼ units, the accuracy of the interpolation is called “¼ accuracy”. In this case, three interpolation pixels can be obtained between two reference pixels adjacent in the horizontal direction or the vertical direction. In addition, when interpolation is performed up to a position where the interval between reference pixels is divided into ½ units, the accuracy of the interpolation is called “½ precision”. In this case, only one interpolation pixel can be obtained between two reference pixels adjacent in the horizontal direction or the vertical direction.

  FIG. 15 shows the positional relationship between the reference pixel and the interpolation pixel. As shown in FIG. 15, pixels A to L represented by black rectangles and capital letters are reference pixels, and their positions are integer positions. Pixels a to v represented by white rectangles and small letters are interpolation pixels.

  The pixel a is a reference pixel on the left side of the two reference pixels among the three interpolation pixels (pixels a, b, and c) between two reference pixels (pixels C and D) adjacent in the horizontal direction. The interpolated pixel closest to (pixel C). The same applies to the pixel t. The positions of the pixel a and the pixel t are expressed as “the horizontal direction is a 1/4 position and the vertical direction is a 0 position”, and are hereinafter referred to as “1/4, 0”.

  The pixel c is a reference pixel on the right side of the two reference pixels among the three interpolation pixels (pixels a, b, c) between two reference pixels (pixels C, D) adjacent in the horizontal direction. This is the closest interpolation pixel to (pixel D). The same applies to the pixel v. The positions of the pixel c and the pixel v are expressed as “the horizontal direction is a 3/4 position and the vertical direction is a 0 position”, and are hereinafter referred to as “3/4, 0”.

  The pixel b is a central interpolation pixel among three interpolation pixels (pixels a, b, and c) between two reference pixels (pixels C and D) adjacent in the horizontal direction. The same applies to the pixel u. The positions of the pixel b and the pixel u are expressed as “the horizontal direction is a 1/2 position and the vertical direction is a 0 position”, and are hereinafter referred to as “1/2, 0”.

  Similarly, the positions of the pixel d and the pixel h are “0, 1/4”, and the positions of the pixel n and the pixel s are “0, 3/4”. The positions of the pixel i and the pixel m are “0, 1/2”.

  The position of each other interpolation pixel is also expressed according to the positional relationship with the reference pixel. For example, the position of the pixel e is “1/4, 1/4”, and the position of the pixel f is “1/2, 1/4”.

  In the following, the interpolation pixels at the positions “1/2, 0”, “0, 1/2”, and “1/2, 1/2” are referred to as “1/2 precision” interpolation pixels. The interpolated pixel at the position is referred to as “¼ accuracy” interpolated pixel.

  That is, when the interpolation accuracy is ½ accuracy, all the interpolation pixels are ½ accuracy interpolation pixels. When the interpolation accuracy is ¼ accuracy, the interpolation pixel is either a ½ accuracy interpolation pixel or a ¼ accuracy interpolation pixel.

Referring to FIG. Next, luminance motion compensation in the case of H.264 will be described.
First, a process for obtaining a half-precision interpolation pixel will be described.
H. In H.264, a 6-tap linear filter is used when obtaining a half-precision interpolation pixel. The processing for obtaining the interpolated pixel b at the “1/2, 0” position is shown in equations (1) and (2).

  “>> 5” in Equation (2) represents a shift process that “shifts to the right by 5 bits”. “Clip ()” is a process of rounding the value in () to unsigned 8 bits (0 to 255). Specifically, when the value in () becomes negative, it is set to 0, and the upper limit value (255 ) Exceeds the upper limit value. In the following description, a process of adding a predetermined value (16 in this case) to a certain value (for example, T) and shifting it, and setting the shifted value to 0 or an upper limit as necessary is summarized. This is called “addition / shift processing” for T. The predetermined value to be added and the number of bits to be shifted are called addition / shift processing parameters.

  That is, the pixel b at the position “1/2, 0” is a value (b ′) obtained by performing interpolation on six reference pixels (E, F, G, H, I, J) arranged in the horizontal direction. Is obtained by adding and shifting.

  Similarly, the pixel s at the position “1/2, 0” is also a value (s ′) obtained by performing interpolation on six reference pixels (K, L, M, N, P, Q) arranged in the horizontal direction. ) Are added and shifted.

Hereinafter, in the description and drawings, two identical lowercase letters such as “aa” and “bb” correspond to b ′ in Expression (1), and are interpolated pixels before addition / shift processing is performed. Indicates the value of.
Aa, bb, gg, and hh in FIG. 16 are calculated by the same method as the process for obtaining b ′ shown in Expression (1) except that the six reference pixels used for obtaining are different.

The processing for obtaining the pixel h at the “0, 1/2” position is shown in Equation (3) and Equation (4).

  That is, the pixel h at the position “1/2, 0” is a value (h ′) obtained by performing interpolation on six reference pixels (A, C, G, M, R, T) arranged in the vertical direction. Is obtained by adding and shifting. The parameters of the addition / shift processing are “16” and “5 bits”, which are the same as the parameters of the addition / shift processing when obtaining the pixel at the “0, 1/2” position.

  Similarly, the pixel m at the position “1/2, 0” is a value (m ′) obtained by performing interpolation on six reference pixels (B, D, H, N, S, U) arranged in the vertical direction. ) Are added and shifted.

  cc, dd, ee, and ff are calculated by the same method as the process for obtaining h ′ shown in Expression (3).

すなわち、画素ｊは、水平方向に並ぶ６つの補間画素の加算・シフト処理前の画素値（ｃｃ、ｄｄ、ｈ'、ｍ'、ｅｅ、ｆｆ）に対して補間を行って得た値（ｊ'）を加算・シフト処理することにより得られる。加算・シフト処理のパラメータは、「５１２」と「１０ビット」である。 The process for obtaining the pixel j at the position “1/2, 1/2” is one of two types represented by Expression (5) and Expression (7) or Expression (6) and Expression (7). . Which one to use is specified during encoding.

That is, the pixel j is a value obtained by performing interpolation on the pixel values (cc, dd, h ′, m ′, ee, ff) before the addition / shift processing of the six interpolation pixels arranged in the horizontal direction (j It can be obtained by adding and shifting '). The parameters for the addition / shift processing are “512” and “10 bits”.

The other processes for obtaining the pixels at the quarter positions and the pixels at the quarter positions are the processes of taking the average of the two pixels (reference pixels or interpolation pixels) and are shown in equations (8) to (19), respectively. It is.

  In the case of VC-1, there are two types of motion compensation for luminance at the time of decoding: Bicubic and Bilinear. Which is used is specified at the time of encoding.

The case of Bicubic will be described with reference to FIGS.
Also in FIG. 17, one lowercase alphabetic character represents an interpolation pixel, and two lowercase alphabetic characters represent an interpolation pixel before addition / shift processing. In the case of VC-1 Bicubic, an interpolation pixel is obtained from four pixels (a reference pixel or another interpolation pixel). For example, the pixel a is obtained from four reference pixels (pixels E, F, G, H) arranged in the same row, and the pixel d is obtained from four reference pixels (B, F, J, N) arranged in the same column. Desired. Further, the pixel r is obtained from four interpolation pixels (pixels nn, n, s, ss) arranged in the same row.

  A more specific description will be given with reference to FIG. In FIG. 18, pixels Q1, Q2, Q3, and Q4 are reference pixels or interpolation pixels, and the direction in which they are arranged is either vertical or horizontal. The pixel w is an interpolation pixel obtained from the pixels Q1 to Q4.

When the pixel w is a pixel at the 1/4 position, the process for obtaining it is expressed by the following equation (20).

When the pixel w is a pixel at the 1/2 position, a process for obtaining it is expressed by the following equation (21).

When the pixel w is a pixel at the 3/4 position, a process for obtaining it is expressed by the following equation (22).

  In the expressions (20), (21), and (22), “shift” indicates the shift amount. “Rnd” indicates a rounded value. The rounding value and the shift amount differ depending on the position of the pixel w. Although not shown in the equations (20) to (22), values obtained by these equations are rounded to unsigned 8 bits as necessary.

  In other words, in the case of VC-1 Bicubic, an interpolation pixel is obtained by performing addition / shift processing on values obtained by performing interpolation on four pixels (reference pixel or interpolation pixel).

  In the case of VC-1 Bilinear, the interpolation pixel is obtained by two-dimensional linear interpolation. Two-dimensional linear interpolation will be described with reference to FIG.

  When the interpolation pixel e is obtained by two-dimensional linear interpolation, four reference pixels (A, B, C, and D) surrounding the pixel e are used. In FIG. 19, “xFrc” and “8-xFrc” indicate horizontal distances, and “yFrc” and “8-yFrc” indicate vertical distances.

The process for obtaining the interpolation pixel e by two-dimensional linear interpolation is represented by the following equation (23).

  In other words, in the case of VC-1 Bilinear, the interpolation pixel adds and shifts the values obtained by obtaining two-dimensional linear interpolation for the four upper, lower, left, and right reference pixels surrounding the interpolation pixel. Can be obtained. The parameters of the addition / shift processing are “rnd” and “shift”, and differ depending on the position of the interpolated pixel to be obtained. Note that. The two-dimensional linear interpolation indicated by the equation (23) is usually performed by a cubic filter.

  MPEG4 has a half-precision motion compensation mode (half-pel motion compensation: hmc) and a quarter-precision motion compensation mode (quarter-pel motion compensation: qmc). MPEG2 has a motion compensation accuracy of 1/2.

With reference to FIG. 20, a process for obtaining an interpolation pixel in the case of MPEG4 qmc will be described. These processes are shown in equations (24) to (39). C [] in these equations is a coefficient. “Rc” is a rounding_control, and is a parameter for controlling the rounding process. “/ 256” means 8-bit shift.

As shown in equations (25) and (26), in the case of MPEG4 qmc, the interpolation pixel b _i (for example, b ₋₁ and b ₁ in FIG. 20) and (0, 1/1) at the position (1/2, 0). 2) The interpolated pixel at the position (c in FIG. 20) is obtained by performing addition / shift processing on values obtained by performing interpolation (8-tap filter) on the eight reference pixels. The parameters are “128-rc” and “8 bits”.

  As shown in the equation (27), the interpolation pixel (d in FIG. 20) at the (1/2, 1/2) position is interpolated with respect to the interpolation pixels at the eight (1/2, 0) positions. It is obtained by adding and shifting the obtained value.

  As shown in Expression (30), the interpolation pixel (k in FIG. 20) at the position (1/4, 1/2) is interpolated with respect to the interpolation pixels at 8 (1/4, 1/2) positions. The obtained value is obtained by performing addition / shift processing, and parameters of the addition / shift processing are “128-rc” and “8 bits”. Further, as shown in the equation (31), the interpolation pixel at (3/4, 1/2) position (l in FIG. 20) is equal to the eight (3/4, 1/2) position interpolation pixels. The value obtained by performing the interpolation is obtained by performing addition / shift processing, and the parameters of the addition / shift processing are “128-rc” and “8 bits”.

As shown in equations (28), (29), (32), and (36), the interpolation pixel (e _i ) at the position (1/4, 0) and the interpolation pixel (f at the position (3/4, 0) _i ) The interpolation pixel (g) at the position (0, 1/2) and the interpolation pixel (m) at the position (0, 3/4) are obtained by averaging one reference pixel and one interpolation pixel. It is done.

  The other interpolation pixels are obtained by averaging the two interpolation pixels as shown in equations (33) to (35) and equations (37) to (39).

With reference to FIG. 21, motion compensation with 1/2 accuracy of MPEG2 and MPEG4 will be described. In this case, the interpolation pixel is an interpolation pixel (b, e in FIG. 21) at the position (1/2, 0), an interpolation pixel (c in FIG. 21) at the position (0, 1/2), (1 / 2, 1/2) is any of the interpolation pixels (d in FIG. 21). Processing for obtaining these interpolated pixels at different positions is shown in the following equations (40) to (42). In the case of MPEG2, since there is no parameter called rounding_control, “rc” in these equations is 0.

  As shown in equations (40) and (41), the interpolation pixels at the (1/2, 0) position and the (0, 1/2) position are obtained by averaging two reference pixels. Further, the interpolation pixel at the (1/2, 1/2) position is obtained by adding / shifting values obtained by performing two-dimensional linear interpolation on the four reference pixels. The two-dimensional linear interpolation for the four reference pixels is usually performed by a cubic filter.

  The luminance motion compensation defined by various compression standards has been described above. As for the color difference, in any of these standards, the interpolation pixel is obtained by two-dimensional linear interpolation (cubic filter) shown in FIG.

  In this way, the motion compensation specifications at the time of decoding differ depending on the moving image compression standard. In order to cope with a plurality of compression standards, there is a problem that if the H / W for performing motion compensation is provided for each standard, the circuit scale becomes large.

  Patent Document 1 discloses a motion compensation technique that can support a plurality of compression standards. This will be described with reference to FIG.

  FIG. 22 is FIG. 4 of Patent Document 1 and shows a multi-codec motion compensation device. The motion compensation engine 40 in this apparatus includes a DMA I / F 30, a vertical filter 41, a first horizontal filter 42, a second horizontal filter 43, a cubic alignment unit 44, and a cubic filter 45. The vertical filter 41, the first horizontal filter 42, and the second horizontal filter 43 are all filters that perform one-dimensional interpolation, and the cubic filter 45 performs two-dimensional linear interpolation. The cubic alignment unit 44 selects data (pixel value) to be input to the cubic filter 45. At the time of motion compensation, one or more filters are selected according to the compression standard (codec).

  For example, H.M. In the case of H.264, the filters are selected in the order of the vertical filter 41, the first horizontal filter 42, and the second horizontal filter 43, and up to ½ precision interpolation pixels are calculated. Thereafter, the cubic filter 45 calculates an interpolation pixel with ¼ accuracy.

  In the case of VC-1 Bilinear, MPEG4 1/2 accuracy mode and MPEG2, motion compensation of color difference of each codec, only the cubic alignment unit 44 is used, and the vertical filter 41, the first horizontal filter 42, and the second horizontal filter 43 are used. Is not used.

  According to this technique, a filter that can be shared among a plurality of codecs is shared, and a filter is selectively used according to the codec, thereby reducing the number of components and reducing the circuit scale.

JP 2008-125078 A

  The motion compensation engine 40 in the apparatus shown in FIG. 22 includes a horizontal filter, a vertical filter, and a cubic filter for one-dimensional interpolation in the horizontal direction, one-dimensional interpolation in the vertical direction, and two-dimensional linear interpolation.

  H. The cubic filter 45 is used to calculate a ¼ precision pixel in the H.264 case. As described above, H.P. In the case of H.264, the 1/4 precision pixel calculation process is a simple average process (formulas (8) to (19)).

  The present invention has been made in view of the above circumstances, and provides a technique that can further reduce the circuit scale of a motion compensation device that can handle multi-codecs.

  One aspect of the present invention is a motion compensation device that performs motion compensation at the time of decoding a compressed moving image and obtains a pixel value of a pixel at a target position that is a position indicated by a motion vector, and supports a plurality of compression standards. .

  The motion compensation apparatus includes a control unit, a horizontal filtering processing unit, a vertical filtering processing unit, an addition / shift processing unit, and an average processing unit.

  The horizontal filtering processing unit has a horizontal filter. The horizontal filter receives two or more values from the control unit, and performs a one-dimensional interpolation on the two or more values to obtain a horizontal interpolation value. In the horizontal filter, the number of the two or more values to be input and the interpolation parameter are variable.

  The vertical filtering processing unit has a vertical filter. The vertical filter receives two or more values from the control unit, and performs a one-dimensional interpolation on the two or more values to obtain a vertical interpolation value. In the vertical filter, the number of input two or more values and the interpolation parameter are variable.

  The addition / shift processing unit receives a horizontal interpolation value from the horizontal filtering processing unit or a vertical interpolation value from the vertical filtering processing unit, adds a predetermined value to the horizontal interpolation value or the vertical interpolation value, and then shifts a predetermined number of bits. An addition / shift process is performed to obtain an addition / shift value. The predetermined value and the predetermined number of bits are parameters for addition / shift processing.

  In the averaging process, two values are input and an average value of the two values is obtained. These two values are input from one or both of the control unit and the addition / shift processing unit.

  The horizontal filtering processing unit can output a horizontal interpolation value as a processing result to the control unit and the addition / shift processing unit.

  The vertical filtering processing unit can output a vertical interpolation value as a processing result to the control unit and the addition / shift processing unit.

  The addition / shift processing unit can output the addition / shift value as the processing result to the outside as the pixel value of the pixel at the target position, and can output the addition / shift value to the control unit and the average processing unit.

  The average processing unit can output the average value as the processing result to the outside as the pixel value of the pixel at the target position, and can output the average value to the control unit.

When the target position is other than the integer position that is the position of the reference pixel, the control unit performs the following processes according to the compression standard of the moving image and the target position.
(1) Setting of parameters of the horizontal filter, the vertical filter, and the addition / shift processing unit.
(2) Control of the output destination of the processing result by each processing unit.
(3) Retaining the processing result when the output destination of the processing result is the control unit.
(4) The pixel value of one or more reference pixels, the retained one or more horizontal interpolation values, the retained one or more vertical interpolation values, and the retained one or more addition / shift values, , Outputting one or more values of the held one or more average values to any of the horizontal filter, the vertical filter, and the average processing unit.

  In addition, in order to obtain a pixel value at the target position according to the compression standard and the target position, the control unit performs horizontal conversion when performing processing to obtain a cubic interpolation value by performing two-dimensional linear interpolation on the four values. The cubic value is output by outputting two of the four values to one of the filter and the vertical filter, and then outputting two horizontal interpolation values or two vertical interpolation values obtained by the one filter to the other filter. Get the interpolated value.

  It should be noted that the above-described apparatus is replaced with a method or system, and is effective as an aspect of the present invention.

  According to the technique according to the present invention, the circuit scale of a motion compensation device corresponding to a plurality of compression standards can be suppressed.

It is a figure which shows the moving image decoding apparatus concerning the 1st Embodiment of this invention. It is a figure which shows the motion compensation engine in the moving image decoding apparatus shown in FIG. It is a figure which shows the horizontal filter in the motion compensation engine shown in FIG. It is a figure which shows the kind of interpolation pixel which an addition / shift process part and an average process part output for every specification. It is a figure for demonstrating the method of the two-dimensional linear interpolation by the technique of this invention (the 1). It is a figure for demonstrating the method of the two-dimensional linear interpolation by the technique of this invention (the 2). It is a figure which shows the motion compensation engine concerning the 2nd Embodiment of this invention. It is a figure which shows the motion compensation engine concerning the 3rd Embodiment of this invention. FIG. 9 is a diagram for explaining an example of calculating interpolation pixels by the motion compensation engine shown in FIG. 8 (part 1); FIG. 9 is a diagram for explaining an example of calculating interpolation pixels by the motion compensation engine shown in FIG. 8 (part 2); FIG. 9 is a diagram for explaining an example of calculation of interpolation pixels by the motion compensation engine shown in FIG. 8 (No. 3). FIG. 9 is a diagram for explaining an example of calculation of interpolation pixels by the motion compensation engine shown in FIG. 8 (No. 4). FIG. 9 is a diagram for explaining an example of calculation of interpolation pixels by the motion compensation engine shown in FIG. 8 (No. 5). It is a figure which shows the motion compensation engine concerning the 4th Embodiment of this invention. It is a figure for demonstrating the positional relationship of a reference pixel and an interpolation pixel. H. 2 is a diagram for explaining how to obtain an interpolation pixel (luminance) in the case of H.264. It is a figure for demonstrating how to obtain | require the interpolation pixel (luminance) in the case of VC-1 Bicubic (the 1). It is a figure for demonstrating how to obtain | require the interpolation pixel (luminance) in the case of VC-1 Bicubic (the 2). It is a figure for demonstrating two-dimensional linear interpolation. It is a figure for demonstrating how to obtain | require the interpolation pixel (luminance) in the case of the qmc mode of MPEG4. It is a figure for demonstrating how to obtain | require the interpolation pixel (luminance) in the hmc mode of MPEG4 and MPEG2. It is a figure which shows the motion compensation apparatus disclosed by patent document 1. FIG.

  Embodiments of the present invention will be described below with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware, and a program loaded in the memory in terms of software. Etc. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

<First Embodiment>
FIG. 1 shows a moving picture decoding apparatus 80 according to the first embodiment of the present invention. In FIG. 1, only the components necessary for explaining the motion compensation technique of the present invention are shown, and the motion compensation technique of the present invention is provided in a normal moving image apparatus such as a functional block responsible for inverse quantization. Others that are not particularly necessary are omitted.

  The moving picture decoding apparatus 80 includes a memory 84, a DMA (Direct Memory Access) controller 114, an entropy decoding unit 88, a DMA IF 90 (IF: Interface), and a motion compensation engine 100, which are connected to a system bus 82.

  The memory 84 stores reference pictures that have already been decoded. Each pixel in the reference picture stored in the memory 84 becomes a reference pixel. The memory 84 also stores each motion vector of the current decoding target picture obtained by the entropy decoding unit 88.

  The entropy decoding unit 88 performs entropy decoding, and obtains a codec signal indicating a compression standard for moving images and each motion vector of a current picture to be decoded (hereinafter referred to as a target picture). The entropy decoding unit 88 outputs the codec signal to the motion compensation engine 100 and the motion vector to the memory 84 via the system bus 82.

  The motion compensation engine 100 performs motion compensation, and obtains a pixel at a position (target position) indicated by each motion vector in a target picture. The motion compensation engine 100 sequentially reads out motion vectors from the memory 84 and reads out necessary reference pixels from the memory 84 according to the compression standard indicated by the codec signal and the target position indicated by the motion vector. The motion compensation engine 100 reads a motion vector and a reference pixel from the memory 84 via the DMA IF 90. It should be noted that the motion compensation engine 100 in this embodiment is an H.264 standard. H.264, VC-1, MPEG4, and MPEG2.

  The DMA IF 90 issues a DMA request to the DMA controller 86 for the motion vector and the reference pixel read by the motion compensation engine 100 via the system bus 82. The DMA controller 86 causes the memory 84 to output a motion vector and a reference pixel in response to a DMA request from the DMA IF 90, and supplies the motion compensation engine 100 via the system bus 82 and the DMA IF 90.

  FIG. 2 shows the motion compensation engine 100. The motion compensation engine 100 includes a control unit 110, a horizontal filtering processing unit 120, a vertical filtering processing unit 140, an addition / shift processing unit 160, and an average processing unit 170.

  The horizontal filtering processing unit 120 includes a horizontal filter 130. The horizontal filter 130 receives pixel values of two or more pixels arranged in the horizontal direction from the control unit 110, and performs interpolation on the two or more pixel values to obtain one interpolation value. Hereinafter, this interpolation value is referred to as a horizontal interpolation value. Note that two or more pixel values input from the control unit 110 to the horizontal filter 130 may be pixel values of reference pixels or may not be pixel values of reference pixels. This will be described later.

  The horizontal filter 130 has variable number of input pixel values and interpolation parameters. The number of input pixel values and parameters are controlled by the control unit 110.

  Further, the horizontal filtering processing unit 120 can output the horizontal interpolation value obtained by the horizontal filter 130 to the control unit 110 and the addition / shift processing unit 160. The output destination of the horizontal interpolation value is controlled by the control unit 110.

  FIG. 3 shows a configuration example of the horizontal filter 130. The horizontal filter 130 in FIG. 3 includes eight registers fR0 to fR7, seven adders (sum0 to sum6), and four multipliers mul0 to mul3.

  Each value is set by the control unit 110 in the registers fR0 to fR7. The adder sum0, the adder sum1, the adder sum2, and the adder sum3 respectively add the register fR3 and the register fR4, add the register fR2 and the register fR5, add the register fR1 and the register fR6, and add the register fR0 and the register fR7. Do.

  The multiplier mul0 is the multiplier mul1, the multiplier mul2, the multiplier mul3 is the output of the adder sum0 and the coefficient a0, the output of the adder sum1 and the coefficient a1, and the output of the adder sum2 and the coefficient a2. , The output of the adder sum3 and the coefficient a3 are respectively multiplied.

  The adder sum4 adds the outputs of the multiplier mul0 and the multiplier mul1, and the adder sum5 adds the outputs of the multiplier mul2 and the multiplier mul3.

  The adder sum6 adds the outputs of the adder sum4 and the adder sum5. The output of the adder sum6 is the output of the horizontal filter 130 (horizontal interpolation value).

  The values of the registers fR0 to fR7 and the coefficients a0 to a3 are set by the control unit 110. When values are set in all of the registers fR0 to fR7, the horizontal filter 130 is an 8-tap filter. The control unit 110 can adjust the number of taps of the horizontal filter by not setting values in some registers. Not setting a value in the register is equivalent to setting the value of the register to “0”.

  For example, when the control unit 110 sets values for all of the registers fR0 to fR7, the horizontal filter 130 is an 8-tap filter. When the control unit 110 sets values only for the registers fR1 to fR6, the horizontal filter 130 is a 6-tap filter. Furthermore, when the control unit 110 sets values only for the registers fR2 and fR5, the horizontal filter 130 is a 4-tap filter. Further, when the control unit 110 sets values only for the registers fR3 and fR4, the horizontal filter 130 is a 2-tap filter.

Returning to FIG.
The horizontal filtering processing unit 120 can output the horizontal interpolation value obtained by the horizontal filter 130 to the control unit 110 and the addition / shift processing unit 160. The control unit 110 controls which of the control unit 110 and the addition / shift processing unit 160 outputs the data.

  The vertical filtering processing unit 140 includes a vertical filter 150. The vertical filter 150 receives pixel values of two or more pixels arranged in the vertical direction from the control unit 110, and interpolates the two or more pixel values to obtain one interpolation value. Hereinafter, this interpolation value is referred to as a vertical interpolation value. Note that two or more pixel values input from the control unit 110 to the vertical filter 150 may be pixel values of reference pixels or may not be pixel values of reference pixels. This will be described later.

  The vertical filter 150 is variable in the number of input pixel values and interpolation parameters. The number of input pixel values and parameters are controlled by the control unit 110.

  The vertical filtering processing unit 140 can output the vertical interpolation value obtained by the vertical filtering processing unit 140 to the control unit 110 and the addition / shift processing unit 160. The output destination of the vertical interpolation value is controlled by the control unit 110.

  Note that the specific configuration of the vertical filter 150 can be the same as that of the horizontal filter 130 shown in FIG.

  When the horizontal interpolation value is input from the horizontal filtering processing unit 120 or when the vertical interpolation value is input from the vertical filtering processing unit 140, the addition / shift processing unit 160 inputs the horizontal interpolation value or the vertical interpolation value. Addition / shift processing is performed on. In the addition / shift process, a predetermined value is added to the input value to shift the predetermined number of bits, and then rounded as necessary. In the present embodiment, the pixel value is 8 bits, and the addition / shift processing performed by the addition / shift processing unit 160 is necessary after adding a predetermined value to the input value and shifting the predetermined number of bits. The output value is set to “0” or “256” according to the above. The addition / shift processing parameters (a predetermined value to be added and a predetermined number of bits to be shifted) are controlled by the control unit 110. The processing result of the addition / shift processing unit 160 is hereinafter referred to as an addition / shift value.

  The addition / shift processing unit 160 can output the addition / shift value as a pixel value of the pixel at the target position to the outside (for example, a processing block in the next stage of the motion compensation engine 100, not shown), and the addition / shift. The value can be output to the control unit 110 and the average processing unit 170. The output destination of the addition / shift value is controlled by the control unit 110.

  The average processing unit 170 receives two values and calculates an average value of the two values. The two values are input from one or both of the control unit 110 and the addition / shift processing unit 160. Details of the two values input to the average processing unit 170 will be described later.

  The average processing unit 170 can output an average value as a processing result to the outside and the control unit 110. The output destination of the average value is controlled by the control unit 110.

  When the target position indicated by the motion vector is an integer position, the control unit 110 reads the reference pixel at the integer position from the memory 84 and outputs it to the outside. This is the same for both luminance and color difference.

When the target position indicated by the motion vector is not an integer position, the control unit 110 performs the following processing for luminance according to the compression standard indicated by the codec signal and the target position.
(1) Parameter setting of the horizontal filter 130, the vertical filter 150, and the addition / shift processing unit 160.
(2) Control of the output destination of the processing result by each processing unit.
(3) Retaining the processing result when the output destination of the processing result is the control unit 110.
(4) The pixel value of one or more reference pixels, the retained one or more horizontal interpolation values, the retained one or more vertical interpolation values, and the retained one or more addition / shift values, , Outputting one or more values of the held one or more average values to any one of the processing units.

  In addition, the control unit 110 performs a two-dimensional linear interpolation on the four values to obtain a cubic interpolation value in order to obtain a pixel value at the target position according to the compression standard and the target position. Two of the four values are output to one of the horizontal filter 130 and the vertical filter 150, and then two horizontal interpolation values or two vertical interpolation values obtained by the one filter are output to the other filter. To obtain the cubic interpolation value.

  The interpolated pixels are output to the outside by the addition / shift processing unit 160 or the average processing unit 170. FIG. 4 shows the interpolation pixels output to the outside by the addition / shift processing unit 160 and the interpolation pixels output to the outside by the average processing unit 170 in the present embodiment.

  As shown in FIG. All the H.264 half-precision interpolation pixels are output from the addition / shift processing unit 160 to the outside, and all the 1 / 4-system interpolation pixels are output from the average processing unit 170 to the outside.

  In the case of VC-1 Bicubic and VC-1 Bilinear, all interpolation pixels are output from the addition / shift processing unit 160 to the outside.

  In the case of the MPEG4 qmc mode, all ½ precision interpolation pixels and some ¼ precision interpolation pixels are output to the outside from the addition / shift processing unit 160, and other ¼ precision interpolation pixels are output. Output from the average processing unit 170 to the outside.

  In the MPEG4 hmc mode and MPEG2, the interpolation pixel at the (1/2, 1/2) position is output from the addition / shift processing unit 160, and the interpolation pixel at the other position is output from the average processing unit 170 to the outside. .

  For color differences, all interpolation pixels are output from the addition / shift processing unit 160 to the outside in all standards.

The operation of the control unit 110 when obtaining the interpolation pixel for each compression standard will be described in detail.
First, luminance will be described.

<H. For H.264>
1. Interpolated pixel (luminance) at (1/2, 0) position among interpolated pixels of 1/2 accuracy
The interpolation pixel b in FIG. 16 is taken as an example.
In this case, the control unit 110 reads the reference pixels E, F, G, H, I, and J from the memory 84 and sets the horizontal filter 130 so that the processing expressed by the above-described equation (1) is performed. The addition / shift processing unit 160 is set so that the process indicated by Expression (2) is performed. Further, control is performed so that the output destination of the horizontal filter 130 is the addition / shift processing unit 160 and the output destination of the addition / shift processing unit 160 is external. Thus, the interpolation pixel b is obtained and output from the addition / shift processing unit 160 to the outside.

2. Interpolated pixel (luminance) at (0, 1/2) position among interpolated pixels of 1/2 accuracy
The interpolation pixel h in FIG. 16 is taken as an example.
In this case, the control unit 110 reads the reference pixels A, C, G, M, R, and T from the memory 84 and sets the vertical filter 150 so that the process represented by the above-described equation (3) is performed. The addition / shift processing unit 160 is set so that the process indicated by Expression (4) is performed. Further, control is performed so that the output destination of the vertical filter 150 is the addition / shift processing unit 160 and the output destination of the addition / shift processing unit 160 is external. Thus, the interpolation pixel h is obtained and output from the addition / shift processing unit 160 to the outside.

3. Interpolation pixel (luminance) at (1/2, 1/2) position among interpolation pixels of 1/2 accuracy
The interpolation pixel j in FIG. 16 is taken as an example.
In this case, there are two ways to obtain it.
(1) When Obtaining by Expression (5) and Expression (7) As in the case of obtaining the interpolation pixel at the (0, 1/2) position described above, the control unit 110 obtains six references for obtaining the pixel cc. The pixel is read from the memory 84, and the vertical filter 150 is set so that the processing corresponding to Expression (3) is performed. In this case, the control unit 110 performs control so that the output destination of the vertical filter 150 is the control unit 110. That is, for the position of the pixel cc, the pixel value (vertical interpolation value) of the interpolation pixel before the addition / shift processing is output to the control unit 110.

  The control unit 110 holds the vertical interpolation value cc from the vertical filter 150 and causes the vertical filter 150 to obtain and hold the vertical interpolation values dd, h ′, m ′, ee, and ff in the same procedure.

  Then, the control unit 110 outputs the held six vertical interpolation values cc, dd, h ′, m ′, ee, and ff to the horizontal filter 130, and the horizontal filter is processed so that the processing represented by Expression (5) is performed. 130 is set. At this time, the control unit 110 controls the output destination of the horizontal filter 130 to be the addition / shift processing unit 160 and sets the addition / shift processing unit 160 so that the processing shown in Expression (7) is performed. The output destination of the addition / shift processing unit 160 is controlled to be external. Thus, the interpolation pixel j is obtained and output from the addition / shift processing unit 160 to the outside.

(2) When Interpolation Pixel j is Obtained by Equation (6) and Equation (7) The control unit 110 causes the horizontal filter 130 to obtain and hold the horizontal interpolation values aa, bb, b ′, s ′, gg, and hh. . Then, the six horizontal interpolation values are output to the vertical filter 150, and the vertical filter 150 is set so that the processing shown in Expression (6) is performed. At this time, the control unit 110 controls the output destination of the vertical filter 150 to be the addition / shift processing unit 160 and sets the addition / shift processing unit 160 so that the processing shown in Expression (7) is performed. The output destination of the addition / shift processing unit 160 is controlled to be external. Thus, the interpolation pixel j is obtained and output from the addition / shift processing unit 160 to the outside.

4. 1/4 precision interpolation pixel (luminance)
H. In the case of H.264, the interpolation pixel with ¼ accuracy is the average of one reference pixel and one ½ accuracy interpolation pixel (equations (8) to (11)), or two ½ accuracy interpolation pixels. Of the average (formulas (9) to (19)).

(1) When Obtained by Average of One Reference Pixel and One Half Precision Interpolation Pixel As described above, the control unit 110 converts the half precision interpolation pixel into the horizontal filter 130 and / or the vertical filter 150. Then, the addition / shift processing unit 160 determines that the output destination of the addition / shift processing unit 160 is the average processing unit 170. The control unit 110 reads out the above one reference pixel from the memory 84, and outputs the reference pixel from the addition / shift processing unit 160 to the average processing unit 170 as the half-precision interpolation pixel is output to the average processing unit 170. Output to 170. Further, control is performed so that the output destination of the average processing unit 170 is external.
Thus, the interpolated pixels a, c, d, and n in FIG. 16 are obtained and output from the average processing unit 170 to the outside.

(2) When Obtained by Average of Two Half-Precision Interpolated Pixels First, the control unit 110 obtains one half-precision interpolated pixel. In this case, the control unit 110 controls the output destination of the addition / shift processing unit 160 to be the control unit 110 and holds one half-precision interpolation pixel from the addition / shift processing unit 160.

And the control part 110 calculates | requires the interpolation pixel of the other half precision. In this case, the control unit 110 performs control so that the output destination of the addition / shift processing unit 160 is the average processing unit 170, and the other half-precision interpolation pixel is added from the addition / shift processing unit 160 to the average processing unit. Along with the output to 170, the held one half precision interpolation pixel is output to the average processing unit 170. Further, control is performed so that the output destination of the average processing unit 170 is external.
Thus, the interpolated pixels f, i, k, q, e, g, p, and r in FIG. 16 are obtained and output from the average processing unit 170 to the outside.

  That is, H.I. In the case of H.264, all the ½ precision interpolation pixels are output from the addition / shift processing unit 160 to the outside, and all the ¼ precision interpolation pixels are output from the average processing unit 170 to the outside.

<VC-1 Bicubic>
The interpolation pixel w will be described as an example with reference to FIGS.

In the case of an interpolation pixel (luminance) obtained from 1.4 reference pixels In this case, the pixels Q1, Q2, Q3, and Q4 in FIG. 18 are reference pixels, and the interpolation pixels a and d in FIG. This corresponds to the interpolation pixel w at the position, the interpolation pixels b, h, and m correspond to the interpolation pixel w at the 1/2 position, and the interpolation pixels c and n correspond to the interpolation pixel w at the 3/4 position.

  In this case, the control unit 110 reads out the four reference pixels Q1 to Q4 necessary for obtaining the interpolation pixel w from the memory 84, outputs them to the horizontal filter 130 or the vertical filter 150, and also outputs the horizontal filter 130 or the vertical filter 150. Is output to the addition / shift processing unit 160, and the output destination of the addition / shift processing unit 160 is controlled to be external, and the parameter corresponding to the position of the interpolation pixel w is added to the horizontal filter 130 or the vertical filter 150. Set in the shift processing unit 160.

  Specifically, when the four reference pixels Q1 to Q4 are arranged horizontally and the interpolation pixel w is a pixel at the 1/4 position, the control unit 110 applies the four reference pixels Q1 to Q4 to the horizontal filter. The parameters of the horizontal filter 130 and the addition / shift processing unit 160 are set so that the processing shown in Expression (20) is performed.

  When the four reference pixels Q1 to Q4 are arranged horizontally and the interpolation pixel w is a pixel at a 1/2 position, the control unit 110 outputs the four reference pixels Q1 to Q4 to the horizontal filter 130. Then, the parameters of the horizontal filter 130 and the addition / shift processing unit 160 are set so that the processing represented by the equation (21) is performed.

  When the four reference pixels Q1 to Q4 are arranged horizontally and the interpolation pixel w is a pixel at the 3/4 position, the control unit 110 outputs the four reference pixels Q1 to Q4 to the horizontal filter 130. Then, the parameters of the horizontal filter 130 and the addition / shift processing unit 160 are set so that the processing represented by the equation (22) is performed.

  On the other hand, when the four reference pixels Q1 to Q4 are arranged vertically, the control unit 110 outputs the reference pixels Q1 to Q4 to the vertical filter 150, and the position of the interpolation pixel w (1/4 position or 1 / The parameters of the vertical filter 150 and the addition / shift processing unit 160 are set so that any one of the expressions (20) to (22) is performed according to whether the position is 2 position or 3/4 position.

2. In the case of an interpolation pixel (luminance) obtained from four interpolation pixels In this case, the pixels Q1, Q2, Q3, and Q4 in FIG. 18 are interpolation pixels. For example, the interpolation pixel p in FIG. 17 corresponds to the interpolation pixel at the 1/4 position in this case, q corresponds to the interpolation pixel at the 1/2 position in this case, and the interpolation pixel r is 3/4 in this case. Corresponds to the position interpolation pixel.

  The control unit 110 first obtains four interpolation pixels Q1 to Q4 for obtaining the interpolation pixel w. For example, when obtaining the interpolation pixel r, first, the vertical filter 150 and the addition / shift processing unit 160 sequentially obtain the interpolation pixels nn, n, s, and ss, and the output destination of the addition / shift processing unit 160 is the control unit 110. Control to become. The four interpolated pixels nn, n, s, and ss are all interpolated pixels obtained from the four reference pixels, and thus are obtained by the method described above.

  The control unit 110 holds the interpolation pixels nn, n, and s from the addition / shift processing unit 160, and when the interpolation pixel ss is output from the addition / shift processing unit 160, the four interpolation pixels nn, n, and s. , Ss are output to the horizontal filter 130, and the horizontal filter 130 and the addition / shift processing unit 160 are set so that the processing shown in Expression (22) is performed. Also, control is performed so that the output destination of the addition / shift processing unit 160 is external.

  Thus, in the case of VC-1 Bicubic, all the interpolated pixels are output from the addition / shift processing unit 160 in terms of luminance.

<VC-1 Biline>
As described above, in this case, all the interpolated pixels are obtained by the process shown in Expression (23). The part before the addition / shift processing in Expression (23) is normally performed by a cubic filter.

With reference to FIG. 5, a method for realizing the processing represented by Expression (23) in the present embodiment will be described.
In order to obtain the interpolation pixel e, the control unit 110 first reads the reference pixels A and B from the memory 84 and outputs the reference pixels A and B to the horizontal filter 130, and the processing expressed by the following equation (43) is performed. The horizontal filter 130 is set so that the output destination is the control unit 110. Thereby, a horizontal interpolation value at the position of the pixel F is obtained from the horizontal filter 130. The control unit 110 holds the horizontal interpolation value of the pixel F from the horizontal filter 130.

  Then, the control unit 110 reads the reference pixels C and D from the memory 84 and outputs the reference pixels C and D to the horizontal filter 130, so that the processing indicated by Expression (44) is performed, and the output destination of the horizontal filter 130 is the control unit 110. The horizontal filter 130 is set.

  When the horizontal interpolation value of the pixel G is obtained from the horizontal filter 130, the control unit 110 outputs the horizontal interpolation value of the pixel F and the horizontal interpolation value of the pixel G to the vertical filter 150, and Expression (45) is obtained. The parameters of the vertical filter 150 and the addition / shift processing unit 160 are set so that the processing shown in FIG. 4 is performed, and the output destination of the vertical filter 150 is the addition / shift processing unit 160, and the output destination of the addition / shift processing unit 160 is Control to be external.

  Since the processing represented by the equations (43) to (45) is equivalent to the processing represented by the equation (23), in the case of VC-1 Bilinear, all the interpolated pixels are added / The data is output from the shift processing unit 160 to the outside.

Of course, instead of the equations (43) to (45), the processing is equivalent to the processing represented by the equation (23), and therefore, the processing may be performed as the following equations (46) to (48). This will be described with reference to FIG.

  In order to obtain the interpolation pixel e, the control unit 110 first reads the reference pixels A and C from the memory 84 and outputs the reference pixels A and C to the vertical filter 150, and the processing shown in Expression (46) is performed. The vertical filter 150 is set so that becomes the control unit 110. Thereby, a vertical interpolation value at the position of the pixel F is obtained from the vertical filter 150. The control unit 110 holds the vertical interpolation value of the pixel F from the vertical filter 150.

  Then, the control unit 110 reads the reference pixels B and D from the memory 84 and outputs the reference pixels B and D to the vertical filter 150, so that the processing represented by Expression (47) is performed, and the output destination of the vertical filter 150 is the control unit 110. The vertical filter 150 is set.

  When the control unit 110 obtains the vertical interpolation value of the pixel G from the vertical filter 150, the control unit 110 outputs the held vertical interpolation value of the pixel F and the vertical interpolation value of the pixel G to the horizontal filter 130. The parameters of the horizontal filter 130 and the addition / shift processing unit 160 are set so that the processing shown in FIG. 4 is performed, and the output destination of the horizontal filter 130 becomes the addition / shift processing unit 160, and the output destination of the addition / shift processing unit 160 is Control to be external.

  Also in this case, all the interpolated pixels are output from the addition / shift processing unit 160 to the outside.

<MPEG4 qmc mode>
In this case, it is necessary to obtain interpolated pixels up to ¼ precision.
1. In the case of an interpolation pixel (luminance) with 1/2 accuracy (1) Interpolation pixel at position (1/2, 0) Interpolation pixels b ₋₁ and b ₁ in FIG. 20 correspond to the interpolation pixel in this case. The control unit 110 performs setting and control of the horizontal filter 130 and the addition / shift processing unit 160 so that the process represented by Expression (25) is performed on the eight reference pixels. The process for obtaining the interpolated pixels b ₋₁ and b _{1 is the same as} that for H.P. Since this is the same as the process for obtaining the interpolation pixel at the position (1/2, 0) in the case of H.264, detailed description thereof is omitted here.

(2) Interpolation pixel at position (0, 1/2) among interpolation pixels of 1/2 precision The interpolation pixel c in FIG. 20 corresponds to the interpolation pixel in this case. The control unit 110 performs setting and control of the vertical filter 150 and the addition / shift processing unit 160 so that the process represented by Expression (26) is performed on the eight reference pixels. The process for obtaining the interpolated pixel c is the same as that for the H.P. Since this is the same as the process for obtaining the interpolation pixel at the (0, 1/2) position in the case of H.264, detailed description thereof is omitted here.

(3) Interpolation Pixel at (1/2, 1/2) Position Among Interpolation Pixels of 1/2 Precision The interpolation pixel d in FIG. 20 corresponds to the interpolation pixel in this case. In this case, first, the control unit 110 causes the horizontal filter 130 and the addition / shift processing unit 160 to obtain interpolation pixels at eight (1/2, 0) positions for obtaining the interpolation pixel d, and the addition / shift processing. The eight interpolation pixels output from the unit 160 are held. Then, the held eight interpolation pixels are output to the vertical filter 150, and the vertical filter 150 and the addition / shift processing unit 160 are set so that the processing represented by Expression (27) is performed. Further, the addition / shift processing unit 160 is controlled so that the output destination of the addition / shift processing unit 160 is external.
That is, in the MPEG4 qmc mode, all the half-precision interpolation pixels are output from the addition / shift processing unit 160 to the outside.

2. In the case of an interpolation pixel (luminance) with a precision of ¼ (1) (1/4, 0) position and (3/4, 0) position interpolation pixel The interpolation pixels e and f in FIG. Corresponds to interpolation pixel. As shown in equations (28) and (29), the interpolation pixels e and f are obtained by averaging one reference pixel and one (1/2, 0) position interpolation pixel. Therefore, as described above, the control unit 110 first causes the horizontal filter 130 and the addition / shift processing unit 160 to obtain an interpolation pixel at the (1/2, 0) position, and outputs the output destination of the addition / shift processing unit 160. Is controlled to become the average processing unit 170. The interpolation pixel at the (1/2, 0) position is output from the addition / shift processing unit 160 to the average processing unit 170, and the one reference pixel is output to the average processing unit 170. Further, control is performed so that the output destination of the average processing unit 170 is external. As a result, the interpolation pixel at the (1/4, 0) position or the (3/4, 0) position is output from the average processing unit 170 to the outside.

(2) Interpolated Pixels at (1/4, 1/2) Position and (3/4, 1/2) Position Interpolated pixels k and l in FIG. 20 correspond to the interpolated pixels in this case.

  As shown in Equation (30), the interpolation pixel k at the (1/4, 1/2) position performs 8-tap vertical interpolation on the 8 (1/4, 0) interpolation pixels. It is obtained by adding and shifting the value obtained here (vertical interpolation value here). First, the control unit 110 performs setting and control so that interpolation pixels at the eight (1/4, 0) positions are obtained. In this case, the control unit 110 performs control so that the output destination of the average processing unit 170 is the control unit 110, and holds the output from the average processing unit 170.

  Then, the control unit 110 outputs the interpolation pixels at eight (1/4, 0) positions from the average processing unit 170 to the vertical filter 150, and the vertical filter 150 and the vertical filter 150 so that the processing represented by Expression (30) is performed. The addition / shift processing unit 160 is set. Also, control is performed so that the output destination of the addition / shift processing unit 160 is external.

  As shown in Expression (31), the interpolation pixel l at the (3/4, 1/2) position performs 8-tap vertical interpolation on the eight (3/4, 0) interpolation pixels. It is obtained by adding and shifting the vertical interpolation value obtained in this way. The process for obtaining the interpolated pixel l is (1/4, except that 8 (3/4, 0) position interpolated pixels are used instead of 8 (1/4, 0) position interpolated pixels. Since this is the same as the process for obtaining the interpolation pixel k at the 1/2) position, detailed description thereof is omitted here.

  As described above, in the qmc mode of MPEG4, the interpolation pixels at the (1/4, 1/2) position and the (3/4, 1/2) position among the interpolation pixels of 1/4 accuracy are added and The data is output from the shift processing unit 160 to the outside.

(3) Other ¼ precision interpolation pixels g, h, i, j, m, n, o, and p in FIG. 20 correspond to the interpolation pixels in this case. As shown in equations (32) to (39), each interpolation pixel described above is an average value of one reference pixel and one half-precision interpolation pixel (equations (32), (36)), or 2 The average value of two ½ precision interpolation pixels (Equations (34), (35), (38)), or the average value of two ¼ accuracy interpolation pixels (Equations (33), (37), ( 39)). Each interpolation pixel in this case is output from the average processing unit 170 to the outside.

<For MPEG4 hmc mode and MPEG2>
1. Interpolated pixels at positions (1/2, 0) and (0, 1/2) Interpolated pixels b, c, and e in FIG. 21 correspond to the interpolated pixels in this case. As shown in equations (40) and (41), these interpolated pixels are obtained from the average value of the two reference pixels. Therefore, the control unit 110 reads out the two reference pixels necessary for obtaining the interpolation pixel from the memory 84 and outputs them to the average processing unit 170, and controls the output destination of the average processing unit 170 to be external. That is, in this case, the interpolation pixels at the positions (1/2, 0) and (0, 1/2) are output from the average processing unit 170 to the outside.

2. Interpolated Pixel at (1/2, 1/2) Position Pixel d in FIG. 21 corresponds to the interpolated pixel in this case. As shown in the equation (42), this interpolation pixel is an average value of four reference pixels of upper, lower, left, and right, and is usually obtained by a cubic filter.

  In the present embodiment, the interpolation pixel d is obtained by the same method as in the case of VC-1 Bilinear. The processing for obtaining the interpolated pixel d is performed except that “xFrc” and “yFrc” in FIGS. 5 and 6 and equations (43) to (45) are fixed to “0.5” and the parameter “rnd” is different. In the case of VC-1 Bilinear, the process is the same as the process for obtaining the interpolated pixel e, and a detailed description thereof will be omitted here. In the case of MPEG2, since there is no parameter “rnd”, “rnd” is set to “0” for the addition / shift processing unit 160.

  That is, in the MPEG4 hmc mode and MPEG2, the interpolation pixel at the (1/2, 1/2) position is output from the addition / shift processing unit 160.

<In the case of interpolated pixels for color difference>
The interpolated pixels of the color difference are obtained by the same method as in the case of VC-1 Bilinear.

  The motion compensation engine 100 in the moving picture decoding apparatus 80 according to the present embodiment includes a control unit 110, a horizontal filtering processing unit 120 including a horizontal filter 130, a vertical filtering processing unit 140 including a vertical filter 150, an addition / A shift processing unit 160 and an average processing unit 170 are included. The output destinations of the horizontal filtering processing unit 120 and the vertical filtering processing unit 140 can be switched between the control unit 110 and the addition / shift processing unit 160. The output destination of the addition / shift processing unit 160 can be switched among the control unit 110, the average processing unit 170, and the outside. The output destination of the average processing unit 170 can be switched between the outside and the control unit 110. The control unit 110 sets parameters of each processing unit, controls the output destination of each processing unit, and outputs the processing unit output from one of the processing units to the control unit 110 according to the compression standard of the moving image and the target position. The interpolated pixel at the target position is obtained by holding the processing result of this step, outputting the reference pixel and / or the value being held to any of the processes.

  When two-dimensional interpolation is required for four pixels that are adjacent vertically and horizontally in order to obtain an interpolation pixel at the target position, the control unit 110 converts the four pixels horizontally into two pixels arranged horizontally. Then, the two horizontal interpolation values obtained by the horizontal filter 130 are output to the vertical filter 150. Alternatively, four pixels are output to the vertical filter 150 by two pixels arranged vertically, and then the two vertical interpolation values obtained by the vertical filter 150 are output to the horizontal filter 130.

  As described above, the motion compensation engine 100 according to the present embodiment can cope with a plurality of compression standards and can realize the function of a cubic filter by two filters. Therefore, the circuit scale of the motion compensation device can be reduced.

  In the motion compensation device shown in FIG. 22, the interpolation processing is fixed in the order of the vertical filter and the horizontal filter. However, in the ASP (Advanced Simple Profile) of MPEG4, interpolation processing is determined in the order of the horizontal filter and the vertical filter at the time of 1/4 precision motion compensation. Therefore, the motion compensation apparatus shown in FIG. 22 cannot cope with motion compensation with 1/4 accuracy of MPEG4.

  On the other hand, according to the motion compensation engine 100 in the present embodiment, the processing order of the horizontal filter and the vertical filter can be arbitrarily adjusted by the control unit 110, and the motion compensation with 1/4 accuracy of MPEG4 can be supported. .

<Second Embodiment>
FIG. 7 shows a motion compensation engine 200 according to the second embodiment of the present invention. The motion compensation engine 200 can be provided in the video decoding device 80 shown in FIG. 1 instead of the motion compensation engine 100 shown in FIG.

  The motion compensation engine 200 includes a control unit 210, a horizontal filtering processing unit 120, a vertical filtering processing unit 140, an addition / shift processing unit 260, and an average processing unit 270.

  The horizontal filtering processing unit 120 and the vertical filtering processing unit 140 are the same as the horizontal filtering processing unit 120 and the vertical filtering processing unit 140 in the motion compensation engine 100, and detailed description thereof is omitted here.

  The addition / shift processing unit 260 implements the same function as the addition / shift processing unit 160 in the motion compensation engine 100, but is divided into a horizontal addition / shift processing unit 262 and a vertical addition / shift processing unit 264. Yes. The average processing unit 270 implements the same function as the average processing unit 170 in the motion compensation engine 100, but is divided into a horizontal average processing unit 272 and a vertical average processing unit 274.

  The horizontal addition / shift processing unit 262 receives the horizontal interpolation value from the horizontal filtering processing unit 120 and performs addition / shift processing on the horizontal interpolation value. The parameter of the addition / shift processing is variable, and the output destination of the addition / shift value of the processing result can be switched between the control unit 210 and the horizontal average processing unit 272. In the horizontal addition / shift processing unit 262, parameters are set by the control unit 210, and an output destination is controlled by the control unit 210.

  The horizontal addition / shift processing unit 262 receives the horizontal interpolation value from the horizontal filtering processing unit 120 and performs addition / shift processing on the horizontal interpolation value. The parameter of the addition / shift processing is variable, and the output destination of the addition / shift value of the processing result can be switched between the outside, the control unit 210, and the horizontal average processing unit 272. In the horizontal addition / shift processing unit 262, parameters are set by the control unit 210, and an output destination is controlled by the control unit 210.

  The vertical addition / shift processing unit 264 receives the vertical interpolation value from the vertical filtering processing unit 140 and performs addition / shift processing on the vertical interpolation value. The parameter of the addition / shift process is variable, and the output destination of the addition / shift value of the process result can be switched between the outside, the control unit 210, and the vertical average processing unit 274. The parameters of the vertical addition / shift processing unit 264 are also set by the control unit 210 and the output destination is controlled by the control unit 210.

  The horizontal average processing unit 272 receives two values and calculates an average value of the two values. These two values are input from either one or both of the control unit 210 and the horizontal addition / shift processing unit 262. The horizontal average processing unit 272 can switch the output destination between the outside and the control unit 210. The output destination of the horizontal average processing unit 272 is controlled by the control unit 210.

  The vertical average processing unit 274 receives two values and calculates an average value of the two values. These two values are input from one or both of the control unit 210 and the vertical addition / shift processing unit 264. The vertical average processing unit 274 can also switch the output destination between the outside and the control unit 210. The output destination of the vertical average processing unit 274 is controlled by the control unit 210.

  When determining the interpolation pixel, the control unit 210 performs the setting and control performed by the control unit 110 on the addition / shift processing unit 160 with respect to the horizontal addition / shift processing unit 262 and the vertical addition / shift processing unit 264 as appropriate. The setting and control performed by the control unit 110 for the average processing unit 170 are appropriately performed for the horizontal average processing unit 272 and the vertical average processing unit 274. Except for these points, the operation similar to that of the control unit 110 in the motion compensation engine 100 is performed, and thus detailed description thereof is omitted here.

  The motion compensation engine 200 according to the present embodiment can obtain the same effects as those of the motion compensation engine 100 shown in FIG. Further, the addition / shift processing unit 260 is divided into a horizontal addition / shift processing unit 262 and a vertical addition / shift processing unit 264, and the average processing unit 270 is divided into a horizontal average processing unit 272 and a vertical average processing unit 274, thereby controlling the control unit. The control by 210 can be simplified.

  Of course, the motion compensation engine 200 is provided with the addition / shift processing unit 160 in the motion compensation engine 100 instead of the addition / shift processing unit 260, or the average processing in the motion compensation engine 100 instead of the average processing unit 270. A portion 170 may be provided.

<Third Embodiment>
FIG. 8 shows a motion compensation engine 300 according to the third embodiment of the present invention. The motion compensation engine 300 can be provided in the video decoding device 80 shown in FIG. 1 instead of the motion compensation engine 100 shown in FIG. In the motion compensation engine 300, the vertical filtering processing unit includes a plurality of vertical filters operable in parallel.

  As shown in FIG. 8, the motion compensation engine 300 includes a control unit 310, a horizontal filtering processing unit 320, a vertical filtering processing unit 340, a horizontal addition / shift processing unit 360, four vertical addition / shift processing units 372 to 378, horizontal An average processing unit 380 and a vertical average processing unit 390 are provided. The horizontal filtering processing unit 320 includes a horizontal filter 330, the vertical filtering processing unit 340 includes four vertical filters 342 to 348, and the four vertical filters 342 to 348 include four vertical addition / shift processing units. 372 to 378, respectively.

  The horizontal filter 330, horizontal addition / shift processing unit 360, and horizontal average processing unit 380 operate in the same manner as the horizontal filter 130, horizontal addition / shift processing unit 262, and horizontal average processing unit 272 of the motion compensation engine 200 shown in FIG. To do. The vertical addition / shift processing units 372 to 378 operate in the same manner as the vertical filter 150 of the motion compensation engine 200. The vertical average processing unit 390 is connected to the vertical addition / shift processing unit 378, the vertical addition / shift processing unit 376, and the control unit 310, and values are input from any two of these functional blocks. .

  The control unit 310 includes a horizontal register group 312 and a vertical register group 314. The horizontal register group 312 has eight registers respectively corresponding to the eight registers of the horizontal filter 330 and storing values set in the eight registers. The vertical register group 314 corresponds to the registers of the four vertical filters included in the vertical filtering processing unit 340 (32 in total), and has 32 registers that respectively store the values set in the 32 registers.

  When the target position is an integer position, the control unit 310 reads the reference pixel at the target position from the memory 84 and outputs it to the outside. When the target position is not an integer position, various settings and controls are performed for obtaining an interpolation pixel. As an example, the case of several compression standards and target positions will be described. In the drawings to be referred to in the description, functional blocks indicated by solid line frames are functional blocks, and functional blocks not operated by dotted line frames are illustrated. For easy understanding, the input lines to the function blocks that do not operate and the output lines from the function blocks are not shown.

  FIG. 6 is a diagram for explaining processing for obtaining an interpolation pixel at a position of (1/4, 1/2) by the motion compensation engine 300 for luminance in the case of H.264. Since the interpolation pixel i in FIG. 16 corresponds to the interpolation pixel in this case, the interpolation pixel i is taken as an example.

  The control unit 310 reads the reference pixels E, F, G, H, I, and J from the memory 84 via the DMA controller 86, and the horizontal filter 330 via six of the eight registers of the horizontal register group 312. Are set in six of the eight registers respectively. In addition, the parameters of the horizontal filter 330 are set so that the processing represented by Expression (1) is performed, and the output destination of the horizontal filter 330 is controlled to be the control unit 310.

  The control unit 310 temporarily holds the horizontal interpolation value b ′ obtained by the horizontal filter 330 in one of eight registers corresponding to the vertical filter 346 in the vertical register group 314. The control unit 310 causes the horizontal filtering processing unit 320 to determine and hold aa, bb, s ′, gg, and hh in the same process as when determining b ′.

  When the control unit 310 obtains aa, bb, b ′, s ′, gg, and hh, the control unit 310 sets the six horizontal interpolation values in six of the eight registers of the vertical filter 346, respectively. To do. In addition, the parameters of the vertical filter 346 are set so that the processing represented by Expression (6) is performed, and control is performed so that the output destination of the vertical filter 346 becomes the vertical addition / shift processing unit 376.

  In parallel, the control unit 310 reads the six reference pixels A, C, G, M, R, and T from the memory 84 and sets them in six in the eight registers of the vertical filter 348, respectively. Further, the parameters of the vertical filter 348 are set so that the processing represented by the expression (3) is performed, and control is performed so that the output destination of the vertical filter 348 becomes the vertical addition / shift processing unit 378.

  In addition, the control unit 310 sets the addition / shift processing parameters shown in Expression (7) for the vertical addition / shift processing unit 376, and the addition shown by Expression (4) for the vertical addition / shift processing unit 378. Set the parameters of the shift processing so that the output destination of the vertical addition / shift processing unit 376 and the vertical addition / shift processing unit 378 is the vertical average processing unit 390 and the output destination of the vertical average processing unit 390 is external Control.

  The vertical addition / shift processing unit 376 performs addition / shift processing shown in Expression (7) on the vertical interpolation value (j ′) output from the vertical filter 346, obtains an interpolation pixel j, and outputs it to the vertical average processing unit 390. The vertical addition / shift processing unit 378 adds and shifts the vertical interpolation value (h ′) output from the vertical filter 348 as shown in Expression (4), obtains an interpolation pixel h, and outputs it to the vertical average processing unit 390.

  The vertical average processing unit 390 averages the interpolation pixel j and the interpolation pixel h to obtain an average value that becomes the interpolation pixel i and outputs the average value to the outside, as shown in Expression (13).

  FIG. 10 is a diagram for explaining processing for obtaining an interpolation pixel at a position (3/4, 3/4) with respect to luminance in the case of VC-1 Bicubic. Since the interpolation pixel r in FIG. 17 corresponds to the interpolation pixel in this case, the interpolation pixel r is taken as an example.

  The control unit 310 stores reference pixels “A, E, I, M”, “B, F, J, N”, “C, G, K, O”, “D, H, L, P” from the memory 84. This is read out and set in the registers of the vertical filters 342 to 348, respectively. In addition, the parameters of the vertical filters 342 to 348 and the vertical addition / shift processing units 372 to 378 are set so that the processing shown in Expression (22) is performed, and the output destination of each vertical filter corresponds to the vertical filter. The vertical addition / shift processing unit controls the output destination of each addition / shift processing unit to be the control unit 310.

The control unit 310 sets the interpolation pixels nn, n, s, and ss output from the vertical addition / shift processing unit 372 in four of the eight registers of the horizontal filter 330 via the horizontal register group 312. Further, the parameters of the horizontal filter 330 and the horizontal addition / shift processing unit 360 are set so that the processing represented by the expression (22) is performed, and the output destination of the horizontal filter 330 becomes the horizontal addition / shift processing unit 360, Control is performed so that the output destination of the addition / shift processing unit 360 is external.
Thus, the interpolation pixel r is output from the horizontal addition / shift processing unit 360 to the outside.

  FIG. 11 is a diagram for explaining processing for obtaining an interpolation pixel at a (1/4, 3/4) position with respect to luminance in the qmc mode of MPEG4. Since the interpolation pixel n in FIG. 20 corresponds to the interpolation pixel in this case, the interpolation pixel n is taken as an example.

Control unit 310, eight reference pixels from the memory _{84 A -4, -1, A -3} , -1, A -2, -1, A -1, -1, A 1, -1, A 2, - ₁ , A _{3, −1} , A _{4, −1} are read out and set in the eight registers of the horizontal filter 330, respectively. Further, the parameters of the horizontal filter 330 and the horizontal addition / shift processing unit 360 are set so that the processing represented by the equation (25) is performed, and the output destination of the horizontal filter 330 becomes the horizontal addition / shift processing unit 360, Control is performed so that the output destination of the addition / shift processing unit 360 is the horizontal average processing unit 380 and the output destination of the horizontal average processing unit 380 is the control unit 310. As a result, an addition / shift value corresponding to the interpolation pixel b ₋₁ is obtained from the horizontal addition / shift processing unit 360 and is output to the horizontal average processing unit 380.

In parallel, the control unit 310 outputs the reference pixel A _{1, −1} to the horizontal average processing unit 380. As a result, an average value of b ₋₁ and A _{1, −1} is obtained from the horizontal average processing unit 380 and output to the control unit 310. This average value is the interpolated pixel e _{−1 as} shown in Equation (28).

The control unit 310 performs processing similar to that for _obtaining e ₋₁ , e ₋₄ , e ₋₃ , e ₋₂ , e ₁ , e ₂ , e ₃ , e ₄ to the horizontal filter 330, horizontal addition / shift processing 360 and the horizontal average processing unit 380, and temporarily hold them in the vertical register group 314.

When e ₋₄ , e ₋₃ , e ₋₂ , e ₋₁ , e ₁ , e ₂ , e ₃ , and e ₄ are obtained, the control unit 310 sets the eight interpolation pixels in the vertical filter 348. Further, the parameters of the vertical filter 348 and the vertical addition / shift processing unit 378 are set so that the processing represented by the expression (30) is performed, and the output destination of the vertical filter 348 becomes the vertical addition / shift processing unit 378, so Control is performed so that the output destination of the addition / shift processing unit 378 is the vertical average processing unit 390 and the output destination of the vertical average processing unit 390 is external.

The addition / shift value to be the interpolation pixel k is output from the vertical addition / shift processing unit 378 to the vertical average processing unit 390. In parallel, the control unit 310 outputs the interpolation pixel e ₁ to the vertical average processing unit 390. As a result, an average value of k and e ₁ is obtained from the vertical average processing unit 390 and output to the outside. This average value is the interpolated pixel n as shown in Expression (37).

  FIG. 12 is a diagram for explaining processing for obtaining an interpolated pixel for luminance in the case of VC-1 Bilinear. In this case, as shown in FIG. 19 and Expression (23), each interpolation pixel is obtained by performing two-dimensional linear interpolation on four reference pixels on the top, bottom, left, and right surrounding the interpolation pixel.

  In the present embodiment, the processing shown in FIG. 19 and equation (23) is performed as shown in FIG. 5 and equations (43) to (45). Specifically, as shown in FIG. 12, the control unit 310 first reads the reference pixels A and B from the memory 84 and obtains two of the eight registers of the horizontal filter 330 in order to obtain the interpolation pixel e. Set to. In addition, parameters “xFrc” and “8-xFrc” are set for the horizontal filter 330 so that the processing indicated by Expression (43) is performed, and the output destination of the horizontal filter 330 is the control unit 310. Control.

  The output of the horizontal filter 330 is a pixel F. The control unit 310 holds the pixel F in one register of the vertical register group 314 and sets the reference pixels C and D in the horizontal filter 330 to obtain the pixel G.

  When the pixel G is obtained by the horizontal filter 330, the control unit 310 sets the pixels F and G in two of the eight registers of the vertical filter 348. Further, the parameters “yFrc” and “8-yFrc” of the vertical filter 348 and the parameter “rnd” of the vertical addition / shift processing unit 378 are set so that the processing represented by the equation (45) is performed. Control is performed so that the output destination is the vertical addition / shift processing unit 378 and the output destination of the vertical addition / shift processing unit 378 is external.

  Thus, the vertical addition / shift processing unit 378 outputs the addition / shift value to be the interpolation pixel e to the outside.

  FIG. 13 is a diagram for explaining a process for obtaining an interpolation pixel at the (1/2, 0) position with respect to luminance in the MPEG4 hmc mode or MPEG2. Since the interpolation pixel b in FIG. 21 corresponds to the interpolation pixel in this case, the interpolation pixel b is taken as an example.

  As illustrated in FIG. 13, the control unit 310 reads the reference pixels A and B from the memory 84 and outputs the reference pixels A and B to the horizontal average processing unit 380 so that the output destination of the horizontal average processing unit 380 is external. As a result, the average value of the reference pixels A and B is output from the horizontal average processing unit 380 to the outside. This average value is the interpolation pixel b.

  In the case of the MPEG4 hmc mode or MPEG2, the two-dimensional linear interpolation represented by the equation (42) is performed when obtaining the interpolation pixel at the (1/2, 1/2) position (interpolation pixel d in FIG. 21) for luminance. is necessary. This is performed by a method similar to the two-dimensional linear interpolation at the time of VC-1 Bilinear shown in FIG.

  For color difference, see H.C. In any of the H.264, VC-1, MPEG4, and MPEG2 standards, an interpolation pixel is obtained by two-dimensional linear interpolation. Also in this case, an interpolation pixel may be obtained by a method similar to the two-dimensional linear interpolation at the time of VC-1 Bilinear shown in FIG.

  The motion compensation engine 300 according to the third embodiment can provide the same effects as those of the motion compensation engine 100 and the motion compensation engine 200 described above, and is provided with a plurality of vertical filters operable in parallel. As a result, the processing speed can be increased.

<Fourth embodiment>
A plurality of vertical filters and a plurality of horizontal filters may be provided in the motion compensation engine. FIG. 14 shows a motion compensation engine 400 with four horizontal filters that can operate in parallel and eight vertical filters that can operate in parallel.

  The motion compensation engine 400 includes a control unit 410, a horizontal filtering processing unit 420, a vertical filtering processing unit 440, an addition / shift processing unit 460, a horizontal average processing unit 472, and a vertical average processing unit 474.

  The horizontal filtering processing unit 420 includes four horizontal filters, and the four horizontal filters have the same configuration as the horizontal filter of the motion compensation engine in each of the above-described embodiments.

  The vertical filtering processing unit 440 includes eight vertical filters, and the eight vertical filters have the same configuration as the vertical filter of the motion compensation engine in each of the above-described embodiments.

  The addition / shift processing unit 460 includes four horizontal addition / shift processing units corresponding to the horizontal filters of the horizontal filtering processing unit 420 and eight vertical addition / shifts corresponding to the vertical filters of the vertical filtering processing unit 440, respectively. It has a processing part.

  The horizontal average processing unit 472 and the vertical average processing unit 474 constitute an average processing unit 472.

  The output destination of each horizontal filter in the horizontal filtering processing unit 420 can be switched between the corresponding horizontal addition / shift processing unit and the control unit 410. The output destination of each vertical filter in the vertical filtering processing unit 440 can be switched between the corresponding vertical addition / shift processing unit and the control unit 410.

  The output destination of each horizontal addition / shift processing unit of the addition / shift processing unit 460 can be switched among the horizontal average processing unit 472, the control unit 410, and the outside. The output destination of each vertical addition / shift processing unit of the addition / shift processing unit 460 can be switched among the vertical average processing unit 474, the control unit 410, and the outside.

  The output destinations of the horizontal average processing unit 472 and the vertical average processing unit 474 can be switched between the control unit 410 and the outside.

  When the target position is an integer position, the control unit 410 reads the reference pixel at the integer position and outputs it to the outside. On the other hand, when the target position is not an integer position, according to the compression standard and the target position indicated by the codec signal, the parameter setting of each processing unit, the control of the output destination of each processing unit, the processing result of the processing unit When the output destination is the control unit 410, interpolation of the target position is obtained by holding the processing result and setting and controlling the value output to each processing unit.

  The motion compensation engine 400 of the present embodiment can obtain the effects of the motion compensation engines described above, and can perform higher-speed processing because there are a large number of horizontal filters and vertical filters operable in parallel.

  The present invention has been described above based on the embodiment. The embodiment is an exemplification, and various modifications and changes may be made to the above-described embodiment without departing from the gist of the present invention. It will be understood by those skilled in the art that modifications in which these changes and increases / decreases are also within the scope of the present invention.

  For example, in each embodiment described above, the parameters of each processing unit are set by the control unit. A functional block for switching parameters according to the compression standard and the target position may be provided inside these processing units. In this case, these functional blocks become part of the control unit in each of the above-described embodiments.

  Moreover, in each embodiment mentioned above, the output destination of each process part is controlled by the control part. A selector for switching the output destination according to the compression standard and the target position may be provided inside these processing units. In this case, these selectors become part of the control unit in each of the above-described embodiments.

30 DMA I / F
40 Motion Compensation Engine 41 Vertical Filter 42 First Horizontal Filter 43 Second Horizontal Filter 44 Cubic Alignment Unit 45 Cubic Filter 80 Video Decoding Device 82 System Bus 84 Memory 86 DMA Controller 88 Entropy Decoding Unit 90 DMA IF
100 Motion Compensation Engine 110 Control Unit 120 Horizontal Filtering Processing Unit 130 Horizontal Filter 140 Vertical Filtering Processing Unit 150 Vertical Filter 160 Addition / Shift Processing Unit 170 Average Processing Unit 200 Motion Compensation Engine 210 Control Unit 260 Addition / Shift Processing Unit 262 Horizontal Addition / Shift Processing Unit 262 Shift processing unit 264 Vertical addition / shift processing unit 270 Average processing unit 272 Horizontal average processing unit 274 Vertical average processing unit 300 Motion compensation engine 310 Control unit 312 Horizontal register group 314 Vertical register group 320 Horizontal filtering processing unit 330 Horizontal filter 340 Vertical filtering Processing unit 342-348 Vertical filter 360 Horizontal addition / shift processing unit 372-378 Vertical addition / shift processing unit 380 Horizontal average processing unit 390 Vertical average processing unit 400 Can compensation engine 410 control unit 420
Horizontal filtering processing unit 440 Vertical filtering processing unit 460 Addition / shift processing unit 472 Horizontal average processing unit 474 Vertical average processing unit

Claims (5)

In the motion compensation device corresponding to a plurality of compression standards, performing motion compensation at the time of decoding a compressed moving image, and obtaining a pixel value of a pixel at a target position which is a position indicated by a motion vector,
A control unit;
Two or more values are input from the control unit, a horizontal filter that obtains a horizontal interpolation value by performing interpolation on the two or more values, the number of the two or more values to be input; A horizontal filtering processing unit having the horizontal filter with variable interpolation parameters;
Two or more values are input from the control unit, and a vertical filter that obtains a vertical interpolation value by performing interpolation on the two or more values, the number of the two or more values to be input; A vertical filtering processing unit having the vertical filter with variable interpolation parameters;
Addition / shift processing in which the horizontal interpolation value is input from the horizontal filtering processing unit or the vertical interpolation value is input from the vertical filtering processing unit, a predetermined value is added to the horizontal interpolation value or the vertical interpolation value, and then a predetermined number of bits are shifted. An addition / shift processing unit that obtains an addition / shift value by performing the addition / shift processing unit in which a parameter consisting of the predetermined value and a predetermined number of bits is variable;
An average processing unit that receives two values and calculates an average value of the two values, wherein the two values are input from either one or both of the control unit and the addition / shift processing unit An average processing unit,
The horizontal filtering processing unit can output the horizontal interpolation value to the control unit and the addition / shift processing unit,
The vertical filtering processing unit can output the vertical interpolation value to the control unit and the addition / shift processing unit,
The addition / shift processing unit can output the addition / shift value to the outside as a pixel value of a pixel at the target position, and can output the addition / shift value to the control unit and the average processing unit. ,
The average processing unit can output the average value to the outside as a pixel value of a pixel at the target position, and can output to the control unit.
The controller is
When the target position is other than an integer position as a reference pixel position, according to the compression standard of the moving image and the target position,
Setting the parameters of the horizontal filter, the vertical filter, and the addition / shift processing unit;
Control of the output destination of the processing result by each processing unit;
Holding the processing result when the output destination of the processing result is the control unit;
A pixel value of one or more reference pixels, one or more retained horizontal interpolation values, one or more retained vertical interpolation values, and one or more retained addition / shift values. One or more values of the held one or more average values are output to any of the horizontal filter, the vertical filter, and the average processing unit,
In the process of obtaining a cubic interpolation value by performing two-dimensional linear interpolation on the four values,
Two of the four values are output to one of the horizontal filter and the vertical filter, and then two horizontal interpolation values or two vertical interpolation values obtained by the one filter are output to the other filter. A motion compensation device characterized by the above. The addition / shift processing unit
The horizontal interpolation value is input from the horizontal filtering processing unit, and after adding a predetermined value to the horizontal interpolation value, a horizontal addition / shift processing unit that performs addition / shift processing for shifting a predetermined number of bits;
And a vertical addition / shift processing unit that performs addition / shift processing for shifting the predetermined number of bits after the vertical interpolation value is input from the vertical filtering processing unit and the predetermined value is added to the vertical interpolation value. The motion compensation apparatus according to claim 1. The average processing unit is
A horizontal average processing unit that receives two values and calculates an average value of the two values, and the two values are input from one or both of the control unit and the horizontal addition / shift processing unit. The horizontal average processing unit,
A vertical average processing unit that receives two values and calculates an average value of the two values, and the two values are input from one or both of the control unit and the vertical addition / shift processing unit. The motion compensation apparatus according to claim 2, further comprising: the vertical average processing unit. The vertical filtering processing unit includes a plurality of the vertical filters operable in parallel,
The motion compensation apparatus according to claim 3, wherein the addition / shift processing unit includes a plurality of the vertical addition / shift processing units respectively corresponding to the plurality of vertical filters. The horizontal filtering processing unit includes a plurality of the horizontal filters operable in parallel,
The motion compensation apparatus according to claim 4, wherein the addition / shift processing unit includes a plurality of horizontal addition / shift processing units respectively corresponding to the plurality of horizontal filters.

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