JP2005348176A - Image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a huge line memory for vertical filter processing in an image processor and to reduce power consumption for filter processing. <P>SOLUTION: The image processor is constituted so that it comprises a post filter 2 having a vertical filter part which outputs information about at least a part of pixel groups including a pixel group in the vicinity of a vertical boundary between a decoding object pixel block and a vertical pixel block among pixel groups consisting at least a part of the decoding object pixel block, the decoding object pixel block adjacent in the perpendicular direction and the vertical pixel block as distortion correction pixel information and an information for display storage part 3 which holds the distortion correction pixel information outputted from the post filter, pieces of encoding information about a decoding object image frame consisting of a plurality of pixel blocks are sequentially inputted in a decoding part 1 by unit of pixel block as the encoding information about the decoding object pixel block and image frame information for display constituted of pieces of distortion correction pixel information outputted for each of the plurality of pixel blocks are held in the information for display recording part 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image decoding technique in an image decoding apparatus, and more specifically, a display image filtering process performed after decoding compressed code data of an image encoding method that performs orthogonal transform and quantization processing in units of predetermined pixel blocks. It is about technology.

  The standardization of terrestrial digital television broadcasting using an image compression method such as MPEG (Moving Picture Experts Group) is underway, and an inexpensive and low power consumption MPEG decoding device is required.

  In a conventional MPEG decoding apparatus, when image information is output to a display device in order to remove prediction accuracy of predictive encoding, distortion and visual noise generated in the process of orthogonal transform and quantization / inverse quantization. Two-dimensional inter-block distortion removal filter processing and mosquito noise filter processing have been performed (for example, see Non-Patent Document 1). As the vertical filter in the two-dimensional processing, as many line memories as the number of vertical filter taps are used and are built in the MPEG decoding semiconductor device.

  An MPEG decoding apparatus including a conventional post filter will be described. A conventional typical MPEG decoding apparatus shown in FIG. 15 includes an input buffer 111, an inverse variable length encoding unit (iVLD) 112, an inverse quantization unit 113, an inverse discrete cosine transform unit (iDCT) 114, A motion compensation prediction unit 115, an adder 116, a frame memory 105, a post filter 102, and an image output processing unit 104. In this MPEG decoding apparatus, the encoding information (code signal) of the decoding target pixel block is input to the input buffer 111 for each pixel block for a plurality of pixel blocks obtained by dividing an image frame into a plurality of pixels. The encoded signal includes encoded difference image information, prediction mode information, motion vector information, and quantization granularity (quantization step) information in order to reproduce the decoding information of the decoding target pixel block. Yes.

  The encoded differential image information and the quantization granularity information included in the encoded information input to the input buffer 111 are output to the inverse variable length encoding unit 112, and the prediction mode information and the motion vector information included in the encoded information are And output to the motion compensation prediction unit 115. The inverse variable length encoding unit 112 performs inverse variable length encoding on the encoded information from the input buffer 111. The encoded variable image information and the quantization granularity information subjected to inverse variable length encoding are output to the inverse quantization unit 113. The inverse quantization unit 113 refers to the quantization granularity information from the inverse variable length encoding unit 112, and inversely quantizes the encoded differential image information that has been inverse variable length encoded by the inverse variable length encoding unit 112. . The inversely quantized encoded difference image information is output to the inverse discrete cosine transform unit 114. The inverse discrete cosine transform unit 114 performs inverse discrete cosine transform on the inversely quantized encoded difference image information, and generates decoded difference image information for the decoding target pixel block from the inversely quantized encoded difference image information. The decoded difference image information is output to the adder 116. The motion compensation prediction unit 115 calculates a reference pixel address with reference to the motion compensation mode information and motion vector information, and a reference image that has already been processed and held in the frame memory 105 based on the calculated reference pixel address. Predictive image information is extracted from the frame information. The predicted image information is output to the adder 116. The adder 116 generates decoding information of the decoding target pixel block based on the difference image information from the inverse discrete cosine transform unit 114 and the prediction image information from the motion compensation prediction unit 115. The decoding information is output to the frame memory 105. The frame memory 105 additionally holds the decoding information from the adder 116.

  By repeating the above processing for all pixel blocks constituting the decoding target image frame for each pixel block, the frame memory 105 finally holds frame image information relating to the entire decoding target image frame. It will be.

  In the frame memory 105, as shown in the left diagram of FIG. 16, a plurality of image frames necessary for performing motion compensation prediction are held in units of frames. Further, as shown in the right diagram of FIG. 16, each image frame is divided and held in units of pixel blocks (sections shown in the right diagram of FIG. 16). Image frame information held in the frame memory 105 is sequentially read out at a predetermined display frame rate and output to the post filter 102. The post filter 102 corrects the inter-pixel block distortion in the read image frame, and outputs the corrected image frame information to the image output processing unit 104. The corrected image frame information is converted into a predetermined TV signal system by the image output processing unit 104 and output as an output signal.

  Here, a conventional typical post filter will be described in detail. As shown in FIG. 17, the image information read from the frame memory 105 is inspected for the presence or absence of inter-pixel block distortion at the pixel block boundary by the distortion detection unit 123 in the post filter 102, and the inspection result is obtained. Accordingly, the horizontal filter coefficient of the horizontal filter 125 is adjusted to correct inter-pixel block distortion. This visually reduces image distortion.

  Specifically, the distortion detection unit 123 has the configuration shown in FIG. In the two horizontally adjacent pixel blocks, the distortion detection unit 123 calculates the absolute value of the difference between pixels adjacent to the left and right across the pixel block boundary, and the difference absolute value of the adjacent pixels near the boundary in one pixel block. It is detected that there is a visual distortion between the pixel blocks when the average value is larger than the average value of the absolute difference values for adjacent pixels in the vicinity of the boundary in the other pixel block and larger than a predetermined threshold value.

  Here, the operation of the distortion detection unit will be specifically described with reference to FIGS. As shown in FIG. 21, the pixel values of pixels on the same line in the left pixel block and the right pixel block adjacent in the horizontal direction are P00 to P07 and P10 to P17. P00 to P07 and P10 to P17 input from Data In are sequentially held in two-stage shift registers 148a and 148b. The subtractor 141 calculates a difference in pixel value between horizontally adjacent pixels, and the absolute value circuit (ABS) 142 converts the difference into an absolute value. Specifically, from the absolute value conversion circuit 142, the absolute difference values | P01-P02 |, | P02-P03 |,..., | P07-P10 |,. Is output.

  The absolute difference value, which is the output of the absolute value circuit 142, is sequentially held in five stages of shift registers 148g, 148f, 148e, 148d and 148c. For example, five-stage shift registers 148g, 148f, 148e, 148d, and 148c have | P01-P02 |, | P02-P03 |, | P03-P04 |, | P04-P05 |, and | P05-P06 | Is retained. Through the adder 149a and the divider 146a, an average of absolute difference values for horizontally adjacent pixels is obtained. Similarly, the average of absolute difference values for horizontally adjacent pixels is obtained via the adder 149b and the divider 146b. The shift registers 148h, 148i, and 148j hold the same absolute difference values as the shift registers 148c, 148d, and 148e, respectively.

  The pixel values of the pixels arranged in the horizontal direction are sequentially input, and the difference absolute values held in the shift registers 148g, 148f, 148e, 148d, and 148c are | P05-P06 |, | P06-P07 | When | P07-P10 |, | P10-P11 |, and | P11-P12 |, the output from the divider 146a is (| P10-P11 | + | P11-P12 |) / 2, and from the divider 146b. The output of (| P05−P06 | + | P06−P07 |) / 2 is obtained. These are average values of absolute difference values for pixels near the boundary in each block, that is, values indicating the magnitude of change in each block. Also, the output from the shift register 148i at this time is the difference absolute value | P07−P10 | between two horizontally adjacent pixels across the boundary of the pixel block, and is a value indicating the size of the step between the pixel blocks. It is. The comparator 144 compares | P07-P10 | with the distortion detection threshold set in the threshold register 143. If | P07-P10 | is larger than the distortion detection threshold, a signal indicating a true value to the OR circuit 147. If | P07-P10 | is smaller than the distortion detection threshold value, a signal indicating a false value is output to the OR circuit 147. In the comparators 145a and 145b, (| P10-P11 | + | P11-P12 |) / 2 and (| P05-P06 | + | P06-P07 |) / 2 and | P07-P10 | If | P07-P10 | is large, a signal indicating a true value is output to the OR circuit 147, and if | P07-P10 | is smaller than the distortion detection threshold, a signal indicating a false value is output to the OR circuit 147. Output. In the OR circuit 147, if the signals from the comparators 144, 145a, and 145b are all signals indicating true values, a signal indicating true values is output as a distortion detection result output, and at least one of the signals indicates a false value. If so, a signal indicating a false value is output.

  As illustrated in FIG. 19, the horizontal filter 125 refers to the horizontal filter coefficient set selected by the filter coefficient determination unit 124 and performs horizontal filter processing for each horizontal image line on the decoded frame image. I do. Image information from the horizontal filter 125 is output to the vertical filter 126.

  The vertical filter 126 includes line memories 131b to 131e, multipliers 133a to 133e, an adder 134 for adding the outputs of the multipliers 133a to 133e, and a shifter 135. In the vertical filter 126, image information input for each horizontal image line is sequentially held in the line memories 131b to 131e for the number of taps of the vertical filter. Each of the line memories 131a to 131e needs to be large enough to store image information related to the number of horizontal pixels constituting the image frame. The line memories 131b to 131d other than the last stage are connected to the line memories 131c to 131e for the next horizontal image line and the vertical filter arithmetic circuit, while the last line memory 131e is connected to the vertical filter arithmetic circuit. It is connected. The image information subjected to the horizontal filter processing is accumulated by being delayed by one line in each of the line memories 131b to 131e. That is, if the output from the horizontal filter 125 is image information relating to the kth horizontal image line, pixel information relating to the (k−1) th horizontal image line is stored in the line memory 131b, and the line memory 131c is stored. , Image information related to the (k-2) th horizontal image line is stored, image information related to the (k-3) th horizontal image line is stored in the line memory 131d, and (k− 4) Image information relating to the horizontal image line is accumulated.

  The multiplier 133a multiplies the image information related to the kth horizontal image line by the coefficient held in the coefficient register 132a. Similarly, the multiplier 133b converts the image information related to the (k−1) th horizontal image line to the image information related to the (k−1) th horizontal image line. The filter coefficient held in the coefficient register 132b is multiplied. In the multiplier 133c, the image information related to the (k-2) th horizontal image line is multiplied by the coefficient held in the coefficient register 132c, and in the multiplier 133d ( The image information related to the (k-3) th horizontal image line is multiplied by the coefficient held in the coefficient register 132d. In the multiplier 133e, the image information related to the (k-4) th horizontal image line is held in the coefficient register 132e. Multiplied by the filter coefficients. Outputs from the multipliers 133 a to 133 e are added by the adder 134 and then output to the image output processing unit 104 via the shifter 135.

The filter coefficient determination unit 124 selects a horizontal filter coefficient set used for horizontal filter processing in the horizontal filter 125 and a vertical filter coefficient set used for vertical filter processing in the vertical filter 126 according to the detection result in the distortion detection unit 123. . Specifically, as illustrated in FIG. 20, the filter coefficient determination unit 124 includes a coefficient table holding unit 151 that holds a plurality of horizontal filter coefficient sets and a plurality of vertical filter coefficient sets, and a distortion in the distortion detection unit 123. The encoder 152 includes an encoder 152 that encodes a detection result, and a selector 153 that selects one horizontal filter coefficient set and one vertical filter coefficient set from the coefficient table holding unit 151 based on an output from the encoder 152. According to the example shown in FIG. 20, each coefficient of the horizontal filter coefficient set selected by the selector 153 is output to the horizontal filter 125, while each coefficient of the vertical filter coefficient set selected by the selector 153 is It is output to the coefficient registers 132a to 132e. For example, the selector 153 selects the coefficient set 1 or the coefficient set 2 in the coefficient table holding unit 151. In this example, one of coefficient set 1 that functions as a low-pass filter and coefficient set 2 that transmits without functioning as a filter is selected as the horizontal filter coefficient set and the vertical filter coefficient set.
1989 National Congress of the Institute of Television Engineers 19-11.pp.467-468 (july 1989) "Examination of edge-preserving block distortion removal filter for video coding"

  In the filter processing method used in the conventional MPEG decoding apparatus, since the plurality of line memories used in the vertical filter processing are required to store pixel data for the number of horizontal pixels constituting the frame, the area occupied by the line memory is large. This was a factor that hindered miniaturization and a factor that increased the cost of semiconductor devices.

  Also, when the decoded image information is output to the display device at a predetermined frame rate, even if it is the same frame image as the frame image displayed immediately before, the filtering process must be performed sequentially, and the filter is always filtered. Electric power to be processed was necessary.

  Therefore, in the present invention, a huge line memory for vertical filter processing in the image processing apparatus is reduced.

  In order to solve the above-described problem, an image decoding apparatus according to the present invention generates decoding information by decoding encoding information in accordance with input of encoding information of a decoding target pixel block including a plurality of pixels. A pixel that holds at least part of information of a decoding unit and a vertical pixel block that is adjacent to the decoding target pixel block in the vertical direction, and additionally holds decoding information according to the input of decoding information from the decoding unit The processing block information is corrected by filtering the processing block information including the holding unit and the decoding information and at least a part of the vertical pixel block information held in the pixel holding unit, and the decoding target pixel block and the vertical pixel Distorts information on at least some of the pixel groups, including the pixel group in the vicinity of the vertical boundary between the pixel block to be decoded and the vertical pixel block, among the pixel groups that form at least a part of the block A post filter having a vertical filter unit that outputs as positive pixel information; and a display information storage unit that holds distortion correction pixel information output from the post filter. The decoding unit includes a plurality of pixel blocks to be decoded. The encoding information of the image frame is sequentially input as the encoding information of the decoding target pixel block in units of pixel blocks, and the display information recording unit is configured with distortion correction pixel information output for each of the plurality of pixel blocks. The display image frame information is held.

  In the image decoding apparatus according to the present invention, since the distortion between the pixel blocks in the post filter can be corrected according to the input in units of pixel blocks, the line used when correcting the distortion between the pixel blocks in the vertical direction of the post filter is used. Memory capacity can be reduced.

  As described above, an image decoding apparatus according to the present invention includes a decoding unit, a post filter that corrects inter-block distortion according to an input in units of pixel blocks, a pixel holding unit, and a vertical filter unit. Information storage unit. Here, information such as information on the decoding target pixel block, information on the vertical pixel block, information on the pixel group, and the like includes pixel values relating to the pixels constituting each pixel block and pixel group. The pixel value means, for example, a luminance value in the case of monochrome display, and a luminance component (Y component) value (luminance value) and two types of color difference components (I) in the case of full color display. Component and Q component, or Cr component and Cb component) and three types of color components (R component, G component, and B component). The information for each pixel block and the information for the pixel group may further include an address for specifying the position in the pixel block or the image frame.

  The post filter according to the present invention causes the pixel holding unit to hold information on at least some of the pixels in the vertical pixel block necessary for correcting the distortion between the pixel blocks with respect to the decoding target pixel block. By inputting processing block information including at least a part of information of the vertical pixel block held in the holding unit to the vertical filter unit, the distortion between the pixel blocks in the vertical direction is corrected in units of processing blocks. Therefore, unlike the conventional image decoding apparatus, it is not necessary to hold information about all the pixels constituting the horizontal image line of the image frame, and the capacity of the line memory used for correcting the distortion between the pixel blocks in the vertical direction is reduced. Can be reduced. Here, the vertical pixel block is a pixel block that is adjacent to the decoding target pixel block in the vertical direction, and is a pixel block that has been decoded by the decoding unit in the past from the decoding target pixel block.

  The amount of information held in the pixel holding unit when storing information on only a part of the pixels constituting the vertical pixel block compared to the case of storing information on all the pixels constituting the vertical pixel block in the pixel holding unit And the amount of information processed by the post filter can be reduced. Therefore, the post filter processing can be speeded up.

  When the number of input frames of image information input to the decoding unit of the image processing device is smaller than the number of display frames output from the image processing device to the display device by frame interpolation, line interpolation, etc., Power consumption can be reduced. This is because the post filter according to the present invention can perform filter processing on the same number of image frames as the number of input frames and generate interpolation frame information and interpolation line information based on the image frames after the filter processing. In the conventional post filter, the number of image frames to be processed does not depend on the number of input frames, and filter processing is performed on the same number of image frames as the final display frame after frame interpolation, line interpolation, and the like. Had to be done.

  In addition, the post filter of the present invention includes at least a part of a pixel group in the vicinity of a vertical boundary between the decoding target pixel block and the vertical pixel block among pixel groups constituting at least a part of the decoding target pixel block and the vertical pixel block. Distortion correction pixel information relating to the pixel group is generated. Here, the pixel group in the vicinity of the vertical boundary means a pixel adjacent to the boundary between the decoding target pixel block and the vertical pixel block. Note that the pixel group in which the distortion correction pixel information is generated only needs to include at least one pixel constituting the vertical boundary neighboring pixel group. In addition, the pixel group in which the distortion correction pixel information is generated may include all the pixels constituting the decoding target pixel block, or may include only a part of the pixels.

  In the image decoding apparatus according to the present invention, the pixel group in the vicinity of the vertical boundary may include a pixel that constitutes the decoding target pixel block and a pixel that constitutes at least a part of the vertical pixel block. Correction of distortion between pixel blocks in the vertical direction with respect to the decoding target image frame when the decoding information of all the pixel blocks constituting the decoding target image frame is input to the post filter and the post filter processing for the decoding target image frame is completed. Therefore, it is not necessary to generate distortion correction pixel information for all pixels constituting the decoding target pixel block for each decoding information of the decoding target pixel block input to the post filter. Therefore, with the above configuration, the decoding target can be obtained without generating distortion correction pixel information for all the pixels constituting the encoding target pixel block according to the input to the post filter of the decoding information of the decoding target pixel block. Generation of distortion correction pixel information for all the pixels of the decoding target pixel block can be completed when information on the pixel block adjacent to the decoding target pixel block to be processed in the future from the pixel block is input to the post filter.

  In the image decoding apparatus according to the present invention, the post filter detects distortion between pixel blocks between the decoding target pixel block and the vertical pixel block based on the decoding information of the decoding target pixel block and the information of the vertical pixel block. And a filter coefficient determining unit that determines a vertical filter coefficient set according to the detection result of the inter-pixel block distortion in the distortion detecting unit, and the vertical filter unit of the post filter includes the vertical filter coefficient set. With reference to the processing block information, it can be configured to filter. With this configuration, different filter processing is performed depending on whether the pixel block distortion is small or small and the pixel block distortion is large or small, based on the decoding information of the decoding target pixel block and the vertical pixel block information. It can be carried out. As information on the vertical pixel block, information on the vertical pixel block from the decoding unit decoded before the pixel block to be decoded may be used, or all information on the vertical pixel block is held in the pixel holding unit. If it is, information on the vertical pixel block extracted from the pixel holding unit may be used.

  In the image decoding device according to the present invention, the post filter includes a decoding target pixel block and a horizontal pixel block based on decoding information on the decoding target pixel block and information on a horizontal pixel block horizontally adjacent to the decoding target pixel block. A distortion detection unit that detects inter-pixel block distortion between the first and second pixels, and a filter coefficient determination unit that determines a vertical filter coefficient set according to the detection result of the inter-pixel block distortion in the distortion detection unit. The filter unit may be configured to filter the processing block information with reference to the vertical filter coefficient set. With this configuration, different filter processing is performed depending on whether the pixel block distortion is small or small and the pixel block distortion is large or small, based on the decoding information of the decoding target pixel block and the horizontal pixel block information. It can be carried out.

  In the image decoding device according to the present invention, the post filter generates processing block information by combining the decoding information of the decoding target pixel block and the information of at least a part of the vertical pixel block held in the pixel holding unit, An information synthesizing unit that outputs to the distortion detecting unit and the vertical filter unit may be further included. With this configuration, since the decoding information of the decoding target pixel block and the information of at least a part of the vertical pixel block are associated with each other and output to the vertical filter unit, the vertical filter unit simply and reliably Information necessary for correcting the distortion between blocks can be obtained. For example, the processing block information can be information obtained by connecting the decoding information of the decoding target pixel block and at least a part of the information of the vertical pixel block held in the pixel holding unit. The vertical filter unit may be input by any method as long as the decoding information of the encoding target pixel block and at least a part of the information of the vertical pixel block are input in association with each other. For example, the decoding target pixel block information and the vertical pixel block information corresponding thereto may be synchronized and supplied individually to the vertical filter unit.

  The image decoding apparatus according to the present invention further includes a decoding information storage unit that holds information of a reference image frame different from the decoding target image frame, and the encoding information of the decoding target pixel block includes encoding difference image information, quantum The decoding unit is dequantized by an inverse quantization unit that inversely quantizes encoded difference image information with reference to the quantization granularity information, and an inverse quantization unit. An inverse orthogonal transform unit that generates decoded differential image information by performing inverse orthogonal transform on the encoded differential image information, and a prediction image with reference to motion vector information and reference image frame information held in the decoding information storage unit Based on the motion compensated prediction unit that generates information, the decoded differential image information and the predicted image information, the decoding information of the decoding target pixel block is generated, and the decoding information is output to the decoding information storage unit and the post filter And a adder, filter coefficient determining section of the post filter, with additional reference to at least one of the quantization granularity information and motion vector information may be configured to determine the vertical filter coefficient sets. With this configuration, it is possible to generate display image frame information from the encoding information of the decoding target image frame encoded by performing motion compensation prediction. In addition, when the information of the decoding target image frame is referred to in the motion compensation prediction for the image frame processed after the decoding target image frame, it is necessary to write the current decoding pixel block information in the decoding information holding unit. Simultaneously with this writing, the decoding information of the decoding target pixel block can be input to the post filter. That is, the writing to the decoding information holding unit and the filtering process according to the input of the encoding information of the decoding target pixel block can be executed in parallel processing. Further, by referring to the quantization granularity information and the motion vector information together with the detection result of the inter-pixel block distortion in the distortion detection unit, a good vertical filter coefficient set for correcting the inter-pixel block distortion can be determined. .

  The display information storage unit and the decoding information recording unit may be configured by different memory elements, or may be memories allocated to different areas in the same memory element.

  The image decoding apparatus according to the present invention further holds at least part of information of a horizontal pixel block horizontally adjacent to the decoding target pixel block, and the processing block information is at least one of the horizontal pixel blocks held in the pixel holding unit. A pixel to be decoded from among a group of pixels constituting a pixel block to be decoded, at least a part of a vertical pixel block, and at least a part of a horizontal pixel block. A vertical filter that further includes a horizontal filter unit that corrects information of at least a part of the pixel group including a pixel group near a horizontal boundary between the block and the horizontal pixel block, and outputs the corrected processing block information to the vertical filter unit; At least one of the decoding target pixel block, the vertical pixel block, and the horizontal pixel block. It is preferable to adopt a configuration that outputs at least information of a portion of the pixel group and a pixel group of the pixel group and the horizontal vicinity of the border of neighboring vertical boundary of a pixel group constituting the. With this configuration, at least a part of the horizontal pixel block information necessary for correcting the inter-pixel block distortion for the decoding target pixel block is further held in the pixel holding unit, and the encoding information of the decoding target pixel block and the pixel holding unit are stored. Processing block information including at least a part of information of the vertical pixel block held in the pixel holding unit and information of at least a part of the horizontal pixel block held in the pixel holding unit to the vertical filter unit It is possible to correct distortion between pixel blocks in the vertical direction and the horizontal direction. That is, it is possible to correct two-dimensional distortion between pixel blocks in the vertical direction and the horizontal direction. Therefore, it is possible to form an image with higher image quality than when correcting only the distortion between pixel blocks in the vertical direction. Here, the horizontal pixel block is a pixel block decoded in the decoding unit in the past than the decoding target pixel block. The pixel group in the vicinity of the horizontal boundary means a pixel adjacent to the boundary between the decoding target pixel block and the horizontal pixel block. Note that the pixel group in which the distortion correction pixel information is generated only needs to include at least one pixel constituting the pixel group near the horizontal boundary. Hereinafter, an image processing apparatus that includes a vertical filter unit and a horizontal filter unit and corrects a two-dimensional distortion between pixel blocks is also referred to as a two-dimensional distortion correction image processing apparatus.

  In the two-dimensional distortion correction image decoding apparatus according to the present invention, the pixel group in the vicinity of the horizontal boundary may include a pixel constituting the decoding target pixel block and a pixel constituting at least a part of the horizontal pixel block. it can. With this configuration, as in the case of the pixel group in the vicinity of the vertical boundary described above, distortion correction for all the pixels constituting the encoding target pixel block is performed for each decoding information of the encoding target pixel block input to the post filter. Even if pixel information is not generated, generation of distortion-corrected pixel information for a decoding target pixel block when information on a pixel block adjacent to the decoding target pixel block processed in the future from the decoding target pixel block is input to the post filter. Can be completed.

  In the two-dimensional distortion correction image decoding apparatus according to the present invention, the post filter includes decoding target pixel block information, information on at least a part of the vertical pixel block held in the pixel holding unit, and horizontal pixels held in the pixel holding unit. An information synthesizing unit that synthesizes at least a part of information of the block to generate processing block information and outputs it to the distortion detection unit can be adopted. With this configuration, information necessary for two-dimensional inter-block distortion correction can be associated and supplied to the horizontal filter unit and the vertical filter unit, so that the processing block information can be easily and reliably added to the vertical filter unit and the horizontal filter unit. Each of the filter processing in the vertical direction and the filter processing in the horizontal direction can be performed.

  In the two-dimensional distortion correction image decoding apparatus according to the present invention, the reference pixel information held in the pixel holding unit is adjacent to the decoding target pixel block, the vertical pixel block, and the horizontal pixel block, and the decoding target pixel block, vertical The pixel block and the horizontal pixel block further include information on at least a part of a diagonal pixel block, and the processing block information further includes information on at least a part of the diagonal pixel block held in the pixel holding unit, and a post filter Of the pixel group constituting the decoding target pixel block, at least a part of the vertical pixel block, at least a part of the horizontal pixel block, and at least a part of the diagonal pixel block. Among them, the information of at least some pixel groups including the pixel group near the horizontal boundary is corrected, and the vertical filter unit Information on at least some pixel groups including a pixel group near the vertical boundary and a pixel group near the horizontal boundary among the pixel groups constituting at least a part of the elementary block, the vertical pixel block, and the horizontal pixel block. It can be set as the structure which outputs. With this configuration, with respect to processing block information including information on a pixel group constituting at least a part of a decoding target pixel block, a vertical pixel block, at least a part of a horizontal pixel block, and at least a part of a diagonal pixel block. A vertical filter process and a horizontal filter process can be performed in the vertical filter unit and the horizontal filter unit, respectively.

  In the two-dimensional distortion correction image decoding apparatus according to the present invention, the horizontal filter unit of the post filter filters the processing block information, and at least one of the decoding target pixel block, the vertical pixel block, and the horizontal pixel block. And at least a part of pixel groups including a pixel group near the horizontal boundary and a pixel group near the diagonal boundary between the decoding target pixel block and the diagonal pixel block The pixel group near the vertical boundary and the pixel near the horizontal boundary among the pixel groups constituting the pixel block to be decoded, at least part of the vertical pixel block, and at least part of the horizontal pixel block are corrected by the vertical filter unit. The information of at least some pixel groups including the group and the pixel group near the diagonal boundary can be output. With this configuration, distortion correction pixel information for some pixels of the diagonal pixel block can be further generated.

  In the image decoding apparatus for two-dimensional distortion correction according to the present invention, the post filter includes decoding information on the pixel block to be decoded, information on at least a part of the vertical pixel block held in the pixel holding unit, and a pixel holding unit. The processing block information is generated by synthesizing at least a part of information of the held horizontal pixel block and at least a part of the diagonal pixel block held in the pixel holding unit, and output to the distortion detection unit and the horizontal filter unit The information synthesizing unit may be further included.

  In the image decoding apparatus for two-dimensional distortion correction according to the present invention, the post filter is a pixel between the decoding target pixel block and the vertical pixel block based on the decoding information of the decoding target pixel block and the information of the vertical pixel block. A distortion detection unit that detects inter-block distortion; and a filter coefficient determination unit that determines a vertical filter coefficient set and a horizontal filter coefficient set according to a detection result of inter-pixel block distortion in the distortion detection unit. The vertical filter unit may perform a filtering process with reference to the vertical filter coefficient set, and the horizontal filter unit of the post filter may perform a filtering process with reference to the horizontal filter coefficient set. With this configuration, the vertical filter coefficient set and the horizontal filter coefficient set can be determined with reference to the decoding target pixel block and the vertical pixel block.

  In the image decoding apparatus for two-dimensional distortion correction according to the present invention, the post filter is a pixel between the decoding target pixel block and the horizontal pixel block based on the decoding information of the decoding target pixel block and the information of the horizontal pixel block. A distortion detection unit that detects inter-block distortion; and a filter coefficient determination unit that determines a vertical filter coefficient set and a horizontal filter coefficient set according to a detection result of inter-pixel block distortion in the distortion detection unit. The vertical filter unit may perform a filtering process with reference to the vertical filter coefficient set, and the horizontal filter unit of the post filter may perform a filtering process with reference to the horizontal filter coefficient set. With this configuration, the vertical filter coefficient set and the horizontal filter coefficient set can be determined with reference to the decoding target pixel block and the horizontal pixel block.

  The image decoding apparatus for two-dimensional distortion correction according to the present invention further includes a decoding information storage unit that holds information of a reference image frame different from the decoding target image frame, and the encoding information of the decoding target pixel block includes an encoding difference. An inverse quantization unit having image information, quantization granularity information, and motion vector information, and a decoding unit inversely quantizes the encoded difference image information with reference to the quantization granularity information, and an inverse quantization unit Information of the reference image frame held in the motion vector information and the decoding information storage unit, and the inverse orthogonal transform unit that generates the decoded differential image information by performing the inverse orthogonal transform on the encoded differential image information dequantized in step A motion compensation prediction unit that generates prediction image information with reference to the decoding information of the pixel block to be decoded based on the decoded difference image information and the prediction image information, and stores the decoding information in a decoding information storage unit; Post fee And an adder that outputs to the data filter, wherein the filter coefficient determination unit of the post filter further determines the vertical filter coefficient set and the horizontal filter coefficient set by further referring to at least one of the quantization granularity information and the motion vector information It can be. With this configuration, information on a display image frame is generated from information on a decoding target image frame encoded by motion compensation prediction by a horizontal filter unit and a vertical filter unit having a line memory with a reduced capacity. be able to. In addition, writing of decoding information of the decoding target pixel block to the decoding information holding unit and filtering processing according to the input of the encoding information of the decoding target pixel block can be executed in parallel processing. Furthermore, by referring to the quantization granularity information and the motion vector information together with the detection result of the inter-pixel block distortion in the distortion detection unit, a good vertical filter coefficient set for correcting the inter-pixel block distortion can be selected. . The same coefficient set may be selected as the vertical filter coefficient set and the vertical filter coefficient set, or different coefficient sets may be selected for each.

  The display information storage unit and the decoding information recording unit may be configured by different memory elements, or may be memories allocated to different areas in the same memory element.

  Note that the image decoding apparatus according to the present invention is characterized by processing performed after generation of decoded pixel block information, and thus the decoding unit may have any known configuration.

(Embodiment 1)
In the first embodiment, coding information (code signal) of a decoding target pixel block that has been subjected to variable-length coding using a motion compensation prediction technique is decoded, and based on processing block information that includes the decoded decoding information. An image decoding apparatus that corrects distortion between two-dimensional blocks will be described. Note that the processing block information at the time of post-filter processing includes decoding information of a decoding target pixel block, information on a part of a vertical pixel block, information on a part of a horizontal pixel block, and information on a part of a diagonal pixel block. The case where it comprises is demonstrated.

  As shown in FIG. 1, the image decoding apparatus according to the first embodiment includes an input buffer 11, an inverse variable length coding (iVLD) unit 12, an inverse quantization unit 13, an inverse discrete cosine transform (iDCT) unit. (Inverse Orthogonal Transform Unit) 14, Decoding Unit 1 Consisting of Motion Compensation Prediction Unit 15, Adder 16, Post Filter 2, Display Frame Region (Display Information Storage Unit) 3, and Local Decode Reference Frame Region (Decode For example, a frame memory device 10 having an information storage unit 5 and an image output processing unit 4.

  The encoded differential image information and the quantization granularity information included in the encoded information (code signal) input to the input buffer 11 are output to the inverse variable length encoding unit 12, and the prediction mode information included in the encoded information and The motion vector information is output to the motion compensation prediction unit 15. The inverse variable length encoding unit 12 performs inverse variable length encoding on the encoded difference image information from the input buffer 11. The encoded variable image information and the quantization granularity information subjected to inverse variable length encoding are output to the inverse quantization unit 13. The inverse quantization unit 13 refers to the quantization granularity information from the inverse variable length encoding unit 12 and inversely quantizes the encoded difference image information that has been variable length encoded by the inverse variable length encoding unit 12. The inversely quantized encoded difference image information is output to the inverse discrete cosine transform unit 14. The inverse discrete cosine transform unit 14 performs inverse discrete cosine transform on the inversely quantized encoded difference image information, and generates decoded difference image information for the decoding target pixel block from the inversely quantized encoded difference image information. The decoded difference image information is output to the adder 16. The motion compensation prediction unit 15 calculates a reference pixel address by referring to the motion compensation mode information and the motion vector information, and based on the reference pixel address, a prediction that has already been processed and held in the local decoding reference frame region 5 Extract image information. The extracted predicted image information is output to the adder 16. The adder 16 generates decoding information of the decoding target pixel block based on the difference image information from the inverse discrete cosine transform unit 14 and the prediction image information from the motion compensation prediction unit 15. The decoded information is output to the frame memory element 10 and stored in the local decoding reference frame area 5 of the frame memory element 10. Decoding and storage in the frame memory element 10 are repeated for each pixel block, and as shown in FIG. 2, the decoding target image frame including the decoding target pixel block (one of the local decoding reference frames in FIG. 2) Frame) is stored in the frame memory device 10. The decoding target image frame stored in the frame memory element 10 serves as a reference image frame for an image frame decoded after (future) the decoding target image frame.

  Further, the decoding information of the decoding target pixel block is output to the local filter reference frame area 5 of the frame memory element 10 and simultaneously to the post filter 2. In response to this, the post-filter 2 sequentially outputs distortion correction pixel information for all the pixels constituting the decoding target frame to the display frame area 3 of the frame memory element 10 and stores them.

  By repeating the above processing for all pixel blocks constituting the decoding target image frame for each pixel block, as shown in FIG. 2, a display image frame with corrected inter-pixel block distortion (FIG. 2). One frame) in the middle display frame is stored in the frame memory element 10.

  The post-filter processed display image frames stored in the display frame area 3 are sequentially read out at a predetermined display frame rate, and are converted into image signals compliant with a predetermined TV signal system or the like by the image output processing unit 4. It is converted and output as an output signal.

  Here, the configuration of the post filter 2 and post filter processing will be described. As shown in FIG. 3, the post filter 2 includes a pixel holding unit 21, an information synthesis unit 22, a distortion detection unit 23, a filter coefficient determination unit 24, a horizontal filter unit 25, and a vertical filter unit 26. It is the structure provided with.

  The pixel holding unit 21 holds at least a part of the information of the pixel block decoded before (past) the decoding target pixel block, and when the decoding target pixel block information is input, the decoding target pixel block A part of the information is additionally held in order to correct the inter-pixel distortion of the pixel block to be decoded in the future. Specifically, before the encoding information of the decoding target pixel block is input (past), information on a part of the vertical pixel block for the decoding target pixel block and information on a part of the horizontal pixel block for the decoding target pixel block And information on a part of the diagonal pixel block with respect to the decoding target pixel block.

  Note that when the correction of inter-pixel block distortion for all the pixel blocks (eight pixel blocks) adjacent to the decoding target pixel block is completed, the information on the decoding target pixel block held in the pixel holding unit is deleted.

  The information synthesis unit 22 encodes the decoding target pixel block, the partial information of the vertical pixel block held in the pixel holding unit 21, the partial information of the horizontal pixel block, and the diagonal pixel block. And processing block information is generated, and the processing block information is output to the distortion detection unit 23. For example, when the encoding information from the decoding unit 1 is input, the switch element as illustrated in FIG. 3 causes the decoding information to include the partial information of the vertical pixel block and the partial information of the horizontal pixel block. Information and information on a part of the diagonal pixel block are added so as to have a predetermined arrangement. Hereinafter, a pixel group including a decoding target pixel block, a part of a vertical pixel block, a part of a horizontal pixel block, and a part of a diagonal pixel block is also referred to as a processing block.

  In the distortion detection unit 23, based on the processing block information read from the information synthesis unit 22 and the information on the horizontal pixel block decoded immediately before the decoding target pixel block, the decoding target pixel block and the horizontal pixel block The presence or absence of inter-pixel block distortion at the boundary is checked. In the filter coefficient determination unit 24, a horizontal filter coefficient set referred to in the horizontal filter process in the horizontal filter unit 25 and a vertical filter coefficient set referred to in the vertical filter process in the vertical filter unit 26 according to the inspection result in the distortion detection unit 23. To decide.

  Specifically, the strain detection unit 23 has the configuration shown in FIG. With this configuration, in two horizontally adjacent pixel blocks, the difference absolute value for pixels adjacent to the left and right across the boundary of the pixel block is the difference absolute value for pixels adjacent in the vicinity of the boundary in one pixel block. If there is a visual distortion between the pixel blocks when the average absolute value of the difference between adjacent pixels in the vicinity of the boundary in the other pixel block is larger than the average value of the threshold value and larger than the predetermined threshold range. To detect.

  The operation of distortion detection is almost the same as that of the conventional distortion detection unit shown in FIG. 18, but the two distortion detection threshold values can be set, so that the detection range of the distortion magnitude can be specified in more detail than the conventional one. Can do. In the conventional distortion detection unit, since the binary determination of the presence / absence of distortion is made, the filter coefficient determination unit can select only one of coefficient sets 1 and 2 as shown in FIG. There wasn't.

  Here, the operation of the distortion detection unit will be specifically described with reference to FIG. Reference is also made to FIG. The pixel values of the pixels on the same line in the left pixel block and the right pixel block adjacent in the horizontal direction are P00 to P07 and P10 to P17 (see FIG. 21).

  The pixel values of the pixels arranged in the horizontal direction are sequentially input, and the difference absolute values held in the shift registers 48g, 48f, 48e, 48d, and 48c are | P05-P06 |, | P06-P07 |, | When P07-P10 |, | P10-P11 |, and | P11-P12 |, the output from the divider 146a is (| P10-P11 | + | P11-P12 |) / 2, and the output from the divider 146b. The output is (| P05−P06 | + | P06−P07 |) / 2. These are average values of absolute differences with respect to horizontally adjacent pixels in the vicinity of the boundary in each block, that is, values indicating the magnitude of change in each block. The output from the shift register 48j at this time is the difference absolute value | P07-P10 | of two pixels horizontally adjacent across the boundary of the pixel block, and is a value indicating the size of the step between the pixel blocks. It is. The operation so far is the same as the conventional operation.

  The comparator 44a compares | P07-P10 | with the distortion detection threshold value set in the threshold value register 43a (threshold value register 1). If | P07-P10 | is large, the logical sum circuit 47a indicates a true value. If | P07-P10 | is small, a signal indicating a false value is output to the OR circuit 47a. Similarly, the comparator 44b compares | P07-P10 | with the distortion detection threshold set in the threshold register 43b (threshold register 2), and if | P07-P10 | is large, the OR circuit 47b. If | P07-P10 | is small, a signal indicating a false value is output to the OR circuit 47b. In the comparator 45a, (| P10-P11 | + | P11-P12 |) / 2 and | P07-P10 | are compared with each other, and if | P07-P10 | is large, the OR circuit 47a and A signal indicating a true value is output to 47b, and if | P07-P10 | is small, a signal indicating a false value is output to the OR circuits 47a and 47b. Further, the comparator 45b compares (| P05-P06 | + | P06-P07 |) / 2 with | P07-P10 | as in the conventional case, and if | P07-P10 | A signal indicating a true value is output to 47a and 47b, and if | P07-P10 | is small, a signal indicating a false value is output to the OR circuits 47a and 47b.

In the OR circuit 47a, if all the signals from the comparators 44a, 45a, and 45b are signals indicating true values, a signal indicating a true value is output, and if at least one signal indicates a false value, a false value is output. A signal indicating is output. Similarly, in the OR circuit 47b, if all the signals from the comparators 44b, 45a and 45b are signals indicating true values, a signal indicating true values is output, and at least one is a signal indicating false values. If there is, a signal indicating a false value is output. More specifically, when the threshold register (threshold register 1) 43b in FIG. 4 is set to be smaller than the set value of the threshold register (threshold register 2) 43a, the distortion detection result output 1 and the distortion detection result output 2 are output. Depending on the combination of, for example,
Distortion detection result output 1 = 0 (false value), distortion detection result output 2 = 0 (false value): distortion-free distortion detection result output 1 = 1 (true value), distortion detection result output 2 = 0 (false value): Strain lower limit detection Strain detection result output 1 = 1 (true value), Strain detection result output 2 = 1 (true value): Upper limit detection of strain and multi-stage strain detection can be performed.

  The horizontal filter unit 25 uses the horizontal filter coefficient set determined by the filter coefficient determination unit 24 to correct the processing block information by performing horizontal filter processing on the processing block information generated by the information synthesis unit 22. Thereby, the distortion between the pixel blocks in the horizontal direction is corrected, and the distortion of the image in the horizontal direction is reduced. As shown in FIG. 5, the horizontal filter unit 25 refers to the horizontal filter coefficient set determined by the filter coefficient determination unit 24 and held in the coefficient registers 62 a to 62 e for each horizontal image line in the processing block. Next, horizontal filter processing is performed. Specifically, as shown in FIG. 5, the coefficients set in the coefficient registers 62a to 62e and the pixel values of the pixels are multiplied by the multiplier circuits 63a to 63e, and all multiplication results are added to the adder circuit. Add at 64. The shifter 67 performs division (bit shift) so that the sum of the coefficients becomes 1, and outputs the image information subjected to the horizontal filter processing.

  The image information subjected to the horizontal filter processing by the horizontal filter unit 25 is output to the vertical filter 26. In the conventional image decoding apparatus, horizontal filter processing is performed for each horizontal image line constituting the encoding target image frame.

  As shown in FIG. 3, the vertical filter unit 26 includes multipliers 33 a to 33 e, an adder 34 that adds the outputs of the multipliers 33 a to 33 e, and a shifter 27. In the vertical filter 26, image information input for each horizontal image line in the processing block is sequentially held in the line memories 31 b to 31 e for the number of taps of the vertical filter 26. Each of the line memories 31a to 31e has a size capable of storing image information related to the number of horizontal pixels constituting the processing block. It should be noted that the line memory in the conventional post filter must be able to store image information relating to the number of horizontal pixels constituting the decoding target image frame.

  Further, the line memories 31b to 31d other than the last stage shown in FIG. 3 are connected to the line memories 31c to 31e for the next horizontal image line and the multipliers 33b to 33d. The memory 31e is connected only to the multiplier 33e. The image information subjected to the horizontal filter processing is accumulated by being delayed by one line in each of the line memories 31b to 31e. That is, if the output from the horizontal filter 25 is image information related to the kth horizontal image line, the image information related to the (k−1) th horizontal image line is stored in the line memory 31b, and the line memory 31c stores it. , Image information related to the (k-2) th horizontal image line is stored, image information related to the (k-3) th horizontal image line is stored in the line memory 31d, and (k− 4) Image information relating to the horizontal image line is accumulated.

  The multiplier 33a multiplies the image information related to the kth horizontal image line by the filter coefficient held in the coefficient register 32a. Similarly, the multiplier 33b uses the image information related to the (k-1) th horizontal image line. Is multiplied by the filter coefficient held in the coefficient register 32b, and the multiplier 33c multiplies the image information about the (k-2) th horizontal image line by the filter coefficient held in the coefficient register 32c, and the multiplier 33d Is multiplied by the filter coefficient held in the coefficient register 32d by the image information relating to the (k-3) th horizontal image line, and in the multiplier 33e, the image information relating to the (k-4) th horizontal image line is multiplied by the coefficient register 32e. Is multiplied by the filter coefficient held in the. Outputs from the multipliers 33 a to 33 e are added by the adder 34 and then output to the image output processing unit 4 via the shifter 35.

  Here, a method of determining the horizontal filter coefficient set and the vertical filter coefficient set in the filter coefficient determination unit 24 will be described. As shown in FIG. 6, the filter coefficient determination unit 24 includes a coefficient table holding unit 51 that holds a plurality of filter coefficient sets, an encoder 52 that encodes a distortion detection result in the distortion detection unit 23, It is composed of a selector 53 that selects one coefficient set to be used as a horizontal filter coefficient set and a vertical filter coefficient set from the coefficient table holding unit 51 based on the output. The filter coefficients of the filter coefficient set selected by the selector 53 are respectively stored in coefficient registers 62a to 62e (see FIG. 5) in the horizontal filter unit 25 and coefficient registers 32a to 32e (see FIG. 3) in the vertical filter unit 26. Is output. If the coefficient table holding unit 51 includes the coefficient table shown in FIG. 6, one coefficient set is selected from the coefficient sets 1 to 8. For example, when the coefficient set 4 is selected, −6 is stored in the coefficient register 32a and the coefficient register 62a, and the coefficient register 32e and the coefficient register 62e, and the coefficient register 32b and the coefficient table 62b, and the coefficient register 32d and the coefficient register 62d are stored. 34 is stored, and 72 is stored in the coefficient register 32c and the coefficient table 62c (see FIGS. 3 and 5). Note that the coefficient table in FIG. 6 shows a case where the characteristics of the low-pass filter become gradually lower from the coefficient set 1 toward the coefficient set 8.

  As shown in FIG. 6, the encoder 52 encodes the distortion detection result output 1, the distortion detection output result 2, and the distortion detection threshold value, so that a multi-stage filter coefficient (filter coefficient 1) is generated according to the distortion detection threshold value. ˜8) can selectively select one filter coefficient.

  Here, a two-dimensional inter-pixel block distortion correction in the post filter 2 will be described using a specific example. In the following description, the uppermost leftmost pixel block in the decoding target image frame is B (1,1), the uppermost rightmost pixel block is B (1, N), and the lowermost leftmost pixel block is B (1, N). N, 1), and in decoding for each pixel block, the uppermost leftmost pixel of the pixel block to be decoded is E (1,1), the uppermost rightmost pixel is E (1,8), The leftmost pixel at the bottom is represented as E (8,1). Each information means a pixel value.

  In FIG. 7A, square sections represent pixel blocks. As shown in FIG. 7A, pixels (E (1,1) to E (1,8), E, which are represented by gray pentagons constituting the decoding target pixel block B (1,1)). (2,1) to E (2,8),..., E (8,1) to E (8,8)) (decoding target pixel block information) are sequentially input to the post filter 2. Is done. When the information of the decoding target pixel block B (1, 1) is input, as shown in FIG. 8A, the pixel holding unit 21 stores the pixel group (E (1, 1, 5) to E (1,8), E (2,5) to E (2,8), ..., E (4,5) to E (4,8), E (5,1) to E (5, 8), E (6, 1) to E (6, 8), ..., E (8, 1) to E (8, 8)) are stored.

  As shown in FIG. 7B, the inner pixel is subjected to mirror processing around the boundary line of the decoding target image frame, and a mirror pixel group (E (-1, -1) outside the decoding target image frame is displayed. ~ E (-1,8), E (0, -1) ~ E (0,8), E (1, -1) ~ E (1,0), E (2, -1) ~ E (2 , 0), ..., E (8, -1) to E (8, 0)) are virtually formed. The pixel group of B (1,1) and the mirror pixel group are processing blocks.

  In FIG. 7B, the pixel groups (E (1,1) to E (1,6), E (2,1) to E (2,6),... (6, 1) to E (6, 6)) is a distortion correction target image group, and is a pixel group in which distortion correction pixel information is finally formed. In addition, pixel groups (E (−1, −1) to E (−1, 8), E (0, −1) to E (0, 8), E (1, −) represented by gray upper triangles. 1) to E (1,0) and E (1,7) to E (1,8), E (2, -1) to E (2,0) and E (2,7) to E (2, 8), ..., E (6, -1) to E (6,0) and E (6,7) to E (6,8), E (7, -1) to E (7,8) , E (8, -1) to E (8,8)) are a first reference pixel group to which reference is made in the post filter processing. Note that the first reference pixel group is a pixel group having information on the unfiltered pixel group or information derived from the information.

  Subsequently, based on the information on the distortion correction target pixel group and the information on the first reference pixel group, the distortion correction pixel for the distortion correction target pixel group is obtained by the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26. Information is generated. As shown in FIG. 7C, pixel groups (E (1,1) to E (1,6), E (2,1) represented by black circles in the decoding target pixel block B (1,1). ) To E (2,6),..., E (8,1) to E (8,6)) represent a filtered pixel group in which distortion correction pixel information is generated and distortion correction is completed. , Pixel groups represented by white circles (E (1,7) to E (1,8), E (2,7) to E (2,8),..., E (6,7) to E ( 6, 8), E (7, 1) to E (7, 8), E (8, 1) to E (8, 8)), distortion correction pixel information is not generated, and distortion correction is completed. Represents no unfiltered pixel group.

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8),..., Shown in FIG. The information of the decoding target pixel block B (1, 2) consisting of E (8, 1) to E (8, 8)) is input to the post filter 2. Along with the input of information on the decoding target pixel block B (1, 2), the pixel holding unit 21 displays the pixels indicated by circles in FIG. 8B among the decoding target pixel block B (1, 2). Groups (E (1,5) to E (1,8), E (2,5) to E (2,8),..., E (4,5) to E (4,8), E ( 5,1) to E (5,8), E (6,1) to E (6,8),..., E (8,1) to E (8,8)) are stored. .

  Subsequently, as shown in FIG. 7E, the inner pixels are mirrored around the boundary line of the decoding target image frame, and the mirror pixel group (E (−1, − 3) to E (-1,8), E (0, -3) to E (0,8)) are virtually formed. The information about the right half pixel group and the information about the mirror pixel group in the pixel block B (1, 1) stored in the pixel holding unit 21 is added to the information of the decoding target pixel block B (1, 2). And output to the horizontal filter unit 25.

  In FIG. 7 (e), pixels (E (1, -1) to E (1,6), E (2, -1) to E (2,6),... E (6, -1) to E (6, 6)) are distortion correction target image groups, and are finally pixel groups for which distortion correction pixel information is generated. In addition, pixel groups (E (-1, -1) to E (-1, 8), E (0, -1) to E (0, 8), E (1, 7) represented by gray upper triangles. ) To E (1,8), E (2,7) to E (2,8), ..., E (6,7) to E (6,8), E (7, -3) to E (7, 8) and E (8, -3) to E (8, 8)) are the first reference pixel group to be referred to in the post filter processing. In addition, pixel groups (E (−1, −3) and E (−1, −2), E (0, −3) and E (0, −2),. , E (6, -3) and E (6, -2)) are the second reference pixel group referred to in the post filter processing. Here, the second reference pixel group is a pixel group having information before filter processing for a pixel group that has been filtered or a pixel group having information derived from information before filter processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 7F, the pixel group represented by a black circle is a filtered pixel group.

  Next, the same filtering process as that for the decoding target pixel block B (1,2) is performed on the pixel block B (1,3) to the pixel block B (1, N-1).

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8), etc.) indicated by gray pentagons in FIG. The information of the decoding target pixel block B (1, N) composed of E (8, 1) to E (8, 8)) is input to the post filter 2. With the input of information on the decoding target pixel block B (1, N), the pixel holding unit 21 stores the pixel group (E (5, 1) indicated by white circles in FIG. 8C among the decoding target pixel blocks. ) To E (5,8), E (6,1) to E (6,8),..., E (8,1) to E (8,8)) are stored.

  Subsequently, as shown in FIG. 7 (h), mirror processing of inner pixels is performed around the boundary line of the decoding target image frame, and a mirror pixel group (E (−1, − 3) to E (-1,10), E (0, -3) to E (0,10), E (1,9) to E (1,10), E (2,9) to E (2 , 10), ..., E (8,9) to E (8,10)) are virtually formed.

  In FIG. 7H, pixel groups (E (1, -1) to E (1,8), E (2, -1) to E (2,8),. , E (6, -1) to E (6, 8)) are distortion correction target pixels, and finally a pixel group in which distortion correction pixel information is generated. In addition, pixel groups (E (-1, -1) to E (-1, 10), E (0, -1) to E (0, 10), E (1, 9) represented by upper triangles of gray. ) To E (1,10), E (2,9) to E (2,10), ..., E (6,9) to E (6,10), E (7, -3) to E (7, 10) and E (8, -3) to E (8, 10)) are a first reference pixel group referred to in the post filter processing. In addition, pixel groups (E (−1, −3) and E (−1, −2), E (−2, −3) and E (−2, −2)) represented by gray lower triangles, .., E (6, -3) and E (6, -2)) are the second reference pixel group referred to in the post filter processing.

  Subsequently, based on the information (processing block information) regarding the distortion correction target pixel, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Then, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 7 (i), the pixel group represented by the black circle is a filtered pixel group.

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8)) shown in FIG. The information of the decoding target pixel block B (2, 1) composed of E (8, 1) to E (8, 8)) is input to the post filter 2. Along with the input of information on the decoding target pixel block B (1,2), the pixel holding unit 21 stores the pixel group (E shown in white circles in FIG. 10A) of the pixel block B (2,1). (1,5) to E (1,8), E (2,5) to E (2,8), ..., E (4,5) to E (4,8), E (5,1 ) To E (5,8), E (6,1) to E (6,8),..., E (8,1) to E (8,8)) are stored.

  Subsequently, as shown in FIG. 9B, the inner pixel is mirrored around the boundary line of the decoding target image frame, and the mirror pixel group (E (−3, − 1) to E (-3, 0), E (-2, -1) to E (-2, 0), ..., E (8, -1) to E (8, 0)) To form. The information about the lower half pixel group and the information about the mirror pixel group in the pixel block B (1, 1) stored in the pixel holding unit 21 are added to the information of the pixel block B (2, 1). It is output to the horizontal filter unit 25.

  In FIG. 9B, pixel groups (E (-1, 1) to E (-1, 6), E (0, 1) to E (0, 6) represented by gray rhombuses,... , E (6,1) to E (6,6)) are distortion correction target pixels, and finally a pixel group in which distortion correction pixel information is formed. In addition, pixel groups (E (-1, -1) to E (-1, 0), E (-1, 7) to E (-1, 8), E (0, -1) to E (0,0) and E (0,7) to E (0,8), ..., E (6, -1) to E (6,0) and E (6,7) To E (6,8), E (7, -1) to E (7,8), and E (8, -1) to E (8,8)) are referred to in the post-filter processing. It is a pixel group. Further, pixel groups (E (−3, −1) to E (−3, 8), E (−2, −1) to E (−2, 8)) represented by gray lower triangles are post-filters. It is the 2nd reference pixel group referred in processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 9C, a pixel group represented by a black circle is a filtered pixel group.

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8), etc.) indicated by gray pentagons in FIG. The information of the decoding target pixel block B (2, 2) consisting of E (8, 1) to E (8, 8)) is input to the post filter 2. Along with input of information on the decoding target pixel block B (2, 2), the pixel holding unit 21 includes a group of pixels indicated by white circles in FIG. 10B among the decoding target pixel block B (2, 2). (E (1,5) to E (1,8), E (2,5) to E (2,8), ..., E (4,5) to E (4,8), E (5 , 1) to E (5,8), E (6,1) to E (6,8),..., E (8,1) to E (8,8)) are stored. The information about the lower half pixel group in the pixel block B (1, 2) stored in the pixel holding unit 21 and the right half pixel in the pixel block B (2, 1) stored in the pixel holding unit 21 Information regarding the group is added to the information of the decoding target pixel block B (2, 2) and output to the horizontal filter unit 25.

  As shown in FIG. 9E, pixel groups (E (-1, -1) to E (-1, 6), E (0, -1) to E (0) represented by gray rhombuses. , 6),..., E (6, −1) to E (6, 6)) are distortion correction target pixel groups, and are finally pixel groups for which distortion correction pixel information is generated. In addition, pixel groups (E (−1,7) to E (−1,8), E (0,7) to E (0,8),. , 7) to E (6, 8), E (7, -3) to E (7, 8), E (8, -3) to E (8, 8)) are referred to in the post filter processing. 1 is a reference pixel group. In addition, pixel groups (E (-3, -3) to E (-3,8), E (-2, -3) to E (-2,8), E (- 1, -3) to E (-1, -2), E (0, -3) to E (0, -2), ..., E (6, -3) to E (6, -2) ) Is a second reference pixel group referred to in the post filter processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 9F, the pixel group represented by a black circle is a filtered pixel group.

  Next, the same filtering process as that for B (2,2) is performed for B (2,3) to B (2, N-1).

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8)) shown in FIG. The information of the decoding target pixel block B (2, N) composed of E (8, 1) to E (8, 8)) is input to the post filter 2. Along with the input of information on the decoding target pixel block B (2, N), the pixel holding unit 21 includes a group of pixels indicated by white circles in FIG. 10C among the decoding target pixel block B (2, N). (E (5,1) to E (5,8), E (6,1) to E (6,8), ..., E (8,1) to E (8,8)) Stored.

  Subsequently, as shown in FIG. 9 (h), mirror processing of inner pixels is performed around the boundary line of the decoding target image frame, and a mirror pixel group (E (−3, 9) outside the decoding target image frame is performed. ) To E (-3, 10), E (-2, 9) to E (-2, 10), ..., E (8, 9) to E (8, 10)) are virtually formed. . The information about the right half pixel group in the pixel block B (1, N) stored in the pixel holding unit 21 and the right half in the pixel block B (2, N−1) stored in the pixel holding unit 21. Is added to the information of the decoding target pixel block B (1, N), and is output to the horizontal filter unit 25.

  As shown in FIG. 9H, pixel groups (E (-1, -1) to E (-1, 8), E (0, -1) to E (0) represented by gray rhombuses. , 8),..., E (6, −1) to E (6, 8)) are distortion correction target pixel groups, and are finally pixel groups for which distortion correction pixel information is generated. In addition, pixel groups (E (−1,9) to E (−1,10), E (0,9) to E (0,10),. , 9) to E (6, 10), E (7, -3) to E (7, 10), E (8, -3) to E (8, 10)) are referred to in the post-filter processing. 1 is a reference pixel group. In addition, pixel groups (E (-3, -3) to E (-3,10), E (-2, -3) to E (-2,10), E (- 1, -3) to E (-1, -2), E (-2, -3) to E (-2, -2), ..., E (6, -3) to E (6,- 2)) is a second reference pixel group referred to in the post filter processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel is generated. As shown in FIG. 9I, the pixel group represented by a black circle is a filtered pixel group.

  Next, the same filter processing as the processing for the pixel block B (2, 1) to the pixel block B (2, N) is performed as the pixel block B (3, 1) to the pixel block B (3, N) and the pixel block B. (3, 1) to pixel block B (3, N),..., Pixel block B (N-1, 1) to pixel block B (N-1, N).

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8)) shown in FIG. The information of the decoding target pixel block B (N, 1) consisting of E (8, 1) to E (8, 8)) is input to the post filter 2. With the input of information on the decoding target pixel block B (N, 1), the pixel holding unit 21 stores a pixel group indicated by a white circle in FIG. 12A among the decoding target pixel blocks B (N, 1). (E (1,5) to E (1,8), E (2,5) to E (2,8),..., E (8,5) to E (8,8)) Stored.

  Subsequently, as shown in FIG. 11B, the inner pixel is subjected to mirror processing around the boundary line of the decoding target image frame, and the mirror pixel group (E (−3, − 1) to E (-3, 0), E (-2, -1) to E (-2, 0), ..., E (8, -1) to E (8, 0), E (9 , -1) to E (-2,8) and E (10, -1) to E (10,8)) are virtually formed. The information about the lower half pixel group and the information about the mirror pixel group in the pixel block B (N−1, 1) stored in the pixel holding unit 21 is information about the decoding target pixel block B (N, 1). And output to the horizontal filter unit 25.

  As shown in FIG. 11B, pixel groups (E (-1, 1) to E (-1, 6), E (0, 1) to E (0, 6) represented by gray rhombuses. ),..., E (8,1) to E (8,6)) are distortion correction target pixels, and finally a pixel group in which distortion correction pixel information is formed. In addition, pixel groups (E (-1, -1) to E (-1, 0), E (-1, 7) to E (-1, 8), E (0, -1) to E (0,0) and E (0,7) to E (0,8), ..., E (8, -1) to E (8,0) and E (8,7) To E (8,8), E (9, -1) to E (9,8), and E (10, -1) to E (10,8)) are referred to in the post-filter processing. It is a pixel group. Further, pixel groups (E (−3, −1) to E (−3, 8), E (−2, −1) to E (−2, 8)) represented by gray lower triangles are post-filters. It is the 2nd reference pixel group referred in processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 11C, a pixel group represented by a black circle is a filtered pixel.

  Next, the pixel groups (E (1,1) to E (1,8), E (2,1) to E (2,8)) shown in FIG. The information of the decoding target pixel block B (N, 2) composed of E (8, 1) to E (8, 8)) is input to the post filter 2. With the input of information on the decoding target pixel block B (N, 2), the pixel holding unit 21 stores a pixel group indicated by a white circle in FIG. 12B among the decoding target pixel block B (N, 2). (E (1,5) to E (1,8), E (2,5) to E (2,8),..., E (8,5) to E (8,8)) Stored. The information about the lower half pixel group in the pixel block B (N-1, 2) stored in the pixel holding unit 21 and the right half in the pixel block B (N, 1) stored in the pixel holding unit 21 The information regarding the pixel group and the information regarding the mirror pixel group are added to the information of the decoding target pixel block B (N, 2) and output to the horizontal filter unit 25.

  As shown in FIG. 11E, pixel groups (E (-1, -1) to E (-1, 6), E (0, -1) to E (0) represented by gray rhombuses. , 6),..., E (8, −1) to E (8, 6)) are distortion correction target pixel groups, and are finally pixel groups for which distortion correction pixel information is generated. In addition, pixel groups (E (−1,7) to E (−1,8), E (0,7) to E (0,8),. , 7) to E (6,8), E (7, -3) to E (7, -2) and E (7,7) to E (7,8), E (8, -3) to E (8, -2) and E (8,7) to E (8,8), E (7, -3) to E (7,8), E (8, -3) to E (8,8) ) Is a first reference pixel group referred to in the post filter processing. In addition, pixel groups (E (-3, -3) to E (-3,8), E (-2, -3) to E (-2,8), E (- 1, -3) to E (-1, -2), E (0, -3) to E (0, -2), ..., E (6, -3) to E (6, -2) ) Is a second reference pixel group referred to in the post filter processing.

  Subsequently, based on information (processing block information) regarding the distortion correction target pixel group, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Thus, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 11F, the pixel group represented by a black circle is a filtered pixel group.

  Next, the same filtering process as that for B (N, 2) is performed for B (N, 3) to B (N, N-1).

  Next, pixel groups (E (1, 1) to E (1, 8), E (2, 1) to E (2, 8),..., Shown in FIG. The information of the decoding target pixel block B (N, N) composed of E (8, 1) to E (8, 8)) is input to the post filter 2. Note that the pixel holding unit 21 does not store any information of the decoding target pixel block B (N, N) as shown in FIG.

  Subsequently, as shown in FIG. 11 (h), the inner pixel is mirrored around the boundary line of the decoding target image frame, and the mirror pixel group (E (−3, 9) outside the decoding target image frame is displayed. ) To E (-3,10), E (-2,9) to E (-2,10), ..., E (8,9) to E (8,10), E (9, -3) ) To E (9, 10) and E (10, -3) to E (10, 10)) are virtually formed. The information about the lower half pixel group in the pixel block B (N−1, N) stored in the pixel holding unit 21 and the pixel block B (N, N−1) stored in the pixel holding unit 21 Information on the right-half pixel group and information on the mirror pixel group are added to the information on the decoding target pixel block B (N, N) and output to the horizontal filter unit 25.

  As shown in FIG. 11 (h), pixel groups (E (-1, -1) to E (-1, 8), E (0, -1) to E (0) represented by gray rhombuses. , 8),..., E (8, −1) to E (8, 8)) are distortion correction target pixel groups, and are finally pixel groups for which distortion correction pixel information is generated. In addition, pixel groups (E (−1,9) to E (−1,10), E (0,9) to E (0,10),. , 9) to E (6, 10), E (7, -3) to E (7, -2) and E (7, 9) to E (7, 10), E (8, -3) to E (8, -2) and E (8,9) to E (8,10), E (9, -3) to E (9,10), E (10, -3) to E (10,10) ) Is a first reference pixel group referred to in the post filter processing. In addition, pixel groups (E (-3, -3) to E (-3,10), E (-2, -3) to E (-2,10), E (- 1, -3) to E (-1, -2), E (-2, -3) to E (-2, -2), ..., E (6, -3) to E (6,- 2)) is a second reference pixel group referred to in the post filter processing.

  Subsequently, based on the information (processing block information) regarding the distortion correction target pixel, the first reference pixel group, and the second reference pixel group, the horizontal filter process in the horizontal filter unit 25 and the vertical filter process in the vertical filter unit 26 are performed. Then, distortion correction pixel information for the distortion correction target pixel group is generated. As shown in FIG. 11 (i), the pixel group represented by a black circle is a filtered pixel group.

  Thereby, the input to the post filter of the encoding information of all the pixel blocks constituting the decoding target image frame is completed, and the filtering process for all the pixels constituting the decoding target image frame is completed. Thereafter, filter processing is sequentially performed on the other image frames in the same manner as the above-described decoding target image frames.

  As apparent from the above description and FIGS. 7 (h), 9 (h), and 11 (h), the number of horizontal pixels in the processing block information is the largest because the pixel block at the right end of each stage is filtered. In this case, the maximum number of horizontal pixels is 14. Therefore, conventionally, it has been necessary to hold information of at least 8 × N pixels, but in the case of this example, the line memories 31a to 31e in the vertical filter 26 store information of 14 pixels. It can be seen that the capacity can be held.

  When the externally connected display device is an NTSC system TV, the image output processing unit 4 reads image information of 30 frames per second, which is the NTSC system display frame rate, from the frame memory. When the image information input to the input buffer 11 is smaller than the display frame rate, such as 15 frames per second, the post filter 2 performs filter processing on the same number of image frames as input to the input buffer. Therefore, the number of frames to be filtered can be reduced as compared with the conventional post filter. Therefore, the time for driving the post filter can be reduced, and the power consumption in the post filter 2 can be reduced. In particular, when the display device is a liquid crystal display device having a high display frame rate, the effect becomes remarkable.

(Embodiment 2)
In the second embodiment, the filter coefficient determination unit in the post filter refers to the quantization granularity information and the motion vector information together with the result of the distortion detection unit, and individually selects the vertical filter coefficient set and the horizontal filter coefficient set. An image decoding apparatus will be described.

  Since the configuration other than the filter coefficient determination unit is substantially the same as the configuration of the image decoding apparatus according to the first embodiment, only those differences will be described.

  As shown in FIG. 13, the image decoding apparatus according to the second embodiment includes an input buffer 11, an inverse variable length coding (iVLD) unit 12, an inverse quantization unit 13, an inverse discrete cosine transform (iDCT) unit ( A decoding unit 1 comprising an inverse orthogonal transform unit) 14, a motion compensation prediction unit 15 and an adder 16, a post filter 2, a display frame region (display information storage unit) 3, and a local decoding reference frame region (for decoding) And a frame memory element 10 having an information storage unit 5 and an image output processing unit 4. 1 except that the inverse quantization unit 13 outputs quantization granularity information to the post filter 2 and the motion compensated prediction unit 15 outputs motion vector information to the post filter 2. It is the same configuration.

  As shown in FIG. 14, the quantization granularity information and the motion vector information are input to the encoder 52 in the filter coefficient determination unit of the post filter. The selector 53 refers to the quantization granularity information and the motion vector information together with the distortion detection result 1 and the distortion detection result 2, and registers the vertical filter coefficient set to be registered in the coefficient register in the vertical filter and the coefficient register in the horizontal filter unit. The horizontal filter coefficient set to be selected is selected individually. Depending on the quantization granularity information included in the quantization granularity information from the inverse quantization unit 12 and the motion vector length information (speed of motion) from the motion compensation prediction unit 15, a filter is used. Adjust the processing weight.

  For example, when the quantization granularity of the image to be decoded is large (rough), the decoded image is likely to be distorted. In order to make this distortion inconspicuous, a coefficient set that suppresses a high-frequency component that is a distortion component is selected when the quantization granularity is large. Conversely, if the quantization granularity is sufficiently small, a coefficient set that can perform more gentle filtering is selected. In a pixel block with a large motion (when the motion vector is large), distortion is likely to occur in the image due to the accuracy of motion compensation and the restriction on the amount of code that can be used for transmission. In order to make this distortion inconspicuous, a coefficient set that suppresses a distortion component larger than that of a pixel block with small motion is selected for a pixel block with large motion.

  The present invention can be used to reduce the capacity of a post filter line memory in an image decoding apparatus. The present invention can also be used to reduce power consumption in an image decoding apparatus.

FIG. 1 is a block diagram conceptually showing the configuration of the image decoding apparatus according to the first embodiment. FIG. 2 is an explanatory diagram for explaining information accumulated in a frame memory element of the image decoding apparatus according to Embodiment 1. FIG. 3 is a block diagram conceptually showing the structure of the post filter of the image decoding apparatus according to the first embodiment. FIG. 4 is a block diagram conceptually showing the structure of the distortion detector in the post filter of the image decoding apparatus according to Embodiment 1. FIG. 5 is a block diagram conceptually showing the configuration of the horizontal filter section in the post filter of the image decoding apparatus according to Embodiment 1. FIG. 6 is a block diagram illustrating a configuration of a filter coefficient determination unit in the post filter of the image decoding apparatus according to Embodiment 1. FIGS. 7A to 7I are explanatory diagrams for describing post-filter processing for the uppermost pixel block in the image decoding apparatus according to Embodiment 1. FIG. FIG. 8 is an explanatory diagram for explaining information accumulated in the pixel holding unit with respect to the uppermost pixel block in the image decoding apparatus according to the first embodiment. FIGS. 9A to 9I are explanatory diagrams for describing post-filter processing for the middle-stage pixel block in the image decoding apparatus according to Embodiment 1. FIG. FIG. 10 is an explanatory diagram for explaining information accumulated in the pixel holding unit for the middle-stage pixel block in the image decoding apparatus according to the first embodiment. FIGS. 11A to 11I are explanatory diagrams for describing post-filter processing for the lowermost pixel block in the image decoding apparatus according to the first embodiment. FIG. 12 is an explanatory diagram for explaining information accumulated in the pixel holding unit for the lowermost pixel block in the image decoding device according to the first embodiment. FIG. 13 is a block diagram conceptually showing the configuration of the image decoding apparatus according to the second embodiment. FIG. 14 is a block diagram illustrating a configuration of a filter coefficient determination unit in the post filter of the image decoding apparatus according to Embodiment 2. FIG. 15 is a block diagram conceptually showing the structure of a conventional typical image decoding apparatus. FIG. 16 is an explanatory diagram for explaining information stored in a frame memory of a conventional typical image decoding apparatus. FIG. 17 is a block diagram conceptually showing the structure of a post filter of a typical conventional image decoding apparatus. FIG. 18 is a block diagram conceptually showing the structure of the distortion detector in the post filter of a conventional typical image decoding apparatus. FIG. 19 is a block diagram conceptually showing the structure of a horizontal filter section in a post filter of a conventional typical image decoding apparatus. FIG. 20 is a block diagram illustrating a configuration of a filter coefficient determination unit in a post filter of a conventional typical image decoding apparatus. FIG. 21 is an explanatory diagram showing the arrangement of pixels inside a block in order to explain the operation of a conventional block distortion detector.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Decoding part 2 Post filter 3 Display frame area (Display information storage part)
4 Image output processing unit 5,105 Local decoding reference frame area (decoding information storage unit)
10 Frame memory element 11, 111 Input buffer 12, 112 Inverse variable length encoding unit 13, 113 Inverse quantization unit 14, 114 Inverse discrete cosine transform unit (inverse orthogonal transform unit)
15, 115 Motion compensation prediction unit 16,116 Adder circuit 21 Pixel holding unit 22 Switch element (information synthesis unit)
23,123 Distortion detection unit 24,134 Filter coefficient determination unit 25,125 Horizontal filter unit 26,126 Vertical filter unit 32,62,132 Coefficient register 33,63,133 Multiplication circuit 34,64,134 Addition circuit 35,65, 135 Shifter 41, 141 Subtraction circuit 42, 142 Absolute value conversion circuit 43, 143 Threshold register 44, 45, 144, 145 Comparison circuit 46, 146 Division circuit 47, 147 OR circuit 48, 148 Shift register 49, 149 Addition circuit 51 151 Coefficient table holding unit 52, 152 Encoder 53, 153 Selector

Claims (16)

A decoding unit that decodes the encoding information and generates decoding information in response to input of the encoding information of a decoding target pixel block including a plurality of pixels;
Pixels that hold at least part of information of a vertical pixel block that is adjacent to the decoding target pixel block in the vertical direction, and additionally hold the decoding information according to the input of the decoding information from the decoding unit A decoding unit that corrects the processing block information by filtering the processing block information including the decoding information and at least a part of the vertical pixel block information held in the pixel holding unit, and the decoding target Information on at least a part of pixel groups including a pixel group in the vicinity of a vertical boundary between the pixel block to be decoded and the vertical pixel block among pixel groups constituting at least a part of the pixel block and the vertical pixel block is a distortion correction pixel. A post filter having a vertical filter part to output as information;
A display information storage unit that holds the distortion correction pixel information output from the post filter,
Encoding information of a decoding target image frame composed of a plurality of pixel blocks is sequentially input to the decoding unit as the encoding information of the decoding target pixel block in units of pixel blocks, and the display information recording unit includes An image decoding apparatus in which display image frame information configured by the distortion correction pixel information output for each of the plurality of pixel blocks is held.   The image decoding device according to claim 1, wherein the pixel group in the vicinity of the vertical boundary includes a pixel constituting the decoding target pixel block and a pixel constituting at least a part of the vertical pixel block. Distortion detection in which the post filter detects inter-pixel block distortion between the decoding target pixel block and the vertical pixel block based on the decoding information of the decoding target pixel block and the information of the vertical pixel block And a filter coefficient determination unit that determines a vertical filter coefficient set according to the detection result of the inter-pixel block distortion in the distortion detection unit,
The image decoding device according to claim 1, wherein the vertical filter unit of the post filter filters the processing block information with reference to the vertical filter coefficient set. Based on the decoding information of the decoding target pixel block and information of a horizontal pixel block that is horizontally adjacent to the decoding target pixel block, the post filter is arranged between the decoding target pixel block and the horizontal pixel block. A distortion detection unit that detects inter-pixel block distortion; and a filter coefficient determination unit that determines a vertical filter coefficient set according to the detection result of the inter-pixel block distortion in the distortion detection unit;
The image decoding device according to claim 1, wherein the vertical filter unit of the post filter filters the processing block information with reference to the vertical filter coefficient set.   The post filter generates the processing block information by synthesizing the decoding information of the decoding target pixel block and the information of at least a part of the vertical pixel block held in the pixel holding unit, and the distortion detecting unit The image processing apparatus according to claim 3, further comprising an information synthesis unit that outputs to the vertical filter unit.   The image decoding apparatus according to claim 5, wherein the processing block information is information obtained by connecting the decoding target pixel block information and at least a part of information of the vertical pixel block held in the pixel holding unit. A decoding information storage unit that holds information of a reference image frame different from the decoding target image frame;
The encoding information of the decoding target pixel block includes encoded difference image information, quantization granularity information, and motion vector information,
The decoding unit inversely quantizes the encoded differential image information with reference to the quantization granularity information, and reverses the encoded differential image information inversely quantized by the inverse quantization unit. An inverse orthogonal transform unit that performs orthogonal transform to generate decoded difference image information, and a motion that generates predicted image information with reference to the motion vector information and information of the reference image frame held in the decoding information storage unit Based on the compensation prediction unit, the decoded differential image information and the predicted image information, the decoding information of the pixel block to be decoded is generated, and the decoding information is stored in the decoding information storage unit and the post filter. An adder for outputting,
The image decoding device according to claim 3 or 4, wherein the filter coefficient determination unit of the post filter determines the vertical filter coefficient set by further referring to at least one of the quantization granularity information and the motion vector information. The pixel holding unit further holds at least part of information of a horizontal pixel block horizontally adjacent to the decoding target pixel block;
The processing block information further includes information on at least a part of the horizontal pixel block held in the pixel holding unit,
The post-filter filters the processing block information, and the decoding target pixel block among the pixel group constituting the decoding target pixel block, at least a part of the vertical pixel block, and at least a part of the horizontal pixel block And a horizontal filter unit that corrects information of at least a part of pixel groups including a pixel group near a horizontal boundary between the horizontal pixel block and outputs the corrected processing block information to the vertical filter unit,
The vertical filter unit includes a pixel group in the vicinity of the vertical boundary and a pixel in the vicinity of the horizontal boundary among the pixel groups constituting the pixel block to be decoded, at least a part of the vertical pixel block, and at least a part of the horizontal pixel block. The image decoding device according to claim 1, wherein information on at least a part of pixel groups including the group is output.   The image decoding device according to claim 8, wherein the pixel group in the vicinity of the horizontal boundary includes a pixel constituting the decoding target pixel block and a pixel constituting at least a part of the horizontal pixel block.   The post filter includes the pixel block information to be decoded, information on at least part of the vertical pixel block held in the pixel holding unit, and information on at least part of the horizontal pixel block held in the pixel holding unit. The image processing apparatus according to claim 8, further comprising an information combining unit that generates the processing block information by combining the information and outputs the processing block information to the distortion detection unit. The reference pixel information held in the pixel holding unit is adjacent to the decoding target pixel block, the vertical pixel block, and the horizontal pixel block, and the decoding target pixel block, the vertical pixel block, and the horizontal pixel block Further comprising at least part of information of a diagonal pixel block different from
The processing block information further includes at least a part of the diagonal pixel block held in the pixel holding unit;
A horizontal filter unit of the post filter filters the processing block information to obtain at least a part of the pixel block to be decoded, at least a part of the vertical pixel block, at least a part of the horizontal pixel block, and at least a diagonal pixel block. Correcting information of at least some pixel groups including a pixel group near the horizontal boundary among pixel groups constituting a part,
The vertical filter unit includes a pixel group in the vicinity of the vertical boundary and a pixel in the vicinity of the horizontal boundary among the pixel groups constituting the pixel block to be decoded, at least a part of the vertical pixel block, and at least a part of the horizontal pixel block. The image decoding device according to claim 8, wherein information on at least a part of pixel groups including the group is output. The horizontal filter unit of the post filter filters the processing block information to obtain the decoding target pixel block, at least a part of the vertical pixel block, at least a part of the horizontal pixel block, and the diagonal pixel block. Information on at least a part of pixel groups including a pixel group near the horizontal boundary and a pixel group near the diagonal boundary between the pixel block to be decoded and the diagonal pixel block among at least a part of the pixel group is corrected. And
The vertical filter unit includes a pixel group in the vicinity of the vertical boundary and a pixel in the vicinity of the horizontal boundary among the pixel groups constituting the pixel block to be decoded, at least a part of the vertical pixel block, and at least a part of the horizontal pixel block. The image decoding device according to claim 11, wherein information on at least a part of pixel groups including a group and a pixel group near the diagonal boundary is output.   The post filter includes decoding information of the decoding target pixel block, information of at least a part of the vertical pixel block held in the pixel holding unit, and at least a part of the horizontal pixel block held in the pixel holding unit. And an information synthesis unit that generates the processing block information by synthesizing at least a part of the diagonal pixel blocks held in the pixel holding unit and outputs the processed block information to the distortion detection unit and the horizontal filter unit. The image processing apparatus according to claim 8, further comprising: Distortion detection in which the post filter detects inter-pixel block distortion between the decoding target pixel block and the vertical pixel block based on the decoding information of the decoding target pixel block and the information of the vertical pixel block A filter coefficient determination unit that determines a vertical filter coefficient set and a horizontal filter coefficient set according to a detection result of the inter-pixel block distortion in the distortion detection unit,
The vertical filter portion of the post filter performs filtering with reference to the vertical filter coefficient set;
The image decoding apparatus according to claim 8 or 11, wherein the horizontal filter unit of the post filter performs a filtering process with reference to the horizontal filter coefficient set. Distortion detection in which the post filter detects inter-pixel block distortion between the decoding target pixel block and the horizontal pixel block based on the decoding information of the decoding target pixel block and the information of the horizontal pixel block A filter coefficient determination unit that determines a vertical filter coefficient set and a horizontal filter coefficient set according to a detection result of the inter-pixel block distortion in the distortion detection unit,
The vertical filter portion of the post filter performs filtering with reference to the vertical filter coefficient set;
The image decoding apparatus according to claim 8 or 11, wherein the horizontal filter unit of the post filter performs a filtering process with reference to the horizontal filter coefficient set. A decoding information storage unit that holds information of a reference image frame different from the decoding target image frame;
The encoding information of the decoding target pixel block includes encoded difference image information, quantization granularity information, and motion vector information,
The decoding unit inversely quantizes the encoded differential image information with reference to the quantization granularity information, and reverses the encoded differential image information inversely quantized by the inverse quantization unit. An inverse orthogonal transform unit that performs orthogonal transform to generate decoded difference image information, and a motion that generates predicted image information with reference to the motion vector information and information of the reference image frame held in the decoding information storage unit Based on the compensation prediction unit, the decoded differential image information and the predicted image information, the decoding information of the pixel block to be decoded is generated, and the decoding information is stored in the decoding information storage unit and the post filter. An adder for outputting,
The filter coefficient determining unit of the post filter further determines the vertical filter coefficient set and the horizontal filter coefficient set by further referring to at least one of the quantization granularity information and the motion vector information. The image decoding device described.