JP2011249384A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device allows crystal defects in an element region to be suppressed and capable of readily improving the accuracy of dicing and breaking, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device comprises a principal surface and a side surface. The side surface comprises a substrate 10 that includes a side wall of a notch 12 provided from the principal surface side, and a laminate 20 that is provided on the principal surface, extends on the side wall of the notch, and is composed of InGaAlN (0≤x≤1 and 0≤y≤1). For this reason, crystal defects and voids that tend to concentratedly occur in the notch 12 are avoided, thereby forming a semiconductor device with low defect density in an element region AR of the laminate and high reliability.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Since nitride-based semiconductors have a wider band gap and higher electron saturation speed than GaAs, it is expected that their application to light-emitting elements, high-frequency elements, high-power switching elements, and the like will expand.

  For example, a light-emitting element using a nitride-based semiconductor can emit light in the ultraviolet to blue-violet wavelength range. For example, in a light emitting device equipped with phosphor particles that can absorb blue-violet light and emit wavelength-converted yellow light, white light and incandescent light bulb color light can be obtained as blue-violet light, yellow light, and mixed light Can do.

  A semiconductor element or a light emitting element in which a semiconductor laminate is provided on a sapphire substrate may not be broken in a direction perpendicular to the main surface of the sapphire substrate, but may be broken obliquely or bent in the separation process into chips. When sapphire, which is a hexagonal crystal, is scribed in a direction different from the crystal direction, cracks and chips are particularly likely to occur in the chip. For this reason, there is a problem that the chip yield of the semiconductor element is lowered.

JP 2004-296703 A

  Provided are a semiconductor element in which crystal defects in an element region are suppressed and the accuracy of dicing and breaking can be easily increased, and a method for manufacturing the same.

According to the embodiment, the substrate has a main surface and a side surface, and the side surface includes a side wall of a cutout portion provided from the main surface side, and the side wall of the cutout portion provided on the main surface. There is provided a semiconductor element including a stacked body that extends upward and is made of In _x Ga _y Al _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1).

1 is a schematic cross-sectional view of a semiconductor element according to a first embodiment. 2A to 2C are process cross-sectional views up to formation of a laminate in the manufacturing method of the first embodiment. 3A and 3B are process cross-sectional views up to chip separation. It is a schematic cross section of the light emitting element concerning a 2nd embodiment. FIGS. 5A to 5C are process cross-sectional views up to the formation of the laminate in the manufacturing method of the second embodiment. It is a model top view of the board | substrate before crystal growth. 7A and 7B are process cross-sectional views up to chip separation. It is a schematic plan view of the wafer before a scribe process. It is a schematic cross section of the light emitting element concerning the modification of 2nd Embodiment. 10A to 10C are schematic views of light emitting elements according to comparative examples. It is a schematic cross section of a 3rd embodiment. 12A to 12C are process cross-sectional views up to the formation of the stacked body in the method for manufacturing the light emitting device according to the third embodiment. It is a model top view of the board | substrate before crystal growth. 14A and 14B are process cross-sectional views up to chip separation.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and FIGS. 1B to 1D are schematic cross-sectional views of a notch provided in a substrate.
A cutout portion 12 having a predetermined depth D1 is provided from the main surface 10a side of the substrate 10. A laminated body 20 made of InGaAlN is provided on at least a part of the surface of the notch 12 and the main surface 10 a of the substrate 10. For example, the thickness of the substrate 10 after polishing can be set to 100 μm, the predetermined depth D1 can be set to 10 μm, and the like. For example, D1 is larger than D2, and the inclination angle θ _N between the side wall 12a of the notch 12 and the main surface 10a of the substrate 10 is, for example, in the range of 90 to 135 degrees (90 ° ≦ θ _N ≦ 135 °). In this case, since the raw material supplied to the side wall 12a of the notch portion 12 is smaller than the flat portion per unit area, it is more preferable because the film thickness can be reduced.

Note that in this specification, “InGaAlN” is an element which is represented by a composition formula of In _x Ga _y Al _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) and serves as an acceptor or a donor. May be included.

  The cross section of the notch 12 has a structure including an inclined side wall 12a and a bottom surface as shown in FIG. 1B, a structure including a vertical side wall 12a and a bottom surface as shown in FIG. 1C, and FIG. A structure that hardly includes the bottom surface, as in FIG. The substrate 10 can be sapphire, GaN, SiC, or the like.

As described above, the stacked body 20 made of InGaAlN is provided across at least the side wall 12a of the cutout portion 12 and the main surface 10a. In this case, the plane orientation of the main surface 10a of the substrate 10 is selected so that the characteristics of the semiconductor element have desired characteristics. However, the side wall 10a of the notch 12 has an inclined angle theta _N to the major surface 10a. For this reason, the stacked body 20 of the scribe region SR represented by a broken line is likely to be disturbed in crystallinity. Due to the disorder of crystallinity, the vicinity of the notch portion 12 has crystal defects including voids, interstitial atoms such as point defects, dislocations, stacking defects accompanied by dislocations, or voids from the flat portion. Is also likely to occur. For this reason, the stacked body 20 in this region tends to include a polycrystalline region.

  Crystal defects and voids are likely to be concentrated in the notch 12 but are prevented from spreading to the element region AR on the flat main surface 10a of the stacked body 20. As a result, the crystal defect density of the stacked body 20 on the element region AR is the same as the crystal defect density of the stacked body on the flat surface of the wafer having no step such as a notch, Or it can be made lower. For this reason, it becomes easy to obtain a highly reliable semiconductor element.

  The crystal defect density due to dislocation can be measured, for example, by etching the crystal surface and observing the generated etch pits using a scanning electron microscope (SEM) or the like.

  When the semiconductor element is a diode, the first electrode 31 is formed on the first conductive type layer of the stacked body 20, the first pad electrode 32 is formed thereon, the second electrode 40 is formed on the second conductive type layer, and the second electrode 40 is formed thereon. Two pad electrodes 42 are provided. In the case where the semiconductor element is an FET (Field Effect Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or a transistor, a third electrode, a third pad electrode, or the like is further provided.

2A to 2C are process cross-sectional views up to the formation of the stacked body in the semiconductor element manufacturing method according to the first embodiment. As shown in FIG. 2A, a mask material such as SiO ₂ is formed on the substrate 10, and a photoresist film 49 is patterned on the mask material 52. When the mask material 52 is etched, a part of the main surface 10a of the substrate 10 serving as the scribe region SR is exposed. In this case, an alignment mark is provided in the area to be the scribe area SR.

  As shown in FIG. 2B, after removing the photoresist film 49, a recess (groove) 10b having a width of 10 μm and a depth D1 of 10 μm is formed from the main surface 10a side of the substrate 10 using the mask material 52 as a mask. The mask material 52 is removed by forming using RIE (Reactive Ion Etching) or the like. In this way, the groove 10b extending in the first direction is formed. The groove 10b is also formed in a second direction that intersects the first direction. It is also possible to perform RIE using the photoresist film as a mask. In addition, since the roughness of the groove 10b is worse than that of the flatness by RIE processing, polycrystallization is promoted. The roughness of the groove 10b can be formed by partially changing the RIE conditions, controlling the deposits, or by adding an additional wet process. The effect can be promoted by roughening so that the roughness is 10 times or more that of the flat portion.

  Subsequently, as shown in FIG. 2C, the stacked body 20 is crystal-grown on the main surface 10a of the substrate 10 by using, for example, the MOCVD (Metal Organic Chemical Vapor Deposition) method or the MBE (Molecular Beam Epitaxy) method. In this case, if crystal growth is performed so as to leave a dent above the stacked body 20 extending in the groove 10b, crystal defects can be concentrated in the groove 10b. On the other hand, crystal defects are suppressed on the flat main surface. That is, in this manufacturing method, it becomes easy to concentrate the crystal defects near the scribe region SR and reduce the spread of the crystal defects to the flat element region AR. Such an effect is referred to as a “gettering effect”. The plane orientation of the main surface 10a can have an inclination angle in the range of 0 ± 15 degrees from the (0001) plane. Further, it may be a (11-22) plane or a (1-100) plane. Further, the recess 10b can be made to contain voids by increasing the crystal growth conditions and the aspect ratio of the recess 10b, but the effect is not changed. In this way, by changing the morphological difference, crystal plane difference, and flatness difference between the flat portion and the concave portion 10b depending on the element size, the crystal growth mode is locally changed, and the resulting crystal morphology (In segregation) , Polycrystallization, increase in roughness, etc.) and properties (breaking strength, color, transmittance, low efficiency, etc.) can be changed.

3A and 3B are process cross-sectional views up to chip separation.
The first electrode 31 and the first pad electrode 32 are formed on the first electrode 31, respectively. An alignment mark is used for this patterning. The groove portion 10b with many crystal defects appears black in a high-power microscope, so that pattern recognition is easy. As a result, since the peripheral portion of the completed element is black, the image recognition accuracy at the appearance inspection of the chip is improved, and the defective chip can be accurately removed.

  Further, the second electrode 40 and the second pad electrode 42 are formed. Subsequently, when the substrate 10 is polished to a predetermined thickness, it becomes as shown in FIG. The thickness of the substrate 10 after polishing can be set to 100 to 150 μm, for example. Furthermore, it is separated into individual chips by diamond dicing and braking processes. If a YAG laser device is used and the lower portion of the groove 10b is a laser irradiation region 10f, a dicing line can be reliably formed with the laser irradiation region 10f as a starting point. Further, when a blade 56 having a sharp tip is brought into contact with the center line of the scribe region SR from the back side of the substrate 10 and a load is applied to the wafer, the groove 10b is separated as two notches 12 shown in FIG. The groove width of the scribe region SR can be more reliably divided by making the groove width along the direction intersecting the crystal orientation direction wider than the groove width along the crystal orientation direction. The first direction can be a direction parallel to, for example, <1-100> or <11-20>. Further, the width of the notch 12 is half of the groove width.

  Although InAlGaN is a hard material, there are many crystal defects in the notch 12, and the thermal stress of the stacked body 20 in the crystal growth process is relaxed after growth. For this reason, the curvature of the board | substrate 10 is reduced. Further, the notch 12 including the polycrystalline region can be easily scribed, and can reduce the cracks and chipping of the laminate 20 made of hexagonal InGaAlN. On the other hand, due to the notch 12 provided in the substrate 10, the stress generated in the dicing or braking process can be concentrated in the vicinity of the groove 10b. For this reason, even if it is a hexagonal system material which consists of sapphire, SiC, GaN, etc. and is a hard substrate, it becomes possible to scribe reliably. That is, cracks and chipping of the substrate are reduced, and the accuracy of dicing and braking is improved. For this reason, for example, the width of the scribe region can be 10 μm or less. As a result, the yield of chips can be increased.

FIG. 4 is a schematic cross-sectional view of a light emitting device according to the second embodiment.
The substrate 10 is sapphire, and the laminate 20 includes an n-type layer 23, a light emitting layer 22, and a p-type layer 21 from the substrate 10 side. A p-side electrode 30 made of a transparent conductive film such as ITO (Indium Tin Oxide) is provided on the upper surface of the p-type layer 21, and a p-side pad electrode 32 is further provided thereon. Further, the stacked body 20 is etched away from above until a part of the n-type layer 23 is exposed, and an n-side electrode 40 and an n-side pad electrode 42 are provided. As a result, the injection current spreads in the p-side electrode 30 and holes are injected into the light emitting layer 22. On the other hand, injected electrons from the n-side electrode 40 are injected into the light emitting layer 22 to cause light emission recombination. In this case, the light emitting layer 22 in which crystal defects are reduced by the “gettering effect” can maintain high reliability. The conductivity type is not limited to this, and each may be an opposite conductivity type.

FIGS. 5A to 5C are process cross-sectional views up to the formation of a stacked body in the method for manufacturing a light emitting device according to the second embodiment.
As shown in FIG. 5A, for example, a dot pattern of a photoresist film 50 having a diameter W1 of 3 μm is formed. Using the photoresist film 50 with a dot pattern as a mask, the substrate 10 is etched away from the surface side using RIE so that the height T1 of the dot 10d is 1 μm. In this case, the main surface 10a of the substrate 10 has a surface of the dot 10d having a height T1 and a bottom surface surrounding the periphery of the dot 10d. The dot pattern is not formed in the scribe area. A first alignment mark is formed in the scribe region.

Subsequently, after forming a mask material 52 made of SiO ₂ or the like on the whole, as shown in FIG. 5B, the element region AR provided with the dots 10d is covered, and the width W _SR1 of the scribe region _SR1 is 10 μm. A pattern of the photoresist film 50 is formed so as to be an opening. In this case, the first alignment mark is used to superimpose the pattern, and the second alignment mark is formed in the scribe area.

The SiO _{2 in} the opening of the region to be a scribe region is removed using a solution etching method or the like, and the photoresist film 50 is further removed. Using the mask material 52 as a mask, a groove 10b having a width _WSR1 of 10 μm and a depth D1 of 10 μm can be formed on the main surface 10a of the substrate 10 using RIE (Reactive Ion Etching) or the like. It is also possible to perform RIE using the photoresist film as a mask. In this case, the depth of the groove 10b is formed larger than the height of the dot 10d.

  Subsequently, as shown in FIG. 5C, the stacked body 20 made of InGaAlN is crystal-grown on the substrate 10 on which the dots 10d and the grooves 10b are formed by using, for example, the MOCVD method or the MBE method. In this case, if crystal growth is performed so as to leave the groove-shaped recess 20a, crystal defects can be concentrated on the groove 10b. Further, the upper side of the dot 10d having a height T1 of 1 μm can be made flat.

FIG. 6 is a schematic plan view of the substrate before the stacked body is formed.
The dots 10d are provided in the element region AR and are not provided in the scribe regions SR1 and SR2. The widths of the scribe regions SR1 and SR2 may be more reliably divided if the width _WSR1 along the direction intersecting the first direction is wider than the width _WSR2 along the first direction. The shape of the dot 10d is preferably formed so as to reflect the light emitted from the light emitting layer 22 and increase the light extraction efficiency above.

7A and 7B are process cross-sectional views up to chip separation.
As shown in FIG. 7A, a first (p-side) electrode 30 made of ITO and a first (p-side) pad electrode 32 are formed thereon. If the second alignment mark is also used for this patterning, the alignment accuracy can be increased. Since the stacked body 20 on the groove 10b has many crystal defects, the second alignment mark becomes black when viewed with a high-power microscope, and the pattern can be easily recognized.

  Further, a second (n-side) electrode 40, a second (n-side) pad electrode 42, and a p-side pad electrode 32 are formed. Subsequently, the substrate 10 is polished to a predetermined thickness, further subjected to a diamond or laser dicing process, and separated into individual chips by a breaking process.

FIG. 8 is a partial schematic plan view of the wafer before the scribing process.
The element region AR sandwiched between the scribe region SR1 and the scribe region SR2 orthogonal to the scribe region SR1 is separated into individual chips by a dicing and braking process.

FIG. 9 is a schematic cross-sectional view of a modified example of the second embodiment.
After the electrode process, even if the stacked body on the side wall 12a of the notch 12 is removed, the crystal defects in the element region AR do not increase, so that the reliability can be kept high.

FIGS. 10A to 10C are schematic views of light-emitting elements according to comparative examples.
As shown in FIG. 10A, the periphery of the dot portion 110d formed using the photoresist film 150 as a mask is surrounded by a bottom surface having a depth of 1 μm. The dot portions 110d are uniformly formed on the surface of the substrate 110 including the scribe region SR10. A stacked body 120 made of InGaAlN is formed on the surface having the dot portion 110d by using the MOCVD method or the MBE method. A p-side electrode 130 made of ITO is formed on the p-type layer 121, and a p-side pad electrode 132 is further formed thereon. On the other hand, an n-side electrode 140 is formed on the n-type layer 123 where the stacked body 120 is exposed using an etching method, and an n-side pad electrode 142 is formed thereon.

  In the case of the comparative example in which the groove portion is not provided in the substrate 110, the thermal expansion coefficient differs between the substrate 110 and the stacked body 120, so that the substrate 110 after crystal growth is warped. The warp increases as the aperture of the substrate 110 increases. For example, in a substrate having a diameter of 100 mm, the warpage may be 100 μm. Such warpage tends to cause cracks or chipping in the wafer transfer process or pattern abnormality in the exposure process. Further, in the dicing or breaking process, the substrate may not be cracked in the direction perpendicular to the substrate but may be cracked in the bent direction as shown in FIG. This reduces chip yield. In particular, chip breakage tends to increase when dividing into a different orientation from the crystal direction. In the comparative example, when the width of the scribe region is smaller than 30 μm, the chip yield is further reduced.

  Further, as shown in the schematic plan view of FIG. 10C, since no groove is provided on the main surface side of the substrate 110, the getter effect is insufficient, and it is difficult to reduce crystal defects in the element region AR10. .

FIG. 11A is a schematic cross-sectional view of a light emitting device according to the third embodiment, and FIG. 11B is a side view thereof.
The scribe region is constituted by a recess 10e provided in the substrate 10 instead of the groove. That is, as shown in the side view of FIG. 11B, the laminated body 20 is provided inside the recessed portion 10e divided on the plane including the center line of the recessed portion 10e. Further, since the polycrystalline region 20p is formed in the vicinity of the center line, it is easy to concentrate crystal defects, and the gettering effect can be enhanced. Further, when the stacked body 20 is divided along the direction in which the polycrystalline regions 20p are arranged, the stacked body 20 can be surely divided and the yield of chips can be increased.

12A to 12C are schematic cross-sectional views of a method for manufacturing a light emitting device according to the third embodiment.
As shown in FIG. 12A, a dot pattern of a photoresist film 50 having a diameter of 3 μm is formed. Using the photoresist film 50 having a dot pattern as a mask, the surface of the substrate 10 is removed by RIE so that the height T1 of the dot 10d is 1 μm. In this case, the dot pattern is not formed in the scribe region SR3, but the first alignment mark is formed.

A pattern is formed on the photoresist film 50 covering the element region AR and provided with a recess 10e having a width _WSR3 of 6 μm along the scribe region SR3. The shape of the recess 10e is not limited, and may be a circle or an ellipse. In this case, the first alignment mark is used to superimpose the pattern, and the second alignment mark is formed in the scribe region SR3.

As shown in FIG. 12B, a mask material such as SiO ₂ is etched using this photoresist film as a mask. Further, when RIE is performed until the substrate 10 has a depth of 10 μm, a concave portion 10e having a U-shaped or V-shaped cross section can be formed along the scribe region SR3. Thereafter, SiO ₂ is removed. The substrate 10 can also be etched using the photoresist film as a mask.

  As shown in FIG. 12C, the stacked body 20 made of InGaAlN is crystal-grown on the substrate 10 on which the dots 10d and the recesses 10e are formed using, for example, the MOCVD method or the MBE method. In this case, crystal defects are likely to occur in the stacked body 20 grown in the recess 10e. In particular, the vicinity of the center line of the recess 10e tends to be the polycrystalline region 20p. On the other hand, the upper portion of the dot portion 10d having a height T1 of 1 μm can be made flat.

FIG. 13 is a schematic plan view of the substrate 10 before the stacked body is formed.
A recess 10e is provided along the scribe regions SR3 and SR4. In this case, scribing may be facilitated if the width W _SR3 of the recess 10e along the direction intersecting the first direction is larger than the width W _{SR4 of the} recess 10e along the first direction. The shape of the recess 10e is not limited, and may be a circle or an ellipse.

14A and 14B are process cross-sectional views up to chip separation.
As shown in FIG. 14A, a p-side electrode 30 made of ITO and a p-side pad electrode 32 are formed thereon. If the second alignment mark is also used for this patterning, the alignment accuracy can be increased. Since the recess 10e has many crystal defects, the second alignment mark becomes black when viewed with a high-power microscope, and recognition is easy. In addition, the convex portion may be in a state containing voids depending on the crystal growth conditions, but it remains effective for recognition and separation.

  Further, an n-side electrode 40, an n-side pad electrode 42, and a p-side pad electrode 32 are formed. Subsequently, the substrate 10 is polished to a predetermined thickness, further subjected to diamond dicing or laser dicing, and separated into individual chips by braking.

  As described above, in the semiconductor elements according to the first to third embodiments and the modifications associated therewith, the crystal defect density of the InGaAlN-based stacked body on the recess provided in the scribe region of the substrate is the stacked body of the device region. Higher than the crystal defect density. That is, in the semiconductor element of this embodiment, the crystal defects can be concentrated in the vicinity of the scribe region, and the cause of the crystal defects spreading to the element region can be suppressed. For this reason, the crystal quality is improved in the element region, and it becomes easy to improve the reliability.

  Further, in the method of manufacturing a semiconductor device according to the present embodiment, the InGaAlN-based stacked body in the scribe region has many crystal defects such as having a polycrystalline region, so that the stacked body can be diced and braked with high accuracy. In addition, in the dicing and braking processes, stress tends to concentrate on the recesses provided on the substrate, and it becomes easy to further improve the accuracy of dicing and braking.

  Such an InGaAlN-based semiconductor has a wider band gap and a higher electron saturation speed than GaAs, and thus can be applied to light-emitting elements, high-frequency elements, high-power switching elements, and the like.

  The embodiments of the present invention have been described above with reference to the drawings. However, the present invention is not limited to these embodiments. Even if those skilled in the art have made various design changes with respect to the substrate, notch portion, laminate, InAlGaN-based semiconductor, groove portion, scribe region, element region, electrode, transparent conductive film, etc. constituting the present invention, Unless it deviates from the main point of this invention, it is included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 10 Substrate, 10a Main surface, 10b Concave (groove) part, 10d Convex part, 10e Concave part 12 Notch part, 12a Side wall, 20 Laminated body, 20p Polycrystalline region, 22 Light emitting layer, AR element region, SR, SR1, SR2 , SR3, SR4 Scribe area, θ _N inclination angle

Claims (9)

A substrate having a main surface and a side surface, the side surface including a side wall of a notch provided from the main surface side;
A laminated body provided on the main surface, extending on the side wall of the notch, and made of In _x Ga _y Al _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1); ,
A semiconductor device comprising: The notch includes a first notch extending in a first direction and a second notch extending in a second direction intersecting the first direction,
The semiconductor element according to claim 1, wherein the first direction is parallel to <1-100> or <11-20>. The substrate is made of any one of sapphire, SiC, and GaN,
The main surface of the substrate is provided with a convex portion having a height smaller than the depth of the notch,
The semiconductor device according to claim 1, wherein the stacked body includes a light emitting layer, and a surface of the stacked body on a side opposite to the substrate side is flat. The main surface has a non-formation region of the convex portion,
The semiconductor device according to claim 3, wherein the side wall is provided in the non-formation region.   The semiconductor element according to claim 1, wherein a crystal defect density on the side wall is higher than a crystal defect density on the main surface.   6. The semiconductor device according to claim 1, wherein an inclination angle between the main surface and the side wall is in a range of 90 degrees or more and 135 degrees or less.   The semiconductor device according to claim 1, wherein the stacked body extends on a bottom surface of the cutout portion. Forming a recess having a predetermined depth from the main surface side of the substrate;
A step of crystal-growing the laminate so as to cover the concave portion and the main surface, which is made of In _x Ga _y Al _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1);
Dicing and braking the laminate and the substrate along the recess;
A method for manufacturing a semiconductor device, comprising: The step of forming the concave portion includes a step of forming a first concave portion extending in a first direction and a second concave portion extending in a second direction intersecting the first direction. ,
9. The method of manufacturing a semiconductor device according to claim 8, wherein the first direction is parallel to <1-100> or <11-20>.

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