JP2011233216A - Data transmitting/receiving device and method for semiconductor systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fast operating data transmitting/receiving device and method for semiconductor systems permitting, even during data transmission or reception, sampling of all data within the effective window thereof by tracking an internal clock with a stroboscopic signal, thereby enabling the reliability of data transmission to be enhanced.SOLUTION: A semiconductor memory device comprises a stroboscopic signal receiver 220 that receives inputting of a stroboscopic signal and generates a tracking clock, a clock receiver 240 that receives inputting of a clock and generates an internal clock, a plurality of data receivers 200_0 that receive inputting of parallel data correspondingly to the internal clock and generate internal data, and a phase controller 260 that tracks the internal clock according to a tracking clock and adjusts the phase of the internal clock, in order to compensate for phase fluctuations of the internal clock during data transmission or reception.

Description

  The present invention relates to an apparatus and method for data transmission / reception in a semiconductor system, and more particularly to an apparatus and method for performing data transmission / reception at high speed with a parallel-link transceiver of a semiconductor memory device.

  In a system composed of a plurality of semiconductor memory devices, the semiconductor memory device is for storing data. When a memory controller, for example, a central processing unit (CPU) or the like attempts to input data, the semiconductor memory device receives a clock input from the memory controller together with the data, and writes the data to the corresponding memory cell in synchronization with the clock.

  FIG. 1 is a block diagram showing a conventional semiconductor memory device and a memory controller that controls the semiconductor memory device. Specifically, FIG. 1 shows a semiconductor memory device for graphic work and a graphic processing device (GRAPHIC PROCESS UNIT, GPU) for professionally processing image data.

  As shown in FIG. 1, the transmission end of the graphic processing unit GPU transmits a plurality of data DQ together with a clock CLK to the semiconductor memory device.

  At the receiving end of the semiconductor memory device, data input from the outside is converted into internal data DIN by various control circuits that transmit the data to the unit cell, and the clock is converted into the internal clock ICLK through the internal clock control circuit. Used.

  At this time, a circuit that transmits a clock (for example, a PLL (PHASE LOCKED LOOP), a clock distributor, or a local router) has a longer delay time than a circuit that transmits data. Therefore, as illustrated, the clock CLK output from the transmission end of the graphics processing unit GPU is designed to have a rising edge when data is output, and the internal clock ICLK used at the reception end of the semiconductor memory device. Is designed to have a rising edge in the center of the effective window of data.

  However, in a system operating at high speed, it is inevitable that the effective window of data becomes gradually smaller. Therefore, as the data existing in the channel between the semiconductor memory device and the graphic processing device increases, the data operation time and the clock transition time do not coincide with each other, and erroneous data may be input. End up.

  In order to solve this problem, recent semiconductor memory devices and graphics processing unit GPUs can transmit data between them at high speed by using data training. Here, the data training is a skew between data using a data pattern promised in advance between the graphic control unit GPU and the semiconductor memory device in order to stably transmit data for read and write operations. This is a technique for adjusting (skew).

  The recently proposed semiconductor memory device for graphic work is designed to transmit data at a speed of 4 Gbps or higher. In order to ensure the reliability of such high-speed operation, the semiconductor memory device for graphic work is used for data training. Is defined as part of the specification.

  FIG. 2 is a block diagram for explaining data training used in a parallel-link of a conventional semiconductor system. Hereinafter, input / output of data between the memory controller 10 of the semiconductor system and the semiconductor memory device 30 will be described.

  As shown in FIG. 2, the memory controller 10 of the semiconductor system includes a plurality of transmission units (10_0 to 10_N−1) and a first clock generation unit 20.

  The plurality of transmission units (10_0 to 10_N-1) are provided for the number of parallel data DQ <0: N-1> and transmit corresponding parallel data DQ <0: N-1>.

  Each transmission unit includes a transmitter 12 (TX) and a phase interpolator 14 (Phase Interpolator, PI). The transmitter 12 transmits corresponding data to the semiconductor memory device 30. The phase interpolator 14 adjusts the output time point of the data output from the transmitter 12, that is, the phase of the data, according to the multiple phase clock signal PLL_CLK <0: M> and the phase control signal PI_CTRL <0: N-1>. Training clock TCLK <0: N-1> to be generated. Here, the phase control signal PI_CTRL <0: N-1> is a signal generated according to data training.

  The first clock generation unit 20 generates a multiple phase clock signal PLL_CLK <0: M> in response to the reference clock signal CLK_REF and supplies it to the transmission units (10_0 to 10_N−1). The first clock generator 20 generates a clock CLK transmitted to the semiconductor memory device 30 in response to the reference clock signal CLK_REF. The transmitter 22 further buffers and outputs the clock CLK output from the first clock generator 20.

  The memory controller 10 further includes a receiver 24 and a PI control signal generation unit 26 in order to generate the phase control signal PI_CTRL <0: N-1> according to the data training. The receiver 24 receives the training result input from the semiconductor memory device 30. The PI control signal generation unit 26 generates a phase control signal PI_CTRL <0: N-1> according to the received training result.

  On the other hand, the semiconductor memory device 30 includes a plurality of reception units (30_0 to 30_N−1), a second clock generation unit 40, and a clock distribution unit 42.

  A plurality of receiving units (30_0 to 30_N-1) are provided for the number of parallel data DQ <0: N-1>, and receive the corresponding parallel data DQ <0: N-1> to receive internal data DIN. <0: N-1> is generated.

  Each receiving unit includes a receiver 32 (RX), a sample holder 34 (S / H), and a local router 36. The receiver 32 receives data input from the transmission unit (10_0 to 10_N−1) of the memory controller 10. The sample holder 34 samples the output of the receiver 32 in response to the internal clock ICLK. The local router 36 routes the input internal clock ICLK and provides it to the sample holder 34.

  The second clock generation unit 40 receives the clock CLK and generates an internal clock ICLK. The front end of the second clock generator 40 is further provided with a receiver 44 that receives the clock CLK input from the memory controller 10.

  The clock distributor 42 distributes the internal clock ICLK output from the second clock generator 40 and provides it to the local router 36 in each receiver.

  The semiconductor memory device 30 further includes a data training unit 50 for performing data training.

  The data training unit 50 includes a register 52, a serializer 54, and a transmitter 56. The register 52 receives and stores the internal data DIN <0: N-1> output from the plurality of receiving units (30_0 to 30_N-1). The serializer 54 serializes and outputs the parallel internal data DIN <0: N−1> stored in the register. The transmitter 56 outputs the output of the serializer 54 to the receiver 24 of the memory controller 10.

  Hereinafter, data training between the memory controller 10 and the semiconductor memory device 30 will be described with reference to the above configuration. For reference, data training can be performed before an input / output operation of data when an independent command is input. Hereinafter, a certain period before an independent command is input and data input / output operation is performed is referred to as an “initial period”.

  Each phase interpolator 14 in the plurality of transmission units (10_0 to 10_N−1) of the memory controller 10 is initialized in an initial period before data is input / output by the input command. Therefore, the plurality of transmission units (10_0 to 10_N−1) transmit the parallel data DQ <0: N−1> and the clock CLK to the semiconductor memory device 30 without phase adjustment by the phase interpolator 14.

  The semiconductor memory device 30 generates an internal clock ICLK according to the clock CLK, receives parallel data DQ <0: N-1> according to the internal clock ICLK, and generates internal data DIN <0: N-1>. To do. The data training unit 50 receives this feedback, serializes it, and transmits it to the memory controller 10.

  Again, the PI control signal generation unit 26 of the memory controller 10 receives the input of the serialized data, generates the phase control signal PI_CTRL <0: N-1>, and in each transmission unit (10_0 to 10_N-1). The phase interpolator 14 generates the training clock TCLK <0: N-1> in response to the phase control signal PI_CTRL <0: N-1>, and outputs the data output from the transmission units (10_0 to 10_N-1). Adjust the phase.

  Through the above data training process, the rising edge of the internal clock ICLK of the semiconductor memory device 30 is positioned at the center in the effective window of the internal data DIN <0: N−1>. During the data transmission / reception period, the semiconductor memory device 30 can normally transmit / receive data to / from the memory controller 10 by sampling data at the center of the effective window of data according to the internal clock ICLK.

  However, since the conventional data training is performed only during the initial period, if a delay is generated by the internal control circuit during transmission / reception of data, this cannot be compensated. Therefore, the transition point of the internal clock falls outside the data valid window, and an incorrect data value is sampled.

  In particular, when temperature, power supply voltage, etc. fluctuate during operation, a clock having a different path from data may have a different delay value. For this reason, the sampling timing of the semiconductor memory device 30 changes and deviates from the center of the effective data window. As the operating frequency of the semiconductor memory device increases, the above phenomenon occurs more frequently and the semiconductor memory device malfunctions more frequently.

  Also, the clock frequency must increase as the data transmission rate increases. For example, in a semiconductor memory device in which the data transmission speed is Gb / s (giga bit / sec) or higher, the clock frequency must be higher than GHz (giga hertz). However, in this case, it is difficult to distribute the clock on the chip, and it is also difficult to determine the data. Therefore, there is a need for a method for efficiently transmitting and receiving data and clocks without error.

  The present invention is to improve the transmission / reception method of a semiconductor memory device, and even during data transmission / reception, the internal clock is tracked according to the strobe signal, and all data is sampled within the range of the effective window. A data transmission / reception apparatus and method for a semiconductor system capable of improving the reliability of data transmission of a semiconductor memory device operating in a semiconductor memory.

  In addition, the present invention enables the receiving end of the semiconductor memory device to sample data at the center of the data effective window even if the timing of the internal clock of the semiconductor memory device changes due to a change in power supply voltage and a temperature change that occur during operation. A data transmission / reception apparatus and method for a semiconductor system are proposed.

  In addition, the present invention provides a strobe signal training circuit inside a semiconductor memory device with a minimum number of circuits, which can efficiently transmit / receive strobe signals without error, and a highly integrated semiconductor. The present invention proposes a data transmission / reception apparatus and method for a semiconductor system that can satisfy a small area required in an electronic apparatus and system and can be easily changed in design.

  In order to achieve the above technical problem, a semiconductor memory device according to an embodiment of the present invention includes a strobe signal receiving unit that receives a strobe signal and generates a tracking clock, and generates an internal clock that receives the clock. In order to compensate for fluctuations in the phase of the internal clock during data reception, a clock receiving unit that performs parallel data input according to the internal clock, and a plurality of data receiving units that generate internal data. And a phase control unit that adjusts the phase of the internal clock by tracking the tracking clock.

  Preferably, the phase control unit tracks the internal clock with reference to the tracking clock and outputs an internal clock control signal according to the result, and the internal clock according to the internal clock control signal. A phase adjustment unit that adjusts the phase of.

  Preferably, the tracking unit can receive feedback of an internal clock input to a specific data receiving unit among the plurality of data receiving units. Preferably, the specific data receiving unit may be located physically closest to the strobe signal receiving unit among the plurality of data receiving units.

  Further, in a semiconductor system including a first semiconductor chip and a second semiconductor chip for transmitting and receiving data according to another embodiment of the present invention, the first semiconductor chip has a plurality of data for outputting a plurality of parallel data. A strobe signal receiving unit that includes a transmitting unit, a clock transmitting unit that outputs a clock, and a strobe signal transmitting unit that outputs a strobe signal, wherein the second semiconductor chip receives the strobe signal and generates a tracking clock A clock receiving unit that receives an input of the clock and generates an internal clock; a plurality of data receiving units that receive an input of the parallel data and generate internal data according to the internal clock; and tracking the tracking clock And a phase controller for adjusting the phase of the internal clock.

  Further, in a method for transmitting / receiving data between a first semiconductor chip and a second semiconductor chip according to still another embodiment of the present invention, a plurality of parallel data, a clock, and a strobe signal are transmitted from the first semiconductor chip. Transmitting to the second semiconductor chip; receiving a strobe signal; generating a tracking clock; receiving the clock; generating an internal clock; and the parallel data according to the internal clock And generating the internal data, and tracking the tracking clock to adjust the phase of the internal clock.

  As described above, the present invention tracks the internal clock according to the strobe signal during data transmission / reception and samples all data within the effective window range, thereby enabling data transmission in a semiconductor memory device operating at high speed. There is an effect that reliability can be improved.

  In addition, the present invention enables the receiving end of the semiconductor memory device to sample data at the center of the data effective window even if the timing of the internal clock of the semiconductor memory device changes due to a change in power supply voltage and a temperature change that occur during operation. There is an effect that can be done.

  In addition, the present invention is capable of efficiently transmitting / receiving strobe signals without error without separately providing a strobe signal training circuit inside the semiconductor memory device, so that the semiconductor device can be highly integrated and of course operated at all times. This has the effect of reducing power consumption.

It is a block diagram which shows schematic structure of the conventional semiconductor memory device and the memory controller which controls it. It is a block diagram for demonstrating the data training used by the parallel-link of the conventional semiconductor system. It is a block diagram for demonstrating the data transmitter / receiver of the semiconductor system which concerns on 1st Embodiment of this invention. FIG. 3 is a timing diagram for explaining a data transmission / reception method of the semiconductor system according to the first embodiment of the present invention. It is a block diagram for demonstrating the data transmitter / receiver of the semiconductor system which concerns on 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments introduced below are provided as examples to fully convey the technical idea of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below, and may be embodied in other forms. Note that the same reference numerals denote the same components throughout the specification.

  FIG. 3 is a block diagram for explaining the data transmitting / receiving apparatus of the semiconductor system according to the first embodiment of the present invention.

  In the semiconductor system according to the first embodiment of the present invention, only N parallel data DQ <0: N−1> and the clock CLK are provided between the transmission end of the memory controller 100 and the reception end of the semiconductor memory device 200. The strobe signal STB is also input and output.

  As illustrated in FIG. 3, the memory controller 100 includes a plurality of data transmission units (100_0 to 100_N−1), a strobe signal transmission unit 120, and a clock transmission unit 130.

  A plurality of transmission units (100_0 to 100_N-1) are provided for the number of parallel data DQ <0: N-1>, that is, N, and transmit corresponding parallel data DQ <0: N-1>. .

  More specifically, each transmission unit includes a data transmitter 102 (TX) and a data phase interpolator (PI) 104. The data transmitter 102 receives and transmits parallel data DQ <0: N-1>. The data phase interpolator 104 adjusts the phase of the data output from the data transmitter 102 in response to the multiple phase clock signal PLL_CLK <0: M> and the phase control signal PI_CTRL <0: N−1>. TCLK <0: N-1> is generated. Here, the phase control signal PI_CTRL <0: N-1> is a signal generated according to data training performed in an initial period before data input / output is performed by an input command.

  The strobe signal transmitter 120 transmits the strobe signal STB generated in the memory controller 100 in response to the multiple phase clock signal PLL_CLK <0: M> and the phase control signal PI_CTRL <N>.

  More specifically, the strobe signal transmission unit 120 includes a strobe signal transmitter 122 and a strobe signal phase interpolator 124. The strobe signal transmitter 122 receives and transmits a strobe signal STB generated in the memory controller 100. The strobe signal phase interpolator 124 adjusts the phase of the strobe signal STB output from the strobe signal transmitter 122 in response to the multiple phase clock signal PLL_CLK <0: M> and the phase control signal PI_CTRL <N>. Generate TCLK <N>. Here, the phase control signal PI_CTRL <N> is a signal generated in response to data training performed in an initial period before data input / output is performed by an input command.

  The clock transmission unit 130 generates a multi-phase clock signal PLL_CLK <0: M> in response to the reference clock signal CLK_REF and outputs it to the data transmission unit (100_0 to 100_N-1) and the strobe signal transmission unit 120. A clock CLK is generated and transmitted to the semiconductor memory device 200.

  More specifically, the clock transmission unit 130 includes a first clock generation unit 132 and a clock transmitter 134. The first clock generator 132 generates a multi-phase clock signal PLL_CLK <0: M> in response to the reference clock signal CLK_REF and supplies it to the transmitters (100_0 to 100_N, 120). In addition, the first clock generator 132 generates a clock CLK transmitted to the semiconductor memory device 200 in response to the reference clock signal CLK_REF. At this time, the multi-phase clock signal PLL_CLK <0: M> may be a signal generated by changing the phase of the clock CLK. Preferably, the first clock generation unit 132 includes a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit. The clock transmitter 134 buffers and outputs the clock CLK output from the first clock generation unit 132.

  The memory controller 100 further includes a training control unit 140 for performing data training in an initial period before data input / output is performed according to an input command.

  The training control unit 140 receives the serial training data input from the semiconductor memory device 200 during the initial period and generates the phase control signal PI_CTRL <0: N>.

  More specifically, the training control unit 140 includes a receiver 142 and a PI control signal generation unit 144. The receiver 142 receives serial training data input from the semiconductor memory device 200. The PI control signal generation unit 144 generates the phase control signal PI_CTRL <0: N> according to the serial training data received as a result of the data training performed in the initial period.

  On the other hand, the semiconductor memory device 200 includes a plurality of data receivers (200_0 to 200_N-1), a strobe signal receiver 220, a clock receiver 240, and a phase controller 260.

  The plurality of data receiving units (200_0 to 200_N-1) receive the input of parallel data DQ <0: N-1> output from the plurality of transmitting units (100_0 to 100_N-1) and receive data DIN <0: N-1> is generated. Preferably, the data receiving units (200_0 to 200_N-1) are provided for the number of parallel data DQ <0: N-1>.

  More specifically, each data receiving unit includes a data receiver 202 (RX), a sample holder 204 (S / H), and a local router 206. The data receiver 202 receives input of corresponding parallel data DQ <0: N-1>. The sample holder 204 samples the output of the data receiver 202 in response to the internal clock ICLK. The local router 206 routes the input internal clock ICLK and provides it to the sample holder 204.

  The strobe signal receiving unit 220 receives the strobe signal STB transmitted from the memory controller 100 and outputs a tracking clock TRACK_CLK.

  The clock receiver 240 receives the clock CLK output from the clock transmitter 130 and generates the internal clock ICLK. In particular, the clock receiver 240 of the present invention is characterized in that the phase is adjusted according to the internal clock control signal ICLK_CTRL.

  More specifically, the clock receiver 240 includes a clock receiver 242 and a second clock generator 244. The clock receiver 242 receives the clock CLK transmitted from the memory controller 100. The second clock generation unit 244 receives the clock CLK output to the clock receiver 242 and generates a clock signal having multiple phases. Preferably, the second clock generation unit 244 is configured with a PLL or a DLL.

  The phase controller 260 tracks the tracking clock TRACK_CLK by controlling the phase of the internal clock ICLK in order to compensate for the shift of the phase of the internal clock ICLK within the semiconductor memory device during data transmission / reception.

  More specifically, the phase control unit 260 includes a tracking unit 270 and a phase adjustment unit 280. The tracking unit 270 generates an internal clock control signal ICLK_CTRL by tracking the internal clock ICLK according to the tracking clock TRACK_CLK output from the strobe signal receiver 220. The phase adjustment unit 280 receives a clock signal having multiple phases output from the second clock generation unit 244, adjusts these phases according to the internal clock control signal ICLK_CTRL, and generates the internal clock ICLK. Preferably, the phase adjustment unit 280 includes a phase interpolator (PI).

  More specifically, the tracking unit 270 includes a local router 272, a phase detection unit 274, and a control signal generation unit 276. The local router 272 routes the internal clock ICLK and provides it to the phase detector 274. The phase detector 274 compares the internal clock ICLK input from the local router 272 with the phase of the tracking clock TRACK_CLK output from the strobe signal receiver 220. The control signal generation unit 230 generates the internal clock control signal ICLK_CTRL according to the comparison result of the phase detection unit 274.

  The clock distribution unit 250 distributes the internal clock ICLK output from the phase adjustment unit 280 and provides it to the local router provided in each receiving end.

  In addition, the semiconductor memory device 200 compensates for a skew existing in a path connecting from the memory controller 100 to the semiconductor memory device 200 in an initial period before data is input / output according to an input command. A data training unit 290 is further provided to perform data training.

  In particular, the data training unit 290 according to the first embodiment of the present invention receives not only the internal data DIN <0: N-1> at the time of initial operation but also feedback of the tracking clock TRACK_CLK, and these are received by the memory controller 100. It transmits to the training control part 140 of this.

  More specifically, the data training unit 290 includes a register 292, a serializer 294, and a transmitter 296. The register 292 receives feedback of the internal data DIN <0: N-1> output from the plurality of data receiving units (200_0 to 200_N-1) and the tracking clock TRACK_CLK output from the strobe signal receiving unit 220. save. The serializer 294 serializes and outputs the parallel internal data DIN <0: N−1> stored in the register 292 and the tracking clock TRACK_CLK. The transmitter 296 receives the output of the serializer 294 and outputs serial training data to the receiver 142 of the memory controller 100.

  Hereinafter, data training between the memory controller 100 and the semiconductor memory device 200 according to the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 is a timing diagram for explaining a data transmission / reception method of the semiconductor system according to the first embodiment of the present invention. FIG. 4 shows an example in which the first parallel data DQ <0> is trained to help understanding.

  As shown in FIG. 4A, in the initial state, each phase interpolator in the plurality of data transmission units of the memory controller is initialized. Along with this, the training clock TCLK output from the phase interpolator is also initialized. Therefore, the plurality of transmission units of the memory controller transmit the parallel data DQ, the clock CLK, and the strobe signal STB to the semiconductor memory device without phase adjustment by the phase interpolator. At this time, the parallel data DQ can be output with a phase shifted at regular intervals. For example, when 36 pieces of data are output, each piece of data is output so as to have a phase difference of 10 degrees. Therefore, the phase of the data can be changed by a part of the period of the clock CLK or the entire period.

  As shown in FIG. 4B, before an independent command is input and data input / output operation is performed, a skew existing in a connection path from the memory controller to the semiconductor memory device is determined. Data training is performed to compensate. Each data receiving unit of the semiconductor memory device receives the parallel data DQ according to the internal clock ICLK and generates internal data. Similarly, the strobe signal receiving unit receives the strobe signal STB and outputs the tracking clock TRACK_CLK. The data training unit receives feedback of the internal data and the tracking clock TRACK_CLK, serializes it, and transmits serial training data to the memory controller.

  As shown in FIG. 4C, the training control unit of the memory controller receives (N + 1) phase control signals in response to the input of serial training data. The phase interpolator in each data transmission unit adjusts the phase of the data DQ output from the data transmission unit by controlling the training clock TCLK according to the N phase control signals. Similarly, the phase interpolator in the strobe signal transmission unit adjusts the phase of the strobe signal STB by controlling the training clock TCLK according to the remaining one phase control signal.

  Through the above process, the edge of the internal data DIN is aligned with the rising edge of the internal clock ICLK, and the rising edge of the strobe signal STB is also aligned with the rising edge of the internal clock ICLK.

  As shown in FIG. 4D, when the data training is completed, the memory controller shifts the phase of the training clock TCLK and the parallel data DQ output in response thereto by 0.25 × tCK or 90 degrees. . Here, tCK means one cycle. Therefore, the rising edge of internal clock ICLK and the rising edge of strobe signal STB of the semiconductor memory device are positioned at the center of the effective window of internal data DIN, and internal clock ICLK and strobe signal STB are within the effective window of internal data DIN. Can have a maximum fluctuation range of tCK / 2.

  As shown in FIG. 4E, the clock CLK, data DQ, and strobe signal STB are transmitted at the transmission end of the memory controller during normal data transmission / reception between the memory controller and the semiconductor memory device. Each receiving unit of the semiconductor memory device receives the clock CLK, data DQ, and strobe signal STB transmitted from the memory controller. At this time, the strobe signal STB has a rising edge aligned at the center of the effective window of data.

  If the phase of the internal clock ICLK of the semiconductor memory device fluctuates due to a change in power supply voltage and a change in temperature, the phase control unit 260 of the semiconductor memory device uses the clock distribution unit 250 and the local router 206 as a reference based on the phase of the strobe signal STB. The internal clock control signal ICLK_CTRL is generated by tracking the phase of the internal clock ICLK fed back by.

  As shown in FIG. 4F, the phase adjustment unit 260 of the clock reception unit re-adjusts the phase of the internal clock ICLK in the same manner as the phase of the tracking clock TRACK_CLK in accordance with the internal clock control signal ICLK_CTRL. The data is output to the distribution unit 250. Thus, all data can be sampled within the valid window.

  As discussed above, in the semiconductor system according to the first embodiment of the present invention, not only N parallel data and clocks but also strobe signals are input between the transmission end of the memory controller and the reception end of the semiconductor memory device. Is output. Therefore, in a period before an input / output operation of data is performed after an independent command is input, the internal clock used at the receiving end of the semiconductor memory device by data training has a rising edge at the center of the valid window of data. Set as follows. In addition, the strobe signal STB is also adjusted so that the rising edge is aligned with the center of the effective window of data. After that, during data transmission / reception, even if the internal clock timing of the semiconductor memory device changes due to internal circuit delay, power supply voltage change or temperature change, the internal clock is tracked according to the strobe signal and the phase is changed. Readjust the internal clock in real time only if it is distorted. By doing so, the rising edge of the internal clock can be aligned to a desired location within the valid window of internal data. In other words, since the information about the center of the effective window of the data is at the edge of the strobe signal, if the internal clock is tracked and adjusted according to the strobe signal, all data can always be sampled in the effective window. .

  FIG. 5 is a block diagram for explaining a data transmitting / receiving apparatus of a semiconductor system according to the second embodiment of the present invention. Hereinafter, in the description of the second embodiment, the same components as those of the first embodiment will be given the same reference numerals, and only new components will be assigned new reference symbols. Detailed descriptions of the same components are omitted.

  Hereinafter, the semiconductor system according to the second embodiment of the present invention is characterized in that the strobe signal can be efficiently transmitted / received without error even if the strobe signal training circuit is provided at a minimum.

  As shown in FIG. 5, in the second embodiment of the present invention, one data receiving unit is selected and selected from the plurality of data receiving units (200_0 to 200_N−1) in the semiconductor memory device 200. The data receiving unit and the phase control unit 260 share the local router 300. That is, the internal clock ICLK input to the selected data reception unit is fed back to the phase detection unit 274 of the phase control unit 260.

  Further, the phase interpolator 104 in the data transmission unit of the memory controller 100 connected to the selected data reception unit shares the phase control signal PI_CTRL with the phase interpolator 124 of the strobe signal transmission unit 120.

  Preferably, the selected data receiving unit is selected from data receiving units located physically closest to the phase control unit 260. The selected data receiving unit can receive input of LSB (Least Significant Bit) or MSB (Most Significant Bit) of parallel data.

  For example, as shown in FIG. 5, the MSB of parallel data, that is, the data receiving unit (200_N−1) and the phase control unit 260 that receive the input of DQ <N−1> are transmitted from the shared local router 300. Receives input of internal clock ICLK. Further, the phase interpolator (PI) 104 of the data transmission unit (100_N-1) of the memory controller 100 connected to the selected data reception unit (200_N-1) is connected to the phase interpolator 124 in the strobe signal transmission unit 120. The phase control signal PI_CTRL <N-1> is shared.

  In the second embodiment of the present invention, the data training unit 400 for performing data training of the semiconductor memory device 200 receives feedback of the internal data DIN <0: N-1> during the initial operation, and stores it in the memory. This is transmitted to the training control unit 500 of the controller 100.

  In more detail, the data training unit 400 includes a register 420, a serializer 440, and a transmitter 460. The register 420 receives and stores feedback of the internal data DIN <0: N-1> output from the plurality of data receiving units (200_0 to 200_N-1). The serializer 440 serializes and outputs the parallel internal data DIN <0: N−1> stored in the register 420. The transmitter 460 receives the output of the serializer 440 and outputs serial training data to the training control unit 500 of the memory controller 100.

  The training controller 500 of the memory controller 100 receives the serial training data input from the semiconductor memory device 200 and generates the phase control signal PI_CTRL <0: N−1>. At this time, the phase interpolator 104 of the data transmission unit (100_N-1) of the memory controller 100 shares the phase control signal PI_CTRL <N-1> with the phase interpolator 124 in the strobe signal transmission unit 120.

  More specifically, the training control unit 500 includes a receiver 520 and a PI control signal generation unit 540. The receiver 520 receives serial training data input from the semiconductor memory device 200. The PI control signal generation unit 540 generates N phase control signals PI_CTRL <0: N−1> according to serial training data received as a result of data training performed at an initial time point.

  Hereinafter, data training between the memory controller 100 and the semiconductor memory device 200 according to the second embodiment of the present invention will be described with reference to the above configuration.

  First, in an initial state, each phase interpolator in the plurality of data transmission units of the memory controller 100 is initialized. Along with this, the training clock TCLK output from the phase interpolator is also initialized. Therefore, the plurality of transmission units of the memory controller transmit the parallel data DQ, the clock CLK, and the strobe signal STB to the semiconductor memory device 200 without adjusting the phase by the phase interpolator. At this time, the parallel data DQ can be output with a phase shifted at regular intervals. For example, when 36 pieces of data are output, each piece of data can be output so that adjacent data have a phase difference of 10 degrees. Therefore, the data phase can be changed by, for example, a part of the period of the clock signal CLK or the entire period.

  Thereafter, before an independent command is input and data input / output operation is performed, data training for compensating for a skew existing in a path connecting from the memory controller to the semiconductor memory device is performed. . Each data receiving unit 200_0 to 200_N-1 of the semiconductor memory device receives the parallel data DQ according to the internal clock ICLK and generates the internal data DIN. Similarly, the strobe signal receiving unit 220 receives the strobe signal STB and outputs the tracking clock TRACK_CLK. The data training unit 400 receives feedback of the internal data DIN and the tracking clock TRACK_CLK, serializes them, and transmits serial training data to the memory controller.

  The training controller 500 of the memory controller receives the serial training data and generates N phase control signals PI_CTRL. The phase interpolator 104 in each data transmission unit adjusts the phase of the data DQ output from the data transmission unit by controlling the training clock TCLK according to the N phase control signals. Similarly, the phase interpolator 124 in the strobe signal transmission unit 120 adjusts the phase of the strobe signal STB by controlling the training clock TCLK according to one of the N phase control signals.

  In particular, in the second embodiment of the present invention, the training control unit 500 is input to a data transmission unit connected to a data line of parallel data positioned physically closest, for example, DQ <N-1>. The phase interpolator 124 in the strobe signal transmitter is controlled using the phase control signal PI_CTRL <N-1>.

  Through the above process, the rising edge of the internal clock ICLK is aligned with the rising edge of the internal data DIN, and the rising edge of the strobe signal STB is aligned with the rising edge of the internal clock ICLK.

  When the data training is completed, the memory controller shifts the phase of the training clock TCLK and the parallel data DQ output in response thereto by 0.25 × tCK or 90 degrees. Therefore, the rising edge of internal clock ICLK and the rising edge of strobe signal STB of the semiconductor memory device are located at the center of the effective window of internal data DIN, and internal clock ICLK and strobe signal STB are in the effective window of internal data DIN. Can have a maximum fluctuation range (tCK / 2).

  Thereafter, during normal data transmission / reception between the memory controller and the semiconductor memory device, the strobe signal STB in which the rising edge is aligned at the center of the effective window of the data simultaneously with the clock CLK and the data DQ at the transmission end of the memory controller. Is also transmitted. Each receiving unit of the semiconductor memory device receives the clock CLK and data DQ transmitted from the memory controller and the strobe signal STB.

  If the phase of the internal clock ICLK of the semiconductor memory device fluctuates due to a change in power supply voltage and a change in temperature, the phase control unit 260 of the semiconductor memory device uses the clock distribution unit 250 and the local router 300 based on the phase of the strobe signal STB. The internal clock control signal ICLK_CTRL is generated by tracking the phase of the internal clock ICLK that is fed back. In particular, in the second embodiment of the present invention, the internal clock ICLK to be fed back is the MSB of parallel data located physically closest to the phase controller 260, that is, the input of DQ <N−1>. It is a signal output from the shared local router 300 of the received data receiving unit.

  The phase adjusting unit of the clock receiving unit readjusts the phase of the internal clock ICLK according to the internal clock control signal ICLK_CTRL and outputs the read signal to the clock distributing unit 250. This allows all data to be sampled within the valid window.

  As described above, during the data transmission / reception, the internal clock ICLK is re-sent in real time only when the phase is found to be distorted by the comparison result between the phase of the strobe signal STB and the phase of the internal clock ICLK fed back. adjust. By doing so, the rising edge of the internal clock ICLK can be aligned to a desired position within the valid window of the internal data DIN <0: N−1>, for example, the rising edge of the strobe signal STB. As a result, data transmission / reception can be performed without malfunction.

  As discussed above, in the semiconductor memory system according to the second embodiment of the present invention, a circuit for training the strobe signal inside the semiconductor memory device is provided at a minimum, and the strobe signal is efficiently transmitted without error. / Can be received. Accordingly, the semiconductor memory system can be highly integrated, and can easily satisfy the small area required in the electronic device and the system, and can be easily changed in design. Further, in the semiconductor memory system according to the second embodiment of the present invention, even when the frequency of the strobe signal is increased according to the data transmission speed, the data, clock and strobe signal can be transmitted and received efficiently without error. .

  Although the technical idea of the present invention has been specifically described by the above-described preferred embodiments, it should be noted that the above-described embodiments are for explanation and not for limitation. Further, those skilled in the art will readily understand that various embodiments are possible within the scope of the technical idea of the present invention.

DESCRIPTION OF SYMBOLS 10 Memory controller 10_0-10_N-1 Transmitter 12, 22 Transmitter 14 Phase interpolator 20 First clock generator 24 Receiver 26 PI control signal generator 30 Semiconductor memory device 30_0-30_N-1 Multiple receiver 32 Receiver 34 Sample holder (S / H)
36 Local router 40 Second clock generation unit 42 Clock distribution unit 44 Receiver 50 Data training unit 52 Register 54 Serializer
56 Transmitter 56
100 Memory Controller 100_0 to 100_N-1 Data Transmitter 102 Data Transmitter 104 Phase Interpolator 120 Strobe Signal Transmitter 122 Strobe Signal Transmitter 124 Strobe Signal Phase Interpolator 130 Clock Transmitter 132 First Clock Generator 134 Clock Transmitter 140 , 500 Training control unit 142 Receiver 144 PI control signal generation unit 200 Semiconductor memory device 200_0 to 200_N-1 Data reception unit 202 Data receiver 204 Sample holder (S / H)
206 Local router 220 Strobe signal receiver 240 Clock receiver 242 Clock receiver 244 Second clock generator 250 Clock distributor 260 Phase controller 270 Tracking unit 272 Local router 274 Phase detector 276 Control signal generator 280 Phase adjuster 290 , 400 Data training unit 292, 420 Register 294, 440 Serializer 296, 460 Transmitter 520 Receiver 540 PI control signal generation unit

Claims (31)

A strobe signal receiver for receiving a strobe signal and generating a tracking clock;
A clock receiver for receiving an input of the clock and generating an internal clock;
A plurality of data receiving units that receive input of parallel data according to the internal clock and generate internal data;
A phase controller that tracks the tracking clock and adjusts the phase of the internal clock to compensate for variations in the phase of the internal clock during data reception;
A semiconductor memory device comprising: The phase control unit is
A tracking unit that tracks the internal clock with reference to the tracking clock and outputs an internal clock control signal according to the tracking result;
A phase adjuster for adjusting the phase of the internal clock according to the internal clock control signal;
The semiconductor memory device according to claim 1, comprising: The tracking unit is
3. The semiconductor memory device according to claim 2, wherein feedback of an internal clock input to a specific data receiving unit among the plurality of data receiving units is received. The specific data receiver is
4. The semiconductor memory device according to claim 3, wherein the data receiving unit is a data receiving unit physically located closest to the strobe signal receiving unit among the plurality of data receiving units. The specific data receiver is
4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a data receiving unit that receives an input of LSB (Least Significant Bit) or MSB (Most Significant Bit) of parallel data among the plurality of data receiving units. The tracking unit is
A phase detector that detects a phase difference between the tracking clock and the internal clock;
A control signal generator for outputting the internal clock control signal according to the detection result;
The semiconductor memory device according to claim 2, further comprising: The phase adjusting unit is
The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a phase interpolator. The strobe signal is
2. The semiconductor memory device according to claim 1, wherein the rising edge is aligned with the center of the effective window of the parallel data. A clock distributor that distributes a clock output from the clock receiver and outputs the clock as the internal clock;
A local router that routes the internal clock output from the clock distributor and supplies the internal clock to the plurality of data receiving units and the phase control unit;
The semiconductor memory device according to claim 1, further comprising: In a semiconductor system including a first semiconductor chip and a second semiconductor chip for transmitting and receiving data,
The first semiconductor chip is
A plurality of data transmission units for outputting a plurality of parallel data;
A clock transmitter for outputting a clock;
A strobe signal transmitter that outputs strobe signals,
The second semiconductor chip is
A strobe signal receiver that receives the strobe signal and generates a tracking clock;
A clock receiver for receiving the clock and generating an internal clock;
A plurality of data receiving units that receive the parallel data according to the internal clock and generate internal data;
A phase control unit that tracks the tracking clock and adjusts the phase of the internal clock;
A semiconductor system comprising: The phase control unit is
A tracking unit that tracks the internal clock with reference to the tracking clock and outputs an internal clock control signal according to the result;
A phase adjuster for adjusting the phase of the internal clock according to the internal clock control signal;
The semiconductor system according to claim 10, comprising: The tracking unit is
12. The semiconductor system according to claim 11, wherein feedback of the internal clock input to a specific data receiving unit among the plurality of data receiving units is received. The tracking unit is
A phase detector that detects a phase difference between the tracking clock and the internal clock;
A control signal generator for outputting the internal clock control signal according to the detection result;
The semiconductor system according to claim 12, comprising: The first semiconductor chip is
A clock generator for receiving the input of a reference clock and generating the clock and the multiple phase clock signal;
A plurality of first phase adjusters for adjusting a phase of the parallel data in response to a plurality of first phase control signals and the multiple phase clock signal;
A second phase adjustment unit for adjusting a phase of the strobe signal in response to a second phase control signal and the multiple phase clock signal;
The semiconductor system according to claim 10, further comprising: The clock generation unit includes a phase locked loop (PLL) circuit or a delay locked loop (Delay Locked Loop),
The semiconductor system according to claim 14, wherein the first phase adjustment unit and the second phase adjustment unit include a phase interpolator (PI). The second phase adjustment unit is
15. The semiconductor system according to claim 14, wherein a phase of the strobe signal is adjusted so that a rising edge of the strobe signal is aligned with a center of an effective window of the parallel data. The second phase adjustment unit is
Of the plurality of data transmission units of the first semiconductor chip, the first phase control signal input to the data transmission unit connected to the specific data reception unit of the second semiconductor chip is the second phase control signal. 15. The semiconductor system according to claim 14, wherein The first phase control signal and the second phase control signal are:
15. The semiconductor system according to claim 14, wherein the semiconductor system is determined by data training performed in an initial period before data transmission / reception is performed according to an input command. The second semiconductor chip is
A data training unit that outputs training data in response to feedback of the internal data output from the plurality of data reception units in the initial period;
The first semiconductor chip is
15. The apparatus according to claim 14, further comprising a training control unit that receives the training data input from the data training unit and generates the first to third phase control signals in the initial period. The semiconductor system described in 1. The data training unit
A register for receiving and storing feedback of the internal data output from a plurality of the data receiving units;
A serializer that serializes and outputs the data stored in the register;
A transmitter that receives an input of the output of the serializer and transmits the training data to the first semiconductor chip;
20. The semiconductor system according to claim 19, further comprising: A clock distributor for distributing the internal clock output from the clock receiver;
A local router that routes the output of the clock distributor and supplies it to the plurality of data receivers and the phase controller;
The semiconductor system according to claim 10, further comprising: In a method for transmitting and receiving data between a first semiconductor chip and a second semiconductor chip,
Transmitting a plurality of parallel data, clock and strobe signals from the first semiconductor chip to the second semiconductor chip;
Receiving a strobe signal and generating a tracking clock;
Receiving an input of the clock and generating an internal clock; and
Receiving the parallel data according to the internal clock and generating internal data;
Tracking the tracking clock and adjusting the phase of the internal clock to compensate for variations in the phase of the internal clock during data transmission and reception;
A data transmission / reception method for a semiconductor system, comprising: The step of adjusting the phase comprises:
Detecting a phase difference between the tracking clock and the internal clock and outputting an internal clock control signal;
Correcting the phase of the internal clock in response to the internal clock control signal;
23. The data transmission / reception method for a semiconductor system according to claim 22, further comprising: The internal clock is
23. The data transmission / reception method of a semiconductor system according to claim 22, wherein an internal clock input to receive input of the specific parallel data among the plurality of parallel data is used. The first semiconductor chip receiving a reference clock and generating the clock and a multiple phase clock signal;
Adjusting the phase of the parallel data in response to a plurality of first phase control signals and the multiple phase clock signal;
Adjusting the phase of the strobe signal in response to a second phase control signal and the multiple phase clock signal;
25. The data transmission / reception method of a semiconductor system according to claim 24, further comprising: In the step of adjusting the phase of the strobe signal,
26. The data transmission / reception method of a semiconductor system according to claim 25, wherein the phase of the strobe signal is adjusted so that the rising edge of the strobe signal is aligned with the center of the effective window of the parallel data. In the step of adjusting the phase of the strobe signal,
26. The first phase control signal for adjusting the phase of specific parallel data among the plurality of first phase control signals is input to the second phase control signal. Data transmission / reception method for semiconductor system. The first phase control signal and the second phase control signal are:
26. The data transmission / reception method of a semiconductor system according to claim 25, further comprising a step determined according to data training performed in an initial period before data transmission / reception is performed according to an input command. Outputting training data to the first semiconductor chip in response to feedback of the internal data of the second semiconductor chip in an initial period before data is transmitted and received;
Receiving the training data at the first semiconductor chip and generating the first phase control signal and the second phase control signal;
26. The data transmission / reception method of a semiconductor system according to claim 25, further comprising: The step of outputting the training data comprises:
Receiving and storing feedback of the internal data;
Serializing and outputting the stored data; and
Transmitting the serialized data as the training data to the first semiconductor chip;
30. The data transmission / reception method of a semiconductor system according to claim 29, comprising: Distributing the input clock and outputting it to the internal clock;
Routing the internal clock obtained by distribution;
The data transmission / reception method for a semiconductor system according to claim 22, further comprising:

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