JP2011233006A - Electronic circuit, image-forming apparatus and initialization method for ddr-sdram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for suitably reducing the time on initialization for a DDR-SDRAM.SOLUTION: An electronic circuit 31 comprises an internal memory 47 having a shorter access time than a DDR-SDRAM 33, a control part 41 for performing various processes by using the internal memory 47 and the DDR-SDRAM 33 according to a program stored in a nonvolatile memory 32, and a switching part 50 for switching the access from the control part 41 to the internal memory 47 and the access from the control part 41 to the DDR-SDRAM 33. The control part 41 reads an initializing program for initializing the DDR-SDRAM 33 from the nonvolatile memory 32 and stores the read initializing program in the internal memory 47 to initialize the DDR-SDRAM 33 by using the initializing program stored in the internal memory 47.

Description

  The present invention relates to an electronic circuit, an image forming apparatus including the electronic circuit, and a method for initializing a DDR-SDRAM, and more particularly to a technique for initializing a DDR-SDRAM.

  Conventionally, as a technique related to initialization of a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), for example, a DDR-PHY reset (initialization) request signal is generated by a hardware configuration, and the DDR-PHY is reset. Techniques for performing processing are disclosed.

JP 2010-020387A

  However, since the initialization procedure of the DDR-SDRAM is usually more complicated than that of the SDRAM, and the procedure needs to be changed according to the model of the DDR-SDRAM, the DDR-SDRAM is initialized with a hardware configuration. This is not always preferable. Therefore, a method of performing initialization of the DDR-SDRAM in software has also been performed. For example, an initialization instruction code (initialization program) is stored in advance in an external ROM or the like, and when the DDR-SDRAM is initialized, the initialization program is read from the ROM, and the read initialization program There was a method for initializing the DDR-SDRAM. Although this software method can cover the disadvantages of the hardware configuration, there has been a demand for further reduction in the time required for initialization of the DDR-SDRAM.

  The present invention provides a technique for suitably shortening the time required for initialization of a DDR-SDRAM.

  The electronic circuit according to the first invention executes various processes using the internal memory and the DDR-SDRAM according to an internal memory having an access time shorter than that of the DDR-SDRAM and a program stored in the nonvolatile memory. A control unit that is connected to the control unit, the internal memory, and the DDR-SDRAM, and switches from the control unit to an access to the internal memory and an access to the DDR-SDRAM. The control unit reads an initialization program stored in the nonvolatile memory for initializing the DDR-SDRAM from the nonvolatile memory, stores the read initialization program in the internal memory, Initializing the DDR-SDRAM using the initialization program stored in the internal memory To.

  According to this configuration, the initialization of the DDR-SDRAM using the initialization program (software) stored in the nonvolatile memory is more nonvolatile than the initialization using only the nonvolatile memory. The number of accesses to the memory can be reduced. Therefore, the initialization time of the DDR-SDRAM can be shortened by using, for example, an SRAM having a high operation speed as the internal memory. Further, the control unit can effectively use the internal memory other than the initialization purpose by the switching unit after the initialization of the DDR-SDRAM. That is, the initialization time of the DDR-SDRAM can be suitably shortened while rationally using the internal memory.

  Here, the DDR-SDRAM includes so-called DDR2-SDRAM, DDR3-SDRAM and the like having a configuration corresponding to higher speed.

A second invention is the electronic circuit of the first invention, wherein the electronic circuit is connected to the switching unit, and after initialization of the DDR-SDRAM, access to the internal memory from other than the control unit is allowed. It further comprises an interface circuit for enabling.
According to this configuration, the internal memory can be used effectively after initialization of the DDR-SDRAM.

According to a third aspect of the present invention, in the electronic circuit of the second aspect, the interface circuit is a communication interface that receives data from the outside via a communication line and transmits the received data to the internal memory.
According to this configuration, after initialization of the DDR-SDRAM, the internal memory can be used to store data received via the communication line.

According to a fourth aspect of the present invention, in the electronic circuit of the third aspect, the electronic circuit has a normal mode and a power saving mode that consumes less power than the normal mode as operation modes, and the switching unit is a DDR-SDRAM. After the initialization, when the operation mode shifts from the normal mode to the power saving mode, the transmission destination of the reception data is switched from the DDR-SDRAM to the internal memory.
According to this configuration, the internal memory can be effectively used in the power saving mode, and power saving can be achieved as compared with the case of storing data in the DDR-SDRAM.

According to a fifth aspect of the present invention, in the electronic circuit according to the fourth aspect, the control unit returns from the power saving mode to the normal mode triggered by reception of data by the communication interface in the power saving mode.
According to this configuration, it is possible to prevent the received data from overflowing from the internal memory when the capacity of the received data received via the communication line is large.

According to a sixth aspect of the present invention, in the electronic circuit of the fourth or fifth aspect, the control unit includes a main control unit that operates in the normal mode and a sub-control unit that operates in the power saving mode, The sub-control unit reads the program stored in the internal memory and starts the operation when shifting from the normal mode to the power saving mode.
According to this configuration, the internal memory can be effectively used in the power saving mode.

According to a seventh aspect of the present invention, in the electronic circuit of the sixth aspect, the main control unit stores the sub memory in the internal memory before shifting from the normal mode to the power saving mode after the initialization of the DDR-SDRAM. The program for operating the control unit is written, and the operations of the main control unit and the DDR-SDRAM are stopped in the power saving mode.
According to this configuration, the internal memory can be used more effectively.

An eighth invention is the electronic circuit according to any one of the first to seventh inventions, wherein the initialization program is compressed and stored in the nonvolatile memory, and the control unit is stored in the nonvolatile memory. The read initialization program is decompressed and stored in the internal memory.
According to this configuration, the time required for initialization of the DDR-SDRAM can be further shortened.

  According to a ninth aspect of the present invention, in the electronic circuit according to any one of the first to eighth aspects, the switching unit is a DDR-SDRAM read request for reading data in the DDR-SDRAM after the initialization of the DDR-SDRAM. After receiving the internal memory read request for reading the data in the internal memory, the data in the DDR-SDRAM read in response to the DDR-SDRAM read request is output to the request destination, and then the internal The data in the internal memory read in response to the memory read request is output to the request destination.

  According to this configuration, data reading from the DDR-SDRAM usually takes longer time for processing than data reading from the internal memory such as SRAM. Therefore, after initialization of the DDR-SDRAM, for example, when a data read request is made from the internal memory after a data read request from the DDR-SDRAM, the data from the internal memory is first transferred to the control unit. Can be avoided. That is, after initialization of the DDR-SDRAM, processing using the internal memory and the DDR-SDRAM can be suitably performed. Further, even when a process using the internal memory and the DDR-SDRAM is performed by a plurality of control units, the data read process can be suitably performed.

According to a tenth aspect, in the electronic circuit of the ninth aspect, the switching unit suspends a part of the processing related to the internal memory read request until the processing related to the DDR-SDRAM read request is completed.
According to this configuration, in this case, for example, in parallel with the processing related to the DDR-SDRAM read request, data is read from the internal memory in response to the internal memory read request, and the read data is temporarily stored in the switching unit. Save and defer data output to the requestee. Then, after the output of the data in the DDR-SDRAM to the request destination is completed, the data in the internal memory can be output to the request destination immediately.

An eleventh invention is the electronic circuit according to any one of the first to tenth inventions, wherein the switching unit is configured by a DMA control unit, and the DMA control unit is connected to the control unit. A read data selection circuit that receives read data from the internal memory and DDR-SDRAM, selects the read data and selects an output destination of the selected read data, and is connected to the DMA arbitration circuit, and Internal memory / DDR-SDRAM selection circuit for selecting a memory to be accessed by the unit.
According to this configuration, by configuring the switching unit with the DMA control unit, the access process to the internal memory and the DDR-SDRAM can be suitably performed, and the access time can be shortened.

An electronic circuit according to a twelfth aspect of the invention includes an internal memory having an access time shorter than that of a DDR-SDRAM, a control unit that accesses the internal memory and the DDR-SDRAM and executes various processes, the control unit, A switching unit that is connected to the internal memory and the DDR-SDRAM and switches between the access to the internal memory and the access to the DDR-SDRAM from the control unit; and the switching unit includes the DDR-SDRAM When an internal memory read request for reading data in the internal memory is received after receiving a DDR-SDRAM read request for reading data in the data, the data in the DDR-SDRAM read in response to the DDR-SDRAM read request Is output in response to the internal memory read request. And it outputs the data in the internal memory which is a request destination.
According to this configuration, after initialization of the DDR-SDRAM, processing using the internal memory and the DDR-SDRAM can be suitably performed. Further, even when a process using the internal memory and the DDR-SDRAM is performed by a plurality of control units, the data read process can be suitably performed.

  An image forming apparatus according to a thirteenth aspect is an image forming apparatus for forming an image on a recording medium, and is executed by the electronic circuit according to any one of claims 1 to 12 and the control unit. The nonvolatile memory storing various programs for controlling the operation of the image forming apparatus, the DDR-SDRAM, and an image forming unit that forms an image based on the control of the electronic circuit. Prepare.

  According to this configuration, the initialization time of the DDR-SDRAM can be shortened when the operation of the image forming apparatus is controlled by an electronic circuit, for example, an ASIC. In addition, after the initialization of the DDR-SDRAM, the control unit can effectively use the internal memory for purposes other than the initialization purpose. As a result, the efficiency of image formation can be improved.

A DDR-SDRAM initialization method according to a fourteenth aspect of the invention is a method for initializing a DDR-SDRAM, wherein the electronic circuit includes an internal memory having a shorter access time than the DDR-SDRAM. Reads from the nonvolatile memory an initialization program stored in the nonvolatile memory for initializing the DDR-SDRAM into the electronic circuit, and stores the read initialization program in the internal memory. And a step of initializing the DDR-SDRAM using the initialization program stored in the internal memory.
According to this configuration, the initialization time of the DDR-SDRAM can be shortened suitably.

A fifteenth aspect of the invention is the method for initializing a DDR-SDRAM according to the fourteenth aspect of the invention, further comprising an external access step of accessing the internal memory from outside the electronic circuit after the step of initializing.
According to this configuration, the internal memory can be used effectively after the initialization of the DDR-SDRAM, so that the internal memory can be used rationally.

  According to the present invention, the time required for initializing the DDR-SDRAM can be suitably shortened.

1 is a block diagram showing a schematic electrical configuration of a printer according to an embodiment of the present invention. Block diagram showing schematic electrical configuration of electronic circuit of printer Flowchart showing DDR initialization processing A flowchart showing an outline of processing related to a RAM access request A flowchart showing processing of the DMA control unit related to a memory read request Another flowchart showing processing of the DMA control unit related to a memory read request

<Embodiment>
An embodiment of the present invention will be described with reference to FIGS.

1. FIG. 1 is a block diagram showing an electrical configuration of a printing system including a plurality of personal computers (hereinafter referred to as “PCs”) 10 and a printer 30 (an example of an image forming apparatus). . Note that the image forming apparatus is not limited to a printer, and may be, for example, a facsimile machine, a copier, or a multifunction machine having these functions.

  The printer 30 includes an ASIC (an application specific integrated circuit: an example of “electronic circuit”) 31, an external ROM (an example of “nonvolatile memory”) 32, an external DDR2-SDRAM (an example of “DDR-SDRAM”) 33, an external An LSI 34, an operation unit 35, a display unit 36, an image forming unit 37, and the like are included. The ASIC 31 includes a first CPU 41, a second CPU 42, a network interface (I / F) 43, and the like.

  Note that the electronic circuit is not limited to an ASIC, and may be configured by, for example, an individual IC and a logic circuit. In this case, the external ROM (nonvolatile memory) and / or the external DDR2-SDRAM (DDR-SDRAM) may be configured in an electronic circuit. That is, the nonvolatile memory is not limited to the external ROM, and the DDR-SDRAM is not limited to the external DDR2-SDRAM.

  Various programs for controlling the operation of the printer 30 are recorded in the external ROM 32, and the first CPU 41 and the second CPU 42 store the processing results in an external DDR2-SDRAM (hereinafter simply referred to as “ The operation of the printer 30 is controlled while being stored in the SRAM 47 (see FIG. 2) inside the ASIC 31 or 33 (denoted as “external DDR”). The external ROM 32 stores an initialization program for initializing the external DDR 33.

  A network I / F (an example of an “interface circuit” in the present invention) 43 is connected to a plurality of PCs 10 via a LAN (local area network: an example of a “communication line”) 20 so that mutual data communication is possible. It is.

  The operation unit 35 includes a plurality of buttons, and various input operations such as a print start instruction and an operation mode instruction can be performed by the user. The display unit 36 includes a liquid crystal display, a lamp, and the like, and can display various setting screens, operation states, and the like. The image forming unit 37 has a function of printing on a recording medium such as paper.

  In addition, the printer 30 has, as operation modes, a normal mode that performs a normal operation such as a printing process, and a power saving mode that consumes less power than the normal mode. The ASIC 31 also has a normal mode and a power saving mode according to the operation mode of the printer 30.

2. Configuration of ASIC (Electronic Circuit) Next, the configuration of the ASIC 31 will be described with reference to FIG. FIG. 2 is a block diagram showing a schematic configuration of the ASIC 31.

  As shown in FIG. 2, the ASIC 31 includes a first CPU 41, a second CPU 42, a ROM arbitration circuit 46, an SRAM (Static Random-Access Memory: an example of “internal memory”) 47, and a DMA control unit 50.

  The first CPU (an example of “control unit” and “main control unit”) 41 executes various processes using the SRAM 47 and the external DDR 33 in accordance with a program stored in the external ROM 32. For example, the first CPU 41 reads the initialization program of the external DDR 33 from the external ROM 32 and stores the read initialization program in the SRAM 47. Then, the first CPU 32 initializes the external DDR 33 using an initialization program.

  Note that the initialization of the external DDR 33 may be performed by the second CPU 42. In this case, the initialization program is preferably compressed and stored in the external ROM 32, and the first CPU 32 decompresses the initialization program read from the external ROM 32 and stores it in the SRAM 47. With this configuration, the time required for initialization of the external DDR 33 can be further shortened.

  Here, the first CPU 41 is constituted by a CPU having a processing capability larger than that of the second CPU 42, the first CPU 41 is a main CPU that operates in the normal mode, and the second CPU 42 is a sub CPU that operates in the power saving mode. Also good. Then, the second CPU (an example of “control unit”, “sub control unit”) 42 reads the operation program stored in the SRAM 47 and starts the operation when shifting from the normal mode to the power saving mode. Also good. In this case, the internal memory can be used effectively during the power saving mode.

  In this case, further, the first CPU (main control unit) 41 operates so that the second CPU (sub control unit) 42 operates in the SRAM 47 before shifting from the normal mode to the power saving mode after the initialization of the external DDR 33. Write a program. In the power saving mode, the operations of the first CPU 41 and the external DDR 33 may be stopped. In this case, further power saving can be achieved and the SRAM 47 can be used more effectively.

  The ROM arbitration circuit 46 arbitrates access to the external ROM 32 by the first CPU 41 and access to the external ROM 32 by the second CPU 42.

  For example, the SRAM 47 is mainly accessed by the first CPU 41 in the normal mode. In the power saving mode, the SRAM 47 is accessed by the first CPU 41 or the second CPU 42 and from the outside via the network I / F 43. The SRAM 47 consumes less power than the external DDR 33, and the access time of the SRAM 47 is shorter than the access time of the external DDR 33.

  The DMA (Direct Memory Access) control unit 50 includes a DMA arbitration circuit 51, an internal memory / external memory selection circuit 52, a read data selection circuit 53, an SRAM-I / F 54, and a DDR-I / F 55.

  The DMA arbitration circuit 51 is connected to the first CPU 41, the second CPU 42, etc., receives the access request signal REQ and the write data WD for the SRAM 47 and the external DDR 33, arbitrates the access request, and clears the clear signal CLR to the request destination in response to the access request. return it.

  An internal memory / external memory selection circuit (an example of a “switching unit”) 52 is connected to the first CPU 41, the second CPU 42, or the network I / F 43 via the DMA arbitration circuit 51. An internal memory / external memory selection circuit (hereinafter, simply referred to as “memory selection circuit”) 52 is connected to the SRAM 47 via the SRAM-I / F 54 and is connected to the external DDR 33 via the DDR-I / F 55. .

  The memory selection circuit 52 switches between the access from the first CPU 41 or the second CPU 42 or the network I / F 43 to the SRAM 47 and the access from the first CPU 41 or the second CPU 42 or the network I / F 43 to the external DDR 33. In addition, after the initialization of the external DDR 33, the selection circuit 52 switches the transmission destination of received data via the network I / F 43 from the external DDR 33 to the SRAM 47 when the operation mode shifts from the normal mode to the power saving mode. Thereby, the SRAM 47 can be used effectively in the power saving mode after the initialization of the external DDR 33.

  The read data selection circuit 53 receives the read data RD from the SRAM 47 or the external DDR 33, and selects the read data RD and the output destination of the selected read data RD.

  The ASIC 31 also includes a network I / F 43, a first CPU I / F 44, a second CPU I / F 45, and an external ROM-I / F 48 as various interface (I / F) circuits.

  A network I / F (an example of an “interface circuit” in the present invention) 43 includes a DMA-I / F 43C, and is connected to a memory selection circuit 52 via a DMA arbitration circuit 51. The network I / F 43 enables access to the SRAM 47 from other than the first CPU 41 and the second CPU 42 after the initialization of the external DDR 33. Here, the network I / F 43 is a communication interface that receives data from the outside of the printer 30, for example, the PC 10 via the LAN (an example of “communication line”) 20, and transmits the received data to the SRAM 47. Note that transmission of received data to the SRAM 47 is preferably performed mainly in the power saving mode.

  The first CPU 41 preferably returns from the power saving mode to the normal mode triggered by the network I / F 43 receiving data in the power saving mode. When only the SRAM 47 is used in the power saving mode, it is possible to prevent the received data from overflowing from the SRAM 47 when the capacity of the received data received via the communication line 20 is large.

  The first CPU I / F 44 includes a CPU-I / F 44A, a ROM arbitration-I / F 44B, and a DMA-I / F 44C, and is between the first CPU 41 and the external ROM 32, and between the first CPU 41 and the DMA control unit 50. Interface.

  Similarly, the second CPU I / F 45 includes a CPU-I / F 45A, a ROM arbitration-I / F 45B, and a DMA-I / F 45C, between the second CPU 42 and the external ROM 32, and between the second CPU 42 and the DMA control unit 50. Interface between.

3. Initialization of External DDR2-SDRAM Next, an initialization method of the external DDR 33 will be described with reference to FIG. The initialization of the external DDR 33 is started when the printer 30 is turned on, that is, when power is applied to the ASIC 31.

  When power is applied to the ASIC 31, the reset of the first CPU 41 is released, and the first CPU 41 starts up (step S110). Then, the first CPU 41 reads the initialization program for initializing the external DDR 33 stored in the external ROM 32 from the external ROM 32 connected to the ASIC 31 (corresponding to step S120: “reading step”).

  Next, the first CPU 41 stores the read initialization program in the SRAM 47 (step S130: equivalent to “store step”). Then, the first CPU 41 initializes the external DDR 33 by using the initialization program stored in the SRAM 47, that is, fetches the instruction of the initialization program (corresponding to “step S140:“ initializing process ”).

  As described above, the initialization time of the external DDR 33 can be shortened by using, for example, the SRAM 47 whose operation speed is faster (shorter access time) than that of the external ROM 32 as the internal memory.

  Preferably, after the initialization step, the SRAM 47 can be accessed from outside the ASIC 31 (step S150: equivalent to “external access step”). The external access process is performed via the network I / F 43 and the memory selection circuit 52 of the DMA control unit 50. For example, in the power saving mode after the initialization step, when the network I / F 43 receives external data, the memory selection circuit 52 selects the SRAM 47.

4). Memory Access Control by DMA Controller Next, arbitration control of memory access by the DMA controller 50 will be described with reference to FIG. 4 and FIG. FIG. 4 is a flowchart showing an outline of the procedure of memory access control by the DMA control unit 50, and FIG. 5 is a flowchart showing in detail the relationship between the first CPU 41 and the DMA control unit 50 at the time of memory access in the present embodiment. It is.

  First, an overview of RAM (memory) access will be described with reference to FIG. For example, when there is an access request to the RAM from the first CPU 41, the DMA control unit 50 (DMA arbitration circuit 51) determines whether the request is an access request to the SRAM 47 (step S210). If it is an access request to the SRAM 47 (step S210: YES), it is determined whether or not the external DDR 33 is currently being accessed (step S220).

  If it is being accessed (step S220: YES), it waits until the access to the external DDR 33 is completed. When the external DDR 33 is not currently being accessed (step S220: NO), access to the SRAM 47 is started (step S225).

  Here, it is not always necessary to wait for access to the SRAM 47 until all access processing to the external DDR 33 is completed. A part of the access process to the SRAM 47 may be started during the access to the external DDR 33. That is, preferably, as described later, after the data in the external DDR 33 read in response to the external DDR read request is output to the request destination, the data in the SRAM 47 read in response to the SRAM read request is output to the request destination. As described above, the access processing related to the SRAM 47 is on standby.

  On the other hand, if it is not an access request to the SRAM 47 in step S210, that is, if it is an access request to the external DDR 33 (step S210: NO), access to the external DDR 33 is started (step S215).

  Next, it is determined whether or not a FIFO (First-In First-Out) related to memory access is full (step S230). If the FIFO is full (step S230: YES), the process waits until the FIFO is full. If the FIFO is not full (step S230: NO), the DMA control unit 50 generates a clear signal CLR (step S235).

  Next, it is determined whether the access request is a read access (step S240). If the access request is not a read access, that is, a write access (step S240: NO), a write command is issued and a write operation to the SRAM 47 or the external DDR 33 is executed. (Step S245), and the write access ends.

  On the other hand, if it is determined in step S240 that the access is read (step S240: YES), a read command is issued and a read operation from the SRAM 47 or the external DDR 33 is executed (step S250).

  Next, the DMA control unit 50 determines whether or not data for the requested address has been input (step S255). If no data has been input, the DMA control unit 50 waits until it is input (step S255: NO). On the other hand, when data is input (step S255: YES), a read data signal RD and a read data enable signal are generated (step S260), and the read access ends.

  Next, an example of arbitration control of RAM (memory) access by the DMA control unit 50 in the present embodiment will be described in detail with reference to FIG.

  For example, when there is a read request from the first CPU 41 to the external DDR 33, the DMA control unit 50 latches the DDR read command (step S410), generates a clear signal CLR, and transmits the clear signal CLR to the first CPU 41 ( Step S415). Then, a DDR read command is issued and a read operation is executed (step S425).

  On the other hand, when the first CPU 41 receives the clear signal CLR from the DMA control unit 50 (step S420), it makes a read request to the SRAM 47 to the DMA control unit 50 (step S430).

  Then, the DMA control unit 50 latches the SRAM read command during execution of the read operation of the external DDR 33 (step S435), generates the clear signal CLR, and transmits the clear signal CLR to the first CPU 41 (step S440). , S445). Then, an SRAM read command is issued and a read operation is executed (step S450). Next, when the input of read data from the SRAM 47 is completed (step S455), the process waits until the read operation from the external DDR 33 is completed (step S470).

  Next, when the input of the read data from the external DDR 33 is completed, the read data RD is transmitted to the first CPU 41 (step S460). Then, when the first CPU 41 inputs the read data RD from the external DDR 33 (step S465), the DMA control unit 50 transmits the read data RD from the SRAM 47 to the first CPU 41 (step S470). Then, the first CPU 41 inputs the read data RD from the SRAM 47 immediately after the input of the read data RD from the external DDR 33 (step S475).

  As described above, in this embodiment, the DMA control unit (switching unit) 50 receives the DDR read request for reading the data in the external DDR 33 after the initialization of the external DDR 33, and then reads the data in the SRAM 47. When the read request is received, the external DDR 33 data read in response to the DDR read request is output to the first CPU 41 (request destination), and then the SRAM 47 data read in response to the SRAM read request is output to the first CPU 41. At that time, the DMA control unit (switching unit) 50 suspends a part of the process related to the SRAM 47 read request until the process related to the DDR read request is completed.

  Usually, data reading from the external DDR 33 takes a longer time for processing than data reading from an internal memory such as the SRAM 47. Therefore, after initialization of the external DDR 33, for example, when a data read request is made from the internal memory after the data read request from the external DDR 33 from the first CPU 41, the data from the internal memory is first output to the control unit. The inconsistency of being performed can be avoided. In other words, after initialization of the external DDR 33, processing using the SRAM 47 and the external DDR 33 can be suitably performed. The present embodiment is also applied when a process using the SRAM 47 and the external DDR 33 is performed by a plurality of control units such as the first CPU 41 and the second CPU 42, that is, when the data read request destinations are different from the RAM. The data reading process can be suitably performed.

  In parallel with the processing related to the DDR read request, data is read from the SRAM 47 in response to the SRAM read request, the read data is temporarily stored in the DMA control unit 50, and data output to the first CPU 41 is performed. Deferred. Therefore, the data of the SRAM 47 can be output to the first CPU 41 immediately after the output of the data of the external DDR 33 to the first CPU 41 is completed.

5). Effects of the Embodiment When the external DDR 33 is initialized using the initialization program stored in the external ROM 32, the number of accesses to the external ROM 32 is smaller than when the external DDR 33 is initialized using only the external ROM 32. Can be reduced. Therefore, the initialization time of the external DDR 33 can be shortened by using, for example, the SRAM 47 whose operating speed is faster (shorter access time) than the external ROM 32 as the internal memory. Further, the first CPU 41 can effectively use the SRAM 47 by the DMA control unit (switching unit) 50 other than the initialization purpose after the external DDR 33 is initialized. That is, the initialization time of the external DDR-SDRAM can be suitably shortened while rationally using the internal memory.

  In addition, after initialization of the external DDR 33, processing using the SRAM 47 and the external DDR 33 can be suitably performed. At that time, the time from the DDR read request until the SRAM read is completed can be shortened.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  (1) In the above embodiment, in the process related to the DDR read request shown in FIG. 5, only the process of transmitting the SRAM read data to the first CPU 41 (request destination) is completed until the process related to the DDR read request ends (DDR read). Although an example in which data is held (until data is transmitted to the first CPU 41) has been shown, the holding process is not limited to this. For example, as shown in FIG. 6, after the processing of step S440, the subsequent processing is suspended until DDR read data is transmitted to the first CPU 41 (step S510), and thereafter, the SRAM read command is issued (step S515). Read data input (step S520), and SRAM read data input (step S525) to the first CPU 41 may be performed. In FIG. 6, processing at the same timing as the processing shown in FIG. 5 is indicated by the same step code.

  Even in this case, after initialization of the external DDR 33, processing using the SRAM 47 and the external DDR 33 can be suitably performed. In addition, compared with the case where the SRAM read request is made after the SRAM read data is input to the first CPU 41, the time from the DDR read request to the completion of the SRAM read can be shortened.

  (2) In the above-described embodiment and the above-described other embodiments, the example of the arbitration control of the memory access by the DMA control unit 50 after the initialization of the external DDR 33 using the SRAM 47 is shown, but the present invention is not limited to this. That is, the access control to the SRAM 47 and the external DDR 33 shown in FIG. 5 or FIG. 6 can be applied to various electronic circuits without depending on the initialization method of the external DDR 33.

30 ... Printer 31 ... ASIC
32 ... External ROM
33 ... External DDR2-SDRAM
37 ... Image forming unit 41 ... First CPU
42 ... 2nd CPU
43 ... Network I / F
47 ... SRAM
DESCRIPTION OF SYMBOLS 50 ... DMA control part 51 ... DMA arbitration circuit 52 ... Internal memory / external memory selection circuit 53 ... Read data selection circuit

Claims (15)

An internal memory having a shorter access time than DDR-SDRAM;
A control unit that executes various processes using the internal memory and the DDR-SDRAM according to a program stored in a nonvolatile memory;
A switching unit that is connected to the control unit, the internal memory, and the DDR-SDRAM and that switches access from the control unit to the internal memory and access to the DDR-SDRAM;
The controller is
Reading an initialization program for initializing the DDR-SDRAM stored in the nonvolatile memory from the nonvolatile memory, storing the read initialization program in the internal memory,
An electronic circuit for initializing the DDR-SDRAM using the initialization program stored in the internal memory. The electronic circuit of claim 1, wherein the electronic circuit is
An electronic circuit further comprising an interface circuit connected to the switching unit and enabling access to the internal memory from other than the control unit after initialization of the DDR-SDRAM. The electronic circuit according to claim 2,
The interface circuit is an electronic circuit that is a communication interface that receives data from the outside via a communication line and transmits received data to the internal memory. The electronic circuit according to claim 3, wherein the electronic circuit has a normal mode and a power saving mode that consumes less power than the normal mode as operation modes,
An electronic circuit for switching a transmission destination of the reception data from the DDR-SDRAM to the internal memory when the operation mode is shifted from the normal mode to the power saving mode after initialization of the DDR-SDRAM; . The electronic circuit according to claim 4.
The control unit is an electronic circuit that returns from the power saving mode to the normal mode, triggered by reception of data by the communication interface in the power saving mode. The electronic circuit according to claim 4 or claim 5,
The control unit includes a main control unit that operates in the normal mode and a sub-control unit that operates in the power saving mode,
The sub control unit is an electronic circuit that starts an operation by reading a program stored in the internal memory when shifting from the normal mode to the power saving mode. The electronic circuit according to claim 6.
The main control unit writes the program for operating the sub control unit to the internal memory before shifting from the normal mode to the power saving mode after initialization of the DDR-SDRAM.
An electronic circuit in which operations of the main control unit and the DDR-SDRAM are stopped in the power saving mode. The electronic circuit according to any one of claims 1 to 7,
The initialization program is compressed and stored in the nonvolatile memory,
The control unit is an electronic circuit that decompresses the initialization program read from the nonvolatile memory and stores the decompressed program in the internal memory. The electronic circuit according to any one of claims 1 to 8,
When the switching unit receives an internal memory read request for reading data in the internal memory after receiving a DDR-SDRAM read request for reading data in the DDR-SDRAM after initialization of the DDR-SDRAM, An electronic device that outputs data in the DDR-SDRAM read in response to the DDR-SDRAM read request to a request destination, and then outputs data in the internal memory read in response to the internal memory read request to the request destination. circuit. The electronic circuit according to claim 9.
The switching unit is an electronic circuit that suspends a part of the processing related to the internal memory read request until the processing related to the DDR-SDRAM read request is completed. The electronic circuit according to any one of claims 1 to 10,
The switching unit is configured by a DMA control unit,
The DMA control unit
A DMA arbitration circuit connected to the control unit;
A read data selection circuit that receives read data from the internal memory and the DDR-SDRAM, selects the read data, and selects an output destination of the selected read data;
An electronic circuit including an internal memory / DDR-SDRAM selection circuit that is connected to the DMA arbitration circuit and selects a memory to be accessed by the control unit. An internal memory having a shorter access time than DDR-SDRAM;
A control unit that accesses the internal memory and the DDR-SDRAM and executes various processes;
A switching unit that is connected to the control unit, the internal memory, and the DDR-SDRAM and that switches access from the control unit to the internal memory and access to the DDR-SDRAM;
When the switching unit receives an internal memory read request for reading data in the internal memory after receiving a DDR-SDRAM read request for reading data in the DDR-SDRAM, the switching unit responds to the DDR-SDRAM read request. An electronic circuit that outputs data in the internal memory read in response to the internal memory read request to the request destination after outputting the read data in the DDR-SDRAM to the request destination. An image forming apparatus for forming an image on a recording medium,
An electronic circuit according to any one of claims 1 to 12,
The nonvolatile memory storing various programs executed by the control unit for controlling the operation of the image forming apparatus;
The DDR-SDRAM;
An image forming unit that forms an image based on control of the electronic circuit;
An image forming apparatus. A method of initializing a DDR-SDRAM, wherein the electronic circuit includes an internal memory having a shorter access time than the DDR-SDRAM,
Reading an initialization program stored in the nonvolatile memory for initializing the DDR-SDRAM into the electronic circuit from the nonvolatile memory;
Storing the read initialization program in the internal memory;
Initializing the DDR-SDRAM using the initialization program stored in the internal memory;
A method for initializing a DDR-SDRAM. The method of claim 14 comprises:
A method of initializing a DDR-SDRAM, further comprising an external access step of accessing the internal memory from outside the electronic circuit after the initialization step.

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