JP2011232985A - Access timing adjustment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a processing time for access timing adjustment processing between a system LSI and a memory.SOLUTION: By introducing a delay adjustment value calculated from wire length information of each bit data signal and each data strobe signal between a system LSI 2 and a memory 3, a value obtained by adding a result of the access timing adjustment to the delay adjustment value is set as an access timing adjustment value for a bit data subjected to the access timing adjustment processing other than one-bit data.

Description

  The present invention relates to an access timing adjustment device that adjusts access timing to a memory.

  Conventionally, when the memory controller mounted on the system LSI accesses the memory, the operation timing is sometimes slow, and there is no problem even if the same value, that is, a fixed value is used for all the system LSIs. However, as the function of the system LSI has improved, the operating frequency of the memory interface has gradually increased and the access timing has become stricter. Therefore, it has become necessary to make the access timing adjustable according to the state of the system LSI, rather than having a fixed value. .

  Therefore, an access timing adjustment register is provided in the system LSI, and a circuit that can change the timing of the memory interface signal output from the system LSI or the timing of the input internal signal by changing its value is incorporated. It has become like this.

  Further, as disclosed in Patent Document 1, a technique for adjusting an optimum access timing for each device by an access timing adjusting device is disclosed. In this access timing adjustment device, the processor writes data to a specific area of the memory, reads data from the same area, compares the read data with an expected value, and determines whether data can be read. Then, an upper limit value and a lower limit value at which memory access is successful are acquired, and the intermediate value is used as a value that can secure the maximum operation margin.

  By this method, it is possible to ensure the maximum operation margin in consideration of conditions such as temperature fluctuation, voltage fluctuation, and process fluctuation.

Japanese Patent Laid-Open No. 11-316619

  However, the conventional example such as Patent Document 1 has problems with respect to the following points.

  In recent years, it has become possible to adjust the access timing in units of 1 bit of data transferred between the system LSI and the memory by the miniaturization technology of the system LSI, and the adjustment accuracy can be increased.

  However, when the conventional method is adopted, it is necessary to execute the access timing adjustment process by the number of bits of data, leading to an increase in processing time. For example, if the memory data bus is 32 bits, the same processing is executed 32 times.

  In addition, since the access timing adjustment process is executed at the time of system startup, an increase in processing time leads to an increase in system startup time.

  Therefore, the present invention solves the above-mentioned conventional problems, and uses the bit length information of each bit data signal and data strobe signal between the system LSI and the memory, and the access timing which can shorten the processing time compared with the conventional method. An object is to provide an adjusting device.

  In order to solve the above-described conventional problems, the present invention provides an access timing adjustment device for adjusting a timing for accessing a plurality of external memories from a system LSI, wherein the system LSI is connected to the plurality of external memories. Control means for adjusting the access timing by transmitting and receiving data from the memory interface a plurality of times is provided.

  Further, the control means determines whether or not the access is successful while sequentially changing the access timing adjustment value for the specific bit data in the memory interface, and sets the access timing adjustment value within the range where the access is successful. It is characterized by that.

  The control means further adds a delay adjustment value based on a wiring length between the system LSI and the plurality of external memories to the access timing adjustment result for bit data other than the bit data in the memory interface. A value is set as an access timing adjustment value.

  According to the access timing adjustment device of the present invention, the processing time of the conventional access timing adjustment device can be shortened by using the wiring length information of each bit data signal and data strobe signal between the system LSI and the memory. become. This is particularly useful in the field of system LSI technology for digital AV equipment.

Configuration diagram of an access timing adjustment device in Embodiment 1 of the present invention The flowchart which shows the access timing adjustment process in Embodiment 1 of this invention

  The best mode for carrying out the present invention will be described below with reference to the drawings.

A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an access timing adjustment device, and shows a configuration of a device according to a first embodiment of the present invention.
The apparatus shown in FIG. 1 includes a system LSI 2, a plurality of external memories 3, and a nonvolatile memory 4.

  The system LSI 2 includes a processor 21, an external bus controller 22, an SRAM (Static Random Access Memory) 23, a memory controller 24, and a memory interface 25. The processor 21 has a function as a control means for adjusting the access timing with the external memory 3, and the delay calculated from the wiring length information of each bit data signal and data strobe signal between the system LSI 2 and the external memory 3. Has an adjustment value.

  The external bus controller 22 has a function as control means for controlling the data bus between the processor 21 and the nonvolatile memory 3 and the data bus between the processor 21 and the SRAM 23. The SRAM 23 is connected to the processor 21 via the external bus controller 22 and has a role as a work area of the processor 21. The memory controller 24 is connected between the processor 21 and each of the external memories 31 and 32, includes a memory interface 25, and has a function of controlling the external memories 31 and 32. The memory interface 25 is connected to each of the external memories 31 and 32 and has a function as an interface for exchanging data with the external memories 31 and 32.

  The plurality of external memories 3 include external memories 31 and 32. The nonvolatile memory 4 also includes a boot program 41, an access timing adjustment program 42, and an application program 43 as other programs.

  Next, the operation of the apparatus shown in FIG. 1 will be described in detail. First, the processor 21 reads the boot program 41 from the nonvolatile memory 4 via the external bus controller 22 at the time of startup, performs various settings of the system LSI 2, and similarly reads the access timing adjustment program 42 from the nonvolatile memory 4.

  For example, DDR SDRAM (Double Date Rate Synchronous Dynamic Random Access Memory) is used for the external memories 31 and 32 in FIG. A data strobe signal synchronized with the clock signal is used to notify the timing of data transfer from the memory controller 24 to the external memories 31 and 32 or from the external memories 31 and 32 to the memory controller 24.

  When data is read from the external memories 31 and 32, the data is output from the external memories 31 and 32 in the same phase as the data strobe signal. A data strobe signal having a phase delayed by 90 degrees with respect to the data strobe signal thus generated is generated. Data is read when the data strobe signal rises and falls.

  However, the received data strobe signal is distorted due to external factors such as power supply fluctuation and noise, and a phase shift occurs when the edge of the data strobe signal is detected. In order to cope with this, the memory controller 24 needs to secure a window width that is a predetermined phase range with respect to 90 degrees that is a reference phase difference for reading data. The window width is expressed as a phase difference that can be adjusted in units of, for example, 180 degrees divided into 64, and the access timing is changed according to the phase difference set in the access timing adjustment register.

  By the above method, the processor 21 checks the window range that is the phase difference range in which the memory access is successful while changing the access timing setting for the external memory 3. Then, the intermediate value of the window range obtained from the inspection result is set in the access timing adjustment register as an optimum value that can secure the maximum operation margin.

  The optimum value set in the access timing adjustment register may be a value obtained by adding an adjustment value for adjusting the influence of variations such as temperature variation, voltage variation, and process variation to the intermediate value of the window range. . The window range inspection method will be described in detail with reference to FIG. 2 by taking read access timing adjustment as an example.

  FIG. 2 is a flowchart showing the processing of the access timing adjustment program 42 of the present invention. FIG. 2 will be described in detail.

  First, the test data used for the expected value comparison is written in a specific area of the external memory by the processor (step 11). Then, the process proceeds to the next step 12. In step 12, the value of the access timing adjustment register is set to the value to be inspected. For example, a phase difference value obtained by dividing 180 degrees into 64 is defined as one step value, 0 step value (0 degree) in the first inspection, 1 step value in the second inspection, 2 step value in the third inspection, 4 The third step value is set in the second inspection, and the step value is set to 64 step values (180 degrees) in the 65th inspection (step 12). Then, the process proceeds to the next step 13.

  In step 13, the data is read from the area of the external memory where the test data is written in step 11 (step 13). Then, the process proceeds to the next step 14. In step 14, the data read in step 13 is compared with the expected value held in advance in the processor, and it is determined whether or not the 1-bit data has been successfully read (step 14). Then, the process proceeds to the next step 15.

  In step 15, it is determined whether or not the value of the access timing adjustment register is 180 degrees. If it is not 180 degrees, the value of the access timing adjustment register is incremented by one step value, and the processing from step 12 to step 14 is repeated until the value of the access timing adjustment register is changed from 0 degree to 180 degrees. To determine the window range of 1-bit data (step 15). Then, the process proceeds to the next step 16.

  In step 16, an intermediate value of the window range of 1-bit data obtained by the processing from step 11 to step 15 is calculated and set as the optimum value of the access timing adjustment register. The optimum value may be a value obtained by adding an adjustment value for adjusting the influence of variations such as temperature variation, voltage variation, process variation, etc. to the intermediate value of the window range (step 16). Then, the process proceeds to the next step 17.

  In step 17, the delay adjustment value calculated from the bit length information of each bit data signal and data strobe signal between the system LSI and the memory held by the processor at the optimum value in step 16 is applied to the bit data other than the above. The added value is set in the access timing adjustment register. As the optimum value, a value obtained by adding an adjustment value for adjusting the influence of variations such as temperature variation, voltage variation, and process variation may be used (step 17). Then, the process proceeds to the next step 18.

  In step 18, it is determined whether or not the setting of the access timing adjustment register for all bits has been completed. If all bits have not been set, the process is repeated until completion, and if all bits have been set, the process ends (step 18).

  As described above, the access timing adjustment device of the present invention reduces the processing time of the conventional access timing adjustment device by using the wiring length information of each bit data signal and data strobe signal between the system LSI and the memory. Is possible.

  In the system illustrated in FIG. 1, the nonvolatile memory 4 may be inside the system LSI 2, and conversely, the SRAM 23 may be an SRAM outside the system LSI 2.

  The access timing adjustment device according to the present invention can shorten the processing time of the conventional access timing adjustment device by using the wiring length information of each bit data signal and data strobe signal between the system LSI and the memory. Become.

  This is particularly useful in the field of system LSI technology for digital AV equipment.

1 Access timing adjustment device 2 System LSI
21 Processor 22 External bus controller 23 SRAM
24 memory controller 25 memory interface 3 external memory 31 external memory 1
32 External memory 2
4 Nonvolatile memory 41 Boot program 42 Access timing adjustment program 43 Application program

Claims (3)

An access timing adjustment device for adjusting the timing of accessing a plurality of external memories from a system LSI,
The access timing is a timing at which the system LSI latches data from the plurality of external memories,
The plurality of external memories are clock synchronous memories that perform input / output operations in synchronization with a clock signal,
The system LSI is connected to the plurality of external memories, and a memory interface that transmits and receives data in memory access; and
An access timing adjusting apparatus comprising: a control unit that adjusts an access timing by transmitting and receiving data a plurality of times from a memory interface connected to the plurality of external memories. The control means determines whether or not the access is successful while sequentially changing the access timing adjustment value for the specific bit data in the memory interface, and sets the access timing adjustment value within the range where the access is successful. 2. The access timing adjusting device according to claim 1, wherein The control means further includes an access timing adjustment result according to claim 2 for the bit data other than the bit data according to claim 2 in the memory interface, and a wiring length between the system LSI and the plurality of external memories. 2. The access timing adjustment device according to claim 1, wherein a value obtained by adding a delay adjustment value based on the access timing adjustment value is set as an access timing adjustment value.

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