JP2011229010A - Video signal processing apparatus, semiconductor integrated circuit and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce power consumption of a video signal processing apparatus, which subjects externally input analog video signals to signal processing, by discretionarily and respectively optimally controlling individual blocks included in an analog signal processing section to be on standby.SOLUTION: A timing control section 106 and a timing variation section 107 are provided in a video signal processing apparatus that subjects externally input analog video signals to signal processing. The timing control section 106 individually controls CDS/AGC part 101, ADC part 102, clamp part 103 and reference voltage generation part 104, which are included in an analog signal processing section 105, to switch between an operation state and a standby state. The timing variation section 107 varies timing of the switching control performed by the timing control section 106.

Description

  The present invention relates to a video signal processing apparatus that performs signal processing on an analog video signal, and more particularly to a video signal processing apparatus in an imaging apparatus such as a digital still camera or a video camera.

  Conventionally, in an imaging apparatus such as a digital still camera or a video camera, for example, Patent Document 1 discloses analog signal processing not only in an invalid frame period of a video signal output from an image sensor but also in a blanking period within an effective frame period. There has been proposed a technique for reducing the power consumption in a part and thereby further reducing the power consumption.

  An analog signal processing unit in the imaging apparatus of Patent Document 1 will be described with reference to FIG.

  In the figure, an analog signal processing unit 405 includes a CDS (correlated double sampling) / AGC (analog gain control) unit 401, an ADC (analog / digital conversion) unit 402, and a clamp unit 403, and is input from the timing control unit 406. Controlled by the control signal. The timing control unit 406 outputs an OB clamp signal S404 indicating an OB (Optical Black) period and a standby signal S406 as a power control signal. When the analog video signal S401 output from the image sensor (not shown) is input to the CDS / AGC unit 401, the clamp unit 403 displays the OB value (black reference level) of the analog video signal in the period indicated by the OB clamp signal S404. ) Is output to the CDS / AGC unit 401 so that the CDS / AGC unit 401 controls the level of the analog video signal so as to match the target value. The analog video signal S402 subjected to the OB correction in this way is input to the ADC unit 402, converted into a digital video signal S403, and output to the outside of the analog signal processing unit 405.

  The standby signal S406 output from the timing control unit 406 realizes the function stop of the analog signal processing unit 405 by switching to the standby state instead of powering down. That is, the power consumed by the analog signal processing unit 405 is stopped by stopping the function (operation called analog signal processing) while maintaining the power supply voltage supplied to the analog signal processing unit 405 and the internal voltage of the analog signal processing unit 405. Reduce. As a result, the transition of the standby state / operating state can be performed at a higher speed than the switching of the power ON / OFF, so that analog signal processing is performed without causing a delay not only in the invalid frame period but also in the blanking period of the effective frame It is possible to control the function stop / operation switching of the unit 405 to reduce power consumption.

JP 2008-289136 A

  As described above, in the video signal processing apparatus and the imaging apparatus disclosed in Patent Document 1, power consumption can be reduced by setting the analog signal processing unit 405 in the standby state during the blanking period within the effective frame period.

  However, in Patent Document 1, since the standby state is set only within the blanking period within the effective frame period, blocks that do not require operation among the plurality of blocks in the analog signal processing unit 405 are set outside the blanking period. Cannot enter standby state.

  In addition, since there is only one type of standby signal, each block provided in the analog signal processing unit cannot be individually set to the standby state.

  Further, since the standby signal timing variable function is not provided, it is not possible to set the optimum standby timing according to the characteristics of each block of the analog signal processing unit or the optimum standby timing according to the operation mode.

  Therefore, the imaging device of Patent Document 1 has a problem that it is difficult to further reduce power consumption.

  An object of the present invention is to enable each block of an analog signal processing unit to arbitrarily enter a standby state in a video signal processing apparatus, and not only in a blanking period of a video signal but also in a period other than the blanking period. Block that does not require operation can be put into the standby state, and by changing the timing of switching control between the operation state and the standby state, the optimum standby for each block provided in the analog signal processing unit An object of the present invention is to provide a low power consumption video signal processing apparatus and an image pickup apparatus which can set timing and thus can further reduce power consumption.

  In order to solve the above-mentioned problem, the video signal processing device according to claim 1 is a video signal processing device for performing signal processing on an analog video signal inputted from the outside, and for the analog video signal CDS / AGC unit that performs sampling and amplification, ADC unit that converts an analog video signal output from the CDS / AGC unit into a digital video signal, a clamp unit that adjusts the DC level of the video signal, and the CDS / AGC unit An analog signal processing unit having a reference voltage generating unit for supplying a reference voltage to each of the ADC unit and the clamping unit, and the CDS / AGC unit, the ADC unit, the clamping unit, and the reference voltage generating unit of the analog signal processing unit, respectively A timing control unit that performs control to switch between operating and a standby state, and switching by the timing control unit Characterized by comprising a timing variable section for varying the timing of the example control.

  According to a second aspect of the present invention, in the video signal processing device according to the first aspect, in the standby state, the analog signal processing unit stops the analog signal processing while retaining an internal signal. To do.

  According to a third aspect of the present invention, in the video signal processing device according to the second aspect, the analog signal processing unit is configured to hold a power supply voltage supplied to the analog signal processing unit as holding an internal signal in the standby state, It holds at least one of a clamp voltage output from the clamp unit, a voltage generated inside the ADC unit, and a voltage output from the reference voltage generation unit.

  According to a fourth aspect of the present invention, in the video signal processing device according to the second aspect, the analog signal processing unit is connected to the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit in the standby state. The supply of the clock signal is cut off without cutting off the supply of power.

  According to a fifth aspect of the present invention, in the video signal processing device according to the second aspect, in the standby state, the analog signal processing unit is at least one of the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit. A standby state is established by cutting off the supply of current to one.

  According to a sixth aspect of the present invention, in the video signal processing device according to the first aspect, the timing control unit is in a standby state for each of the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit from the outside. It is possible to control whether or not to do.

  According to a seventh aspect of the present invention, in the video signal processing device according to the first aspect, the timing variable section can vary the timing of switching control by the timing control section from the outside. And

  According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit including the video signal processing apparatus according to the first aspect.

  An image pickup apparatus according to a ninth aspect of the present invention provides a lens, an image pickup device that converts light transmitted through the lens into an analog video signal, and signal processing on the analog video signal output from the image pickup device. 1. A video signal processing apparatus according to claim 1.

  As described above, in the first to ninth aspects of the invention, the timing control unit has a plurality of standby signals, for example, and the CDS / AGC unit, ADC unit, clamp unit, and reference voltage generation unit of the analog signal processing unit are arbitrarily set individually. Can be in standby state.

  In addition, the CDS / AGC unit included in the analog signal processing unit can be changed by the timing variable unit, so that the CDS / AGC unit, ADC unit, etc. included in the analog signal processing unit can be controlled to be switched between the operation state and the standby state. The CDS / AGC unit and the like can be individually set in a standby state in accordance with individual characteristics such as the optimum period, so that power consumption can be reduced.

  Therefore, the CDS / AGC unit, the ADC unit, and the like that do not require operation can be set in a standby state even during a period other than the blanking period within the effective frame period, and power consumption can be reduced.

  The present invention can be realized not only as the video signal processing apparatus as described above, but also as a semiconductor integrated circuit such as an LSI mounted with the video signal processing apparatus having the above-described configuration, or a lens and the lens. As an imaging device such as a digital camera comprising an image sensor that converts light transmitted through the image sensor into an analog video signal and a video signal processor as described above that performs signal processing on the analog video signal output from the image sensor It can also be realized.

  As described above, according to the video signal processing device of the inventions of claims 1 to 9, not only the blanking period of the video signal but also the blocks that do not require operation in the analog signal processing unit are not included in the blanking period. The standby state can be set, the CDS / AGC unit and the ADC unit provided in the analog signal processing unit can be individually set to the standby state, and the timing for switching between the operation state and the standby state Therefore, it is possible to set an optimum standby period. Therefore, it is possible to provide a video signal processing apparatus that reduces power consumption in the analog signal processing unit and realizes further lower power consumption. In addition, it is possible to provide a low power consumption LSI or an imaging device equipped with such a video signal processing device.

  In particular, in the present day when battery-driven portable devices equipped with an imaging device have become widespread, the present invention can further reduce the power consumption of portable devices, and its practical value is extremely high.

It is a figure which shows the structure of the video signal processing apparatus of the 1st Embodiment of this invention. It is a figure explaining the blanking period and OB period of a video signal. It is a timing chart figure which shows the standby operation | movement of the video signal processing apparatus in the embodiment. It is a figure which shows the structure of the imaging device in the 2nd Embodiment of this invention. It is a figure which shows the structure of the video signal processing apparatus of a prior art. It is a timing chart figure which shows the standby operation | movement of the conventional video signal processing apparatus.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a configuration of a video signal processing apparatus according to an embodiment of the present invention. The video signal processing apparatus of FIG. 1 is a semiconductor integrated circuit such as an LSI that performs signal processing such as noise removal, amplification, and A / D conversion on an analog video signal input from the outside (image sensor). An analog signal processing unit 105, a timing control unit 106, and a timing variable unit 107 are provided.

  The analog signal processing unit 105 is a circuit that performs various kinds of signal processing on an analog video signal S101 output from an image sensor represented by a CCD or MOS sensor and outputs a digital video signal S103, and is a CDS / AGC. Unit 101, ADC unit 102, clamp unit 103, and reference voltage generation unit 104.

  The CDS / AGC unit 101 includes two circuits for sampling and amplifying the analog video signal S101, that is, a CDS circuit and an AGC circuit. The CDS circuit is a correlated double sampling circuit that suppresses the influence of reset noise by sampling the difference between the reset level and the pixel level of the image sensor indicated by the input analog video signal S101. The AGC circuit is an analog gain control circuit that functions as a variable gain amplifier that amplifies the output signal from the CDS circuit according to its magnitude.

  The timing control unit 106 is an OB clamp signal S104 indicating an OB period and a control signal (ie, a signal indicating a standby period) for switching between the analog signal processing unit 105 and the standby state. Four types of standby signals S106, S107, S108, and S109 are generated, and each of the standby signals is output to the analog signal processing unit 105. The blanking period includes a vertical blanking period and a horizontal blanking period as shown in FIG. Further, as shown in FIG. 2, the OB period is a period in which a black reference signal is output from the image sensor, and includes a vertical OB period and a horizontal OB period.

  Further, the timing variable unit 107 outputs a signal S110 for setting the start timing and end timing of the four types of standby signals S106, S107, S108, and S109 output from the timing control unit 106 to the timing control unit 106.

  In addition, the clamp unit 103 is a circuit that outputs a clamp voltage for making the black reference level of the analog video signal S102 output from the CDS / AGC unit 101 constant, specifically, the OB clamp signal S104. The CDS / AGC unit 101 outputs a clamp voltage S105 for controlling the level of the analog video signal in the CDS / AGC unit 101 so that the OB value in the period indicated by As a result, the analog video signal S102 subjected to the OB correction is input to the ADC unit 102.

  In FIG. 1, the ADC unit 102 converts an input analog video signal S102 into a digital video signal S103, and outputs the digital video signal S103 to the outside of the analog signal processing unit 105.

  Further, the reference voltage generator 104 outputs a plurality of reference voltages serving as a reference for the blocks 101 to 103 and the video signal processing to the CDS / AGC unit 101, the ADC unit 102, and the clamp unit 103. .

  In the video signal processing apparatus having such a configuration, the function stop of the analog signal processing unit 105 is realized as follows. Details thereof will be described with reference to FIGS. 1, 3, and 6.

  Four standby signals output from the timing control unit 106, that is, a standby signal S106 output toward the CDS / AGC unit 101, a standby signal S107 output from the timing control unit 106 toward the ADC unit 102, and timing With respect to the standby signal S109 output from the control unit 106 toward the clamp unit 103 and the standby signal S108 output from the timing control unit 106 toward the reference voltage generation unit 104, the CDS / AGC unit 101 changes from the standby state to the normal operation. The time until return is t1, the time until the ADC unit 102 returns from the standby state to the normal operation is t2, the time until the clamp unit 103 returns from the standby state to the normal operation is t3, and the reference voltage generation unit 104 is from the standby state. Normal The time to return to work and t4. In the present embodiment, the return time t2 of the ADC unit 102 is assumed to be the longest, and t2> t3> t4> t1.

  Here, a case where one standby signal is common to each of the blocks 101, 102, and 103 and the standby signal output timing and end timing variable functions are not provided will be described with reference to FIG.

  The blanking period is a period in which analog signal processing is not required, and there is a standby signal start timing simultaneously with or immediately after the start of the blanking period. The CDS / AGC unit 101, the ADC unit 102, the clamp unit 103, the reference voltage The generation unit 104 enters a standby state.

  Since the CDS / AGC unit 101, the ADC unit 102, and the reference voltage generation unit 104 need to return to the normal operation before the effective pixel period after the standby state is set, the end timing of the standby signal is from the standby state. The time until returning to the normal operation is determined by the time t2 of the ADC unit 102 having the longest time.

  Since one standby signal is common to each block, the other CDS / AGC unit 101, clamp unit 103, and reference voltage generation unit 104 are also released from the standby state at the same timing as the ADC unit 102. Therefore, the CDS / AGC unit 101 uses tbl-ts0-t1, the reference voltage generation unit 104 uses tbl-ts0-t3, and the clamp unit 103 uses thd-ts0-tob-t4. A period that can be assumed to occur). Here, tbl is a blanking period, ts0 is a Lo period (standby period) of a standby signal, thd is one period of horizontal synchronization, and tob is an OB period. Further, the operating frequency fck is set to a high frequency (for example, fck = 45 MHz), and this case is set as a high-speed operation mode.

  Next, when there is a low-speed operation mode with a low operating frequency (half frequency fck = 22.5 MHz of the high-speed operation mode), the output and end timing of the standby signal of the ADC unit 102 is the high-speed operation mode. Since the set timing is reached, the standby period is ts0 × 2. Therefore, the ADC unit 102 has a useless operation period of 2 · tbl−2 · ts0−t2 (a period in which the standby state can be originally set). appear. Similarly, the CDS / AGC unit 101 has 2 · tbl-2 · ts0-t1, the reference voltage generator 104 has 2 · tbl-2 · ts0-t3, and the clamp unit 103 has 2 · thd-2 · ts0-t1. A useless operation period of 2 · tob−t4 (a period during which the standby state can be originally set) occurs.

  Therefore, in the present embodiment, a plurality of types (four types) of standby signals are provided, and each of the four blocks 101 to 104 is independently set to a standby state, and further, a standby signal output and end timing variable function is provided. It is said. Hereinafter, the operation in this embodiment will be described with reference to FIGS. 1 and 3.

  For the standby signal S106 output to the CDS / AGC unit 101, the end timing of the standby signal S106 is set before the time t1 when the effective pixel period is reached (standby period ts1). Thereby, it is possible to reduce power consumption in an optimum state as the CDS / AGC unit 101.

  Similarly, for the standby signal S107 output to the ADC unit 102, the end timing of the standby signal S107 is set before the time t2 when the effective pixel period is reached (standby period ts0). Thereby, it is possible to reduce power consumption in an optimum state as the ADC unit 102.

  Further, for the standby signal S108 to be output to the reference voltage generation unit 104, the end timing of the standby signal S108 is set before the time t3 when the effective pixel period is reached (standby period ts3). Thereby, low power consumption can be achieved in an optimum state as the reference voltage generation unit 104.

  In addition, since the clamp unit 103 mainly operates in the OB period, for the standby signal S109 output to the clamp unit 103, the end timing of the standby signal S109 is set before the time t4 that becomes the OB period (standby). Period ts4). Thereby, it is possible to reduce power consumption in an optimum state as the clamp unit 103.

  Further, even when there is a low-speed operation mode (operation frequency fck = 22.5 MHz) that operates at a lower speed than the high-speed operation mode (operation frequency fck = 45 MHz) state of the operation, the CDS / AGC unit is the same as described above. For the standby signal S106 output to 101, the end timing of the standby signal S106 is set before the time t1 during which the effective pixel period is reached (standby period ts1 × 2 + α1). Thereby, it is possible to reduce power consumption in an optimum state as the CDS / AGC unit 101.

  Similarly, for the standby signal S107 output to the ADC unit 102, the end timing of the standby signal S107 is set before the time t2 when the effective pixel period is reached (standby period ts0 × 2 + α2). Thereby, it is possible to reduce power consumption in an optimum state as the ADC unit 102.

  Further, for the standby signal S108 to be output to the reference voltage generation unit 104, the end timing of the standby signal S108 is set before the time t3 that becomes the effective pixel period (standby period ts3 × 2 + α3). Thereby, low power consumption can be achieved in an optimum state as the reference voltage generation unit 104.

  In addition, since the clamp unit 103 mainly operates during the OB period, the standby signal S109 output to the clamp unit 103 is set to have an end timing of the standby signal S109 before the time t4 when the OB period is reached (standby period). ts4 × 2 + α4). Thereby, it is possible to reduce power consumption in an optimum state as the clamp unit 103.

  In contrast to the case where the standby state is set as described above and one standby signal is common to each block and the standby signal output and end timing variable functions are not provided, in this embodiment, the standby period In the high-speed operation mode of the CDS / AGC unit 101, power consumption is reduced by tbl-ts0-t1, and in the low-speed operation mode of the CDS / AGC unit 101, power consumption is reduced by 2 · tbl-2 · ts0-t1. Similarly, in the high-speed operation mode of the reference voltage generation unit 104, power consumption is reduced by tbl-ts0-t3, and in the low-speed operation mode of the reference voltage generation unit 104, power consumption is reduced by 2 · tbl-2 · ts0-t3. In the high-speed operation mode of the clamp unit 103, power consumption is reduced by thd-ts0-tob-t4, and in the low-speed operation mode of the clamp unit 103, power consumption is reduced by 2 · thd-2 · ts0-2 / tob-t4. In the low-speed operation mode of the ADC unit 102, the power consumption is reduced by the time of 2 · tbl-2 · ts0-t2.

  The above-described embodiment is merely an example of the present invention, and the present invention is not limited to the above-described embodiment. Forms obtained by making various modifications to the embodiment and forms realized by arbitrarily combining the components in the embodiment are also included in the present invention.

  For example, not only the case where each block 101 to 104 in the analog signal processing unit 105 is provided with an individual standby signal but also a configuration in which a standby signal for simultaneously controlling a plurality of some blocks may be provided.

  The standby state may be configured not only to completely stop the block operation but also to stop only a part of the analog signal processing function while maintaining the internal signal state. As the holding of the state, for example, the power supply voltage supplied to the analog signal processing unit 105, the voltage generated inside the ADC unit 102, the clamp voltage output from the clamp unit 103, and the reference voltage generation unit 104 are output. It is sufficient to hold at least one of the voltages.

  Further, the means for setting the analog signal processing unit 105 to the standby state may be realized in any way, for example, supply of power to the CDS / AGC unit 101, the ADC unit 102, the clamp 103 unit, and the reference voltage generation unit 104. The supply of the clock signal may be cut off without cutting off, or the supply of current to at least one of the CDS / AGC unit 101, the ADC unit 102, and the like may be cut off to enter a standby state.

  In addition, the timing control unit 106 can be controlled from the outside to determine whether the CDS / AGC unit 101, the ADC unit 102, the clamp unit 103, and the reference voltage generation unit 104 are in a standby state. Alternatively, the timing variable unit 107 may be configured such that the timing of the switching control by the timing control unit 106 is variable from the outside.

  As described above, according to the present invention, it is possible to have a plurality of standby signals, each block of the analog signal processing unit can be arbitrarily set to the standby state, and the start timing or end timing of the standby signal can be set. By making it variable, it is possible to set an optimum standby timing for each block of the analog signal processing unit, thereby further reducing power consumption as compared with the prior art.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the present embodiment, an imaging apparatus such as a digital camera is realized by using the video signal processing apparatus of the first embodiment.

  FIG. 4 shows a configuration of an imaging apparatus 300 that mounts the video signal processing apparatus in the first embodiment and realizes low power consumption. The imaging apparatus 300 includes a lens 301, an imaging element 302, a memory 303, a digital signal processing unit 304, and a display device 305 in addition to the video signal processing apparatus in the first embodiment.

  The lens 301 is an optical element that collects light. The imaging element 302 is a CCD, C-MOS sensor, or the like that converts light transmitted through the lens 301 into an analog video signal. The memory 303 is a DRAM or the like that stores images. The display device 305 is an LCD (liquid crystal display device) or the like that displays an image. The digital signal processing unit 304 generates image data by performing signal processing such as color adjustment and compression on the digital video signal S103 output from the analog signal processing unit 105 of the video signal processing device, and stores the image data in the memory 303. Or a DSP (digital signal processor) 304a that outputs to the display device 305, and a CPU 304b that controls each component.

  Such an image pickup apparatus 300 can arbitrarily set each of the blocks 101 to 104 of the analog signal processing unit 105 to a standby state, and makes the standby signal timing variable so that it is optimal for each block. Standby timing can be set, and power consumption is lower than before.

  Needless to say, the video signal processing device mounted on the imaging device is not limited to the video signal processing device in the second embodiment, and may be a modified example thereof.

  As described above, the present invention is a video signal processing apparatus that performs signal processing on an analog video signal, and an imaging apparatus equipped with the video signal processing apparatus, for example, a digital still camera, a video camera, a television, a medical device This is useful when applied to general imaging devices such as industrial cameras.

DESCRIPTION OF SYMBOLS 101 CDS / AGC part 102 ADC part 103 Clamp part 104 Reference voltage generation part 105 Analog signal processing part 106 Timing control part 107 Timing variable part 300 Imaging device 301 Lens 302 Imaging element 303 Memory 304 Digital signal processing part 304a DSP
304b CPU
305 Display devices S101, S401 Analog video signal S102, S402 Analog video signal (CDS / AGC voltage)
S103, S403 Digital video signal S104, S404 OB clamp signal S105, S405 Clamp voltage S106 Standby signal 1
S107 Standby signal 2
S108 Standby signal 3
S109 Standby signal 4
S110 Standby timing setting signal S406 Standby signal

Claims (9)

A video signal processing device that performs signal processing on an analog video signal input from the outside,
A CDS / AGC unit that samples and amplifies the analog video signal, an ADC unit that converts the analog video signal output from the CDS / AGC unit into a digital video signal, and a clamp unit that adjusts the DC level of the video signal And an analog signal processing unit having a reference voltage generating unit for supplying a reference voltage to each of the CDS / AGC unit, the ADC unit, and the clamp unit;
A timing control unit that performs control to switch between the operation of the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit of the analog signal processing unit or a standby state;
A video signal processing apparatus comprising: a timing variable unit that varies a timing of switching control by the timing control unit. The video signal processing apparatus according to claim 1, wherein
The analog signal processor is
In the standby state, the analog signal processing is stopped while retaining the internal signal. The video signal processing apparatus according to claim 2, wherein
The analog signal processor is
As the holding of the internal signal in the standby state, the power supply voltage supplied to the analog signal processing unit, the clamp voltage output from the clamp unit, the voltage generated inside the ADC unit, and the reference voltage generation unit A video signal processing apparatus characterized by holding at least one of output voltages. The video signal processing apparatus according to claim 2, wherein
The analog signal processor is
In the standby state, the clock signal supply is cut off without cutting off the power supply to the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit. The video signal processing apparatus according to claim 2, wherein
The analog signal processor is
The video signal processing apparatus according to claim 1, wherein in the standby state, the standby state is established by cutting off current supply to at least one of the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit. The video signal processing apparatus according to claim 1, wherein
The timing controller is
A video signal processing apparatus characterized in that it is possible to control from the outside whether the CDS / AGC unit, the ADC unit, the clamp unit, and the reference voltage generation unit are in a standby state. The video signal processing apparatus according to claim 1, wherein
The timing variable section is
A video signal processing apparatus characterized in that the timing of switching control by the timing control unit can be varied from the outside. A semiconductor integrated circuit comprising the video signal processing device according to claim 1. A lens,
An image sensor that converts light transmitted through the lens into an analog video signal;
An image pickup apparatus comprising: the image signal processing apparatus according to claim 1, wherein signal processing is performed on an analog image signal output from the image pickup element.

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