JP2011227592A - Data processor and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor capable of allowing flexible mapping of a program, which is initially loaded from an external memory, on the external memory using a simple configuration.SOLUTION: A data processor which executes a program initially loaded from an external memory to a RAM is provided with a boot loader controller. The boot loader controller reads transfer control information from the external memory in response to a given reset instruction, downloads a program from the external memory using address information indicated in the read transfer control information, transfers the downloaded program to the RAM, and instructs a central processing unit to cancel the given reset instruction upon completion of the transfer. Thus, it is only necessary to provide transfer control information on the basis of program mapping on the external memory, which would allow flexible mapping of programs on an external memory just with a simple configuration.

Description

  The present invention relates to a data processor that executes a program that is read from an external memory and stored in a RAM, and a data processing system that uses the data processor for controlling an input device, for example, a PC (personal computer) keyboard and data for power control. The present invention relates to a technology effective when applied to a processor and a PC on which the processor is mounted.

  When the program to be executed by the data processor is stored in the electrically rewritable ROM on-chip in the data processor, the time and cost for designing the mask ROM can be saved individually, but it can be electrically rewritten. The cost increases by installing a simple ROM. In this regard, there is a data processor that employs a configuration in which a program is read from an external memory into a RAM and executed.

  In Patent Document 1, in a microcomputer composed of a CPU, a serial flash interface circuit, a program transfer circuit, a program built-in RAM, a write mask circuit, and the like, a serial flash memory is connected to the outside of the microcomputer, When the power is turned on, the program is read from the serial flash memory and written into the program internal RAM before the CPU operates. A configuration is described in which the CPU executes a program on the program internal RAM and prohibits writing to the program internal RAM as necessary.

  In Patent Document 2, a boot loader that is an interface for a serial flash memory is provided in a system LSI, a boot program is read from the serial flash memory, the read boot program is executed, and a main program in the serial flash memory is executed by an SDRAM. Describes the configuration to be copied.

JP 2003-141096 A JP 2009-169485 A

  However, in the technique described in Patent Document 1, when the source address for reading the program to be transferred to the RAM is arbitrarily set, it is necessary to control using the MMU, and the MMU is used before releasing the reset of the CPU. In this case, the MMU must be set using special means. The technique described in Patent Document 2 is configured to download the main program according to the contents of the boot program, and does not take into consideration the arbitrary setting of the arrangement of the boot program on the serial flash memory. When the main program is arbitrarily arranged on the flash memory, it must be done in the description of the boot program, and it is difficult to respond flexibly.

  An object of the present invention is to provide a data processor that can allow free mapping on an external memory to a program to be initially loaded from the external memory with a simple configuration.

  Another object of the present invention is to provide a data processing system that can allow free mapping on an external memory to a program that is initially loaded from the external memory, and that can contribute to a reduction in system cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, in response to a predetermined reset release instruction, the transfer control information is read from the external memory to the data processor that executes the program initially loaded from the external memory to the RAM, and the address information indicated by the read transfer control information is displayed. Based on this, a boot loader controller is used that downloads a program from the external memory, transfers the downloaded program to the RAM, and after this transfer is completed, gives a reset release instruction to the central processing unit.

  Since the program is downloaded based on the address information indicated by the transfer control information, it is sufficient to prepare transfer control information corresponding to the mapping on the external memory for the program, and free mapping on the external memory for the program. It can be tolerated with a simple configuration. In this respect, the system cost can be reduced.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, free mapping on the external memory can be permitted with a simple configuration for a program that is initially loaded from the external memory.

  This can contribute to a reduction in system cost.

FIG. 1 is a block diagram illustrating a data processor according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating a more detailed configuration of the boot loader controller. FIG. 3 is an explanatory diagram showing an example of program transfer information. FIG. 4 is a flowchart of download processing by the boot loader controller. FIG. 5 is a block diagram illustrating a data processor according to the second embodiment. FIG. 6 is a block diagram illustrating a data processor according to the third embodiment. FIG. 7 is an explanatory diagram illustrating the configuration of program transfer information used in the fourth embodiment. FIG. 8 is a timing chart illustrating the access operation timing for the serial flash memory 101 when the access size is 1/16 of the program size and the program is downloaded. FIG. 9 is a block diagram illustrating a data processor according to the fifth embodiment. FIG. 10 is an explanatory diagram showing whether initialization is performed for each reset factor in units of functional blocks (CPU, boot loader controller, RAM, etc.). FIG. 11 is an explanatory diagram illustrating the relationship between the arrangement of programs on the serial flash memory and the arrangement of programs downloaded to the RAM according to the seventh embodiment. FIG. 12 is a block diagram illustrating a schematic configuration example of a notebook PC that employs the data processor described in the embodiment as a keyboard and a controller for power control.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Program download based on read transfer control information>
A data processor (102, 102A to 102C) according to a representative embodiment of the present invention is a data processor that executes a program (131) transferred from an external memory (101) to a RAM (105). A central processing unit (103) for starting execution of a program with a predetermined address in the RAM as a start address in response to a reset release instruction. Further, in response to a predetermined reset release instruction, the transfer control information (130) is read from the external memory, and the program is downloaded from the external memory based on the address information indicated by the read transfer control information. A boot loader controller (104) is provided for transferring a program to the RAM and giving a reset release instruction to the central processing unit after the transfer is completed.

  Since the program is downloaded based on the address information indicated by the transfer control information, it is sufficient to prepare transfer control information corresponding to the mapping on the external memory for the program, and free mapping on the external memory for the program. It can be tolerated with a simple configuration. In this respect, the system cost can be reduced.

[2] <Program transfer dedicated path to RAM>
The data processor according to item 1, further comprising a dedicated path (108) for transferring a program from the boot loader controller to the RAM.

  Compared to the case of transferring via the common bus, the boot loader controller does not need to have a common bus access function, and the circuit scale required for transfer control can be reduced.

[3] <Detect error in program transfer>
In the data processor according to item 1 or 2, the boot loader controller has an error detection circuit (122) that detects the presence or absence of a transfer error in the downloaded program.

  It is possible to prevent malfunctions due to transfer errors.

[4] <Specifying retry count when program transfer error is detected>
In the data processor according to item 3, when the boot loader controller detects an error in program transfer by the error detection circuit, the program is executed until it is detected that there is no transfer error up to the number of times specified by the transfer control information. Retry download.

  By permitting the retry, a transfer error due to a temporary factor that can be eliminated can be easily eliminated.

[5] <Enable / disable switching of error detection>
In the data processor according to item 3 or 4, the boot loader controller performs a detection operation when an instruction to validate the detection operation by the error detection circuit (activation of CRCEN) is given.

  In the case where processing is performed in an environment in which transfer errors hardly occur, it is possible to give priority to speeding up the boot operation.

[6] <Specify program transfer size>
In the data processor according to any one of Items 1 to 5, the boot loader controller starts downloading a program from a start address indicated by the transfer control information, and downloads a program having a capacity indicated by the transfer control information.

  The transfer control information is not limited to having a start address and an end address.

[7] <Program transfer end notification>
In the data processor according to any one of Items 1 to 5, the boot loader controller notifies the outside of the transfer of the program to the RAM (PGMTR).

  The state in which the program can be executed by the data processor can be quickly ascertained externally, and can be applied to trigger the start of operation or initialization of an upper layer system connected to the data processor.

[8] <Notification of program transfer failure>
In the data processor according to any one of Items 3 to 7, the boot loader controller notifies the outside of failure to transfer the program to the RAM (BLERR).

  A state in which the program cannot be executed by the data processor can be quickly ascertained externally, and can be applied to display on an indicator or a trigger for recovery processing.

[9] <Built-in RAM>
In the data processor according to any one of Items 1 to 8, the RAM is a RAM built in the data processor.

[10] <External RAM>
In the data processor according to any one of Items 1 to 8, the RAM is a RAM connected to the outside of the data processor.

  It can cope with a case where the capacity of the built-in RAM is small.

[11] <Adjustment of program transfer time>
In the data processor according to any one of Items 1 to 10, the boot loader controller downloads the program in synchronization with a frequency specified by the transfer control information (a frequency specified by a synchronization clock).

  Based on the transfer control information, it is possible to adjust the time required to transfer the program from the external memory to the RAM. Since the reset release to the CPU is instructed when the transfer of the program from the external memory to the RAM is completed, the reset of the CPU is canceled by the boot loader controller for the time required to complete the initialization operation inside and outside the data processor. You can avoid timing too early or too late.

[12] <Adjustment of program transfer time>
In the data processor according to any one of Items 1 to 10, the boot loader controller downloads the program in a plurality of times in units of a data size (transfer unit) specified by the transfer control information.

  If the data size unit is reduced, the number of program download operations to be divided increases, so that the time required to complete the program download increases. Therefore, similarly to the above, it is possible to adjust the time required for transferring the program from the external memory to the RAM based on the transfer control information, and the time required for completing the initialization operation inside and outside the data processor. On the other hand, the reset release timing of the CPU by the boot loader controller can be prevented from being too early or too late.

[13] <Restart level selection by reset factor>
In the data processor according to any one of Items 1 to 12, the predetermined reset release instruction responded by the boot loader controller is a reset factor (RES, RES_LVD) for which the reset release instruction does not guarantee the storage information of the RAM. In response to a reset release instruction corresponding to a reset factor (RES_WDT) that guarantees retention of stored information in the RAM, the CPU executes the program in the RAM in response to the reset release instruction. .

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[14] <Selection of restart level by reset factor>
In the data processor according to any one of Items 1 to 12, the predetermined reset release instruction responded by the boot loader controller is an instruction corresponding to a reset factor (rising of res1) by a reset signal (RES) supplied from the outside, and An instruction (rising of res1_LVD) corresponding to a reset factor by an internal reset signal (RES_LVD) due to a decrease in power supply voltage level is included. The instruction (res1_WDT) corresponding to the reset factor by the internal reset signal (RES_WDT) due to timeout of the watchdog timer is not included. When the transfer of the program from the boot loader controller is completed, the RAM is write protected, and the write protection is performed by a reset instruction by a reset signal supplied from the outside and a reset instruction by an internal reset signal by the power supply voltage level drop. Canceled.

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[15] <Restart level selection by reset factor>
Item 12. The reset factor activation level control register for setting whether to download a program to the RAM using the boot loader controller for each reset factor when there are a plurality of reset factors in the data processor of any one of Items 1 to 12. 123.

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[16] <Scrambled program download>
In the data processor according to any one of Items 1 to 15, the address information indicated by the transfer control information (130) is one of predetermined programs (131A to 131D) to be downloaded that are discretely mapped on an external memory. Address information indicating the location of the part program (131A). A part of the predetermined program is a boot program downloaded by the boot loader controller, and the rest of the predetermined program is downloaded from the external memory by the central processing unit executing the boot program and transferred to the RAM. Is a discretely mapped program.

  As a result, the predetermined program to be downloaded can be scrambled and stored on the external memory, so that the security of the program can be improved in that the theft or illegal use of the program can be suppressed.

[17] <Program download based on read transfer control information>
A data processing system according to another embodiment of the present invention includes a data processor (102 and the like) that controls an input device connected to the outside by executing a program transferred from an external memory to a RAM; An input / output controller hub (201, 205) connected to the data processor via an LPC bus; and a main processor (200) connected to the input / output controller hub via a system bus. The data processor has a central processing unit that starts execution of a program using a predetermined address in the RAM as a start address in response to a given reset release instruction. Further, the data processor reads transfer control information from the external memory in response to a predetermined reset release instruction, downloads a program from the external memory based on address information indicated by the read transfer control information, A downloaded program is transferred to the RAM, and after the transfer is completed, a boot loader controller is provided that gives a reset release instruction to the central processing unit.

  Since the program is downloaded based on the address information indicated by the transfer control information, it is sufficient to prepare transfer control information corresponding to the mapping on the external memory for the program, and free mapping on the external memory for the program. It can be tolerated with a simple configuration. In this respect, the system cost of the data processing system can be reduced.

[18] <Detection of program transfer error>
In the data processor of item 17, the boot loader controller has an error detection circuit (122) for detecting the presence or absence of a transfer error in the downloaded program.

  It is possible to prevent malfunctions due to transfer errors.

[19] <Specifying the number of retries when a program transfer error is detected>
In the data processor according to item 17, when the boot loader controller detects an error in program transfer by the error detection circuit, the boot loader controller sets a program until the number of times specified by the transfer control information is detected as an upper limit until no transfer error is detected. Retry download.

  By permitting the retry, a transfer error due to a temporary factor that can be eliminated can be easily eliminated.

[20] <Enable / disable switching of error detection>
In the data processor according to item 18 or 19, the boot loader controller performs a detection operation when an instruction to validate the detection operation by the error detection circuit (activation of CRCEN) is given.

  In the case where processing is performed in an environment in which transfer errors hardly occur, it is possible to give priority to speeding up the boot operation.

[21] <Specifying program transfer size>
In the data processor according to any one of Items 17 to 20, the boot loader controller starts downloading a program from a start address indicated by the transfer control information, and downloads a program having a capacity indicated by the transfer control information.

  The transfer control information is not limited to having a start address and an end address.

[22] <Program transfer end notification>
In the data processing system according to items 17 to 21, the boot loader controller notifies the outside of the transfer of the program to the RAM.

  The input / output controller hub and further the main processor upstream thereof can quickly grasp the program executable state by the data processor, and trigger the operation start or initialization of the higher-level system connected to the data processor. It becomes applicable to.

[23] <Notification of program transfer failure>
In the data processing system according to Items 18 to 22, the boot loader controller notifies the outside of the failure to complete the transfer of the program to the RAM.

  It becomes possible to quickly grasp the state in which the program cannot be executed by the data processor by the input / output controller hub and the main processor upstream thereof, and it can be applied to display on an indicator or a trigger for recovery processing. Become.

[24] <Adjustment of program transfer time>
In the data processing system according to any one of items 17 to 23, the boot loader controller downloads the program in synchronization with a frequency specified by the transfer control information.

  Based on the transfer control information, it is possible to adjust the time required to transfer the program from the external memory to the RAM. Since the reset release to the CPU is instructed upon completion of the transfer of the program from the external memory to the RAM, the input / output controller hub is further provided for the time required for the internal initialization by the data processor reset instruction. It is possible to prevent the boot loader controller from releasing the reset of the CPU too early or too late with respect to the time required to initialize the connected device.

[25] <Adjustment of program transfer time>
In the data processing system according to any one of items 17 to 23, the boot loader controller downloads the program in a plurality of times in units of data size specified by the transfer control information.

  If the data size unit is reduced, the number of program download operations to be divided increases, so that the time required to complete the program download increases. Therefore, as described above, it is possible to adjust the time required to transfer the program from the external memory to the RAM based on the transfer control information, and to the time required until the internal is initialized by the reset instruction of the data processor. In contrast, it is possible to prevent the boot loader controller from releasing the reset of the CPU too early or too late with respect to the time required to initialize the device connected to the input / output controller hub.

[26] <Selection of restart level depending on reset factor>
In the data processing system according to any one of Items 17 to 25, the predetermined reset release instruction responded by the boot loader controller corresponds to a reset factor for which the reset instruction does not guarantee the storage information of the RAM, In response to a reset release instruction corresponding to a reset factor that guarantees retention of storage information in the RAM, the CPU executes the program in the RAM in response to the reset release instruction.

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[27] <Selection of restart level depending on reset factor>
26. In the data processing system according to any one of items 17 to 25, the predetermined reset release instruction to which the boot loader controller responds is an instruction corresponding to a reset factor by a reset signal supplied from the outside, and an internal reset by a power supply voltage level drop The instruction corresponding to the reset factor by the signal is included, and the instruction corresponding to the reset factor by the internal reset signal due to the timeout of the watchdog timer is not included. The RAM is write protected when the transfer of the program from the boot loader controller is completed, and the write protection is performed by a reset instruction by a reset signal supplied from the outside and a reset instruction by an internal reset signal by the power supply voltage level drop. Canceled.

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[28] <Selection of restart level depending on reset factor>
Item 20. The reset factor activation level control register for setting whether to download a program to the RAM using the boot loader controller for each reset factor when there are a plurality of reset factors in the data processor of any one of items 17 to 25. have.

  Whether or not to download the program to the RAM using the boot loader controller can be appropriately controlled according to the reset factor.

[29] <Scrambled program download>
In the data processing system according to any one of Items 17 to 28, the address information indicated by the transfer control information is address information indicating the location of a predetermined program to be downloaded that is discretely mapped on the external memory. A part of the predetermined program is a boot program downloaded by the boot loader controller, and the rest of the predetermined program is downloaded from the external memory by the central processing unit executing the boot program and transferred to the RAM. Is a discretely mapped program.

  As a result, the predetermined program to be downloaded can be scrambled and stored on the external memory, so that the security of the program can be improved in that the theft or illegal use of the program can be suppressed.

2. Details of Embodiments Embodiments will be further described in detail.

[Embodiment 1]
FIG. 1 illustrates a data processor according to Embodiment 1 of the present invention. The data processor (MCU) 102 is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique or the like. The data processor 102 executes a program initially loaded from an external memory connected to the outside, for example, the serial flash memory 101.

  The data processor 102 includes a central processing unit (CPU) 103, a RAM 105, a system controller (SYSC) 106, a boot loader controller (BLC) 104, and the like that are representatively shown. The CPU 103 accesses the program via the bus 107 using a predetermined address on the RAM 105 as a start address, thereby executing the sequentially fetched instructions.

  The SYSC 106 generates an internal initialization signal (reset signal) based on a reset signal RES supplied from the outside of the data processor 102 and other reset signals (not shown) generated inside the data processor. Based on a mode signal (not shown) supplied from the outside of the data processor 102, the operation mode of the data processor is controlled.

  The boot loader controller 104 is connected to the serial flash memory 101 via a serial flash memory interface circuit as a memory controller (not shown). The boot loader controller 104 reads transfer control information (also referred to as program transfer information) 130 from the serial flash memory 101 in response to a reset release instruction caused by a change of the initialization signal res1 output from the SYSC 106 to a high level. The program 131 is downloaded from the serial flash memory 101 based on the address information indicated by the read transfer control information 130, and the downloaded program is transferred to the RAM 105. After completing this transfer, the boot loader controller 104 instructs the central processing unit to cancel the reset by changing the initialization signal res2 to high level. The initialization signal res2 is set to the low level in synchronization with the change of the initialization signal res1 to the low level, thereby instructing the CPU 103 to reset, and the change of the initialization signal res2 to the high level is instructed to release the reset. As a result, the CPU 103 starts fetching an instruction on the RAM 105 using a predetermined memory address as a start address, and starts executing the initially loaded program.

  Since the program 131 is downloaded based on the address information indicated by the transfer control information 130, the transfer control information 130 corresponding to the mapping on the serial flash memory 101 may be prepared for the program 131, and the flash memory is stored in the data processor 102. Does not have to be on-chip. Furthermore, free mapping on the serial flash memory 101 can be allowed for the program 130 with a simple configuration. In this respect, the system cost of the data processing system to which the data processor 102 is applied can be reduced.

  FIG. 2 illustrates a more detailed configuration of the boot loader controller 104. The boot loader controller 104 is connected to the serial flash memory 101 via the serial flash memory interface circuit 110. The serial flash memory 101 includes serial terminals for chip select, memory clock, data input, and data output as external interface terminals. The serial flash memory interface circuit 110 receives an access request via the bus 107 or an access request from the boot loader controller 104. In response to the control, each terminal of the serial flash memory 101 is controlled. Memory selection is performed by the chip selection terminal, the type of access operation is performed by an access command supplied to the data input terminal, the address is supplied from the data input terminal, the write data is supplied from the data input terminal, and the read data is output from the data Output from the terminal.

  The boot loader controller 104 includes a control circuit 121, a CRC calculation circuit 122, and a program transfer information register 120. The control circuit 121 issues an access request to the serial flash memory interface circuit 110 and transfers it from the serial flash memory 101 in response to a reset release instruction caused by a change of the initialization signal res1 output from the SYSC 106 to a high level. The control information (program transfer information) 130 is read and stored in the program transfer information register 120. At this time, if the operation operation of the CRC operation circuit 122 is enabled by the operation enable signal CRCEN, a CRC check is performed on the read program transfer information, and the result is returned to the control unit 121 by the signal CRCOK, which is necessary. In response to this, the download process is retried. The storage destination of the transfer control information 130 on the serial flash memory 101 is determined in advance, and the address is incorporated in the sequence control logic of the control circuit 121.

  When the transfer control information 130 is loaded into the register 120, the control circuit 121 reads the transfer control information 130 and issues an access request for downloading the program 130 using the address indicated by the information to the serial flash memory interface circuit 110. Accordingly, the serial flash memory interface circuit 110 sequentially reads the program 131 from the serial flash memory 101. At this time, if the arithmetic operation of the CRC arithmetic circuit 122 is enabled by the arithmetic valid signal CRCEN, the CRC check for the read program is performed, and the result is returned to the control unit 121 by the signal CRCOK, and if necessary The program download process is retried.

  The program 131 that has been read and CRC-checked as necessary to make no error is sequentially stored in a predetermined storage area of the RAM 105 under the control of the control circuit 121. The storage destination is sequentially stored based on the start address of the program execution by the CPU 103. Information on the head address is also incorporated in the sequence control logic of the control circuit 121.

  The control circuit 121 instructs the CPU 103 to reset by setting the initialization signal res2 to the low level in synchronization with the reset instruction due to the change of the initialization signal res1 to the low level, whereby the initialization of the CPU 103 is performed. Although not shown, the reset operation is instructed to other circuits in the data processor, and the initialization operation is performed. When the transfer of the program 131 to the RAM 105 is completed, the control circuit 121 instructs the reset release by a change of the initialization signal res2 to the CPU 103 to a high level. The CPU 103 is instructed to release the reset by a change of the initialization signal res2 to the high level, whereby the CPU 103 starts fetching an instruction from the RAM 105 with a predetermined memory address as a start address, and executes the initially loaded program 131. Start.

  The control circuit 121 notifies the end of the transfer of the program 131 to the RAM 105 to the outside of the data processor 102 by a program transfer signal PGMTR. The state in which the program by the data processor 102 can be executed can be quickly ascertained externally, and can be applied to an operation start or initialization trigger of an upper layer system connected to the data processor.

  In addition, the control circuit 121 notifies the outside of the data processor 102 by the failure signal BLERR that the transfer of the program to the RAM is unsuccessful due to circumstances such that the error due to the CRC check of the CRC calculation circuit 122 cannot be resolved even by retrying. As a result, it becomes possible to quickly ascertain the state in which the data processor 102 cannot execute the program, and it can be applied to display on an indicator or a trigger for recovery processing.

  The serial flash memory 101 is also used for storing programs other than the program 131 and control data. In order to load these programs and control information into a prescribed circuit based on the control of the CPU 103, a serial flash memory interface is used. 110 is connected to the bus 107 and can receive access control of the CPU 103. For example, when an LPC interface circuit (LPCIF) 111 to which an LPC (Low Pin Count) bus used for low-band device connection in a PC or the like is connected is provided as a peripheral circuit on the bus 107, the serial flash memory 101 has a BIOS. If a (Basic Input / 0utput System) program is stored, the CPU 103 sets the register of the LPC interface circuit 111 by executing the program 131, and passes through the LPC interface circuit 111 in response to a request from the LPC bus. A BIOS program can be read from the serial flash memory 101 via the serial flash memory interface 110 and output to the LPC bus via the LPC interface circuit 111.

  FIG. 3 shows an example of the program transfer information 130. The serial flash memory 101 includes the CRC 131 corresponding to the program 131 and the CRC code 2 so that the CRC calculation circuit 122 can perform a CRC check. As described above, the serial flash memory 101 can store the program 133 other than the program 131 and the control information 134.

  As the program transfer information 130, for example, the start address of the area where the program 131 is stored, the size of the program 131 (for example, the number of bytes), the number of program transfer retries when an error is caused by CRC check, etc., the program transfer information 130 CRC code 1 corresponding to. Instead of the program size, the end address of the area where the program 131 is stored may be held. Alternatively, the address area may be specified so that the higher-order address information of the address area is defined and the size is defined by the lower-order bit number and regarded as the size.

  FIG. 4 shows a flowchart of download processing by the boot loader controller 104.

  When the reset release instruction is given by the high level of the initialization signal res1 (S1), the boot loader controller 104 reads the program transfer information 130 from the serial flash memory 101 (S2). A CRC check is performed on the read information to determine whether there is an error (S3). If there is an error, S2 and S3 are repeated until the specified number of retries is reached (S4), and if the error cannot be resolved by this, a failure signal BLERR is output (S8).

  If it is determined in step S3 that the CRC check result is normal, this time, the program 131 is transferred from the serial flash memory 101 to the RAM 105 (S5). A CRC check is performed on the program 131 to be transferred to the RAM 105 to determine whether there is an error (S6). If there is an error, steps S5 and S6 are repeated until the specified number of retries is reached (S7), and if the error cannot be resolved by this, a failure signal BLERR is output (S8).

  When it is determined that the CRC check result is normal in step S6, the boot loader controller 104 changes the initialization signal res2 to the CPU 103 to a high level and gives a reset release instruction (S9). The transfer signal PGMTR is asserted (S10). As a result, the CPU 103 shifts to execution of the program downloaded to the RAM 105 (S11).

[Embodiment 2]
FIG. 5 shows a data processor 102A according to the second embodiment. In the data processor 102 of FIG. 1, the dedicated bus 108 is used for transferring the program 131 from the BLC 104 to the RAM 105. In the example of FIG. 5, the common bus 107 is used for the transfer. The BLC 104A must have control logic for accessing the common bus. When the dedicated bus 108 is used, the BLC 104 may have a bus access control logic with a local configuration and a simple configuration.

  Further, the external memory is not limited to the serial flash memory 101, and a parallel flash memory 101A having a parallel interface may be employed.

[Embodiment 3]
FIG. 6 shows a data processor 102B according to the third embodiment. The data processor 102 in FIG. 1 loads the downloaded program 131 into the on-chip RAM 105. In the example of FIG. 6, the download program is loaded into an external RAM 105B composed of a synchronous DRAM or the like arranged outside the data processor 102B. In this case, the data processor 102B needs to be equipped with a memory controller 109 that interfaces with the external RAM 105B.

[Embodiment 4]
As a fourth embodiment, a case where the program transfer time can be adjusted will be described. FIG. 7 illustrates the configuration of the program transfer information 130A used in the fourth embodiment. The difference from FIG. 3 is that it has communication clock designation information and transfer unit designation information.

  In this case, for example, the boot loader controller 104 downloads the program in synchronization with the frequency designated by the designation information of the communication clock. For example, the frequency determines the frequency of the clock signal supplied to the memory clock terminal of the serial flash memory 101. This makes it possible to adjust the time required to transfer the program from the serial flash memory 101 to the RAM 105 based on the transfer control information. Since the reset release instruction to the CPU 103 is given to the completion of the transfer of the program from the serial flash memory 101 to the RAM 105, the boot loader controller is compared with the time required for the initialization operation inside and outside the data processor to be completed. The timing for releasing the reset of the CPU 103 by 104 can be prevented from being too early or too late.

  In addition, for example, the boot controller 104 downloads the program 131 in a plurality of times in units of data size designated by the information of the transfer unit. That is, an access command is issued to the serial flash memory 101 in the specified data size unit. Even when a program of the same size is read, the time required to complete the download of required data becomes longer as the access operation is issued and the access operation is cut into smaller pieces.

  FIG. 8 shows the access operation timing for the serial flash memory 101 when the program is downloaded with an access size of 16 bytes. In FIG. 8, SPIS indicates a chip selector signal, SPICK indicates a memory clock signal, SPIDO indicates a data output, and SPIDI indicates a data input. I is an access command, A is a program start address, and S is a program size. P means a program.

  As described above, if the data size unit is reduced, the number of program download operations performed in a divided manner increases, so that the time required to complete the program download increases. Therefore, similarly to the above, it is possible to adjust the time required for transferring the program from the serial flash memory 101 to the RAM 105 based on the transfer control information, and it is necessary until the initialization operation inside and outside the data processor is completed. It is possible to prevent the timing of the CPU reset release by the boot loader controller from being too early or too late with respect to time.

[Embodiment 5]
FIG. 9 shows a data processor 102C according to the fifth embodiment. In the data processor 102 of FIG. 1, the initial load of the program has been described by paying attention to the release of the reset instruction by the external reset signal RES as a representative. It goes without saying that the initial load of the program can be similarly applied to the reset release corresponding to the reset instruction by other initialization factors. In particular, in the fifth embodiment, a description will be given of a configuration in which a processing mode by reset cancellation corresponding to a reset factor is selected.

  FIG. 9 shows a data processor 102C in which the illustration of a watchdog timer (WDT) 141 and a power supply voltage drop detection circuit (LVD) 140 is added as an internal circuit that is a reset request source to the data processor of FIG. Show.

  The LVD 140 instructs the reset by setting the internal reset signal RES_LVD to a low level when the power supply voltage level becomes equal to or lower than a specified voltage. The WDT 141 instructs the reset by setting the internal reset signal RES_WDT to low level due to timeout. The reset factor caused by the internal reset signal RES_LVD due to the drop in the power supply voltage level is a reset factor that does not guarantee the retention of the stored information in the RAM, similarly to the reset factor caused by the reset signal RES supplied from the outside. On the other hand, the reset factor by the internal reset signal RES_WDT due to timeout of the WDT 141 is a reset factor that guarantees retention of the storage information of the RAM. The latter reset factor is that when the transfer of the program from the boot loader controller 104C is completed, the RAM 105 is write protected, and the write protect is a reset instruction by the reset signal RES supplied from the outside and the power supply voltage level drop. This is premised on being released by a reset instruction by the internal reset signal RES_LVD. Even when a reset instruction is given by the internal reset signal RES_LVD, the program 130 held in the RAM 105 is maintained in a normal state without being undesirably rewritten.

  In the fifth embodiment, the boot load controller 104C is operated in accordance with the difference in the cause of the reset instruction. res1 is an initialization signal corresponding to RES, res1_WDT is an initialization signal corresponding to RES_WDT, and res1_LVD is an initialization signal corresponding to RES_LVD.

  The predetermined reset release instruction to which the boot loader controller 104C responds is a reset release instruction due to a change of res1 to a high level and a reset release instruction due to a change of res1_LVD to a high level, and the change of res1_WDT to a high level The reset release instruction by is not covered.

  Thereby, it is possible to appropriately control whether or not to download the program to the RAM 105 using the boot loader controller 104C according to the reset factor. When reset is instructed in a state where it is guaranteed that a valid program is already held, it is possible to instruct the CPU 103 to cancel reset without performing useless program download. In short, when the reset signal res1_WDT is set to the high level and the reset release instruction is given, the control 121 of the boot loader controller 104C immediately changes the reset signal res2 from the low level to the high level to cancel the reset state of the CPU 103. To do.

  FIG. 10 shows whether initialization is performed for each reset factor in units of functional blocks (CPU, boot loader controller, RAM, etc.). “Initialization” means that initialization is performed by a corresponding reset instruction, and “hold” means that initialization is not performed by a corresponding reset instruction. The “CPU reset release” column shows the circuit blocks that are operated when the CPU reset is released and the circuit blocks that are not operated.

[Embodiment 6]
As a sixth embodiment, a function of selecting a processing mode by reset release according to a reset factor of the fifth embodiment will be described for setting a reset factor activation level control register 123 for each reset factor.

  For example, the LVD 140 has a register that can freely set a power supply voltage level for instructing a reset by setting the internal reset signal RES_LVD to a low level. Since the data in the RAM 105 is guaranteed when the power supply voltage level instructing the reset set in the register is higher than the specified voltage level for data retention in the RAM 105, it is not necessary to download the program to the RAM 105 by the reset signal RES_LVD. In such a case, the reset factor RES_LVD may be set in the reset factor activation level control register 123 so that no program download is necessary.

[Embodiment 7]
In the seventh embodiment, a configuration in which a scrambled program stored in the serial flash memory 101 is downloaded to the RAM will be described.

  FIG. 11 illustrates the arrangement of the program on the serial flash memory 101 and the arrangement of the program downloaded to the RAM in the seventh embodiment. In the seventh embodiment, the address information indicated by the transfer control information 130 is address information indicating the location of some programs 131A of the predetermined programs 1321A to 131D to be downloaded that are discretely mapped on the external memory. The part 131A of the predetermined program is a boot program downloaded by the boot loader controller 104. The remaining 131B to 131D (main program) of the predetermined program are discretely mapped programs that are downloaded from the serial flash memory 101 and transferred to the RAM 105 when the CPU 103 executes the boot program 131A.

  RSADR1 is the head address of the boot program 131A on the RAM 105. When the reset is released after the boot program is downloaded, the CPU 103 starts executing the program from the address indicated by RSADR1. RSADR2 is the start address of the main programs 131B to 131D on the RAM 105, and after the CPU 103 executes the boot program and downloads the main programs 131B to 131D to the RAM 105, execution of the program starts from the address indicated by RSADR2.

  As a result, a predetermined program to be downloaded can be scrambled and stored on the serial flash memory 101, so that it is possible to improve the security for the program in that theft or illegal use of the program can be suppressed. it can.

[Embodiment 8]
FIG. 12 shows a schematic configuration of a data processor described in the above embodiment, for example, a notebook PC adopting the data processor 102 as a keyboard and a power supply controller.

  In a notebook PC as a data processing system, the data processor 102 controls an input device connected to the outside by executing a program transferred from the serial flash memory 101 to the RAM 105. As an input / output device, an LED indicator 235, a battery system 241, a cooling fan 236, a key scan circuit 237, a thermistor 230, a power monitor 231, a card interface 232, a display dimming circuit 233, a pointing device 234 such as a mouse, and an expansion processor 244 Etc. are connected. An FWH 242, a super I / O 243, a user-specific ASIC 240, and the like are connected to the LPC bus. The signal PGMTR is not particularly limited, but is used as a peripheral circuit reset signal.

  The data processor 102 is connected to the input / output controller hub 205 via the LPC bus. For example, the input / output controller hub 205 constitutes a south bridge (ICH), and the input / output controller hub 201 constitutes a north bridge (MCH). A south bridge (ICH) 205 includes a local area network controller 206 through a LAN port 207, an HDD 210 having a serial ATA interface, a card bus 220, a wireless LAN 221, an amplifier 222 for driving a speaker 223, USB controllers 211 and 212, a USB. A port 208, a PCI controller, and the like are connected. The north bridge (MCH) 201 is connected to a graphic controller 203 that performs display control of the display 204, a main memory 202, and a main processor 200.

  As described above, since the program stored in the serial flash memory 101 is downloaded to the RAM 105 based on the address information indicated by the transfer control information, the transfer control information corresponding to the mapping on the serial flash memory 101 is transferred to the program. Just prepare. Since free mapping on the serial flash memory 101 can be permitted with respect to the program with a simple configuration, it is possible to contribute to reduction of the system cost of the notebook PC. When the BIOS program of the serial flash memory 101 is stored, it can be transferred to an upper layer such as the ICH 205 through the LPC under the control of the CPU 103.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

102 Data processor (MCU)
101 Serial flash memory (SIFLSH)
103 Central processing unit (CPU)
105 RAM
106 System controller (SYSC)
104 Boot loader controller (BLC)
107 bus RES reset signal res1 initialization signal res2 initialization signal 130 transfer control information 131 program 121 control circuit 122 CRC arithmetic circuit 120 program transfer information register

Claims (29)

A data processor for executing a program transferred from an external memory to a RAM,
A central processing unit for starting execution of a program with a predetermined address of the RAM as a start address in response to a given reset release instruction;
In response to a predetermined reset release instruction, the transfer control information is read from the external memory, the program is downloaded from the external memory based on the address information indicated by the read transfer control information, and the downloaded program is stored in the RAM. A data processor comprising: a boot loader controller that transfers and completes the transfer and gives a reset release instruction to the central processing unit.   The data processor according to claim 1, further comprising a dedicated path for transferring a program from the boot loader controller to the RAM.   The data processor according to claim 1, wherein the boot loader controller includes an error detection circuit that detects the presence or absence of a transfer error in the downloaded program.   When the boot loader controller detects an error in program transfer by the error detection circuit, the boot loader controller performs a program download retry until it is detected that there is no transfer error, with the upper limit being the number of times specified by the transfer control information. Item 4. The data processor according to item 3.   4. The data processor according to claim 3, wherein the boot loader controller performs the detection operation when an instruction to validate the detection operation by the error detection circuit is given.   The data processor according to claim 1, wherein the boot loader controller starts downloading a program from a start address indicated by the transfer control information, and downloads a program having a capacity indicated by the transfer control information.   The data processor according to claim 1, wherein the boot loader controller notifies the end of transfer of the program to the RAM.   The data processor according to claim 6, wherein the boot loader controller notifies a failure of completion of transfer of the program to the RAM to the outside.   The data processor according to claim 1, wherein the RAM is a RAM built in the data processor.   The data processor according to claim 1, wherein the RAM is a RAM connected to the outside of the data processor.   The data processor according to claim 1, wherein the boot loader controller downloads the program in synchronization with a frequency specified by the transfer control information.   The data processor according to claim 1, wherein the boot loader controller downloads the program in a plurality of times in units of data size specified by the transfer control information. The predetermined reset release instruction to which the boot loader controller responds corresponds to a reset factor for which the reset release instruction does not guarantee the storage information of the RAM,
2. The data processor according to claim 1, wherein the CPU executes the program of the RAM in response to the reset release instruction with respect to a reset factor that guarantees retention of the storage information in the RAM. The predetermined reset release instruction responded by the boot loader controller includes an instruction corresponding to a reset factor by an externally supplied reset signal and an instruction corresponding to a reset factor by an internal reset signal due to a power supply voltage level drop, and a watchdog Does not include an instruction corresponding to the reset cause by the internal reset signal due to timer timeout,
When the transfer of the program from the boot loader controller is completed, the RAM is write protected, and the write protection is performed by a reset instruction by a reset signal supplied from the outside and a reset instruction by an internal reset signal by the power supply voltage level drop. The data processor of claim 1, wherein the data processor is released. The predetermined reset release instruction to which the boot loader controller responds corresponds to a reset factor for which the reset release instruction does not guarantee the storage information of the RAM,
18. The data processor according to claim 17, further comprising a register for setting whether or not the boot loader controller executes program transfer for each reset factor. The address information indicated by the transfer control information is address information indicating the location of a part of a predetermined program to be downloaded that is discretely mapped on an external memory,
A part of the predetermined program is a boot program downloaded by the boot loader controller,
The data processor according to claim 1, wherein the remainder of the predetermined program is a discretely mapped program that is downloaded from the external memory and transferred to the RAM when the central processing unit executes the boot program. . A data processor for controlling an input device connected to the outside by executing a program transferred from the external memory to the RAM;
An input / output controller hub connected to the data processor via an LPC bus;
A data processor having a main processor connected to the input / output controller hub via a system bus,
The data processor, in response to a given reset release instruction, a central processing unit for starting execution of a program with a predetermined address of the RAM as a start address;
In response to a predetermined reset release instruction, the transfer control information is read from the external memory, the program is downloaded from the external memory based on the address information indicated by the read transfer control information, and the downloaded program is stored in the RAM. And a boot loader controller for giving a reset release instruction to the central processing unit after completing the transfer.   The data processor according to claim 17, wherein the boot loader controller has an error detection circuit that detects the presence or absence of a transfer error in the downloaded program.   When the boot loader controller detects an error in program transfer by the error detection circuit, the boot loader controller performs a program download retry until it is detected that there is no transfer error, with the upper limit being the number of times specified by the transfer control information. Item 18. The data processor according to Item 17.   18. The data processor according to claim 17, wherein the boot loader controller performs the detection operation when an instruction to validate the detection operation by the error detection circuit is given.   18. The data processor according to claim 17, wherein the boot loader controller starts downloading a program from a start address indicated by the transfer control information, and downloads a program having a capacity indicated by the transfer control information.   The data processing system according to claim 17, wherein the boot loader controller notifies the outside of the transfer of the program to the RAM.   The data processing system according to claim 17, wherein the boot loader controller notifies a failure of completion of transfer of the program to the RAM.   The data processing system according to claim 17, wherein the boot loader controller downloads the program in synchronization with a frequency specified by the transfer control information.   The data processing system according to claim 17, wherein the boot loader controller downloads the program in a plurality of times for each data size specified by the transfer control information. The predetermined reset release instruction to which the boot loader controller responds corresponds to a reset factor for which the reset instruction does not guarantee retention of the storage information in the RAM,
18. The data processing system according to claim 17, wherein the CPU executes the program of the RAM in response to a reset release instruction corresponding to a reset factor for guaranteeing retention of storage information in the RAM in response to the reset release instruction. . The predetermined reset release instruction responded by the boot loader controller includes an instruction corresponding to a reset factor by an externally supplied reset signal and an instruction corresponding to a reset factor by an internal reset signal due to a power supply voltage level drop, and a watchdog Does not include an instruction corresponding to the reset cause by the internal reset signal due to timer timeout,
The RAM is write protected when the transfer of the program from the boot loader controller is completed, and the write protection is performed by a reset instruction by a reset signal supplied from the outside and a reset instruction by an internal reset signal by the power supply voltage level drop. The data processing system of claim 17, wherein the data processing system is released. The predetermined reset release instruction to which the boot loader controller responds corresponds to a reset factor for which the reset release instruction does not guarantee the storage information of the RAM,
18. The data processor according to claim 17, further comprising a register for setting whether or not the boot loader controller executes program transfer for each reset factor. The address information indicated by the transfer control information is address information indicating the location of a part of a predetermined program to be downloaded that is discretely mapped on an external memory,
A part of the predetermined program is a boot program downloaded by the boot loader controller,
18. The data processing according to claim 17, wherein the remainder of the predetermined program is a discretely mapped program that is downloaded from the external memory and transferred to the RAM when the central processing unit executes the boot program. system.

Images