JP2011227576A - Noise analysis device and noise analysis method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow accurate analysis of the power supply noise, which is generated when the power supply of an internal circuit is connected/disconnected by a power control circuit, in a short time during the early stage of semiconductor integrated circuit design.SOLUTION: An analysis model of a basic unit circuit for a power supply noise analysis is created and embedded as the analysis model of an internal circuit in a semiconductor integrated circuit so as to calculate a power supply noise, which is generated when the power supply of the internal circuit is connected/disconnected in the semiconductor integrated circuit that includes a power control circuit with a plurality of sets of switch group for controlling power supply to the internal circuit.

Description

  The present invention relates to a noise analysis apparatus and a noise analysis method for analyzing power supply noise generated in a power supply in a semiconductor integrated circuit.

  Conventionally, the power supply in the semiconductor integrated circuit is based on the premise that when the power is turned on at the start of the operation of the semiconductor integrated circuit, a constant voltage is always supplied regardless of whether the semiconductor integrated circuit is in operation or not. On the other hand, in recent years, with the progress of miniaturization of transistors constituting a semiconductor integrated circuit, the tendency of increasing current consumption during non-operation of the semiconductor integrated circuit after the power is turned on has become remarkable. For this reason, in order to suppress power consumption when the semiconductor integrated circuit is not operating, it is necessary to produce a power supply control circuit in the semiconductor integrated circuit.

  However, it has become clear that an unexpected amount of current flows from a PCB (Print Circuit Board), which is a power supply source, to a semiconductor integrated circuit when the power is turned on when the conventional semiconductor integrated circuit is operating. Then, due to the current flowing when the power of the semiconductor integrated circuit is turned on, power supply noise is generated on the power supply wiring in the semiconductor integrated circuit which has conventionally supplied a constant voltage power. There is a problem that a circuit operating in the semiconductor integrated circuit malfunctions due to the power supply noise.

  There has been proposed a technique for optimizing the ON timing of a power switch to suppress power noise in a semiconductor integrated circuit equipped with a power gating circuit having a plurality of power switches (see, for example, Patent Document 1). In addition, a circuit connection verification method for a semiconductor integrated circuit that realizes low power consumption while ensuring an operation margin has been proposed (see, for example, Patent Document 2).

JP 2008-65732 A JP 2004-241106 A

  A configuration of a semiconductor integrated circuit having a power supply control circuit and a generation state of power supply noise will be described with reference to FIG. In the semiconductor integrated circuit shown in FIG. 1A, the power supplied from the power supply unit PW1 of the board (BOARD) is supplied via the power supply potential, the inductance L2, and the resistance R2 via the inductance L1 and resistance R1 of the package (PKG). Each of the ground potentials is applied to a die (DIE) constituting an internal circuit. The power supply potential and the ground potential become predetermined VDD power supply and VSS power supply by the resistors R3 and R4, respectively, and are supplied to the internal circuit.

  An internal circuit on the DIE is configured by a power domain PD1 that is simultaneously turned on / off, and low power consumption control is performed on the power domain PD1. Further, the DIE includes a plurality of power switch groups PSWG1, PSWG2,..., PSWGn that turn on power supply when the power domain PD1 in which the internal circuit is laid out operates and turn off when the power domain PD1 does not operate. Each of the power switch groups PSWG1, PSWG2,..., PSWGn has one or more power switches (PSW), and according to a control signal from a power switch (PSW) control circuit PSWC1 that controls the power switch. Each power switch group is turned on / off. The control signal from the PSW control circuit PSWC1 is supplied to the power switches of the power switch groups PSWG1, PSWG2,..., PSWGn via the PSW drive buffers BF1, BF2,.

  The power switch group PSWG1, PSWG2,..., PSWGn, PSW control circuit PSWC1, and PSW drive buffers BF1, BF2,. The The power supply control circuit supplies VDDPD power to the power domain PD1 of the internal circuit.

  When logically analyzing the semiconductor integrated circuit designed in this way, simulation is performed using the power supplied from the power supply unit PW1 as an ideal power supply and the VDDPD power supplied to the internal circuit as a virtual power supply.

  When the power switches of the power switch groups PSWG1, PSWG2,..., PSWGn are turned on / off, power noise is generated by the power gating, and an inflow current to the internal circuit is generated. The graph shown in FIG. 1B represents the state of the power supply noise amount [mV] and the VDDPD power supply voltage [V] corresponding to the passage of time T when the power switch is turned on, and LN11 is the VDDPD power supply. Voltage is shown, and LN12 shows power supply noise. It shows that the amount of power supply noise generated suddenly between the VDD and VSS power supply peaks at a certain time t until the VDDPD power supply voltage rises to a predetermined voltage by turning on the power switch. The waveform of the VDDPD power supply voltage and the amount of power supply noise as shown in this graph are waveforms obtained by analysis using layout data such that the design of the logic circuit is almost completed.

  However, in order to create an analysis model of power supply noise based on the layout data, when it is found that the power supply noise amount calculated by analyzing the power supply noise causes malfunction or performance degradation of the internal circuit in the semiconductor integrated circuit, Even if it is attempted to suppress power supply noise, it is difficult to significantly correct the original layout, and there are limited correction methods for suppressing power supply noise, which cannot be effectively suppressed. Also, in order to extract the circuit model of the power circuit network and internal circuit based on the layout data and create an analysis model, it is necessary to input very large size data. Takes a lot of time. Therefore, in actual design, it is difficult to examine power supply noise generated in the semiconductor integrated circuit when the power supply control circuit is used to connect / disconnect the power supply of the internal circuit in the semiconductor integrated circuit.

  In the conventional analysis method as described above, it is necessary to create a power wiring model and a detailed circuit operation model of a large-scale semiconductor integrated circuit before estimating the power noise generated when the power of the internal circuit of the semiconductor integrated circuit is connected. there were. For this reason, it is difficult to estimate the power supply noise generated in the semiconductor integrated circuit when the internal circuit is connected to or disconnected from the internal circuit in the semiconductor integrated circuit in an actual semiconductor integrated circuit design.

In an actual semiconductor integrated circuit, there are other internal circuits that operate by sharing the VDD power supply in addition to the internal circuit connected to the power supply. For this reason, when power supply noise occurs when the internal circuit is connected to the power supply, the power supply noise may cause other internal circuits that share the power supply to malfunction or degrade performance. The power supply noise generated on the power supply wiring of the semiconductor integrated circuit includes not only the power supply noise generated when the power supply is connected but also the input / output of the semiconductor integrated circuit represented by the power supply noise generated during the operation of the internal circuit and the SSO power supply noise. There is a power supply noise during circuit (IO circuit) operation, and there is a situation where the influence of the power supply noise cannot be avoided.
For this reason, it is important to design each internal circuit in consideration of power supply noise generated when the power supply is connected.

  According to one aspect of the present invention, an analysis model creating means for creating an analysis model of a basic unit circuit related to power supply noise analysis, and a semiconductor integrated circuit using a power supply control circuit in a stage prior to the layout of the semiconductor integrated circuit There is provided a noise analysis device including a power supply noise calculation unit that calculates power supply noise generated when a power supply of an internal circuit is connected and disconnected. The power control circuit has a plurality of switch groups that control power supply to the internal circuit. The power supply noise calculation unit calculates the power supply noise by incorporating the basic unit circuit created by the analysis model creation unit as an analysis model of the internal circuit of the semiconductor integrated circuit.

  In the initial design stage of the semiconductor integrated circuit, the amount of power supply noise generated when the power supply control circuit connects and disconnects the power supply of the internal circuit can be accurately estimated in a short time.

It is a figure for demonstrating the structure and power supply noise of a semiconductor integrated circuit which have a power supply control circuit. It is a figure which shows an example of an analysis model. It is a figure which shows the other example of an analysis model. It is a figure for demonstrating the relationship between the electric current path of an internal circuit, and a voltage waveform. It is a figure which shows an example of the analysis model for analyzing a power supply noise. It is a figure which shows the other example of the analysis model for analyzing a power supply noise. It is a figure for demonstrating the basic stage number estimation method of an internal circuit. It is a figure which shows the evaluation flow of the amount of power supply noises in the noise analysis apparatus by this embodiment. It is a figure for demonstrating the output in power supply noise amount evaluation in this embodiment. It is a figure which shows the structural example of the computer which can implement | achieve the noise analysis apparatus by embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The noise analysis apparatus according to the present embodiment is generated in the semiconductor integrated circuit when the internal circuit in the semiconductor integrated circuit is connected / disconnected using, for example, a power supply control circuit for suppressing standby power consumption of the internal circuit. It is a noise analysis device that analyzes power supply noise to be performed with high accuracy and in a short time.

  First, an example of an analysis model for analyzing power supply noise generated in a semiconductor integrated circuit when a power supply is connected / disconnected in a semiconductor integrated circuit having a power supply control circuit that suppresses standby power consumption of the internal circuit explain. Assume that the semiconductor integrated circuit as shown in FIG. In the internal circuit analysis model shown in FIG. 1A, a power supply wiring resistance of the internal circuit is modeled, and a circuit model using a transistor model of the internal circuit is modeled from the model of the power supply wiring resistance. Then, capacity components such as a power stabilization capacitor (decoupling cell capacity) inserted between the power supply wirings and a parasitic capacitance between the power supplies on the Si substrate are modeled.

  FIG. 2 is a diagram illustrating an example of an analysis model. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals. FIG. 2A shows a semiconductor integrated circuit that is designed as an internal circuit by modeling the internal circuit with a power supply stabilization capacitor C1 in the semiconductor integrated circuit shown in FIG. As in the semiconductor integrated circuit shown in FIG. 1A, the other components of the semiconductor integrated circuit shown in FIG. 2A are supplied from the power supply unit PW1 of the board (BOARD) as a package (PKG). The power supply potential and the ground potential via the inductance L2 and the resistor R2, respectively, are applied to the die (DIE) constituting the internal circuit. The power supply potential and the ground potential become predetermined VDD power supply and VSS power supply by the resistors R3 and R4, respectively, and are supplied to the internal circuit. .., PSWGn, PSW control circuit PSWC1, and PSW drive buffers BF1, BF2,... BFn perform power gating on the internal circuit. A power supply control circuit is configured. Here, in the circuit in the semiconductor integrated circuit, each circuit using the same VDD power supply and VSS power supply is separated into one internal circuit.

  Then, an analysis model of power supply noise is created for each separated internal circuit. In the analysis model to be created, it is assumed that ideal power is supplied from the PCB board on which the semiconductor integrated circuit is mounted, and the resistance, inductance, capacitance, etc. by the power supply wiring on the package of the semiconductor integrated circuit are modeled. When ideal power is not supplied from the PCB board, the wiring resistance, inductance, and capacitance on the PCB board are also modeled.

  Also, the resistance, inductance, and capacity of the power supply wiring on the DIE of the semiconductor integrated circuit are modeled from the package, and the power switch that is a power control circuit in the semiconductor integrated circuit is modeled on the power supply wiring (VDDPD power supply) directly connected to the internal circuit. Wiring). With respect to the connection point of the power switch, there is a case where it is connected to the VDD power source side or the VSS power source side depending on the characteristics of the power switch of the power control circuit. In the analysis model, the necessary power supply noise amount can be analyzed by creating the analysis model according to the connection location of the power switch.

  The internal circuit is modeled by a power supply stabilization capacitor C1 based on a power supply stabilization capacitor (decoupling cell capacitor) inserted between the power supply wirings.

  When a power supply noise amount and a VDDPD power supply voltage are simulated using an analysis model of a semiconductor integrated circuit in which an internal circuit is modeled only by a power stabilization capacitor, a graph result as shown in FIG. 2B, for example, is obtained. The graph shown in FIG. 2B shows the state of the power supply noise amount [mV] and the VDDPD power supply voltage [V] corresponding to the passage of time T when the power switch is turned on by simulation. In FIG. 2B, the amount of power supply noise obtained when the actually produced semiconductor integrated circuit is measured by a tester is indicated by an actual power supply noise amount LN22. Further, the power supply noise amount obtained by the simulation using the analysis model is indicated by a power supply noise amount LN23, and the VDDPD power supply voltage is indicated by LN21. In the analysis model modeled using only the power supply stabilization capacity, the rise time of the VDDPD power supply voltage LN21 can be analyzed with high accuracy, while the power supply noise amount LN23 at time t at which the actual power supply noise amount LN22 is maximized is analyzed with high accuracy. It turns out that is difficult. In other words, the analysis model modeled using only the power supply stabilization capacity cannot reveal the noise generated during the operation of the internal circuit.

  Next, an analysis model modeled including the power supply capacitance of the transistors existing between the power supplies of the internal circuits in addition to the power supply stabilization capacitance will be described with reference to FIG. FIG. 3 is a diagram illustrating another example of the analysis model. 3, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals. The configuration of the semiconductor integrated circuit shown in FIG. 3A is the same as that of the semiconductor integrated circuit in FIG. 2A, and an analysis model is created as described above. In the semiconductor integrated circuit shown in FIG. 3A, the internal circuit is modeled by a capacitor C2 including a power supply capacitance of a transistor existing between the power supplies of the internal circuit in addition to the power supply stabilization capacitance shown in FIG. And shown as an internal circuit.

  When a power supply noise amount and a VDDPD power supply voltage are simulated using an analysis model of a semiconductor integrated circuit as shown in FIG. 3A, for example, a graph result as shown in FIG. 3B is obtained. The graph shown in FIG. 3B shows the state of the power supply noise amount [mV] and the VDDPD power supply voltage [V] corresponding to the passage of time T when the power switch is turned on by simulation. In FIG. 3B, the amount of power supply noise obtained when a semiconductor integrated circuit actually produced is measured by a tester is indicated by an actual power supply noise amount LN33, and the VDDPD power supply voltage is indicated by LN31. Further, the power supply noise amount obtained by the simulation using the analysis model is indicated by a power supply noise amount LN34, and the VDDPD power supply voltage is indicated by LN32.

  In the analysis model shown in FIG. 3A, the maximum value of the power supply noise amount at time t can be correctly analyzed, while the rise time of the VDDPD power supply voltage LN32 of the internal circuit is determined by the capacitance inserted between the power supplies of the internal circuit. It is difficult to analyze with high accuracy. The same applies to the case where the inter-power source capacitance of the transistor existing between the power sources of the internal circuits and the load capacitance of the signal wiring are modeled as one capacitive element.

  This embodiment will be described below. To analyze power supply noise generated in the power supply when the power supply control circuit is used to connect / disconnect the power supply to / from the internal circuit of the semiconductor integrated circuit, accurately analyze the inflow current when the internal circuit power supply is turned on There is a need. As shown in FIG. 4A, the inflow current of the internal circuit includes currents flowing through the paths CP1, CP2, and CP3, and changes with time. In the present embodiment, a basic unit circuit capable of accurately analyzing the amount of current flowing into the power source of the internal circuit when boosting the power source of the internal circuit is modeled as an analysis model. Here, a case where an inverter circuit is used for the basic unit circuit as shown in FIG. 4B will be described as an example.

  The current path and voltage waveform of the internal circuit will be described with reference to FIG. 4 on the assumption that the input signal of the internal circuit is fixed on the VSS power supply side before the internal circuit power supply (VDDPD power supply) is boosted. FIG. 4 is a diagram for explaining the relationship between the current path of the internal circuit and the voltage waveform. FIG. 4B shows an internal circuit modeled by the inverter INV1 and the inverter INV2. In FIG. 4C, the voltage waveform LN43 of the VDDPD power supply of the internal circuit by the output terminal node A of the inverter INV1 and the output terminal node B of the inverter INV2 is shown as time T passes.

  At the time of boosting the VDDPD power supply in the internal circuit, as shown in FIG. 4C, the output signal appearing at the output terminal node A of the inverter INV1, for example, at the beginning of the period (a) is driven so that the inverter INV1 can drive the output load. Since it has no capability, it outputs an intermediate potential between the VDDPD power supply and the VSS power supply.

  After that, when the VDDPD power supply boosts to a voltage value at which the inverter INV1 can operate, the node A is boosted to the voltage value of the VDDPD power supply by the inverter INV1 in the period (b) (voltage waveform LN41 of the node A). At this time, a current flows from the power source of the internal circuit to the internal circuit through a route indicated by a route CP1.

  Next, shortly after the node A starts to boost the voltage of the VDDPD power supply, the circuit inverter INV2 next to the inverter INV1 that has been operated first starts to operate. In the initial time zone when the inverter INV2 starts to operate, a relatively large amount of through current passing through the inverter INV2 between the VDDPD power supply and the VSS power supply of the internal circuit flows through the path CP2.

  Next, the inverter INV2 steps down the node B at the intermediate potential between the VDDPD power supply and the VSS power supply to the voltage value of the VSS power supply. At this time, current flows to the internal circuit through the path indicated by path CP3 to the power supply of the internal circuit. Thereafter, after the inverter INV2 steps down the node B to the voltage value of the VSS power supply, the through current flowing through the path CP2 hardly flows (the voltage waveform LN42 at the node B).

  As described above, current flowing through the paths CP1, CP2, and CP3 is generated when the VDDPD power supply of the internal circuit is boosted. These currents cause power supply noise. Therefore, by inserting a basic unit circuit group corresponding to the circuit scale of the logic circuit to be designed into the internal circuit part of the analysis model, the current flowing into the power supply of the internal circuit of the semiconductor integrated circuit can be analyzed with high accuracy. Power supply noise can be verified.

  An analysis model in this embodiment for analyzing power supply noise generated in a power supply when the power supply control circuit is used to connect / disconnect the power supply of the internal circuit will be described.

  FIG. 5 is a diagram illustrating an example of an analysis model for analyzing power supply noise in the present embodiment. In the example shown in FIG. 5, in the analysis model reproducing the power supply structure connected to the internal circuit via the power switch from the power supply connected to the outside of the semiconductor integrated circuit, the circuit of the logic circuit designed in the internal circuit portion of the analysis model The inverter circuit group corresponding to the scale is modeled.

  In the example shown in FIG. 5, the internal circuit including the power domain PD5 in which the internal circuit in the semiconductor integrated circuit shown in FIG. 1A is modeled by a basic unit circuit using an inverter circuit group as shown in FIG. 5B. A semiconductor integrated circuit logically designed is shown. The other components of the semiconductor integrated circuit are the same as those in FIG.

  An inverter circuit group as a basic unit circuit of the analysis model illustrated in FIG. 5B is a series of ten inverters 51 to 60, and corresponds to five gates. As an input signal of the inverter circuit group, an input signal having the same potential as the VSS power supply is input to the first-stage inverter 51.

  When the circuit scale of the internal circuit to be analyzed is large and the analysis model becomes large and the analysis time becomes long, an inverter circuit group having a certain scale is created. Then, by creating a plurality of created inverter circuit groups as basic unit circuits, an analysis model corresponding to the circuit scale of the logic circuit to be designed can be created. For example, in the actual simulation, the simulation is performed by using the number of basic unit circuits illustrated in FIG. 5B according to the circuit scale. As a result, the simulator that analyzes the operation of the analysis model generates a power supply when multiple inverter circuit groups in the analysis model are connected to the power supply at the same time by simply analyzing the inverter circuit group of one basic unit circuit in detail. Power supply noise can be analyzed in a short time. For example, when the circuit scale is equivalent to 10,000 gates, for example, the simulation result of the basic unit circuit for five gates may be multiplied by 2000.

  FIG. 6 is a diagram illustrating another example of an analysis model for analyzing power supply noise in the present embodiment. In the example shown in FIG. 6, in the analysis model reproducing the power supply structure connected to the internal circuit through the power switch from the power supply connected to the outside of the semiconductor integrated circuit, the circuit of the logic circuit designed in the internal circuit portion of the analysis model A NAND (Negative AND operation) circuit group corresponding to the scale is modeled.

  In the example shown in FIG. 6, an internal circuit including a power domain PD6 in which the internal circuit is modeled by a basic unit circuit using a NAND circuit group as shown in FIG. 6B in the semiconductor integrated circuit shown in FIG. A semiconductor integrated circuit logically designed is shown. The other components of the semiconductor integrated circuit are the same as those in FIG.

  The NAND circuit group as the basic unit circuit of the analysis model illustrated in FIG. 6B is a series of ten NAND circuits 61 to 70, and corresponds to 10 gates. As an input signal of the NAND circuits 61 to 70, an input signal having the same potential as the VSS power supply is input to the NAND circuit 61 of the first stage for both inputs. Further, the NAND circuits 62, 64, 66, 68, and 70 receive the output of the preceding NAND circuit at one input and a signal having the same potential as the VDDPD power supply at the other input. Further, the NAND circuit 63, 65, 67, 69 receives the output of the preceding NAND circuit at one input and the signal having the same potential as the VSS power supply at the other input.

  Similar to the above-described example, when the circuit scale of the internal circuit to be analyzed is large and the circuit scale of the analysis model is large and the analysis time is long, a NAND circuit group of a certain scale is created. Then, by creating a plurality of created NAND circuit groups as basic unit circuits, an analysis model corresponding to the circuit scale of the logic circuit to be designed can be created. For example, in the actual simulation, the simulation is performed using a number of basic unit circuits as illustrated in FIG. 6B according to the circuit scale. As a result, the simulator that analyzes the operation of the analysis model generates a power supply when multiple inverter circuit groups in the analysis model are connected to the power supply at the same time by simply analyzing the inverter circuit group of one basic unit circuit in detail. Power supply noise can be analyzed in a short time. For example, when the circuit scale corresponds to 10,000 gates, for example, the simulation result of the basic unit circuit for 10 gates may be multiplied by 1000.

  The basic unit circuit is an example, and is not limited to the above-described inverter circuit group or NAND circuit group. For example, the basic unit circuit may be configured using a buffer circuit. Further, the basic unit circuits may be as many as the number of average logic circuits. As shown in FIG. 7A, the average number of stages of the logic circuit is the number of stages between the flip-flop (FF) circuit from which input data is output and the flip-flop circuit of the next stage. A signal between flip-flop circuits propagates within a clock cycle time determined by the operating frequency of the semiconductor integrated circuit to be designed. Therefore, if the operating frequency of the semiconductor integrated circuit is f [Hz] and the gate delay per inverter circuit or NAND circuit constituting the basic unit circuit is p [s], the required number of stages N is N = 1 / ( f · p). It is also possible to obtain the number of stages used in another process technology from the number of stages determined in one process technology. Here, if the conversion coefficient of the gate delay per inverter circuit or NAND circuit constituting the basic unit circuit is κ, the gate delay is κ · p [s], so the number of stages to be calculated is N = 1. / (F · κp). If there is no flip-flop circuit, the number of stages of logic circuits from the input terminal to the output terminal of the internal circuit may be used as shown in FIG. 7B.

  By using the analysis model described above, it is possible to analyze not only the maximum amount of power supply noise generated when boosting the VDDPD power supply of the internal circuit but also the power supply noise waveform. As a result, the boosting time of the power supply of the internal circuit can be analyzed with high accuracy. Further, since the circuit scale of the logic circuit is not significantly changed before and after the layout, the power supply noise can be analyzed with high accuracy even in the initial design stage before the layout. In addition, when the power source of the internal circuit is cut off, the amount of current that decreases the current flowing into the power source of the internal circuit can be analyzed with high accuracy as in the case of connecting the power source.

  FIG. 8 is a diagram showing an evaluation flow of the power supply noise amount in the noise analyzing apparatus according to the present embodiment. In FIG. 8, a noise analysis device which is a computer device as shown in FIG. 10 is that a designer has power switch (PSW) cell drive stage number information 81, PSW drive buffer cell type information 82, PSW cell type information 83, an internal circuit. The inter-power supply capacitance value information 84 and the information 85 of the resistance value (R) and inductance value (L) of the power supply wiring in the PKG are input. Further, the current consumption amount information 86 of the internal circuit, the circuit scale information 87, and the operating frequency information 88 of the internal circuit estimated in advance are inputted. Based on these pieces of information, the noise analyzer creates an overall analysis model of the semiconductor integrated circuit to be designed (S1). This is an overall analysis netlist for an analysis simulator using the basic unit circuit described above.

  Then, the noise analysis device performs analysis during circuit operation by power gating using the created overall analysis model (S2). For example, the analysis is performed using a circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis).

As an analysis result, as shown in FIG. 9, power noise amount information 89 and VDDPD power supply voltage rise time information 90 when each power switch group is turned on (becomes conductive) are output. As shown in FIG. 9, the power supply noise Vnoise_max (PSWn) and the rise time t _PSWn of the VDDPD power supply voltage are output. As shown in FIG. 9B, when the power supply noise Vnoise_max (PSWn) and the rise time t _PSWn of the VDDPD power supply voltage are output, the maximum value of Vnoise_max (PSWn) is used as the estimated value of the power supply noise, and t _PSWn The sum total may be used as an estimate of the rise time.

  The noise analyzing apparatus performs power source noise criteria determination using the power source noise amount information 89 and the power source noise criteria information 91 indicating a reference value for the power source noise being equal to or less than a predetermined value (S3). As a result, when the power noise peak value (Vnoise_max (PSWn)) indicated by the power noise amount information 89 is equal to or greater than the power noise reference value indicated by the power noise criteria information 91, the number of PSW stages is increased (S5). ). That is, since the power supply noise can be suppressed by increasing the number of power switch groups, the number of drive stages of the PSW cell is increased, and the entire analysis model is created and analyzed again.

  On the other hand, as a result of the determination, if the power noise peak value (Vnoise_max (PSWn)) indicated by the power noise amount information 89 is equal to or less than the power noise reference value indicated by the power noise criteria information 91, the noise analysis device Then, criteria determination of the rise time of the VDDPD power supply voltage is performed (S6). This determination is performed using the rise time information 90 of the VDDPD power supply voltage and the rise time criteria information 92 of the VDDPD power supply voltage indicating a reference value for the rise time of the VDDPD power supply voltage being equal to or less than a predetermined value.

As a result, if the rise time t _PSWn of the VDDPD power supply voltage indicated by the rise time information 90 of the VDDPD power supply voltage is equal to or greater than the reference value of the rise time indicated by the rise time criteria information 92 of the VDDPD power supply voltage, parameter adjustment is performed. (S8). In this parameter adjustment, if the number of PSW stages can be reduced, the number of PSW stages is reduced. In other words, since the rise time of the VDDPD power supply voltage can be shortened by reducing the number of PSW stages, the number of drive stages of the PSW cell is reduced, and an overall analysis model is created and analyzed again. In addition, the criteria may be relaxed or the circuit scale may be reviewed.

On the other hand, as a result of the determination, when the rise time t _PSWn of the VDDPD power supply voltage indicated by the rise time information 90 of the VDDPD power supply voltage is equal to or less than the reference value of the rise time indicated by the rise time criteria information 92 of the VDDPD power supply voltage. End the evaluation.

  As described above, when the noise analysis apparatus according to the present embodiment is used, the generated power noise and power supply voltage are reduced with respect to the semiconductor integrated circuit that uses the plurality of power switch groups to connect and disconnect the power of the internal circuit in the semiconductor integrated circuit. Rise time can be optimized. In addition, since the noise analysis apparatus according to the present embodiment analyzes using the circuit model of the basic unit circuit based on the circuit scale information of the logic circuit of the internal circuit, the internal circuit is not extracted from the layout data after layout. Thus, it is possible to optimize power supply noise and power supply rise time generated in the initial design stage before layout.

  As described above, at the initial stage of design, particularly during operation of an input / output circuit (IO circuit) of a semiconductor integrated circuit typified by power supply noise represented by IR-Drop power supply noise or SSO power supply noise. When considering power supply noise and the like, power supply noise generated when the power supply is connected can be considered. As a result, it is possible to take a correction method that affects the power supply design and logic circuit of the semiconductor integrated circuit without performing analysis using layout data in the latter half of the design.

  The noise analysis apparatus according to the above-described embodiment can be realized by, for example, a computer having a CPU or MPU, RAM, ROM, and the like executing a program stored in a storage unit such as a ROM, and the program is an embodiment of the present invention. include. Further, a program that causes a computer to perform the above functions can be realized by recording the program on a recording medium such as a CD-ROM and causing the computer to read the program. It is included in the embodiment. As a recording medium for recording the program, besides a CD-ROM, a flexible disk, a hard disk, a magnetic tape, a magneto-optical disk, a nonvolatile memory card, or the like can be used.

  In addition, a program product in which the functions of the above-described embodiments are realized by a computer executing a program and performing processing is included in the embodiments of the present invention. Examples of the program product include a program that realizes the functions of the embodiment and a computer in which the program is read. The program product includes a transmission device that can provide the program to a computer that is communicably connected via a network, a network system that includes the transmission device, and the like.

  In addition, when the supplied program realizes the functions of the above embodiment in cooperation with an OS (operating system) running on a computer or other application software, the program is included in the embodiment of the present invention. It is. In addition, when all or part of the processing of the supplied program is performed by a function expansion board or a function expansion unit of a computer to realize the functions of the embodiment, such a program is included in the embodiment of the present invention. . In order to use the present invention in a network environment, all or a part of the program may be executed by another computer.

For example, the noise analysis apparatus according to the above-described embodiment can be realized by a computer function 1000 as shown in FIG. 10, and the CPU 1001 performs the operation in the above-described embodiment.
As shown in FIG. 10, the computer function 1000 includes a CPU 1001, a ROM 1002, a RAM 1003, a controller (CONSC) 1005 of an operation unit (CONS) 1009, and a display controller (DISPC) of a display (DISP) 1010 as a display unit. 1006, a controller (DCONT) 1007 of a storage device (STD) 1012 such as a hard disk (HD) 1011 and a flexible disk, and a network interface card (NIC) 1008 are connected to each other via a system bus 1004. It is configured.

  The CPU 1001 generally controls each component connected to the system bus 1004 by executing software (program) stored in the ROM 1002 or the HD 1011 or software (program) supplied from the STD 1012. That is, the CPU 1001 reads out from the ROM 1002, the HD 1011 or the STD 1012 and executes a processing program for realizing the functions as described above, thereby performing control for realizing the functions in the embodiment. The RAM 1003 functions as a main memory or work area for the CPU 1001.

  The CONSC 1005 controls an instruction input from the CONS 1009 or a pointing device (not shown). The DISPC 1006 controls the display of the DISP 1010. The DCONT 1007 controls access to the HD 1011 and the STD 1012 that store a boot program, various applications, user files, a network management program, a processing program for realizing the functions according to the embodiment, and the like. The NIC 1008 exchanges data with other devices on the network 1013 in both directions.

The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Appendix 1)
An analysis model creation unit for creating an analysis model of a basic unit circuit related to power supply noise analysis;
The basic unit circuit created by the analysis model creation unit is incorporated as an analysis model of the internal circuit of the semiconductor integrated circuit, and a plurality of switch groups for controlling power supply to the internal circuit are provided in the previous stage of the layout of the semiconductor integrated circuit. A noise analysis apparatus comprising: a power supply noise calculation unit that calculates power supply noise generated when a power supply of an internal circuit is connected and disconnected in a semiconductor integrated circuit using the power supply control circuit.
(Appendix 2)
The noise analysis apparatus according to claim 1, further comprising a reference value determination unit that determines whether or not the calculated power supply noise is equal to or less than a reference value.
(Appendix 3)
The analysis model created by the analysis model creation unit is a basic unit capable of evaluating a current flowing into the power supply of the internal circuit when the internal circuit of the semiconductor integrated circuit is connected to or disconnected from the power supply by the power supply control circuit. The noise analysis apparatus according to appendix 1 or 2, wherein the noise analysis apparatus is a circuit.
(Appendix 4)
A power rise time calculation unit for calculating a rise time of the power supplied to the power domain in the internal circuit;
The noise analysis apparatus according to any one of appendices 1 to 3, wherein the reference value determination unit determines whether or not the calculated power-on rise time is equal to or less than a reference value.
(Appendix 5)
Incorporating a basic unit circuit related to power supply noise analysis as an analysis model of an internal circuit of the semiconductor integrated circuit,
When the power supply of the internal circuit is connected and disconnected in the semiconductor integrated circuit using the power supply control circuit having a plurality of switch groups for controlling the power supply to the internal circuit in the previous stage of the layout of the semiconductor integrated circuit. A noise analysis method comprising: a power supply noise calculation step of calculating generated power supply noise.
(Appendix 6)
A step of incorporating a basic unit circuit related to power supply noise analysis as an analysis model of an internal circuit of the semiconductor integrated circuit;
When the power supply of the internal circuit is connected and disconnected in the semiconductor integrated circuit using the power supply control circuit having a plurality of switch groups for controlling the power supply to the internal circuit in the previous stage of the layout of the semiconductor integrated circuit. A program for causing a computer to execute a power noise calculation step for calculating power noise generated.

PW1 Power supply section PSWC1 Power switch control circuit BF Power switch drive buffer PSWG Power switch group PD Power domain

Claims (5)

An analysis model creation unit for creating an analysis model of a basic unit circuit related to power supply noise analysis;
The basic unit circuit created by the analysis model creation unit is incorporated as an analysis model of the internal circuit of the semiconductor integrated circuit, and a plurality of switch groups for controlling power supply to the internal circuit are provided in the previous stage of the layout of the semiconductor integrated circuit. A noise analysis apparatus comprising: a power supply noise calculation unit that calculates power supply noise generated when a power supply of an internal circuit is connected and disconnected in a semiconductor integrated circuit using the power supply control circuit.   The noise analysis apparatus according to claim 1, further comprising a reference value determination unit that determines whether or not the calculated power supply noise is equal to or less than a reference value.   The analysis model created by the analysis model creation unit is a basic unit capable of evaluating a current flowing into the power supply of the internal circuit when the internal circuit of the semiconductor integrated circuit is connected to or disconnected from the power supply by the power supply control circuit. 3. The noise analyzing apparatus according to claim 1, wherein the noise analyzing apparatus is a circuit. A power rise time calculation unit for calculating a rise time of the power supplied to the power domain in the internal circuit;
The noise analysis apparatus according to claim 1, wherein the reference value determination unit determines whether or not the calculated rise time of the power supply is equal to or less than a reference value. Incorporating a basic unit circuit related to power supply noise analysis as an analysis model of an internal circuit of the semiconductor integrated circuit,
When the power supply of the internal circuit is connected and disconnected in the semiconductor integrated circuit using the power supply control circuit having a plurality of switch groups for controlling the power supply to the internal circuit in the previous stage of the layout of the semiconductor integrated circuit. A noise analysis method comprising: a power supply noise calculation step of calculating generated power supply noise.

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