JP2011217134A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operation speed of a semiconductor integrated circuit by rapidly setting an internal voltage line at a predetermined voltage without degrading reliability of a switch.SOLUTION: This semiconductor integrated circuit includes: a first switch turned on in response to activation of a first switch control signal for connecting a first high-voltage line supplied with a first high voltage to an internal voltage line; a first voltage generation circuit operating in response to activation of a first voltage generation signal for generating the first high voltage; and a level comparator operating in response to the activation of the first voltage generation signal, comparing the first high voltage with the voltage of the internal voltage line, and activating the first switch control signal when a difference between the first high voltage and the voltage of the internal voltage line is set at a predetermined value. By comparing voltages applied to both ends of the first switch with each other and turning on the first switch when the voltage difference is decreased, the internal voltage line can be rapidly set at the predetermined voltage without degrading reliability of the first switch.

Description

  The present invention relates to a semiconductor integrated circuit having an internal voltage line set to a predetermined voltage.

  A voltage generation circuit that generates an internal voltage lower than the power supply voltage by connecting a power supply voltage line and an internal voltage line to the source and drain of the transistor and receiving a control voltage at the gate is known. In this type of voltage generation circuit, a control voltage supplied to the gate of the transistor is generated by comparing a monitor voltage corresponding to the internal voltage with a reference voltage (see, for example, Patent Document 1).

  When a high voltage or a low voltage is selectively supplied to the internal voltage line, the high voltage line and the low voltage line are respectively connected to the internal voltage line by a switch that is selectively turned on (see, for example, Patent Document 2). An internal voltage higher than the power supply voltage is generated by operating the booster circuit in synchronization with the clock signal. At this time, an internal voltage having a predetermined value is generated by adjusting the frequency of the clock signal by comparing the internal voltage with the reference voltage (see, for example, Patent Document 3).

JP 2000-058661 A JP 2004-186435 A JP 2000-31471 A

  When supplying a voltage generated by a voltage generation circuit or the like to the internal voltage line through the switch, it is not desirable in terms of reliability to turn on the switch in a state where the voltage difference between both ends of the switch is large. For example, when the switch is turned on after the voltage of the internal voltage line becomes sufficiently low, the switch reliability can be prevented from being lowered, but the switch on timing is delayed. As a result, it takes time until the internal voltage line is set to a predetermined voltage, and the operation speed of the semiconductor integrated circuit cannot be improved.

  An object of the present invention is to quickly set an internal voltage line to a predetermined voltage without reducing the reliability of the switch, and to improve the operation speed of the semiconductor integrated circuit.

  In one form of the present invention, a semiconductor integrated circuit includes a first switch that is turned on in response to activation of a first switch control signal to connect a first high voltage line supplied with a first high voltage to an internal voltage line. A first voltage generation circuit that operates in response to the activation of the first voltage generation signal to generate the first high voltage, and a first high voltage that operates in response to the activation of the first voltage generation signal. A level comparator that compares the voltage of the internal voltage line and activates the first switch control signal when the difference between the first high voltage and the voltage of the internal voltage line reaches a predetermined value is provided.

  By comparing the voltage applied to both ends of the first switch and turning on the first switch when the voltage difference becomes small, the internal voltage line can be quickly brought to a predetermined voltage without degrading the reliability of the first switch. Can be set. As a result, the operation speed of the semiconductor integrated circuit can be improved.

1 illustrates an example of a semiconductor integrated circuit according to an embodiment. The example of the semiconductor integrated circuit in another embodiment is shown. 3 shows an example of the memory core shown in FIG. The example of the voltage control circuit shown in FIG. 2 is shown. 5 shows an example of the level comparator shown in FIG. The example of the 2nd voltage generation circuit, voltage switching circuit, and discharge circuit which were shown in FIG. 2 is shown. 7 shows an example of the level comparator shown in FIG. 5 shows an example of the operation of the voltage control circuit shown in FIG. 3 shows another example of a voltage control circuit and a voltage switching circuit. 10 illustrates an example of operations of the voltage control circuit and the voltage switching circuit illustrated in FIG. 9. 10 shows another example of the operation of the voltage control circuit and the voltage switching circuit shown in FIG. The example of the voltage control circuit in another embodiment is shown. 13 shows an example of a control gate voltage generation operation of a semiconductor integrated circuit having the voltage control circuit shown in FIG. The example of the voltage control circuit in another embodiment is shown. 15 shows an example of the operation of the voltage control circuit shown in FIG. 15 shows another example of the operation of the voltage control circuit shown in FIG. 15 shows another example of the operation of the voltage control circuit shown in FIG. The example of the semiconductor integrated circuit in another embodiment is shown. An example of the voltage control circuit shown in FIG. 18 is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. The example of the voltage control circuit in another embodiment is shown. An example of the operation of the voltage control circuit shown in FIG. 26 is shown. 1 illustrates an example of a system in which the semiconductor integrated circuit according to the above-described embodiment is mounted.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, the signal lines indicated by bold lines are composed of a plurality of lines. A part of the block to which the thick line is connected is composed of a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal preceded by “/” indicates negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor integrated circuit SEM in an embodiment. The semiconductor integrated circuit SEM includes a first voltage generation circuit V1GEN, a first switch SW1, and a level comparator CMP1. The first voltage generation circuit V1GEN operates in response to the activation of the first voltage generation signal VCG1GEN, and generates the first high voltage VCG1. The first switch SW is turned on in response to activation of the first switch control signal SW1ON in order to connect the first high voltage line VCG1 to which the first high voltage VCG1 is supplied to the internal voltage line VCG. The level comparator CMP1 operates in response to the activation of the first voltage generation signal VCG1GEN, and compares the first high voltage VCG1 with the internal voltage VCG. The level comparator CMP1 activates the first switch control signal SW1ON when the difference between the first high voltage VCG1 and the internal voltage VCG reaches a predetermined value.

  For example, when the first voltage generation circuit V1GEN stops operating and the first switch SW1 is turned on when the voltage of the first high voltage line VCG1 is low, a high voltage is applied across the first switch SW1. There is a fear. In this embodiment, after the first voltage generation circuit V1GEN starts generating the first high voltage VCG1, the first switch control signal SW1ON is turned on when the difference between the first high voltage VCG1 and the internal voltage VCG becomes a predetermined value. Is activated. For example, the first switch control signal SW1ON is activated when the internal voltage VCG becomes equal to the first high voltage VCG1. Alternatively, the first switch control signal SW1ON is activated when the internal voltage VCG becomes lower than the first high voltage VCG1. Alternatively, the first switch control signal SW1ON is activated when the internal voltage VCG becomes lower than a value obtained by adding a predetermined voltage to the first high voltage VCG1.

  Thereby, the first switch SW1 can be turned on after the voltage difference applied between both ends of the first switch SW1 becomes small. In other words, it is possible to prevent the first switch SW1 from being turned on in a state where a high voltage is applied between both ends of the first switch SW1, and it is possible to prevent the reliability of the first switch SW1 from being lowered. In addition, since the operation of the first voltage generation circuit V1GEN can be started without waiting for the internal voltage VCG to decrease, the internal voltage VCG can be quickly set to the first high voltage VCG1. Thereby, the semiconductor integrated circuit SEM can be operated at high speed.

  As described above, in this embodiment, the first high voltage VCG1 and the internal voltage VCG applied to both ends of the first switch SW1 are compared by the level comparator CMP1, and the first switch SW1 is turned on when the voltage difference becomes small. Thereby, the internal voltage line VCG can be quickly set to the predetermined voltage VCG1 without reducing the reliability of the first switch SW1, and the operation speed of the semiconductor integrated circuit SEM can be improved.

  FIG. 2 shows an example of a semiconductor integrated circuit SEM in another embodiment. For example, the semiconductor integrated circuit SEM is a nonvolatile semiconductor memory such as a NOR flash memory. The semiconductor integrated circuit SEM includes a command decoder 12, an operation control circuit 14, an address decoder 16, a data input / output circuit 18, a voltage control circuit 20, a first voltage generation circuit 22, a second voltage generation circuit 24, a voltage switching circuit 26, a discharge. The circuit 28 and the memory core 30 are included.

  The command decoder 12 decodes command signals such as the chip enable signal / CE and the write enable signal / WE, and outputs the decoded result to the operation control circuit 14. The operation control circuit 14 outputs a control signal and a timing signal for operating the memory core 30 in accordance with a signal from the command decoder 12. For example, when a write command is supplied as a command signal, the operation control circuit 14 outputs a program control signal PG for causing the memory core 30 to execute a write operation. When an erase command is supplied as a command signal, the operation control circuit 14 outputs an erase control signal ERS for causing the memory core 30 to execute an erase operation. Further, when a read command is supplied as a command signal, the operation control circuit 14 outputs a read control signal RD for causing the memory core 30 to execute a read operation.

  The write operation is an operation of setting logic 0 to the memory cell MC shown in FIG. The erase operation is an operation for setting logic 1 to the memory cell MC. For example, the logic 0 is set by increasing the threshold voltage of the memory transistor MT (FIG. 3) that forms the memory cell MC. For example, the logic 1 is set by lowering the threshold voltage of the memory transistor MT. The threshold voltage of the memory transistor MT increases when charges are accumulated in the floating gate, and decreases when charges are extracted from the floating gate.

  The address decoder 16 decodes the address signal AD and outputs it to the memory core 30 as the address decode signal ADEC. The data input / output circuit 18 outputs the logic of the read data output from the memory core 30 to the data terminal I / O during the read operation. The data input / output circuit 18 outputs the logic of the write data supplied to the data terminal I / O to the memory core 30 during the write operation.

  The voltage control circuit 20 operates to set the control gate, source, and drain of the memory cell MC (that is, the memory transistor MT) to a predetermined voltage in the write operation, the erase operation, and the read operation. In the following description, a circuit that operates to control the control gate voltage VCG connected to the control gate of the memory transistor in the write operation will be described. The voltage control circuit 20 generates a first voltage generation signal VCG1GEN, a second voltage generation signal VCG2GEN, a switch control signal SW1ON, and a discharge enable signal DCEN based on the program control signal PG, and receives the switch control signal / SW1ON. An example of the voltage control circuit 20 is shown in FIG.

  The first voltage generation circuit 22 generates the first high voltage VCG1 on the first high voltage line VCG1 when the first voltage generation signal VCG1GEN is activated to a high level. The first voltage generation circuit 22 stops generating the first high voltage VCG1 when the first voltage generation signal VCG1GEN is inactivated to a low level. For example, the first high voltage VCG1 is 5V and is supplied to the control gate when checking the threshold voltage of the memory transistor. The threshold voltage is confirmed during a read operation and a verify operation in a write operation. An example of the first voltage generation circuit 22 is shown in FIG.

  The second voltage generation circuit 24 generates the second high voltage VCG2 on the second high voltage line VCG2 when the second voltage generation signal VCG2GEN is activated to a high level. The second voltage generation circuit 24 stops generating the second high voltage VCG2 when the second voltage generation signal VCG2GEN is inactivated to a low level. For example, the second high voltage VCG2 is 9V and is supplied to the control gate when the threshold voltage of the memory transistor is increased.

  The voltage switching circuit 26 connects the first high voltage line VCG1 to the control gate line VCG that is an internal voltage line when the switch control signal SW1ON is activated to a high level. The voltage switching circuit 26 connects the second high voltage line VCG2 to the control gate line VCG when the second voltage generation signal VCG2GEN is activated to a high level. Further, the voltage switching circuit 26 inverts the logic level of the switch control signal SW1ON and outputs it to the voltage control circuit 20 as the switch control signal / SW1ON. An example of the voltage switching circuit 26 is shown in FIG.

  When the discharge enable signal DCEN is activated to a high level, the discharge circuit 28 connects the control gate line VCG to the ground line VSS and discharges the charge on the control gate line VCG. For example, the discharge circuit 28 is connected to the control gate line VCG on the side close to the voltage control circuit 20 and the voltage switching circuit 26 (near end side). The discharge circuit 28 may be connected to a control gate line VCG on the end side (far end side; lower side in FIG. 2) of the memory core 30 that is separated from the voltage control circuit 20 and the voltage switching circuit 26. An example of the discharge circuit 28 is shown in FIG.

  The memory core 30 has, for example, 16 sectors SEC (SEC0, SESC1,..., SEC15). Each sector SEC includes a sector switch SSW, a word decoder WDEC, and a memory cell array ARY. An example of the memory core 30 is shown in FIG.

  FIG. 3 shows an example of the memory core 30 shown in FIG. The sector switch SSW of each sector SEC has a pMOS transistor that is turned on when the sector selection signal SSEL (SSEL0, SSEL1,..., SSEL15) is at a low level. In the write operation, one of the sector selection signals SSEL is activated to a low level according to the address decode signal ADEC, and any sector switch SSW of the sector SEC is turned on. When the sector switch SSW is turned on, the corresponding sector control gate line SVCG is connected to the control gate line VCG and set to a high level voltage (first high voltage VCG1 or second high voltage VCG2). The control gate line VCG is wired to many sectors SEC and has a long wiring length. The control gate line VCG is connected to a sector switch SSW having a transistor size larger than that of a logic circuit transistor. For this reason, the parasitic capacitance of the control gate line VCG is large.

  The word decoder WDEC operates in response to the high level voltage of the sector control gate line SVCG, and sets one of the word lines WL to the high level voltage according to the address decode signal ADEC. The memory cell array ARY has a plurality of nonvolatile memory cells MC arranged in a matrix. Each memory cell MC has a memory transistor MT. The memory transistor MT has an nMOS transistor structure, and has a floating gate for storing electrons and a control gate connected to the word line WL. Note that the memory transistor MT may be formed using a trap gate in which electrons are accumulated at a predetermined location. In the memory transistor MT, the threshold voltage changes by changing the amount of charge accumulated in the floating gate in accordance with the control gate voltage VCG applied to the control gate. The memory cell MC stores data logic according to the threshold voltage.

  The control gates of the columns of the memory transistors MT arranged in the horizontal direction in FIG. 3 are connected to a common word line WL. The source and drain of the column of memory transistors MT arranged in the vertical direction in FIG. 3 are connected to a common source line SL and a common bit line BL.

  FIG. 4 shows an example of the voltage control circuit 20 shown in FIG. The voltage control circuit 20 includes a timing control circuit 21, a level comparator CMP1, and a buffer circuit BUF1. The timing control circuit 21 generates a first voltage generation signal VCG1GEN and a second voltage generation signal VCG2GEN according to the program control signal PG. The level comparator CMP1 compares the first high voltage VCG1 with the control gate voltage VCG, and activates the switch control signal SW1ON to a high level when the control gate voltage VCG is lower than the first high voltage VCG1. An example of the level comparator CMP1 is shown in FIG. Note that the level comparator CMP1 may be formed outside the voltage control circuit 20.

  Buffer circuit BUF1 activates discharge enable signal DCEC to a high level when both first voltage generation signal VCG1GEN and switch control signal / SW1ON are at a high level. The double line power supply shown in the level comparator CMP1 and the buffer circuit BUF1 indicates that the same high voltage (for example, 9V) as the second high voltage VCG2 is supplied, for example. In a logic element such as a buffer circuit BUF1 that operates by receiving a power source indicated by a double line, a voltage dividing transistor DTR is inserted in order to prevent a high voltage from being applied between the source and drain of each transistor. Also in the subsequent drawings, the logic circuit that receives the power of the double line is supplied with the same high voltage (for example, 9V) as the second high voltage VCG2, and the voltage dividing transistor DTR is inserted.

  FIG. 5 shows an example of the level comparator CMP1 shown in FIG. The level comparator CMP1 includes a current mirror type amplifier AMP1, a pMOS transistor PM1, and an inverter IV1. The amplifier AMP1 differentially amplifies the voltage levels of the control gate voltage VCG and the first high voltage VCG1, and outputs a signal indicating the level difference between the control gate voltage VCG and the first high voltage VCG1 to the output node OUT1. The amplifier AMP1 performs a voltage level comparison operation when the first voltage generation signal VCG1GEN is at a high level. The nMOS transistor NM1 that receives the voltage VCMN at its gate operates as a constant current source. For example, the voltage VCMN is set to a constant value that does not depend on the power supply voltage using a semiconductor band gap.

  The pMOS transistor PM1 resets the output node OUT1 to high level when the first voltage generation signal VCG1GEN is inactivated to low level. The inverter IV1 inverts the logic level of the output node OUT1 and outputs it as the switch control signal SW1ON.

  FIG. 6 shows an example of the first voltage generation circuit 22, the voltage switching circuit 26, and the discharge circuit 28 shown in FIG. The first voltage generation circuit 22 has a constant voltage generation circuit CVGEN having a level comparator CMP2 and a regulator RGL formed of an nMOS transistor. The constant voltage generation circuit CVGEN includes a pMOS transistor PM2, an nMOS transistor NM2, and resistors Ra and Rb connected in series between a high voltage line and a ground line. The gate of the pMOS transistor PM2 receives the output RON of the level comparator CMP2. The nMOS transistor NM2 is diode-connected.

  The level comparator CMP2 operates when the first voltage generation signal VCG1GEN is activated to a high level. The level comparator CMP2 uses the monitor voltage MONI1 generated at the connection node of the resistors Ra and Rb as the reference voltage VREF. And a control signal RON for turning on the regulator RGL is generated. The regulator RGL generates a first high voltage VCG1 by stepping down the high voltage (for example, 9V) generated by the high voltage generation circuit.

  For example, when the gate voltage VG of the regulator RGL is lower than the expected value, the monitor voltage MONI1 becomes lower than the reference voltage VREF, and the voltage of the control signal RON becomes lower. As a result, the source-drain resistance of the pMOS transistor PM2 decreases and the gate voltage VG increases. On the other hand, when the gate voltage VG of the regulator RGL is higher than the expected value, the monitor voltage MONI1 becomes higher than the reference voltage VREF, and the voltage of the control signal RON becomes higher. As a result, the resistance between the source and drain of the pMOS transistor PM2 increases and the gate voltage VG decreases. By repeating such control, the gate voltage VG is held at a predetermined value.

  In this embodiment, for example, the threshold voltage of the nMOS transistor of the regulator RGL is 0.5V, the source voltage is 9V, and the gate voltage VG is set to 5.5V. At this time, the first high voltage VCG1 (5V) lower than the gate voltage VG by the threshold voltage of the nMOS transistor is generated by the regulator RGL. In the first voltage control circuit 22, a regulator RGL is formed to supply charges to the first high voltage line VCG1, but a discharge path when the first high voltage VCG1 exceeds a target value (design value). There is no. Therefore, the bleeder circuit BLD formed by the high resistance element is disposed between the first high voltage line VCG1 and the ground line VSS in order to discharge excess charges. For example, the bleeder circuit BLD causes so-called creep-up in which the voltage on the first high voltage line VCG1 rises due to the leakage current of the regulator RGL even when the charge on the first high voltage line VCG1 is hardly used and the current consumption is small. Reduction can be prevented.

  The voltage switching circuit 26 includes, for example, a first switch SW1 and a second switch SW2 including a CMOS transmission gate. The first switch SW1 is turned on when the switch control signal SW1ON is activated to a high level, and connects the first high voltage line VCG1 to the control gate line VCG. The second switch SW2 is turned on when the second voltage generation signal VCG2GEN is activated to a high level, and connects the second high voltage line VCG2 to the control gate line VCG.

  The discharge circuit 28 includes nMOS transistors NM3 and NM4 connected in series between the control gate line VCG and the ground line VSS. The nMOS transistor NM3 receives the power supply voltage VDD at its gate and functions as a voltage dividing transistor. For example, the power supply voltage VDD is supplied to the power supply terminal of the semiconductor integrated circuit SEM. The nMOS transistor NM4 is turned on when receiving a high level discharge enable signal DCEC at its gate. The nMOS transistors NM3 and NM4 function as a discharge switch that connects the control gate line VCG to the ground line VSS.

  FIG. 7 shows an example of the level comparator CMP2 shown in FIG. The level comparator CMP2 is the same circuit as the level comparator CMP1 shown in FIG. 5, and includes an amplifier AMP1, a pMOS transistor PM1, and an inverter IV1. The amplifier AMP1 operates when the first voltage generation signal VCG1GEN is activated to a high level, and outputs a signal indicating a level difference between the monitor voltage MONI1 and the reference voltage VREF to the output node OUT1.

  The pMOS transistor PM1 resets the output node OUT1 to high level when the first voltage generation signal VCG1GEN is inactivated to low level. The inverter IV1 inverts the logic level of the output node OUT1 and outputs it as the switch control signal SW1ON.

  FIG. 8 shows an example of the operation of the voltage control circuit 20 shown in FIG. FIG. 8 shows an operation when the verify operation VRFY is performed after the program operation PGM in the write operation of the memory core 30. In the write operation, the program operation PGM and the verify operation VRFY are repeatedly performed until the threshold voltage of the memory transistor MT of the memory cell MC becomes higher than a preset verify voltage. The control gate line VCG is set to the second high voltage VCG2 (for example, 9V) during the program operation PGM, and is set to the first high voltage VCG1 (for example, 5V) during the verify operation VRFY. The voltage of the control gate line VCG is changed from the second high voltage VCG2 to the first high voltage VCG1 during the switching period SWP.

  During the program operation PGM, since the first voltage generation signal VCG1GEN is deactivated to a low level, the level comparator CMP1 shown in FIG. 5 outputs a low-level switch control signal SW1ON (FIG. 8A). ). The second switch SW2 shown in FIG. 6 is turned on in response to the high level second voltage generation signal VCG2GEN, and the first switch SW1 is turned off in response to the low level switch control signal SW1ON (FIG. 8 ( b)). Thereby, the control gate line VCG is connected to the second high voltage line VCG2 and set to the second high voltage VCG2 (for example, 9 V) (FIG. 8C).

  The voltage control circuit 20 shown in FIG. 2 deactivates the second voltage generation signal VCG2GEN to a low level in response to the completion of the program operation PGM, and activates the first voltage generation signal VCG1GEN to a high level (FIG. 8). (D)). The second voltage generation circuit 24 illustrated in FIG. 2 stops the generation operation of the second high voltage VCG2 in response to the change of the second voltage generation signal VCG2GEN to the low level. The second switch SW2 is turned off in response to the change of the second voltage generation signal VCG2GEN to the low level ((e) in FIG. 8). Thereby, the control gate line VCG is set to a floating state of the high voltage VCG2.

  The buffer circuit BUF1 shown in FIG. 4 activates the discharge enable signal DCEC to a high level in response to the activation of the first voltage generation signal VCG1GEN (FIG. 8 (f)). The nMOS transistor NM4 of the discharge circuit 28 shown in FIG. 6 is turned on in response to the high level discharge enable signal DCEC, and draws charges from the control gate line VCG. As a result, the control gate voltage VCG decreases (FIG. 8 (g)). The level comparator CMP1 shown in FIG. 4 activates the switch control signal SW1ON when the control gate voltage VCG becomes lower than the first high voltage VCG1 (FIG. 8 (h)). The first switch SW1 is turned on in response to the activation of the switch control signal SW1ON (FIG. 8 (i)).

  In response to the activation of the switch control signal SW1ON, the switch control signal / SW1ON is activated to a low level. The buffer circuit BUF1 shown in FIG. 4 deactivates the discharge enable signal DCEC to a low level in response to the activation of the switch control signal / SW1ON (FIG. 8 (j)). The nMOS transistor NM4 of the discharge circuit 28 shown in FIG. 6 is turned off in response to the low level discharge enable signal DCEC. As a result, the connection between the control gate line VCG and the ground line VSS is released, and the discharge operation is stopped. The control gate line VCG is connected to the first high voltage line VCG1 when the first switch SW1 is turned on. The control gate voltage VCG follows the rise of the first high voltage VCG1 and rises to a voltage necessary for the verify operation VRFY (FIG. 8 (k)).

  In this embodiment, the level comparator CMP1 can stop the discharge of the control gate line VCG before the control gate voltage VCG drops to the ground voltage VSS. For this reason, the discharge period DCP can be minimized and the current consumption can be reduced. Further, the period from the completion of the program operation PGM to the start of the verify operation VRFY can be minimized, and the write operation time can be shortened.

  FIG. 9 shows another example of the voltage control circuit and the voltage switching circuit. The configuration excluding the voltage control circuit 20A and the voltage switching circuit 26A is the same as that shown in FIG. The voltage control circuit 20A does not have the level comparator CMP1 shown in FIG. The voltage control circuit 20A receives the program control signal PG and generates the second voltage generation signal VCG2GEN, the discharge enable signal DCEN, and the first voltage generation signal VCG1GEN. For example, the second voltage generation signal VCG2GEN, the discharge enable signal DCEN, and the first voltage generation signal VCG1GEN are sequentially activated to a high level in response to the program control signal PG using a delay circuit. Further, the first switch SW1 of the voltage switching circuit 26A shown in FIG. 9 is turned on during the high level period of the first voltage generation signal VCG1GEN.

  FIG. 10 shows an example of the operation of the voltage control circuit 20A and the voltage switching circuit 26A shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. FIG. 10 shows the operation when the verify operation VRFY is performed after the program operation PGM in the write operation of the memory core 30 as in FIG. The control gate line VCG is set to the second high voltage VCG2 during the program operation PGM, and is set to the first high voltage VCG1 during the verify operation VRFY. The waveform until the second voltage generation signal VCG2GEN changes to a low level is the same as that in FIG. 8 except that the switch control signal SW1ON is not present.

  After deactivating the second voltage generation signal VCG2GEN, the voltage control circuit 20A activates the discharge enable signal DCEN to a high level for a predetermined period (FIG. 10 (a)). The discharge period DCP, which is the activation period of the discharge enable signal DCEN, is designed with a margin so that the control gate voltage VCG is lowered to the ground voltage VSS by the discharge circuit 28. As a result, even when the power supply voltage is low and the threshold voltage of the transistor is high, the control gate voltage VCG reliably decreases to the ground voltage VSS (FIG. 10B).

  Next, the voltage control circuit 20A activates the first voltage generation signal VCG1GEN to a high level in response to the inactivation of the discharge enable signal DCEN (FIG. 10 (c)). Thereby, the generation of the first high voltage VCG1 is started, and the first switch SW1 is turned on (FIG. 10 (d)). When the first switch SW1 is turned on, the control gate voltage VCG rises together with the first high voltage VCG1 (FIG. 10 (e)).

  In the operation shown in FIG. 10, since the discharge period DCP is set using a timing circuit such as a delay circuit, it is necessary to consider a temperature margin and a circuit margin, which is longer than that in FIG. Since the generation start timing of the high voltage VCG1 is set after the end of the discharge period DCP, it is delayed as compared with FIG. In order to prevent the control gate voltage VCG at the start of the verify operation VRFY from becoming higher than the first high voltage VCG1 (5V), the ON period of the first switch SW1 is set without overlapping the discharge period DCP. Is done. As a result, the time from the completion of the program operation PGM to the start of the verify operation VRFY becomes longer, and the write operation time becomes longer. In particular, since the operation of FIG. 10 is performed a plurality of times during one write operation, the influence of the decrease in the write operation speed is great. Further, since the charge on the control gate voltage VCG is discharged to the ground voltage VSS, a wasteful current is consumed as compared with FIG.

  FIG. 11 shows another example of the operation of the voltage control circuit 20A and the voltage switching circuit 26A shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. FIG. 11 shows the operation when the verify operation VRFY is performed after the program operation PGM in the write operation of the memory core 30, as in FIG. 8 and FIG. The waveform until the second voltage generation signal VCG2GEN changes to a low level is the same as that in FIG. 8 except that the switch control signal SW1ON is not present. FIG. 11 shows an example in which the generation timing of the first voltage generation signal VCG1GEN by the voltage control circuit 20A shown in FIG. 9 is too early. For example, the waveform of FIG. 11 is likely to occur when the power supply voltage is high and the operating temperature is low in the circuit shown in FIG.

  When the discharge period DCP is short, the first switch SW1 is turned on before the control gate voltage VCG drops to a predetermined value (for example, 5 V) of the first high voltage VCG1 (FIG. 11A). It is not desirable to turn on the first switch SW1 when the control gate voltage VCG is high and the first high voltage VCG1 is low. In other words, turning on the first switch SW1 with a high voltage applied between the source and drain of the transistor formed in the first switch SW1 reduces the reliability of the first switch SW1.

  As shown in FIG. 3, the control gate line VCG is wired to many sectors SEC and has a large parasitic capacitance. As a result, the charge on the control gate line VCG flows into the first high voltage line VCG1 via the first switch SW1, and the first high voltage VCG1 becomes higher than a target value (for example, 5 V) by the regulator RGL (FIG. 11 (b)). Before the verify operation VRFY is started, the discharge path (current consumption path) from the first high voltage line VCG1 to the ground line VSS is only the bleeder circuit BLD (high resistance element). Therefore, if the voltage of the first high voltage line VCG1 becomes higher than the target value, it takes time until the control gate voltage VCG becomes a normal value (for example, 5V), and there is a possibility that the correct verify operation VRFY cannot be performed. (FIG. 11C).

  On the other hand, in the circuit of FIG. 6, as shown in FIG. 8, the first switch SW1 is turned on after the control gate voltage VCG becomes lower than the first high voltage VCG1. Therefore, even when the discharge period DCP is short, the first high voltage VCG1 does not become higher than the target value, and a correct verify operation can always be performed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by using the level comparator CMP1, the discharging operation by the discharging circuit 28 and the generating operation of the first high voltage VCG1 by the first voltage generating circuit 22 can be performed simultaneously. As a result, the time from the completion of the program operation PGM until the control gate voltage VCG becomes lower than the first high voltage VCG1 (that is, the discharge period DCP) can be shortened, and the verify operation VRFY can be started early. As a result, the write operation time of the semiconductor integrated circuit SEM can be shortened. In particular, when the program operation PGM and the verify operation VRFY are repeatedly performed in the write operation of the memory cell MC having the floating gate, the write operation time can be shortened and the performance of the semiconductor integrated circuit SEM can be improved.

  FIG. 12 shows an example of a voltage control circuit 20B in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20B is the same as that in FIG. That is, the voltage control circuit 20B is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  The voltage control circuit 20B is different from the timing control circuit 21 in FIG. Further, the voltage control circuit 20B is obtained by adding a NOR gate, a buffer circuit BUF2, and a flip-flop circuit FF1 to the voltage control circuit 20 shown in FIG. Further, the level comparator CMP1 of the voltage control circuit 20B receives the control gate voltage VCG at the positive (+) input terminal and the first high voltage VCG1 at the negative (−) input terminal. The level comparator CMP1 may be formed outside the voltage control circuit 20B.

  The timing control circuit 21 sets the low voltage mode signal LMODE and the other mode signal OMODE to a low level during a program operation in response to the program control signal PG. The timing control circuit 21 sets the low voltage mode signal LMODE to a high level during a verify operation in response to the program control signal PG. The timing control circuit 21 sets the other mode signal OMODE to a high level when neither the program operation nor the verify operation is executed.

  The NOR gate activates the second voltage generation signal VCG2GEN to a high level when both the low voltage mode signal LMODE and the other mode signal OMODE are at a low level, that is, during a program operation. The buffer circuit BUF2 activates the first voltage generation signal VCG1GEN to a high level when the low voltage mode signal LMODE is at a high level, that is, during a verify operation.

  The level comparator CMP1 outputs a high level when the control gate voltage VCG is higher than the first high voltage VCG1, and outputs a low level when the control gate voltage VCG is lower than the first high voltage VCG1. The level comparator CMP1 operates during the activation of the first voltage generation signal VCG1GEN, and outputs a high level during the inactivation of the first voltage generation signal VCG1GEN. Therefore, the level comparator CMP1 has an nMOS transistor having a drain connected to the output node OUT1 and a source connected to the ground line VSS instead of the pMOS transistor PM1 shown in FIG. The gate of the nMOS transistor receives an inverted signal of the first voltage generation signal VCG1GEN. The flip-flop circuit FF1 activates the switch control signal SW1ON to a high level in response to the low level output of the level comparator CMP1. The flip-flop circuit FF1 deactivates the switch control signal SW1ON to a low level in response to the deactivation of the first voltage generation signal VCG1GEN to a low level.

  The flip-flop circuit FF1 activates the switch control signal SW1ON to a high level when the control gate voltage VCG <the first high voltage VCG1 is first detected by the level comparator CMP1. Thereafter, even if the levels of the control gate voltage VCG and the first high voltage VCG1 are inverted and the output level of the level detector CMP1 changes, the output of the flip-flop circuit FF1 does not change. Therefore, it is possible to prevent the level of the switch control signal SW1ON from being repeatedly inverted even when the control gate voltage VCG and the first high voltage VCG1 are substantially equal and the output of the level comparator CMP1 is unstable. The operation of the voltage control circuit 12B shown in FIG. 12 is the same as that in FIG.

  FIG. 13 shows an example of the operation of generating the control gate voltage VCG in the semiconductor device SEM having the voltage control circuit 20B shown in FIG. When the other mode signal OMODE and the low voltage mode signal LMODE are both at the low level L, the second voltage generation signal VCG2GEN changes to the high level H in order to perform the program operation PGM. As a result, the second switch SW2 is turned on, and the control gate line VCG is connected to the second high voltage line VCG2.

  When the other mode signal OMODE is at the low level L and the low voltage mode signal LMODE is at the high level H, the first voltage generation signal VCG1GEN changes to the high level H and the discharge enable signal DCEC is set to a predetermined level in order to perform the verify operation. It changes to the high level H during this period. As a result, the first switch SW1 is turned on, and the control gate line VCG is connected to the first high voltage line VCG1.

  When the other mode signal OMODE is at the high level H and the low voltage mode signal LMODE is at the low level L, the first and second voltage generation signals VCG1GEN, VCG2GEN and the discharge enable signal DCEC are all held at the low level. As a result, the connection between the control gate line VCG and the first and second high voltage lines VCG1 and VCG2 is released.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by disposing the flip-flop circuit FF1 between the level detector CMP1 and the first switch SW1, it is possible to prevent the level of the switch control signal SW1ON from being repeatedly inverted during the operation of the level detector CMP1. As a result, the first switch SW1 can be prevented from being repeatedly turned off, and the voltage of the control gate line VCG can be quickly set to the target value of the first high voltage VCG1.

  FIG. 14 shows an example of a voltage switching circuit 20C in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20C is the same as that shown in FIG. That is, the voltage control circuit 20C is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  In the voltage control circuit 20C, resistors R1, R2, R3, and R4 are added to the voltage control circuit 12B shown in FIG. Other configurations of the voltage control circuit 12C are the same as those in FIG. The resistors R1 and R2 are disposed between the control gate line VCG and the ground line VSS. A divided voltage VCGM is generated from the connection node VCGM of the resistors R1 and R2. The resistors R3 and R4 are disposed between the first high voltage line VCG1 and the ground line VSS. A divided voltage VCG1M is generated from a connection node VCG1M of the resistors R3 and R4.

  For example, the resistance ratio R1: R2 of the resistors R1 and R2 and the resistance ratio R3: R4 of the resistors R3 and R4 are both “1”. Therefore, the divided voltage VCGM is half of the control gate voltage VCG, and the divided voltage VCG1M is half of the first high voltage VCG1. As a result, the voltage to be compared by the level comparator CMP1 can be lowered, and the level comparator CMP1 need not be formed of a high voltage transistor. For example, the transistor of the level comparator CMP1 can be formed using a thin gate insulating film with a low breakdown voltage. Thereby, the level comparator CMP1 can be operated at high speed, and the write operation time can be shortened. Further, the circuit scale of the level comparator CMP1 can be reduced.

  The resistors R1-R4 and the level comparator CMP1 may be formed outside the voltage control circuit 20C. Further, by making the resistors R3 and R4 high, the resistors R3 and R4 can function instead of the bleeder circuit BLD shown in FIGS. As a result, the bleeder circuit BLD can be eliminated.

  FIG. 15 shows an example of the operation of the voltage control circuit 20C shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. FIG. 15 shows the operation when the verify operation VRFY is performed after the program operation PGM in the write operation of the memory core 30 as in FIG.

  In this example, the level detector CMP1 shown in FIG. 14 compares the divided voltages VCGM and VCG1M. The level detector CMP1 outputs a low level when the divided voltage VCGM becomes lower than the divided voltage VCG1M, and activates the switch control signal SW1ON to a high level (FIGS. 15A and 15B). Waveforms other than the divided voltages VCGM and VCG1M are the same as those in FIG.

  FIG. 16 shows another example of the operation of the voltage control circuit 20C shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 15 are omitted. In this example, the values of the resistors R1 and R2 shown in FIG. 14 are set to R1 <R2. For this reason, the divided voltage VCGM is higher than half the value of the control gate voltage VCG (FIG. 16A). The sum of the values of the resistors R1 and R2 (R1 + R2) is the same as that in FIG. The values of the resistors R3 and R4 are the same as in FIG. For this reason, the divided voltage VCG1M is half the value of the first high voltage VCG1. That is, the ratio of the divided voltage VCGM to the internal voltage VCG is higher than the ratio of the divided voltage VCG1M to the first high voltage VCG1.

  In this example, the level detector CMP1 compares the relatively high divided voltage VCGM with the divided voltage VCG1M. In other words, the first switch SW1 is turned on when the voltage of the control gate line VCG becomes lower than the first high voltage VCG1 by a predetermined value. For this reason, the timing at which the first switch SW1 is turned on is later than those in FIGS. 8 and 15 (FIG. 16B).

  The dashed-dotted line shown in FIG. 16 indicates the voltage of the control gate line VCG on the sector SEC15 side (far end side) in FIG. When the discharge circuit 28 is arranged on the side close to the voltage control circuit 20 (near end side), the charge on the far end side of the control gate line VCG escapes more slowly than on the near end side. Therefore, as shown in FIG. 8, when the first switch SW1 is turned on when the control gate voltage VCG is lower than the first high voltage VCG1, the voltage on the far end side of the control gate line VCG becomes the first high voltage. The voltage VCG1 may be higher than the target value. At this time, the voltage change on the far end side of the control gate line VCG is the same as in FIG. 11, and the time until the control gate voltage VCG becomes a normal value in the verify operation of the sector SEC located on the far end side. It will hang.

  By making the divided voltage VCGM relatively high, the first switch SW1 can be turned on after the voltage on the far end side of the control gate line VCG becomes lower than the first high voltage VCG1. This can prevent the problem shown in FIG. 11 from occurring. The on-timing of the first switch SW1 can be delayed by relatively reducing the divided voltage VCG1M.

  FIG. 17 shows another example of the operation of the voltage control circuit 20C shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 15 are omitted. In this example, the values of the resistors R1 and R2 shown in FIG. 14 are set such that R1> R2. For this reason, the divided voltage VCGM is lower than half the value of the control gate voltage VCG (FIG. 17A). The sum of the values of the resistors R1 and R2 (R1 + R2) is the same as that in FIG. The values of the resistors R3 and R4 are the same as in FIG. For this reason, the divided voltage VCG1M is half the value of the first high voltage VCG1.

  In this example, the level detector CMP1 compares the relatively low divided voltage VCGM with the divided voltage VCG1M. In other words, the first switch SW1 is turned on when the difference between the voltage of the control gate line VCG and the first high voltage VCG1 approaches a predetermined value. For this reason, the timing at which the first switch SW1 is turned on is earlier than that in FIGS. 8 and 15 (FIG. 17B). For example, the activation timing of the switch control signal SW1ON is designed such that the first switch SW1 is turned on after the control gate voltage VCG is slightly lower than the target value of the first high voltage VCG1. Since the first switch SW1 is turned on early, the discharge period DCP can be shortened, and wasteful current that does not contribute to operation can be prevented from being consumed. In addition, the write operation time can be shortened.

  When the first switch SW1 is turned on, the voltage on the far end side of the control gate line VCG shown by the one-dot chain line in FIG. 17 is slightly higher than the target value of the first high voltage VCG1 (FIG. 17C). In this example, after the first switch SW1 is turned on, in addition to the operation of the regulator RGL, the control gate voltage VCG is quickly set to the target value (by the charge transfer from the far end side to the near end side of the control gate line VCG. For example, it can be set to 5 V) (FIG. 17D). Note that the on-timing of the first switch SW1 can also be accelerated by relatively increasing the divided voltage VCG1M.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by comparing the divided voltages VCGM and VCG1M with the level comparator CMP1, the level comparator CMP1 can be formed using a transistor that operates at high speed, and the write operation time can be shortened.

  By increasing the ratio of the divided voltage VCGM to the internal voltage VCG as compared with the ratio of the divided voltage VCG1M to the first high voltage VCG1, the on-timing of the first switch SW1 can be delayed. Thereby, the first switch SW1 can be turned on after the voltage on the far end side of the control gate line VCG becomes lower than the first high voltage VCG1, and the internal voltage VCG is higher than the target value of the first high voltage VCG1 during the verify operation VRFY. It can be prevented from becoming high. Furthermore, the bleeder circuit BLD can be made unnecessary by providing the resistors R3 and R4 with the function of the bleeder circuit BLD.

  FIG. 18 shows an example of a semiconductor integrated circuit SEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor integrated circuit SEM is a nonvolatile semiconductor memory such as a NOR flash memory. The semiconductor integrated circuit SEM has a voltage control circuit 20D instead of the voltage control circuit 20 of FIG. An example of the voltage control circuit 20D is shown in FIG. Further, the semiconductor integrated circuit SEM has a test terminal TEST and a test control circuit 10D. Other configurations of the semiconductor integrated circuit SEM are the same as those in FIG.

  The test control circuit 10D has a program circuit PGMC, and sets any one of the test control signals TM0, TM1, and TM2 to a high level according to a value programmed in the program circuit PGMC. For example, the program circuit PGMC has a nonvolatile memory cell similar to the memory cell MC. In other words, the nonvolatile memory cell has a memory transistor having a floating gate, and stores a value according to the threshold voltage of the memory transistor. Note that the program circuit PGMC may be formed outside the test control circuit 10D.

  The test control circuit 10D determines the values of the test control signals TM0 to TM2 according to the address signal AD supplied via the external terminal during the test mode in which the test terminal TEST is set to a predetermined level (for example, high level). Set. During the test mode, values programmed in the program circuit PGMC are masked. That is, the test control circuit 10D generates the test control signals TM0 to TM2 according to the address signal AD regardless of the program state of the program circuit PGMC during the test mode.

  FIG. 19 shows an example of the voltage control circuit 20D shown in FIG. The voltage control circuit 20D is different from FIG. 14 in resistance for generating the divided voltages VCGM and VCG1M. The configuration other than the resistor is the same as that shown in FIG.

  The voltage control circuit 20D is connected in series between resistors R11, R12, R13, and R14 connected in series between the control gate line VCG and the ground line VSS, and between the first high voltage line VCG1 and the ground line VSS. Resistors R31, R32, R33, and R34 are provided. The divided voltage VCGM1 is generated from the connection node of the resistors R32 and R33. The resistors R11-R14, R31-R34 and the level comparator CMP1 may be formed outside the voltage control circuit 20D.

  The connection node of the resistors R11 and R12 is connected to the voltage dividing node VCGM via the nMOS transistor NM10. The gate of the nMOS transistor NM10 receives the test control signal TM0. The connection node of the resistors R12 and R13 is connected to the voltage dividing node VCGM via the nMOS transistor NM11. The gate of the nMOS transistor NM11 receives the test control signal TM1. The connection node of the resistors R13 and R14 is connected to the voltage dividing node VCGM via the nMOS transistor NM12. The gate of the nMOS transistor NM12 receives the test control signal TM2.

  In this embodiment, one of the nMOS transistors NM10 to NM12 is turned on by the test control signals TM0 to TM2, so that three types of divided voltages VCGM can be generated. For example, the three types of divided voltages VCGM are the voltages shown in FIGS. 15, 16, and 17. That is, the nMOS transistors NM10 to NM12 function as a divided voltage changing circuit that changes the value of the divided voltage VCGM.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, the on-timing of the first switch SW1 can be set optimally in accordance with the electrical characteristics of the manufactured semiconductor integrated circuit SEM.

  FIG. 20 shows an example of a voltage control circuit 20E in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20E is the same as that in FIG. That is, the voltage control circuit 20E is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  In this embodiment, the divided voltage VCG1M can be changed according to the test control signals TM0 to TM2. The configuration other than the resistor is the same as that shown in FIGS. The voltage control circuit 20E is connected in series between the resistors R11, R12, R13, and R14 connected in series between the control gate line VCG and the ground line VSS, and between the first high voltage line VCG1 and the ground line VSS. Resistors R31, R32, R33, and R34 are provided. The resistors R11-R14, R31-R34 and the level comparator CMP1 may be formed outside the voltage control circuit 20E.

  The connection node of the resistors R31 and R32 is connected to the voltage dividing node VCG1M via the nMOS transistor NM10. The gate of the nMOS transistor NM10 receives the test control signal TM0. The connection node of the resistors R32 and R33 is connected to the voltage dividing node VCG1M via the nMOS transistor NM11. The gate of the nMOS transistor NM11 receives the test control signal TM1. The connection node of the resistors R33 and R34 is connected to the voltage dividing node VCG1M via the nMOS transistor NM12. The gate of the nMOS transistor NM12 receives the test control signal TM2.

  In this embodiment, one of the nMOS transistors NM10 to NM12 is turned on by the test control signals TM0 to TM2, so that three types of divided voltages VCG1M can be generated. That is, the nMOS transistors NM10 to NM12 function as a divided voltage changing circuit that changes the value of the divided voltage VCG1M. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 21 shows an example of a voltage control circuit 20F in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20F is the same as that shown in FIG. That is, the voltage control circuit 20F is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  The voltage control circuit 20F has capacitors C1-C4 instead of the resistors R1-R4 shown in FIG. The configuration other than the resistor is the same as that shown in FIG. Capacitors C1-C4 and level comparator CMP1 may be formed outside voltage control circuit 20F. The capacitors C1 and C2 are arranged between the control gate line VCG and the ground line VSS. The divided voltage VCGM is generated from the connection node of the capacitors C1 and C2. The capacitors C3 and C4 are disposed between the first high voltage line VCG1 and the ground line VSS. The divided voltage VCG1M is generated from the connection node of the capacitors C3 and C4.

  For example, the capacitance values of the capacitors C1 to C4 are all equal, and the capacitance ratio C1: C2 of the capacitors C1 and C2 and the capacitance ratio C3: C4 of the capacitors C3 and C4 are both “1”. Therefore, the divided voltage VCGM is half of the control gate voltage VCG, and the divided voltage VCG1M is half of the first high voltage VCG1. By generating the divided voltages VCGM and VCG1M using the capacitors C1 to C4, it is possible to eliminate a leakage current flowing from the control gate line VCG to the ground line VSS via the divided node VCGM. Further, it is possible to eliminate a leak current flowing from the high voltage line VCG1 to the ground line VSS via the voltage dividing node VCG1M. The operation of the voltage control circuit 20F is the same as that in FIG. The voltage control circuit 20F can be operated in the same manner as in FIG. 16, for example, by setting the capacitance ratio of the capacitors C1 and C2 to C1> C2, and by setting the capacitance ratio to C1 <C2, FIG. It can be operated in the same way. 16 and 17 can be realized by changing the capacitance ratio of the capacitors C3 and C4 instead of changing the capacitance ratio of the capacitors C1 and C2.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by generating the divided voltages VCGM and VCG1M using the capacitors C1 to C4, it is possible to eliminate a leakage current flowing in a circuit that generates the divided voltages VCGM and VCG1M.

  FIG. 22 shows an example of a voltage control circuit 20G in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20G is the same as that in FIG. 18 except that the test control circuit 10D is different. That is, the voltage control circuit 20G is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory. The voltage control circuit 20G is different from FIG. 21 in the capacitors for generating the divided voltages VCGM and VCG1M. The configuration other than the capacitor is the same as in FIG.

  The voltage control circuit 20G includes capacitors C1 and C2, which are connected in series between the control gate line VCG and the ground line VSS, capacitors C10 and C20, and a first high voltage line VCG1 and the ground line VSS, respectively. It has connected capacitors C3 and C4 and capacitors C30 and C40. Voltage dividing node VCG1M is connected to a connection node of capacitors C3 and C4 and a connection node of capacitors C30 and C40. For example, the capacitance values of the capacitors C1-C4 and C10-C40 are all equal. Therefore, the capacitance ratio C1: C2 of the capacitors C1 and C2 and the capacitance ratio C3: C4 of the capacitors C3 and C4 are both “1”. The capacitance ratio C10: C20 of the capacitors C10 and C20 and the capacitance ratio C30: C40 of the capacitors C30 and C40 are both “1”.

  The voltage dividing node VCGM is connected to a connection node of the capacitors C1 and C2. Capacitor C10 has one end connected to voltage dividing node VCGM and the other end connected to control gate line VCG or ground line VSS via nMOS transistors NM13 and NM14. Capacitor C20 has one end connected to voltage dividing node VCGM and the other end connected to control gate line VCG or ground line VSS via nMOS transistors NM15 and NM16. The capacitors C1-C4, C10-C40, the nMOS transistors NM13-NM16, and the level comparator CMP1 may be formed outside the voltage control circuit 20G.

  The nMOS transistor NM13 receives the test control signal TMa at the gate, and the nMOS transistor NM14 receives the inverted signal of the test control signal TMa at the gate. The nMOS transistor NM15 receives the test control signal TMb at the gate, and the nMOS transistor NM16 receives the inverted signal of the test control signal TMb at the gate. The test control signals TMa and TMb are generated according to the program state of the program circuit PGMC in the test control circuit 10D (FIG. 18), or are generated according to the address signal AD during the test mode.

  When the test control signal TMa is set to a high level and the test control signal TMb is set to a low level, the voltage dividing node VCGM is connected to the control gate line VCG via the capacitors C1 and C10. The voltage dividing node VCGM is connected to the ground line VSS via the capacitors C2 and C20. Since the capacitance ratio C1: C2 = C10: C20 = 1, the value of the divided voltage VCGM is half of the control gate voltage VCG. Since the capacitance ratio C3: C4 = C30: C40 = 1, the value of the divided voltage VCG1M is half of the first high voltage VCG1. Therefore, the operation of the voltage control circuit 20G is the same as that in FIG. Note that when the test control signal TMa is set to a low level and the test control signal TMb is set to a high level, the value of the divided voltage VCGM becomes half of the control gate voltage VCG. Therefore, the operation of the voltage control circuit 20G is the same as that in FIG.

  When the test control signals TMa and TMb are both set to a high level, the capacitors C1, C10 and C20 are connected to the control gate line VCG, and the capacitor C2 is connected to the ground line VSS. As a result, the divided voltage VCGM becomes relatively high, and the operation of the voltage control circuit 20G is the same as that in FIG. On the other hand, when the test control signals TMa and TMb are both set to a low level, the capacitor C1 is connected to the control gate line VCG, and the capacitors C2, C10 and C20 are connected to the ground line VSS. As a result, the divided voltage VCGM is relatively low, and the operation of the voltage control circuit 20G is the same as that in FIG.

  As described above, by switching the connection destinations of the capacitors C10 and C20 according to the test control signals TMa and TMb, as shown in FIG. 15, FIG. 16, and FIG. 17, the voltage using three types of divided voltages VCGM is used. The control circuit 20G can be operated. That is, the nMOS transistors NM13 to NM16 function as a divided voltage changing circuit that changes the value of the divided voltage VCGM. Thereby, the on-timing of the first switch SW1 can be set optimally in accordance with the electrical characteristics of the manufactured semiconductor integrated circuit SEM. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 23 shows an example of a voltage control circuit 20H in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20H is the same as that of FIG. 18 except that the test control circuit 10D is different. That is, the voltage control circuit 20H is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory. The voltage control circuit 20H is different from FIG. 22 in the capacitors for generating the divided voltages VCGM and VCG1M. The configuration other than the capacitor is the same as in FIG.

  The voltage control circuit 20G includes capacitors C1 and C2 and capacitors C10 and C20 connected in series between the control gate line VCG and the ground line VSS, and is connected in series between the first high voltage line VCG1 and the ground line VSS. Capacitors C3 and C4 and capacitors C30 and C40. Capacitor C30 has one end connected to voltage dividing node VCG1M and the other end connected to first high voltage line VCG1 or ground line VSS via nMOS transistors NM17 and NM18. Capacitor C40 has one end connected to voltage dividing node VCG1M and the other end connected to first high voltage line VCG1 or ground line VSS via nMOS transistors NM19 and NM20. The capacitors C1-C4, C10-C40, the nMOS transistors NM17-NM20, and the level comparator CMP1 may be formed outside the voltage control circuit 20H.

  Capacitance values of the capacitors C1-C4 and C10-C40 are the same as those in FIG. Therefore, the capacitance ratios C1: C2, C10: C20, C3: C4, and C30: C40 are all “1”. In this embodiment, as in FIG. 23, three types of divided voltages VCG1M can be generated by switching the connection destination of the capacitors C30 and C40 according to the test control signals TMa and TMb. That is, the nMOS transistor NM17-20 functions as a divided voltage changing circuit that changes the value of the divided voltage VCG1M. Thus, the operations shown in FIGS. 15, 16, and 17 can be realized using the voltage control circuit 20G. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 24 shows an example of the voltage control circuit 20I in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20I is the same as that of FIG. 18 except that the test control circuit 10D is different. That is, the voltage control circuit 20I is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  Voltage control circuit 20I includes capacitors C1, C10, C2, C20 and nMOS transistors NM13-NM16 shown in FIG. 22, and capacitors C3, C30, C4, C40 and nMOS transistors NM17-NM20 shown in FIG. ing. The capacitors C1-C4, C10-C40, the nMOS transistors NM13-NM20, and the level comparator CMP1 may be formed outside the voltage control circuit 20I.

  The gates of the nMOS transistors NM17 to NM18 are controlled by a test control signal TMc. The gates of the nMOS transistors NM19 to NM20 are controlled by a test control signal TMc. Test control signals TMa-TMd are generated according to the program state of program circuit PGMC in test control circuit 10D (FIG. 18), or are generated according to address signal AD during the test mode. Other configurations of the voltage control circuit 20I are the same as those in FIG.

  In this embodiment, the connection destinations of the capacitors C10 and C20 are switched according to the test control signals TMa and TMb, and the connection destinations of the capacitors C30 and C40 are switched according to the test control signals TMc and TMd. A voltage VCGM and three types of divided voltage VCG1M can be generated. That is, the nMOS transistors NM13 to NM20 function as a divided voltage changing circuit that changes the values of the divided voltages VCGM and VCG1M. As a result, the on-timing of the first switch SW1 can be set more optimally according to the electrical characteristics of the manufactured semiconductor integrated circuit SEM. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 25 shows an example of a voltage control circuit 20J in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20J is the same as that shown in FIGS. 2 and 6 except that the bleeder circuit BLD shown in FIG. 6 is not provided. That is, the voltage control circuit 20J is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  The voltage control circuit 20J has resistors R3 and R4 shown in FIG. 14 instead of the capacitors C3 and C4 shown in FIG. Other configurations of the voltage control circuit 20J are the same as those in FIG. The resistors R3-R4, the capacitors C1-C2, and the level comparator CMP1 may be formed outside the voltage control circuit 20J. The resistance values of the resistors R3 and R4 are high and substantially equal to the resistance value of the bleeder circuit BLD shown in FIG. That is, the resistors R3 and R4 not only generate the divided voltage VCG1M but also function as a bleeder circuit BLD. In this embodiment, a plurality of types of divided voltages VCGM and VCG1M can be generated according to the capacitance ratio of the capacitors C3 and C4 or the resistance ratio of the resistors R3 and R4. The operation shown in FIGS. 15 to 17 can be realized. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, the divided voltage VCGM is generated by the capacitors C1 and C2, and the functions of the bleeder circuit BLD are given to the resistors R3 and R4, so that the bleeder circuit BLD can be eliminated and the leakage current can be reduced.

  FIG. 26 shows an example of a voltage control circuit 20K in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration excluding the voltage control circuit 20K is the same as in FIG. That is, the voltage control circuit 20K is formed in a semiconductor integrated circuit SEM such as a NOR type flash memory.

  In the voltage control circuit 20K, a delay circuit DLY is arranged between the level comparator CMP1 and the flip-flop circuit FF1 shown in FIG. The other configuration of the voltage control circuit 20K is the same as that of the voltage control circuit 20B shown in FIG. Note that the level comparator CMP1 and the delay circuit DLY may be formed outside the voltage control circuit 20K.

  The delay circuit DLY delays the falling edge of the output signal DET of the level comparator CMP1 by the delay time D1 and outputs it as the output signal DETD. Thereby, the flip-flop circuit FF1 sets the switch control signal SW1ON to the high level after the delay time D1 after the level comparator CMP1 detects that the control gate voltage VCG is lower than the first high voltage VCG1.

  FIG. 27 shows an example of the operation of the voltage control circuit 20K shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 16 are omitted. The waveforms shown in FIG. 27 are the same as those in FIG. 16 except for the output signals DET and DETD. In this example, the output signal DETD is generated after the delay time D1 from the falling edge of the output signal DET, and the switch control signal SW1ON changes to the high level (FIG. 27A). That is, the activation timing of the switch control signal SW1ON is delayed by the delay circuit DLY. Accordingly, the output timing of the switch control signal SW1ON can be delayed without generating the divided voltage VCGM or VCG1M by the resistance ratio or the capacitance ratio.

  In order to lower the voltage to be compared by the level comparator CMP1 shown in FIG. 26, the divided voltages VCGM and VCG1M may be supplied to the level comparator CMP1 as shown in FIGS. Further, as shown in FIGS. 14 and 25, the bleeder circuit BLD shown in FIG. 6 can be eliminated by generating the divided voltage VCG1M using the resistors R3 and R4.

  Further, the discharge circuit 28 shown in FIG. 2 is connected to the control gate line VCG on the end side (far end side; lower side in FIG. 2) of the memory core 30 that is away from the voltage control circuit 20 and the voltage switching circuit 26. May be. Thereby, in the control gate line VCG, the discharge speed is high on the far end side, and the discharge speed is low on the near end side close to the voltage control circuit 20 (level comparator CMP1) and the voltage switching circuit 26 (first switch SW1). Become. At this time, the level comparator CMP1 operates in response to the control gate voltage VCG having a low discharge rate, so that the operation shown in FIG. 27 can be realized without arranging the delay circuit DLY.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, the output timing of the switch control signal SW1ON can be delayed without generating the divided voltage VCGM or VCG1M by the resistance ratio or the capacitance ratio. As a result, the control gate voltage VCG can be set to a normal value (for example, 5V).

  FIG. 28 shows an example of a system SYS on which the semiconductor integrated circuit SEM of the above-described embodiment is mounted. The system SYS (user system) constitutes at least a part of a microcomputer system such as a portable device. The system SYS has a system-on-chip SoC in which a plurality of macros are integrated on a silicon substrate. Alternatively, the system SYS has a multi-chip package MCP in which a plurality of chips are stacked on a package substrate. Alternatively, the system SYS has a system-in-package SiP in which a plurality of chips are mounted on a package substrate such as a lead frame. Furthermore, the system SYS may be configured in the form of chip-on-chip CoC or package-on-package PoP.

  For example, the SoC includes a CPU (controller), a ROM, a peripheral circuit I / O, and the semiconductor integrated circuit SEM (flash memory) described above. The CPU, ROM, peripheral circuit I / O, and semiconductor integrated circuit SEM are connected to each other by a system bus SBUS. A memory controller may be arranged between the CPU and the semiconductor integrated circuit SEM.

  The CPU accesses the ROM, the peripheral circuit I / O, and the semiconductor integrated circuit SEM and controls the operation of the entire system. The semiconductor integrated circuit SEM performs a write operation, a read operation, and an erase operation in response to an access request from the CPU. The minimum configuration of the system SYS is a CPU and a semiconductor integrated circuit SEM.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first switch that is turned on in response to activation of the first switch control signal to connect the first high voltage line to which the first high voltage is supplied to the internal voltage line;
A first voltage generation circuit that operates in response to activation of a first voltage generation signal to generate the first high voltage;
The first voltage generation signal operates in response to the activation, compares the first high voltage with the voltage of the internal voltage line, and the difference between the first high voltage and the voltage of the internal voltage line is a predetermined value. And a level comparator that activates the first switch control signal when the circuit becomes a semiconductor integrated circuit.
(Appendix 2)
A second switch that is turned on in response to activation of a second switch control signal to connect a second high voltage line supplied with a second high voltage higher than the first high voltage to the internal voltage line;
A discharge switch disposed between the internal voltage line and the ground line and turned on in response to activation of a third switch control signal;
In the switching period in which the voltage of the internal voltage line is switched from the second high voltage to the first high voltage, the second switch control signal is deactivated and the first voltage generation signal and the third switch control signal are The semiconductor integrated circuit according to claim 1, further comprising: a voltage control circuit that is activated and deactivates the third switch control signal in response to the activation of the first switch control signal.
(Appendix 3)
A first voltage dividing circuit for dividing the first high voltage to generate a first divided voltage;
A second voltage dividing circuit for dividing a voltage of the internal voltage line to generate a second divided voltage;
The level comparator receives the first divided voltage as the first high voltage, receives the second divided voltage as a voltage of the internal voltage line, and receives the first divided voltage and the second divided voltage. The semiconductor integrated circuit according to appendix 1 or appendix 2, wherein the first switch control signal is activated when a difference between the first and second switches becomes a predetermined value.
(Appendix 4)
The semiconductor integrated circuit according to appendix 3, wherein a ratio of the second divided voltage to the voltage of the internal voltage line is set higher than a ratio of the first divided voltage to the first high voltage.
(Appendix 5)
The semiconductor according to appendix 3 or appendix 4, wherein the discharge switch and the level comparator are connected to a side closer to the first switch in the internal power supply line extending from the first switch. Integrated circuit.
(Appendix 6)
The first voltage generation circuit includes a regulator having an nMOS transistor having a drain connected to a power supply line, a constant voltage received at a gate, and a source connected to the first high voltage line,
The first voltage dividing circuit includes a plurality of resistors connected in series between the first high voltage line and a ground line. Semiconductor integrated circuit.
(Appendix 7)
A divided voltage changing circuit that is provided in any of the first and second voltage dividing circuits and changes any one of the first and second divided voltages in accordance with a test control signal;
A program circuit for fixing the test control signal to a predetermined level according to a program state;
A test control circuit that operates during a test mode and generates the test control signal in accordance with a signal supplied from the outside of the semiconductor integrated circuit regardless of a program state of the program circuit. The semiconductor integrated circuit according to any one of appendix 3 to appendix 6.
(Appendix 8)
A delay circuit is provided between the level comparator and the first switch, and delays the activation timing of the first switch control signal supplied from the level comparator to the first switch. The semiconductor integrated circuit according to any one of appendix 1 to appendix 6.
(Appendix 9)
A non-volatile memory cell including a memory transistor having a control gate and a floating gate;
An operation control circuit for controlling a write operation for repeatedly performing a program operation and a verify operation when data is written to the memory cell;
The voltage of the internal voltage line is supplied to the control gate, set to the second high voltage during a program operation, and set to the first high voltage during the verify operation,
9. The semiconductor integrated circuit according to any one of appendices 2 to 8, wherein the level comparator operates when the program operation is switched to the verify operation.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10D ... Test control circuit; 12 ... Command decoder; 14 ... Operation control circuit; 16 ... Address decoder; 18 ... Data input / output circuit; 20, 20A-20K ... Voltage control circuit; Generation circuit; 24, second voltage generation circuit, 26, 26A, voltage switching circuit, 28, discharge circuit, 30, memory core, ADEC, address decode signal, AMP1, amplifier, ARY, memory cell array, BL, bit line, BLD ... bleeder circuit; BUF1, BUF2 ... buffer circuit; CMP1, CMP2 ... level comparator; CVGEN ... constant voltage generation circuit; DCEN ... discharge enable signal; DLY ... delay circuit; DTR ... voltage divider transistor; Flip-flop circuit; LMODE Low-voltage mode signal; MC Memory MT, memory transistor, OMODE, other mode signal, PG, program control signal, RD, read control signal, RGL, regulator, SEC, sector, SEM, semiconductor integrated circuit, SL, source line, SSW, sector switch, SVCG Sector control gate line; SW1 First switch; SW2 Second switch; SW1ON First switch control signal; SYS System TM0-2, TMa, TMb, TMc, TMd Test control signal; V1GEN First voltage VCG: Internal voltage line, control gate line; VCG1: First high voltage line; VCG1GEN: First voltage generation signal; VCG2: Second high voltage line; VCG2GEN: Second voltage generation signal; VCGM, VCG1M Voltage: WDEC: Word decoder; WL: Word line; W DRV ‥ word line driver

Claims (6)

A first switch that is turned on in response to activation of the first switch control signal to connect the first high voltage line to which the first high voltage is supplied to the internal voltage line;
A first voltage generation circuit that operates in response to activation of a first voltage generation signal to generate the first high voltage;
The first voltage generation signal operates in response to the activation, compares the first high voltage with the voltage of the internal voltage line, and the difference between the first high voltage and the voltage of the internal voltage line is a predetermined value. And a level comparator that activates the first switch control signal when the circuit becomes a semiconductor integrated circuit. A second switch that is turned on in response to activation of a second switch control signal to connect a second high voltage line supplied with a second high voltage higher than the first high voltage to the internal voltage line;
A discharge switch disposed between the internal voltage line and the ground line and turned on in response to activation of a third switch control signal;
In the switching period in which the voltage of the internal voltage line is switched from the second high voltage to the first high voltage, the second switch control signal is deactivated and the first voltage generation signal and the third switch control signal are 2. The semiconductor integrated circuit according to claim 1, further comprising: a voltage control circuit that is activated and deactivates the third switch control signal in response to activation of the first switch control signal. A first voltage dividing circuit for dividing the first high voltage to generate a first divided voltage;
A second voltage dividing circuit for dividing a voltage of the internal voltage line to generate a second divided voltage;
The level comparator receives the first divided voltage as the first high voltage, receives the second divided voltage as a voltage of the internal voltage line, and receives the first divided voltage and the second divided voltage. The semiconductor integrated circuit according to claim 1, wherein the first switch control signal is activated when a difference between the first switch control signal and the second switch becomes a predetermined value. 4. The semiconductor integrated circuit according to claim 3, wherein a ratio of the second divided voltage to the voltage of the internal voltage line is set higher than a ratio of the first divided voltage to the first high voltage. . The said discharge switch and the said level comparator are connected to the side close | similar to the said 1st switch in the said internal power supply line extended from the said 1st switch. Semiconductor integrated circuit.   A delay circuit is provided between the level comparator and the first switch, and delays the activation timing of the first switch control signal supplied from the level comparator to the first switch. 6. The semiconductor integrated circuit according to claim 1, wherein:

Images