JP2011215853A - Semiconductor device and control method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the configuration is simplified and the yield is improved.SOLUTION: Fuses 122, 132 store information whether a CPU 120 and a CPU 130 are normal respectively. When the fuse 122 stores information concerned with failure, the CPU 120 is not started. When the fuse 122 stores information concerned with normality, the CPU 120 is started, and after starting the CPU 120, the CPU 130 is controlled not to be started. When the fuse 132 stores information concerned with failure, the CPU 130 is not started. When the fuse 132 stores information concerned with normality, the CPU 130 is started, and after starting the CPU 130, the fuse 122 is referred to, and when the fuse 122 stores information concerned with normality, the CPU 130 is controlled not to be started. When the fuse 122 stores information concerned with failure, processing of the CPU 130 is continued and the CPU 120 is controlled not to be started.

Description

  The present invention relates to a semiconductor device and a control method thereof, and more particularly to a semiconductor device equipped with a multiprocessor core type CPU (Central Processing Unit) and a control method thereof.

  Currently, multiprocessor core type semiconductor devices having a plurality of processor cores are widely used. In the semiconductor device, since a plurality of processor cores are mounted, the die size increases. Due to the increase in die size, there is a problem of a decrease in yield at the time of manufacturing a semiconductor device.

  However, even a multiprocessor core type semiconductor device may not use all of the installed processor cores depending on the intended use. When it is sufficient to use only some of the processor cores in this way, even if some processor cores have a failure in the manufacturing process, by having a mechanism that controls to use only the processor cores that have not failed It can be shipped as a good semiconductor device.

  Patent Document 1 discloses a technique that can improve the yield by relieving a partial core non-defective chip during semiconductor manufacturing. FIG. 7 is a block diagram showing the configuration of the multi-core processor described in Patent Document 1.

  In the multi-core processor described in Patent Document 1, the pass / fail state of each core processor is reflected in the fuse in a wafer test during semiconductor manufacturing. When a certain core processor is in a defective state, a fuse corresponding to the core processor is cut. On the other hand, when a certain core processor is not in a defective state, the fuse corresponding to the core processor is not cut.

  When the fuse is blown, the logic gate 91n (n is an integer of 1 or more) is cut off. As a result, load data or the like input via a JTAG (Joint Test Action Group) interface is not written to the setting register (911 or 912). Only the core processor that can operate normally operates by not loading the load data or the like.

JP 2006-003949 A

  However, the multi-core processor described in Patent Document 1 has the following problems. In the multi-core processor described in Patent Document 1, a control signal input via the JTAG interface becomes a common control signal for all core blocks (Core-n Block). Therefore, in order to perform individual control for each core block, a dedicated circuit corresponding to the circuit to be controlled is required. This complicates the circuit control method.

  In the technique described in Patent Document 1, dedicated internal logic (900 in the figure) for controlling each core block is required. Since it is necessary to create the internal logic, the design of the semiconductor device becomes complicated. Furthermore, when designing a semiconductor device using a different type of core block from existing core blocks, a new control circuit (a portion corresponding to 900 in FIG. 7) needs to be newly designed and developed.

  One aspect of the semiconductor device according to the present invention includes a first processor having a first priority, and a first storage unit that stores first failure information indicating whether or not the first processor is normal. When the first failure information is a value indicating that the first failure information is normal when the power is turned on, the first processor is activated, and when the first failure information is a value indicating that the failure information is not normal. A first control unit that does not activate the first processor; a second processor having a second priority lower than the first priority; and a second that indicates whether the second processor is normal A second storage unit that stores the failure information of the second, and when the second failure information is a value indicating normality when the power is turned on, the second processor is started, and the second failure information Is a value indicating that it is not normal, A second control unit that does not start the processor of the first processor, and the first processor continues the processing in the first processor after stopping the operation of the second processor at the time of startup, and the second processor The two processors refer to the first failure information at the time of start-up, and when the first failure information is a value indicating that it is not normal, the second processor continues the processing. To do.

  In the present invention, the first storage unit and the second storage unit store failure information indicating whether or not the processor is normal, and control the startup process of the processor and the control of the continuation of the process using the information. Do. By using the information stored in the storage unit, it is controlled so that only a normal processor operates, so that the yield of the semiconductor device can be improved. In addition, the semiconductor device according to the present invention can be controlled so that a normal processor operates only by including the above-described storage unit. Therefore, the circuit configuration can be simplified.

  According to the present invention, it is possible to provide a semiconductor device in which the circuit configuration is simplified and the yield can be improved.

1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment; FIG. 6 is a diagram showing a semiconductor device sorting process according to the first embodiment; 3 is a flowchart showing the operation of the semiconductor device when both of the CPUs 1 and 2 according to the first embodiment have not failed. 3 is a flowchart showing the operation of the semiconductor device when only the CPU 2 according to the first embodiment is faulty. 3 is a flowchart showing the operation of the semiconductor device when only the CPU 1 according to the first embodiment is faulty. FIG. 3 is a diagram illustrating a configuration of a semiconductor device according to a second embodiment. 1 is a diagram of a multi-core processor described in Patent Document 1. FIG.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. In the following example, a multiprocessor core type semiconductor device having two CPUs will be described. FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to the present embodiment. FIG. 1 shows a hardware configuration of a semiconductor device and software processing.

  The semiconductor device 100 includes a reset control circuit 110, a CPU 1 (120), a CPU ID register 121, a fuse 1 (122), a logic gate 123, a CPU 2 (130), a CPU ID register 131, and a fuse 2 (132). A logic gate 133.

  The Reset control circuit 110 is a control circuit for supplying a Reset signal to the CPU 1 (120) and the CPU 2 (130). CPU1 (120) and CPU2 (130) are processor cores.

  The CPU ID register 121 is a register for storing the processor ID (identifier for identifying the processor) of the CPU 1 (120). In this example, the CPU ID register 121 stores “1”, which is the identifier of the CPU 1 (120). Similarly, the CPU ID register 131 is a register for storing the processor ID of the CPU 2 (130). In this example, the CPU ID register 131 stores “2”, which is the identifier of the CPU 2 (130). The values of the CPUID register 121 and the CPUID register 131 are values that are set when the semiconductor device 100 is manufactured and are not rewritten.

  The Fuse 1 (122) operates as a storage unit that stores failure information indicating whether the CPU 1 (120) is normal. The information of Fuse 1 (122) is set when the semiconductor device 100 is manufactured. Similarly, Fuse2 (132) operates as a storage unit that stores failure information indicating whether the CPU2 (130) is normal. The information of Fuse 2 (132) is set when the semiconductor device 100 is manufactured. Fuse 1 (122) and Fuse 2 (132) are disconnected when the corresponding CPU is not normal.

  The logic gate 123 is a logic gate that supplies a Reset signal to the CPU 1 (120). The logic gate 123 continues to output the Reset signal to the CPU 1 (120) when the Fuse 1 (122) is disconnected, that is, when the CPU 1 (120) is not normal. The CPU 1 (120) to which the Reset signal is input does not start.

  The logic gate 133 is a logic gate that supplies a Reset signal to the CPU 2 (130). The logic gate 133 continues to output the Reset signal to the CPU 2 (130) when the Fuse 2 (132) is disconnected, that is, when the CPU 2 (130) is not normal. The CPU 2 (130) to which the Reset signal is input does not start.

  Next, software control executed when each CPU is activated will be described with reference to FIG. Each CPU is activated when the corresponding Fuse is not disconnected (S1). When the corresponding Fuse is disconnected, a Reset signal is supplied to each CPU, so that the CPU cannot be activated. Each CPU executes the instruction written in the reset vector when the activation is successful.

  After activation (S1), each CPU reads the CPUID from the corresponding CPUID register (S2). Each CPU determines whether it is CPU1 (120) from the read CPUID (S3).

  When the activated CPU is the CPU 1 (120) (S3: Yes), the CPU sets the CPU 2 (130) to a WFI (Wait For Interrupt) state (S4). Thereafter, the CPU which is the CPU 1 shifts to normal processing.

  On the other hand, when the activated CPU is not CPU1 (120) (S3: No), the CPU reads Fuse1 (122) (S6). The activated CPU determines whether or not the CPU 1 (120) is out of order (Fail state) from the state of the read Fuse 1 (122) (S7).

  When the CPU 1 (120) is out of order (S7: Yes), the activated CPU sets the CPU 1 (120) to the WFI state (S8) and shifts to normal processing. On the other hand, when the CPU 1 (120) has not failed (S7: No), the CPU sets itself to the WFI state (S10).

  Next, the semiconductor device sorting process according to the present embodiment will be described with reference to FIG. In this example, the failure information at the time of manufacture is reflected in the Fuse corresponding to each CPU of the semiconductor device to be selected. That is, the Fuse corresponding to the CPU that has failed during manufacture is disconnected. Whether or not each CPU has failed is determined, for example, from the result of a wafer test.

  At the time of sorting, the states of Fuse 1 and Fuse 2 of the semiconductor device to be sorted are examined. When both Fuse 1 and Fuse 2 are not in the Fail state (disconnected state), the semiconductor device can be shipped as a multi-core compatible product or a single-core compatible product.

  When either Fuse 1 or Fuse 2 is in a Fail state (a disconnected state), the semiconductor device can be shipped as a single core compatible product. In this case, the CPU associated with the Fuse that is not in the Fail state operates.

  When Fuse 1 and Fuse 2 are in the Fail state (disconnected state), the semiconductor device cannot operate as a single-core compatible product or a multi-core compatible product. Therefore, the semiconductor device cannot be shipped.

  Next, in the semiconductor device according to the present embodiment, a processing flow when both the CPUs 1 and 2 have not failed, that is, when Fuse 1 and Fuse 2 are not disconnected will be described with reference to FIG.

  The CPU 1 is activated because Fuse 1 is not disconnected (S1). The activated CPU 1 sets the processing content stored in the reset vector in the program counter and executes it. Subsequently, the CPU 1 reads the CPU ID (S2). Here, since the CPU ID read by the CPU 1 is related to “CPU 1” (S3: Yes), the CPU 1 sets the CPU 2 to the WFI state (S4). Then, the CPU 1 shifts to normal processing (S5).

  The CPU 2 is activated because the Fuse 2 is not disconnected (S1). The activated CPU 2 sets the contents of the processing stored in the reset vector in the program counter and executes them. Subsequently, the CPU 1 reads the CPU ID (S2). Here, since the CPU ID read by the CPU 1 is not related to “CPU 1” (S3: No), the Fuse corresponding to the CPU 1 is read (S6). Since the Fuse is not disconnected, the CPU 2 determines that the CPU 1 is normal (S7: No), and the CPU 2 sets itself to the WFI state (S10).

  Next, in the semiconductor device according to the present embodiment, a processing flow when only the CPU 2 has failed, that is, only the Fuse 2 has been disconnected will be described with reference to FIG.

  Since Fuse 1 is not disconnected, CPU 1 starts up (S 1) and reads the CPU ID (S 2). Here, since the CPU ID read by the CPU 1 is related to “CPU 1” (S3: Yes), the CPU 1 sets the CPU 2 to the WFI state (S4). Then, the CPU 1 shifts to normal processing (S5).

  Next, the operation of the CPU 2 will be described. Since Fuse 2 is disconnected, CPU 2 is always controlled to be in the Reset state, that is, not activated. Since the CPU 2 is not activated, processing such as reading of the CPU ID is not executed. Thus, when only the CPU 2 has failed at the time of manufacture, only the CPU 1 is controlled to operate normally.

  Next, in the semiconductor device according to the present embodiment, a processing flow when only the CPU 1 has failed, that is, only the Fuse 1 has been disconnected will be described with reference to FIG.

  First, the operation of the CPU 1 will be described. Since Fuse 1 is disconnected, CPU 1 is always controlled to be in the Reset state, that is, not activated. For this reason, processing such as reading of the CPUID is not executed.

  Next, the operation | movement concerning CPU2 is demonstrated. The CPU 2 is activated because the Fuse 2 is not disconnected (S1). The activated CPU 2 reads its own CPU ID (S2). Here, since the CPU ID read by the CPU 2 is related to “CPU 2” (S3: No), the state of Fuse 1 corresponding to the CPU 1 is read (S6). Since CPU 1 has failed as described above, Fuse 1 is disconnected. Therefore, the CPU 2 determines that the CPU 1 is not normal (S7: Yes). Since the CPU 1 is not normal, the CPU 2 sets the CPU 1 to the WFI state (S8). Thereafter, the CPU 2 shifts to normal processing (S9).

  As described above, when only the CPU 1 is not normal, the CPU 2 that does not normally operate operates. Thereby, even if only the CPU 1 is in a failure state, it can operate normally as a single core processor.

  Next, effects of the semiconductor device according to the present embodiment will be described. As described above, the semiconductor device according to the present embodiment includes only a storage unit such as a fuse for each CPU, and activates each CPU using the failure information stored in the storage unit. Each CPU after activation is controlled according to the failure information of the other CPUs.

  The control of the CPU described above is realized by using software. Therefore, it is not necessary to perform complicated control by hardware. In addition, since a hardware configuration for performing control is not necessary, the circuit configuration is simplified. By simplifying the circuit configuration, the circuit scale can be reduced.

  Furthermore, software for performing the above-described control is applied even when different IP cores (partial circuit information for configuring the semiconductor device), that is, different types of CPUs are used due to a design change of the semiconductor device. It is possible. Thereby, it becomes possible to reduce the development man-hour of the above-mentioned control processing.

Embodiment 2
The semiconductor device according to the second embodiment of the present invention is characterized in that power is not supplied to an abnormal CPU. The configuration of the semiconductor device according to the present embodiment will be described with reference to FIG. In FIG. 6, processing units having the same name and the same reference numerals perform basically the same processing as in the first embodiment.

  FIG. 6 is a diagram showing a configuration of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment includes a power supply control circuit 140 instead of the Reset control circuit 110. The power supply control circuit 140 is a control circuit that operates to supply power to each CPU. In addition, power switches (151 and 152) corresponding to each CPU are provided.

  The power switch 151 is a power switch that controls supply of power to the CPU 1 (120). The power switch 152 is a power switch that controls supply of power to the CPU 2 (130). The power switches 151 and 152 are turned off when the corresponding fuse is disconnected. That is, a control signal for controlling the power supply to the abnormal CPU is input to each power switch. On the other hand, when the corresponding Fuse is not disconnected, the power switch is turned on. That is, a control signal for controlling power supply to a normal CPU is input to each power switch.

  Next, effects of the semiconductor device according to this embodiment will be described. As described above, the semiconductor device according to this embodiment performs control so that power is not supplied to an abnormal CPU. As a result, only necessary power is supplied, and power consumption can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the number of CPUs provided in the semiconductor device is not limited to two, and an arbitrary number of CPUs can be provided. An outline of a control example of a semiconductor device including three or more CPUs will be described below.

  When the CPU 1 is normal, the CPU 1 is activated and all other CPUs are set to the WFI state. On the other hand, if the CPU 1 is not normal, for example, if the CPU 2 with higher priority following the CPU 1 is normal, the CPU 1 is activated and all other CPUs are set to the WFI state. If CPU1 and CPU2 are not normal, the CPU with the next highest priority is activated. That is, the CPUs are activated in the order of higher priority, and CPUs with lower priority than the activated CPU are set in the WFI state. When a processor with a lower priority is activated, if there is a processor with a higher priority than itself, it sets itself to the WFI state. Desired control becomes possible by the above processing. Note that the priority order is determined in advance.

100 Semiconductor Device 110 Reset Control Circuit 120, 130 CPU
121, 131 CPUID register 122, 132 Fuse
123, 133 Logic gate 140 Power control circuit 151, 152 Power switch

Claims (11)

A first processor having a first priority;
A first storage unit that stores first failure information indicating whether or not the first processor is normal;
When the first failure information is a value indicating that the first failure information is normal when the power is turned on, the first processor is activated, and when the first failure information is a value indicating that the first failure information is not normal, A first control unit that does not activate the first processor;
A second processor having a second priority lower than the first priority;
A second storage unit for storing second failure information indicating whether or not the second processor is normal;
When the second failure information is a value indicating that the second failure information is normal when the power is turned on, the second processor is started. When the second failure information is a value indicating that the second failure information is not normal, A second control unit that does not activate the second processor;
Have
The first processor continues processing in the first processor after stopping the operation of the second processor at the time of startup, and the second processor refers to the first failure information at the time of startup, If the first failure information is a value indicating that it is not normal, the second processor continues the processing.   The semiconductor device according to claim 1, wherein the first processor sets the second processor to a WFI (Wait For Interrupt) state when stopping the operation of the second processor.   The first control unit fixes the reset signal of the first processor in an activated state when the first failure information is a value indicating that the first failure information is not normal when power is turned on. The semiconductor device according to claim 1, wherein: A first power switch for controlling supply of power to the first processor;
The power supply to the first processor is stopped when the first control unit is a value indicating that the first failure information is not normal when the power is turned on. 3. The semiconductor device according to claim 1 or 2.   5. The semiconductor device according to claim 1, wherein the first storage unit and the second storage unit are configured by fuses. 6. A first processor having a first priority; a first storage for storing first failure information indicating whether or not the first processor is normal; and a second lower than the first priority A control method of a semiconductor device comprising: a second processor having a priority of: a second storage unit that stores second failure information indicating whether or not the second processor is normal;
When the first failure information is a value indicating that the first failure information is normal when the power is turned on, the first processor is activated, and when the first failure information is a value indicating that the first failure information is not normal, Control the first processor not to start,
When the second failure information is a value indicating that the second failure information is normal when the power is turned on, the second processor is started. When the second failure information is a value indicating that the second failure information is not normal, Control not to start the second processor,
The first processor continues processing after stopping the operation of the second processor when starting the first processor, refers to the first failure information when starting the second processor, and When the failure information of 1 is a value indicating that the failure information is not normal, the process is continued by the second processor.   7. The semiconductor device according to claim 6, wherein when the operation of the second processor is stopped when the first processor is started, the second processor is set to a WFI (Wait For Interrupt) state. Control method.   7. The reset signal of the first processor is fixed to an activated state when the first failure information is a value indicating that the first failure information is not normal when power is turned on. A method for controlling a semiconductor device according to claim 7.   8. The power supply to the first processor is stopped when the first failure information is a value indicating that the first failure information is not normal when the power is turned on. Method for controlling a semiconductor device.   The semiconductor device according to claim 6, wherein the first storage unit and the second storage unit are configured by fuses. A plurality of processors having priorities for activation;
A method for controlling a semiconductor device, comprising: a plurality of storage units that are associated with each of the plurality of processors and store failure information indicating whether or not the associated processors are normal;
A processor corresponding to the storage unit holding a value indicating that the failure information is normal when power is turned on, and a processor corresponding to the storage unit holding a value indicating that the failure information is not normal Control not to start,
One of the plurality of processors continues processing in the processor when the priority is highest at the time of startup, and in the processor when the priority of another processor is higher than the priority of the processor A method for controlling a semiconductor device, characterized in that the processing is not continued.

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