JP2011211563A - Receiving circuit, receiving method and communication system with receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that noise resistance is low in a conventional receiving circuit.SOLUTION: The present invention relates to a receiving circuit Rx, which operates in a power supply system different from a transmitting circuit Tx, having: a state holding circuit 10 for switching a logical level of reception data Drx1 in accordance with a change in signal level of a reception signal A generated on the basis of a transmission signal that the transmitting circuit Tx outputs via an insulating element ISO; and a state holding control circuit 20 for generating a hold signal D instructing the state holding circuit 10 to hold the logical level of the reception data Drx1 during a period from first timing, in which the logical level of the reception data Drx1 is switched, till the lapse of a preset first period of time.

Description

  The present invention relates to a receiving circuit, a receiving method, and a communication system including a receiving circuit, and in particular, a receiving circuit that receives a transmission signal output from a transmitting circuit via an insulating element and generates received data, a receiving method, and a communication including the receiving circuit. About the system.

  As means for transmitting a signal between two semiconductor chips having different reference potentials of a power source, there are a photocoupler, an inductor coupled isolator, a capacitive coupled isolator, a GMR element (Giant Magneto Resistive) isolator, and the like. It is used. The photocoupler converts an electrical signal into an optical signal, and converts the optical signal into an electrical signal with another chip, thereby insulating between the two semiconductor devices. An inductor-coupled isolator performs insulation between two semiconductor devices by converting an electric signal into magnetism using a coil and converting magnetism into an electric signal using another coil. A capacitively coupled isolator converts an electrical signal into an electric field using one electrode of a capacitive element, and insulates between two semiconductor devices by converting the electric field into an electric signal using another electrode. A GMR element type isolator performs insulation between two semiconductor devices by converting an electric signal into magnetism using a coil and converting a magnetism into an electric signal using a GMR element.

  Here, an outline of a communication system using these insulating elements will be described. Here, an example in which an inductor-coupled isolator is used as an insulating element will be described as a representative example. FIG. 31 shows a configuration example of a semiconductor device using an inductor-coupled isolator. In the example shown in FIG. 31, semiconductor chips CHP21 and CHP2 are mounted on a semiconductor package 71 having a plurality of external terminals 72. The semiconductor chips CHP1 and CHP2 are insulated by two coils (hereinafter referred to as on-chip transformers) having magnetic coupling formed on the semiconductor chip CHP2. Further, a transmission circuit Tx that drives the coil L1 is formed in the semiconductor chip CHP1, and a reception circuit Rx that receives a reception signal generated by the coil L2 is formed in the semiconductor chip CHP2. In the example shown in FIG. 31, an electric signal is converted into a magnetic signal using one coil L1 of the on-chip transformer, and the magnetic signal is converted into an electric signal using the other coil L2 of the on-chip transformer. Thus, signal transmission between the electrically insulated semiconductor chips CHP1 and CHP2 is enabled. Examples in which communication is performed between semiconductor chips thus insulated using an insulating element are disclosed in Patent Documents 1 and 2. Patent Document 3 discloses a technique for improving communication reliability against a failure that occurs in a signal transmission path.

Japanese Patent Laid-Open No. 2002-270756 JP-A-2005-244305 JP 7-212414 A

  However, in a communication system using a conventional insulating element, noise may occur in a received signal due to power supply noise on the receiving circuit side or parasitic capacitance formed between semiconductor chips. And there exists a problem which a receiver circuit malfunctions with the said noise. Therefore, a problem caused by this noise will be specifically described.

  A communication system having a plurality of semiconductor chips that are insulated by an insulating element and operate with different power supply systems, for example, operates with a low power supply voltage and generates a control signal (small amplitude) generated by a highly miniaturized arithmetic circuit or the like. Signal) is used to control a load driving circuit that generates a driving signal having a large amplitude based on a higher power supply voltage. Therefore, a problem due to noise will be described as an example in which the communication system is applied to control of a half-bridge driver.

  FIG. 32 shows a block diagram of a communication system for controlling the half-bridge driver. As shown in FIG. 32, in the communication system, transmission circuits Txa and Txb are formed in the first semiconductor chip CHP1, and an inductor-coupled insulating portion, a reception circuit Rxa, and a gate driver GDrva are formed in the second semiconductor chip CHP2. Thus, the inductor-coupled insulating part, the receiving circuit Rxb, and the gate driver GDrvb are formed in the third semiconductor chip CHP3. The first semiconductor chip CHP1 is supplied with the power supply voltage VDD0 and the ground voltage GND0, the second semiconductor chip CHP2 is supplied with the power supply voltage VDD1 and the ground voltage GND1, and the third semiconductor chip CHP3 is supplied with the power supply voltage. VDD2 and ground voltage GND2 are applied. The power transistors PTr1 and PTr2 constitute a half bridge driver that operates based on the power supply voltage HVDD and the ground voltage GND2. The power supply voltage HVDD is higher than the power supply voltages VDD1 and VDD2.

  Then, the transmission data Dtxa and Dtxb are propagated to the gate drivers GDrva and GDrvb via the transmission circuits Txa and Txb, an insulating part formed by inductor coupling, and the reception circuits Rxa and Rxb. The gate drivers GDrva and GDrvb generate gate control signals G1 and G2 for the power transistors PTr1 and PTr2, and drive the power transistors PTr1 and PTr2.

  Next, FIG. 33 shows an example of a timing chart during ideal operation of the communication system shown in FIG. As shown in FIG. 33, the half-bridge driver is turned on or off based on the gate control signals G1 and G2, and generates a load drive signal Vcm for driving the load. The load drive signal Vcm has a voltage amplitude larger than the signal output from the first to third semiconductor chips (for example, about 100 V to 5 kV).

  However, in the communication system shown in FIG. 32, parasitic capacitance is formed. FIG. 34 shows a block diagram in which parasitic capacitance is loaded on the communication system shown in FIG. As shown in FIG. 34, the low voltage region (first semiconductor chip CHP1) and the high voltage region (second semiconductor chip CHP2, third semiconductor chip CHP3) are coupled through a parasitic capacitance or the like. Then, due to the parasitic capacitance and the like, the reception data Drxa and Drxb generated based on the reception signal are affected by noise. A timing chart showing the operation of the communication system including the influence of the noise is shown in FIG.

  As shown in FIG. 35, in the communication system shown in FIG. 34, when the load drive signal Vcm fluctuates greatly, noise is mixed into the power supply voltage (VDD1-GND1 in FIG. 35) via the parasitic capacitance. Due to the power supply noise, the logic level of the received data Drxa (or Drxb) is indefinite. If a malfunction occurs in the receiving circuits Rxa and Rxb, the gate control signals G1 and G2 may not be able to maintain correct values.

  In addition, in the case of a semiconductor device (hereinafter referred to as an isolator) using an insulating element such as an inductor coupling, a capacitive coupling, an optical element, or a GMR element, an element (coil, electrode, LED, etc.) and reception on the transmitting circuit side of the insulating element. Parasitic capacitance exists between elements on the circuit side (coil, electrode, GMR element, photodiode, etc.). When the load drive signal Vcm largely fluctuates, noise mixed in the element on the receiving circuit side via the parasitic capacitance between the elements may be confused with the signal from the transmitting side circuit, resulting in malfunction. When such a malfunction occurs, not only the device does not operate correctly, but also the power transistors PTr1 and PTr2 are turned on at the same time, and the power supply in the high voltage region is short-circuited to the ground voltage, resulting in the destruction of the device. is there.

  In view of such a problem, an object of the present invention is to prevent malfunction caused by noise in a receiving circuit that receives a signal through an insulating element and generates reception data.

  One aspect of the receiving circuit according to the present invention is a receiving circuit that operates in a power supply system different from the transmitting circuit, and the signal level of the received signal that is generated based on the transmitting signal that the transmitting circuit outputs via an insulating element. A state holding circuit for switching the logical level of the received data in accordance with the change of the state, and the state holding circuit in a period from a first timing at which the logical level of the received data is switched until a preset first period elapses And a state holding control circuit for generating a hold signal instructing to hold the logic level of the received data.

  One aspect of a reception method of a reception circuit according to the present invention is a change in the signal level of a reception signal that is operated based on a transmission signal that operates through a power supply system different from the transmission circuit and that the transmission circuit outputs via an insulating element. A reception circuit that switches a logic level of received data in accordance with the first period that is set in advance after a change in the logic level of the received data is detected by detecting a change in the logic level of the received data The logic level of the received data is fixed in a period until the elapses, and after the elapse of the first period, the logic level of the received data is switched according to a change in the received signal.

  One aspect of a communication system according to the present invention operates in a transmission circuit that outputs a transmission signal to an insulating element based on transmission data, and in a power supply system different from the transmission circuit, and the transmission circuit outputs via the insulating element A reception circuit that switches a logic level of received data in accordance with a change in signal level of a reception signal generated based on a transmission signal, wherein the reception circuit receives the signal in response to a change in signal level of the reception signal. A state holding circuit for switching the logic level of data, and instructing the state holding circuit to hold the logic level of the received data in a first period preset from a first timing at which the logic level of the received data is switched. A state holding control circuit for generating a hold signal.

  According to the receiving circuit, the receiving method, and the communication system including the receiving circuit according to the present invention, it is possible to prevent the receiving circuit from malfunctioning due to noise.

1 is a block diagram of a communication system according to a first exemplary embodiment. FIG. 3 is a circuit diagram of a timer according to the first exemplary embodiment. 3 is a timing chart illustrating an operation of a timer according to the first exemplary embodiment. 3 is a timing chart illustrating an operation of the receiving circuit according to the first exemplary embodiment; FIG. 3 is a block diagram of a communication system according to a second exemplary embodiment. 6 is a timing chart illustrating an operation of the receiving circuit according to the second exemplary embodiment; FIG. 6 is a block diagram of a communication system according to a third exemplary embodiment. 10 is a timing chart illustrating an operation of the receiving circuit according to the third exemplary embodiment; FIG. 6 is a block diagram of a communication system according to a fourth exemplary embodiment. 6 is a timing chart illustrating an operation of a receiving circuit according to a fourth exemplary embodiment; FIG. 10 is a block diagram of a communication system according to a fifth exemplary embodiment. 10 is a timing chart illustrating an operation of the transmission circuit according to the fifth exemplary embodiment; It is a block diagram which shows an example of the insulating element concerning this invention. It is a block diagram which shows an example of the insulating element concerning this invention. It is a block diagram which shows an example of the insulating element concerning this invention. It is a block diagram which shows an example of the insulating element concerning this invention. It is a block diagram which shows an example of the insulating element concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. FIG. 25 is a schematic diagram illustrating a cross-sectional view of the semiconductor device according to FIG. 24. FIG. 25 is a schematic diagram illustrating another example of a cross-sectional view of the semiconductor device according to FIG. 24. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system concerning this invention. It is a schematic diagram which shows the mounting state of the communication system using an insulating element. It is a block diagram which shows the example of the communication system for demonstrating a subject. FIG. 33 is a timing chart showing an ideal operation of the communication system shown in FIG. 32. FIG. It is a block diagram of the communication system for demonstrating the malfunction which arises in the communication system shown in FIG. It is a timing chart for demonstrating the malfunction operation | movement in the communication system shown in FIG.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. The communication system according to the present invention has one of the characteristics of the reception method in the reception circuit. Therefore, the following description will focus on the receiving circuit. Further, in the following description, an example in which the conduction state of the power transistor is controlled by the reception data generated in the reception circuit will be described, but the control target of the reception data generated by the reception circuit according to the present invention is limited to this. It is not a thing.

  FIG. 1 shows a block diagram of a communication system 1 according to the first embodiment. As shown in FIG. 1, the communication system 1 includes a first semiconductor chip CHP1 and a second semiconductor chip CHP2 that are electrically insulated. In FIG. 1, the power transistor PTr1 to be controlled by the received data is shown. The power transistor PTr1 outputs a load drive signal Vcm. Further, in the example shown in FIG. 1, an on-chip transformer is provided as the insulating element ISO.

  A transmission circuit Tx is formed in the first semiconductor chip CHP1. The transmission circuit Tx outputs a transmission signal to the primary coil of the on-chip transformer based on the transmission data Dtx1. The first semiconductor chip CHP1 operates based on the power supply voltage VDD1 and the ground voltage GND1.

  On the second semiconductor chip CHP2, an on-chip transformer, a receiving circuit Rx1, and a gate driver GDrv are formed. The secondary coil of the on-chip transformer is connected to the receiving circuit Rx1. The secondary side coil gives the reception circuit Rx1 a reception signal whose voltage level fluctuates based on a magnetic field change generated in the primary side coil. The reception circuit Rx1 switches the logic level of the reception data Drx1 according to a change in the signal level of the reception signal generated based on the transmission signal output from the transmission circuit Tx via the on-chip transformer. Further, the reception circuit Rx1 according to the present embodiment has a function of holding the logical level of the reception data Drx1 in a first period set in advance after the logical level of the reception data Drx1 is switched. The gate driver GDrv drives the power transistor PTr1 based on the reception data Drx1. The second semiconductor chip CHP2 operates based on the power supply voltage VDD2 having a voltage value higher than the power supply voltage VDD1 and the ground voltage GND1. That is, the circuit formed in the second semiconductor chip CHP2 operates in a power supply system different from the transmission circuit Tx. In the power transistor PTr1, the power supply voltage HVDD having a voltage value higher than the power supply voltage VDD1 is supplied to the collector. That is, the load drive signal Vcm has a voltage amplitude larger than the voltage amplitude of the gate control signal output from the reception circuit Rx1 and the gate driver GDrv.

  Here, the receiving circuit Rx1 will be described in more detail. The reception circuit Rx1 includes a state holding circuit 10 and a state holding control circuit 20. The state holding circuit 10 switches the logic level of the reception data Drx1 according to a change in the signal level of the reception signal generated based on the transmission signal output from the transmission circuit Tx through the insulating element. The state holding circuit 10 includes an amplifier circuit AMP and a data recovery circuit (for example, a hysteresis comparator 11). In the reception circuit Rx1, the reception signal A generated in the secondary coil by the amplifier circuit AMP is amplified to generate the reception signal A to be given to the hysteresis comparator 11. That is, the reception signal A is obtained by amplifying the amplitude of the reception signal generated in the secondary coil, and these two signals can be treated as equivalent. Further, when the voltage amplitude of the reception signal generated in the secondary coil has a sufficient magnitude, the amplifier circuit AMP can be omitted.

  The hysteresis comparator 11 generates reception data Drx1 based on the reception signal A. More specifically, the received signal A and a reference voltage (not shown) are input to the hysteresis comparator 11, and when the voltage difference between the received signal A and the reference voltage exceeds a predetermined voltage difference, the logic level of the received data Drx1 is set. Switch. In addition, the hold signal D generated by the state holding control circuit 20 is input to the hysteresis comparator 11. The hysteresis comparator 11 has a function of holding the logical level of the reception data Drx1 output before the hold signal D is enabled during a period in which the hold signal D is enabled (for example, high level).

  The state holding control circuit 20 holds the logical level of the reception data Drx1 in the state holding circuit 10 during a period from the first timing at which the logical level of the reception data Drx1 is switched until a preset first period elapses. A hold signal D to be instructed is generated. The state holding control circuit 20 includes an edge detection circuit 21 and a timer 22. The edge detection circuit 21 detects the rising edge or the falling edge of the reception data Drx1, and generates the edge detection signal C. The timer 22 enables the hold signal D in the first period based on the edge detection signal C. That is, the timer 22 sets the length of the first period.

  An example of a circuit for realizing the timer 22 is shown in FIG. The timer 22 illustrated in FIG. 2 includes a capacitor CAP, a PMOS transistor P1, an NMOS transistor N1, a current source 30, a comparator 31, and a set / reset latch circuit 32.

  One end of the current source 30 is supplied with the power supply voltage VDD1, and the other end is connected to the source of the PMOS transistor P1. An inverted signal of the hold signal D is input to the gate of the PMOS transistor P1. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1. An inverted signal of the hold signal D is input to the gate of the NMOS transistor N1. The ground voltage GND1 is supplied to the source of the NMOS transistor N1. One end of the capacitor CAP and the non-inverting input terminal of the comparator 31 are connected to a connection node between the drain of the NMOS transistor N1 and the drain of the PMOS transistor P1. The ground voltage GND1 is supplied to the other end of the capacitor CAP. A reference voltage Vref is input to the inverting input terminal of the comparator 31. Then, the comparator 31 switches the reset signal RST from the low level to the high level when the voltage at the non-inverting input terminal (hereinafter referred to as a timed voltage Vc) becomes larger than the reference voltage Vref. In the set / reset latch circuit 32, the reset signal RST is input to the reset terminal, and the edge detection signal C is input to the set terminal. The set / reset latch circuit 32 outputs a hold signal D from the output terminal Q and outputs an inverted signal of the hold signal D from the output terminal Qb. The set / reset latch circuit 32 sets the hold signal D to the low level according to the rising edge of the reset signal RST, and sets the hold signal D to the high level according to the rising edge of the edge detection signal C.

  Here, the operation of the timer 22 will be described. A timing chart showing the operation of the timer 22 is shown in FIG. As shown in FIG. 3, when the rising edge of the edge detection signal C is input at the timing t1, the timer 22 switches the hold signal D from the low level to the high level (enabled state). Further, when the hold signal D becomes high level, the NMOS transistor N1 is turned off and the PMOS transistor P1 is turned on. Thereby, the constant current Iref is input to the capacitor CAP from the current source 30, and the voltage of the time measuring voltage Vc gradually increases. When the measured voltage Vc exceeds the reference voltage Vref at timing t2, the comparator 31 raises the reset signal RST. In response to the rising edge of the reset signal RST, the hold signal D changes from the high level to the low level (disabled state).

  That is, the timer 22 sets the length of the first period according to the length from the timing t1 to t2, and enables the hold signal D in the first period. The length of the first period can be adjusted by the capacitance value of the capacitor CAP or the current amount of the constant current Iref. In the communication system 1 according to the first embodiment, the length of the first period is set to be longer than the time required for the noise generated by the fluctuation of the load drive signal Vcm to converge.

  Subsequently, an operation of the communication system 1 according to the first exemplary embodiment will be described. A timing chart showing the operation of the communication system 1 is shown in FIG. As shown in FIG. 4, in the communication system 1, a positive pulse is generated as the reception signal A according to the rising edge of the transmission data Dtx1, and a negative pulse is generated as the reception signal A according to the falling edge of the reception data Drx1. The Then, the reception circuit Rx1 switches the reception data Drx1 from the low level to the high level according to the positive pulse of the reception signal A. The reception circuit Rx1 switches the reception data Drx1 from the high level to the low level in response to the negative pulse of the reception signal A. Further, the edge detection circuit 21 outputs a pulse signal as the edge detection signal C according to the switching edge of the reception data Drx1. Then, the timer 22 enables the hold signal D during the first period in accordance with the pulse of the edge detection signal C.

  Subsequently, the load drive signal Vcm starts to change with a delay from the change of the reception data Drx1. In the example illustrated in FIG. 4, the load drive signal Vcm increases the voltage when the reception data Drx1 rises, and decreases the voltage when the reception data Drx1 falls. Then, noise occurs in the power supply voltage VDD1 due to the fluctuation of the load drive signal Vcm. Then, voltage fluctuation occurs in the received signal A due to this noise.

  At this time, in the receiving circuit Rx1, the hysteresis comparator 11 is in an operating state during a period in which the hold signal D is disabled, and the switching of the logical level of the received data Drx1 according to the voltage fluctuation of the received signal A is permitted. On the other hand, in the receiving circuit Rx1, the hysteresis comparator 11 is in the hold state while the hold signal D is in the enabled state, and switching of the logic level of the received data Drx1 according to the voltage fluctuation of the received signal A is not permitted. In the example shown in FIG. 4, the hold signal D is controlled to be in an enabled state during the period when noise is mixed in the received signal A by the operation of the state holding control circuit 20. That is, the reception circuit Rx1 fixes the logic level of the reception data Drx1 by the hysteresis comparator 11 during a period in which noise is mixed in the reception signal A. As a result, the reception circuit Rx1 prevents the reception data Drx1 from becoming indefinite due to noise. As illustrated in FIG. 4, the reception circuit Rx1 resumes the normal operation that permits switching of the logical level of the reception data Drx1 based on the fluctuation of the reception signal A after the first period has elapsed.

  Generation of noise through the parasitic coupling capacitance of the semiconductor device constituting the communication system 1 occurs when the voltage of the load drive signal Vcm for driving the load by the power transistor PTr1 changes. This voltage change is triggered by a change in the gate control signal of the power transistor PTr1 propagated through the isolator. In the example shown in FIG. 4, this gate control signal changes according to the change of the transmission data Dtx1 in the low voltage region. The load is, for example, a switching power supply circuit that operates with a household power supply, a motor, a lighting device, or the like, and the voltage amplitude of the load drive signal Vcm is assumed to be about several tens to several kilovolts. As described above, the load drive signal Vcm has an extremely large voltage amplitude as compared with the power supply voltage VDD1 (for example, 5 V) supplied to the second semiconductor chip CHP2. The injected noise tends to increase. And when the voltage amplitude of noise is large, the malfunction of the communication system 1 resulting from noise may occur. In particular, if noise is injected into the receiving circuit Rx1 and a state holding circuit such as the hysteresis comparator 11 in the receiving circuit Rx1 sticks to an incorrect logical value, a malfunction occurs.

  Here, since the noise injected into the reception signal A is triggered by changes in the transmission data Dtx1 and the reception data Drx1, it is possible to predict the timing at which the noise is generated. Specifically, the load drive signal Vcm changes and noise occurs several tens to several hundreds ns after the logical value of the reception data Drx1 output from the reception circuit Rx changes. This time difference is a delay of the gate driver and a delay of the power transistor PTr1. Further, this noise is a damped oscillation due to the parasitic inductance, parasitic resistance and parasitic capacitance of the peripheral circuit, and its duration can also be predicted (for example, about several tens to several hundreds ns). Since the duration of noise can be predicted with a certain degree of accuracy, the length of the first period can be set based on this prediction.

  From the above description, in the communication system 1 according to the first embodiment, the reception circuit Rx1 receives the reception by the state holding circuit 10 until the first period elapses from the timing when the logical level of the reception data Drx1 changes. The logic level of the data Drx1 is fixed. Thereby, in the communication system 1 according to the first embodiment, even when noise of the reception signal A is injected due to circuit operation, the reception data Drx1 is prevented from being inverted or indefinite due to the influence of noise. be able to.

Embodiment 2
FIG. 5 is a block diagram of the communication system 2 according to the second embodiment. The communication system 2 according to the second embodiment shows a state holding circuit 10a that is a modification of the state holding circuit 10 of the communication system 1 according to the first embodiment. In the description of the communication system 2 according to the second exemplary embodiment, the same components as those of the communication system 1 according to the first exemplary embodiment are denoted by the same reference numerals as those of the first exemplary embodiment and description thereof is omitted.

  The state holding circuit 10a according to the second embodiment includes a switch circuit SWTr in addition to the amplifier circuit AMP and the hysteresis comparator 11. The switch circuit SWTr is connected between the hysteresis comparator 11 and the amplifier circuit AMP. That is, in the form in which the amplifier circuit AMP is omitted, the switch circuit SWTr is connected between the secondary coil and the hysteresis comparator 11.

  As the switch circuit SWTr, an NMOS transistor is used in the example shown in FIG. The source of the NMOS transistor is connected to the amplifier circuit AMP, and the drain is connected to the input of the hysteresis comparator 11. A hold signal D is input to the gate of the NMOS transistor. In FIG. 5, in order to distinguish between the transmission signal input to the switch circuit SWTr and the transmission signal output from the switch circuit SWTr, the transmission signal input to the switch circuit SWTr is denoted by A. The transmission signal output from the switch circuit SWTr is denoted by B.

  In the communication system 2 according to the second embodiment, the switch circuit SWTr controls whether to allow the hysteresis comparator 11 to switch the logic level of the reception data Drx1. Therefore, the hold signal D is not input to the hysteresis comparator 11 according to the second embodiment, and a mechanism for switching the operation mode by the hold signal D is not provided. In the example shown in FIG. 5, an NMOS transistor is configured as the switch circuit SWTr. Therefore, a signal output from the output terminal Qb of the set / reset latch circuit 32 shown in FIG.

  Subsequently, an operation of the communication system 2 according to the second exemplary embodiment will be described. FIG. 6 shows a timing chart showing the operation of the communication system 2. As shown in FIG. 6, also in the communication system 2, the relationship between the timing when the hold signal D is enabled (low level in the second embodiment) and the timing when the logical level of the received data Drx1 is switched is the same as in the first embodiment. This is the same as the communication system 1.

  In the communication system 2 according to the second embodiment, the switch circuit SWTr is turned off during the period in which the hold signal D is in the enabled state. Therefore, while the hold signal D is in the enabled state, the reception signal A input to the switch circuit SWTr is injected with noise due to the fluctuation of the load drive signal Vcm, but the reception signal output from the switch circuit SWTr. The noise is not injected into B. As a result, during the period in which the hold signal D is enabled, the logic level of the reception data Drx1 output from the hysteresis comparator 11 is fixed, and malfunction is prevented.

  On the other hand, since the hold signal D is disabled (high level in the second embodiment) after the first period has elapsed, the switch circuit SWTr is turned on, and the reception signal A is directly used as the reception signal B. The hysteresis comparator 11 switches the logic level of the reception data Drx1 based on the fluctuation of the reception signal B.

  From the above description, in the communication system 2 according to the second embodiment, similarly to the communication system 1 according to the first embodiment, malfunction due to noise generated after the change in the logic level of the reception data Drx1 is prevented.

Embodiment 3
FIG. 7 shows a block diagram of the communication system 3 according to the third embodiment. A communication system 3 according to the third embodiment shows a state holding circuit 10b that is a modification of the state holding circuit 10 of the communication system 1 according to the first embodiment. Further, the communication system 3 includes a state holding control circuit 20 a that is a modification of the state holding control circuit 20 of the communication system 1. In the description of the communication system 3 according to the third embodiment, the same components as those of the communication system 1 according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The state holding circuit 10b includes an amplifier circuit AMP, a positive pulse detection circuit 12, a negative pulse detection circuit 13, and a latch circuit 14. The positive pulse detection circuit 12 obtains the reception signal A from the amplifier circuit AMP. When a positive pulse (for example, a pulse having an amplitude on the positive potential side) is generated in the reception signal A, the rising detection signal E having a predetermined pulse width is output. A reception signal A is obtained from the negative pulse detection circuit 13 and the amplification circuit AMP. When a negative pulse (for example, a pulse having an amplitude on the negative potential side) is generated in the reception signal A, the rising detection signal F having a predetermined pulse width is output. The latch circuit 14 is, for example, a set / reset latch circuit, and the rising detection signal E is input to the set input terminal, and the rising detection signal F is input to the reset input terminal. Then, the reception data Drx1 is output from the output terminal Q. That is, the latch circuit 14 raises the reception data Drx1 in response to the rising detection signal E, and lowers the reception data Drx1 in response to the rising detection signal F. Further, the hold signal H is input to the latch circuit 14, and when the hold signal H is in an enable state (for example, high level), the logic level of the reception data Drx1 is fixed, and the hold signal H is in the disable state. In the case of (for example, low level), the logic level of the reception data Drx1 is switched according to the rising detection signal E or the rising detection signal F.

  The state holding control circuit 20 a is obtained by replacing the edge detection circuit 21 of the state holding control circuit 20 with an edge detection circuit 23. The edge detection circuit 23 generates an edge detection signal G in response to a change in either the rising detection signal E or the rising detection signal F. Then, the timer 22 generates a hold signal H based on the edge detection signal G.

  Subsequently, an operation of the communication system 3 according to the third exemplary embodiment will be described. A timing chart showing the operation of the communication system 3 is shown in FIG. As shown in FIG. 8, in the communication system 3, the rising detection signal E and the rising detection signal F are in an indefinite state for a certain period due to noise generated due to fluctuations in the load drive signal Vcm. However, in the communication system 3, the hold signal G is controlled to be in an enabled state during a period when noise is generated. As a result, the latch circuit 14 is in a hold state during a period in which noise is generated, and fixes the logical level of the reception data Drx1.

  From the above description, in the communication system 3 according to the third embodiment, similarly to the communication system 1 according to the first embodiment, malfunction due to noise generated after the change in the logic level of the reception data Drx1 is prevented.

Embodiment 4
FIG. 9 shows a block diagram of the communication system 4 according to the fourth embodiment. The communication system 4 according to the fourth embodiment shows a state holding circuit 10c that is a modification of the state holding circuit 10 of the communication system 1 according to the first embodiment. In the description of the communication system 4 according to the fourth embodiment, the same components as those of the communication system 1 according to the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The state holding circuit 10c includes a hysteresis comparator 15, a gating circuit (for example, a latch circuit 16), an AND circuit 17 with an inverting input, and an AND circuit 18. The hysteresis comparator 15 receives the reception signal A output from the amplifier circuit AMP and generates intermediate reception data I. The intermediate reception data I is switched in logic level according to the voltage level of the reception signal A. The latch circuit 16 switches the logic level of the reception data Drx1 according to the intermediate reception data I. The latch circuit 16 fixes the logical level of the reception data Drx1 when the hold signal K is in an enable state (for example, high level). In the present embodiment, the hold signal K is generated based on the edge detection signal J generated based on the reception data Drx1.

  In the AND circuit 17 with an inverting input, the reception data Drx1 is input to the inverting input terminal, and the hold signal K is input to the other input terminal. The AND circuit 17 with an inverting input outputs a logical product value of the inverted value of the reception data Drx1 and the logical value of the hold signal K as a reset signal R. In the AND circuit 18, the reception data Drx1 is input to one input terminal, and the hold signal K is input to the other input terminal. Then, the AND circuit 18 outputs a logical product value of the reception data Drx1 and the hold signal K as a set signal S.

  The hysteresis comparator 15 switches the logic level of the intermediate reception data I to be output according to the set signal S and the reset signal R. Specifically, the hysteresis comparator 15 sets the intermediate reception data I to a high level when the set signal S is in an enabled state (for example, high level), and intermediate when the reset signal R is in an enabled state (for example, high level). The reception data I is set to the low level. The set signal S is enabled when the hold signal K is enabled and the received data Drx1 is at a high level, and the reset signal R is enabled when the hold signal K is enabled and the received data Drx1 is at a low level. .

  Next, the operation of the communication system 4 will be described. FIG. 10 is a timing chart showing the operation of the communication system 4. As shown in FIG. 10, in the communication system 4, even if the intermediate reception data I becomes indefinite due to noise, the set signal S or the reset signal R returns to the logic level before the noise is injected. In addition, since the latch circuit 16 is controlled to be in the hold state by the hold signal K during the period when noise is injected, the logic level of the reception data Drx1 is not affected by the noise.

  From the above description, in the communication system 4 according to the fourth embodiment, similarly to the communication system 1 according to the first embodiment, the malfunction due to the noise generated after the change in the logic level of the reception data Drx1 is prevented.

Embodiment 5
FIG. 11 is a block diagram of the communication system 5 according to the fifth embodiment. As shown in FIG. 5, the communication system 5 includes a transmission circuit Tx1 used in combination with the reception circuit described in the first to fourth embodiments. As shown in FIG. 11, the transmission circuit Tx1 is formed on the first semiconductor chip CHP1.

  The transmission circuit Tx1 includes a latch circuit 40, a pulse generation circuit 41, a transmission drive circuit 42, and a timer 50. The latch circuit 40 generates transmission data Dtx12 according to the transmission data Dtx1. The pulse generation circuit 41 generates a transmission signal for the transmission drive circuit 42 to drive the primary coil based on the transmission data Dtx12.

  The state holding control circuit 50 includes an edge detection circuit 51 and a timer 52. The edge detection circuit 51 and the timer 52 are substantially the same as the edge detection circuit 21 and the timer 22. At this time, the timer 52 sets a second period longer than the first period set by the timer 22. That is, in the timer 52, the edge detection circuit 51 generates the edge detection signal L, and the hold signal M is enabled in the second period according to the edge detection signal L. Thereby, the pulse generation circuit 41 fixes the logical level of the transmission data Dtx12 until the second period elapses after the transmission data Dtx1 changes. Then, the latch circuit 40 changes the transmission data Dtx12 according to the transmission data Dtx1 after the second period has elapsed.

  Here, the operation of the communication system 5 will be described. A timing chart showing the operation of the communication system 5 is shown in FIG. FIG. 12 shows an example in which the receiving circuit Rx1 according to the first embodiment is used as the receiving circuit Rx.

  As shown in FIG. 12, in the transmission circuit Tx1, the logical level of the transmission data Dtx12 is fixed regardless of the change of the transmission data Dtx1 until the second period elapses after the transmission data Dtx12 is changed. Then, the second period is set longer than the first period. Thereby, in the communication system 5, the reception signal A is prevented from fluctuating according to the transmission data Dtx1 while the hysteresis comparator 11 of the reception circuit Rx1 is in the hold state.

  As described above, in the communication system 5, the transmission circuit Tx1 waits for the transmission of the edge data until the reception circuit Rx1 can detect the change of the transmission data Dtx1. As a result, the communication system 5 prevents the edge data of the transmission data Dtx1 from being erroneously transmitted or not transmitted.

  As described above, by using the reception circuit Rx1 according to the communication system 5, it is possible to prevent the edge data of the transmission data Dtx1 from being transmitted in the reception circuits Rx1 to Rx4. Thereby, in the communication system 5, the reliability of communication can be improved.

Other Embodiments As other embodiments, an example of an insulating element and a mounting example of the insulating element will be described below. First, an example of an insulating element is shown in FIGS. FIG. 13 uses an on-chip transformer 60 as an insulating element. In FIG. 14, a capacitor 61 is used as an insulating element. FIG. 15 uses a GMR element 62 as an insulating element. In FIG. 16, a pulse drive type photocoupler 63 is used as an insulating element. In FIG. 17, a DC drive type photocoupler 64 is used as an insulating element.

  As shown in FIGS. 13 to 17, since the method or element for transmitting data differs depending on the insulating element, it is necessary to change the input format of the transmission drive circuit 42 or the amplifier circuit AMP when the insulating element is changed. is there. However, in any example, it can be seen that the same processing can be applied in the reception circuit Tx and the reception circuit Rx.

  Subsequently, FIGS. 18 to 28 show schematic views of mounting examples when an on-chip transformer is used as an insulating element. In addition, FIGS. 29 and 30 show schematic views of mounting examples when an on-chip transformer is used as an insulating element.

  FIG. 18 shows an example in which the on-chip transformer shown in FIG. 31 is provided in the first semiconductor chip CHP1. 19 and 20 show a case where a primary coil and a secondary coil are formed by wiring formed in the same wiring layer. In FIG. 21, an on-chip transformer is formed on a semiconductor chip different from the transmission circuit Tx and the reception circuit Rx. 22 and 23, the transmission circuit Tx and the reception circuit Rx are formed on different semiconductor chips, and the primary side coil and the secondary side coil are formed on different semiconductor chips. In FIG. 24, a transmission circuit Tx, an on-chip transformer, and a reception circuit Rx are formed on one semiconductor chip. In this semiconductor chip, one chip is substantially separated into a transmitting chip and a receiving chip by an insulating layer formed on a semiconductor substrate. Cross-sectional views of the semiconductor device showing this separation are shown in FIGS. 27 and 28 are schematic diagrams of a communication system used when transmission data is transmitted as a differential signal, or when a rising edge and a falling edge are transmitted using different on-chip transformers. FIG. 29 is obtained by replacing the on-chip transformer shown in FIG. 30 with a capacitor. FIG. 30 is obtained by replacing the on-chip transformer shown in FIG. 28 with a capacitor.

  From the above description, it can be seen that in the communication system to which the transmission circuit Tx and the reception circuit Rx according to the present invention can be applied, there is no particular limitation on the type of the insulating element or the arrangement of the insulating elements. In the above description, the insulating element is formed on the semiconductor chip. However, the insulating element can be provided as an external component.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

The present invention includes the following other aspects.
(Appendix 1)
A receiving circuit that operates in a power supply system different from the transmitting circuit,
A state holding circuit that switches a logic level of received data in accordance with a change in signal level of a received signal generated based on a transmission signal output from the transmitting circuit via an insulating element;
A hold signal for instructing the state holding circuit to hold the logical level of the received data is generated in a period from a first timing at which the logical level of the received data is switched until a preset first period elapses. A state holding control circuit;
A receiving circuit.
(Appendix 2)
The state holding circuit is
A data recovery circuit for generating the received data based on the received signal;
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The receiving circuit according to claim 1, further comprising: a timer that enables the hold signal in the first period based on the edge detection signal.
(Appendix 3)
The receiving circuit according to appendix 2, wherein the state holding circuit includes a switch circuit that is provided between the insulating element and the data recovery circuit and is in a cut-off state during a period in which the hold signal is enabled.
(Appendix 4)
The data recovery circuit includes:
A positive pulse detection circuit that detects a positive pulse in the received signal and outputs a rising detection signal;
A negative pulse detection circuit that detects a negative pulse in the received signal and outputs a falling detection signal;
A latch circuit that sets the received data to a first logic level in response to the rising edge detection signal and sets the received data to a second logic level in response to the falling edge detection signal;
The receiving circuit according to appendix 2, wherein the edge detection circuit generates an edge detection signal by detecting a change in a logic level of the received data based on the falling detection signal and a change in the falling detection signal.
(Appendix 5)
The state holding circuit is
A data recovery circuit for generating intermediate received data based on the received signal;
A gating circuit that switches the logic level of the received data according to the logic level of the intermediate received data, and switches whether to fix the logic level of the received data according to the hold signal;
A state return circuit that sets a value of the received data output by the data recovery circuit based on an output of the gating circuit and the hold signal to a value of either a first logic level or a second logic level; Have
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The receiving circuit according to claim 1, further comprising: a timer that enables the hold signal in the first period based on the edge detection signal.
(Appendix 6)
The timer is
A constant current source that outputs a constant current;
A capacitor that generates a timed voltage based on the constant current;
A reset transistor for initializing charges accumulated in the capacitor based on an inverted signal of the hold signal;
A comparator that compares the timekeeping voltage with a reference voltage and outputs a reset signal;
And a set / reset latch circuit that inputs the edge detection signal to a set terminal, inputs the reset signal to a reset terminal, and generates the hold signal based on the edge detection signal and the reset signal. The receiving circuit according to any one of the above.
(Appendix 7)
The receiving circuit according to any one of appendices 1 to 6, wherein the receiving circuit supplies the received data to a load driving circuit that generates a load driving signal having a voltage amplitude higher than a power supply voltage of the receiving circuit.
(Appendix 8)
The reception circuit according to any one of appendices 1 to 7, wherein the transmission circuit stops generating the transmission signal regardless of a change in transmission data during a second period longer than the first period.
(Appendix 9)
The receiving circuit according to any one of appendices 1 to 8, wherein the insulating element is any one of a transformer, a capacitor, a GMR element, and a photocoupler.
(Appendix 10)
10. The receiver circuit according to any one of appendices 1 to 9, wherein the receiver circuit is formed on a semiconductor substrate insulated from the transmitter circuit.
(Appendix 11)
Reception of a reception circuit that operates in a power supply system different from that of the transmission circuit and switches the logical level of received data in accordance with a change in the signal level of the reception signal generated based on the transmission signal output from the transmission circuit via an insulating element. A method,
Detecting a change in the logic level of the received data;
Fixing the logical level of the received data in a period from when the logical level of the received data changes until a preset first period elapses;
A reception method of a reception circuit that switches a logic level of the reception data in accordance with a change in the reception signal after the first period has elapsed.
(Appendix 12)
12. The reception method of the reception circuit according to appendix 11, wherein the first period is a period longer than a period during which a power supply voltage variation caused by an operation of a load driving circuit to which the reception data is applied converges.
(Appendix 13)
The transmission circuit stops the change in the logical level of the transmission signal in a period from when the logical level of the transmission signal is changed to when a second period longer than the first period elapses. A receiving method for the receiving circuit according to claim 1.
(Appendix 14)
A transmission circuit that outputs a transmission signal to the insulating element based on the transmission data;
A receiving circuit that operates in a power supply system different from the transmitting circuit and switches a logic level of received data in accordance with a change in a signal level of a received signal generated based on a transmission signal output from the transmitting circuit via an insulating element; Have
The receiving circuit is
A state holding circuit for switching the logic level of the received data in accordance with a change in the signal level of the received signal;
A state holding control circuit for generating a hold signal instructing the state holding circuit to hold the logical level of the received data in a first period set in advance from a first timing at which the logical level of the received data is switched;
A communication system.
(Appendix 15)
The state holding circuit is
A data recovery circuit for generating the received data based on the received signal;
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The communication system according to appendix 14, further comprising a timer that enables the hold signal in the first period based on the edge detection signal.
(Appendix 16)
The communication system according to supplementary note 15, wherein the state holding circuit includes a switch circuit that is provided between the insulating element and the data recovery circuit and is cut off during a period in which the hold signal is enabled.
(Appendix 17)
The data recovery circuit includes:
A positive pulse detection circuit that detects a positive pulse in the received signal and outputs a rising detection signal;
A negative pulse detection circuit that detects a negative pulse in the received signal and outputs a falling detection signal;
A latch circuit that sets the received data to a first logic level in response to the rising edge detection signal and sets the received data to a second logic level in response to the falling edge detection signal;
16. The communication system according to appendix 15, wherein the edge detection circuit generates an edge detection signal by detecting a change in logic level of the received data based on the falling detection signal and a change in the falling detection signal.
(Appendix 18)
The state holding circuit is
A data recovery circuit for generating the received data based on the received signal;
A gating circuit that transmits a logic level of the received data to a subsequent circuit and switches whether to fix the logic level of the received data according to the hold signal;
A state return circuit that sets a value of the received data output by the data recovery circuit based on an output of the gating circuit and the hold signal to a value of either a first logic level or a second logic level; Have
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The communication system according to appendix 14, further comprising a timer that enables the hold signal in the first period based on the edge detection signal.
(Appendix 19)
The timer is
A constant current source that outputs a constant current;
A capacitor that generates a timed voltage based on the constant current;
A reset transistor for initializing charges accumulated in the capacitor based on an inverted signal of the hold signal;
A comparator that compares the timekeeping voltage with a reference voltage and outputs a reset signal;
Additional remarks 14 to 18, further comprising: a set / reset latch circuit that inputs the edge detection signal to a set terminal, inputs the reset signal to a reset terminal, and generates the hold signal based on the edge detection signal and the reset signal. The communication system according to any one of the above.
(Appendix 20)
The communication system according to any one of appendices 14 to 19, wherein the reception circuit supplies the reception data to a load drive circuit that generates a load drive signal having a voltage amplitude higher than a power supply voltage of the reception circuit.
(Appendix 21)
The communication system according to any one of appendices 14 to 20, wherein the transmission circuit stops generating the transmission signal regardless of a change in transmission data during a second period longer than the first period.
(Appendix 22)
The communication system according to any one of appendices 14 to 21, wherein the insulating element is any one of a transformer, a capacitor, a GMR element, and a photocoupler.
(Appendix 23)
The communication system according to any one of appendices 14 to 22, wherein the reception circuit is formed on a semiconductor substrate insulated from the transmission circuit.

1-5 Communication system 10, 10a, 10b, 10c State holding circuit 11, 15 Hysteresis comparator 12 Positive pulse detection circuit 13, 16 Negative pulse detection circuit 14, 40 Latch circuit 17 AND circuit with inverting input 18 AND circuit 20, 20a, DESCRIPTION OF SYMBOLS 50 State maintenance control circuit 21, 23, 51 Edge detection circuit 22, 52 Timer 30 Current source 31 Comparator 32 Set reset latch circuit 41 Pulse generation circuit 42 Transmission drive circuit 60 On-chip transformer 61 Capacitor 62 GMR element 63 Pulse drive type photocoupler 64 DC-driven photocoupler 71 Semiconductor package 72 External terminal L1 Primary side coil L2 Secondary side coil Tx, Tx1 Transmitter circuit Rx, Rx1 to Rx4 Receiver circuit ISO insulation element CHP1 First semiconductor chip CHP2 Second semiconductor chip Dtx1, Dtx12 Transmission data Drx1 Reception data A, B Reception signal C, G, J, L Edge detection signal D, H, K, M Hold signal E Rise detection signal F Rise detection signal I Intermediate reception Data S Set signal R Reset signal Vcm Load drive signal

Claims (7)

A receiving circuit that operates in a power supply system different from the transmitting circuit,
A state holding circuit that switches a logic level of received data in accordance with a change in signal level of a received signal generated based on a transmission signal output from the transmitting circuit via an insulating element;
A hold signal for instructing the state holding circuit to hold the logical level of the received data is generated in a period from a first timing at which the logical level of the received data is switched until a preset first period elapses. A state holding control circuit;
A receiving circuit. The state holding circuit is
A data recovery circuit for generating the received data based on the received signal;
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The receiving circuit according to claim 1, further comprising: a timer that enables the hold signal in the first period based on the edge detection signal.   The receiving circuit according to claim 2, wherein the state holding circuit includes a switch circuit that is provided between the insulating element and the data recovery circuit, and is in a cut-off state during a period in which the hold signal is enabled. The data recovery circuit includes:
A positive pulse detection circuit that detects a positive pulse in the received signal and outputs a rising detection signal;
A negative pulse detection circuit that detects a negative pulse in the received signal and outputs a falling detection signal;
A latch circuit that sets the received data to a first logic level in response to the rising edge detection signal and sets the received data to a second logic level in response to the falling edge detection signal;
The receiving circuit according to claim 2, wherein the edge detection circuit generates an edge detection signal by detecting a change in a logic level of the reception data based on the falling detection signal and a change in the falling detection signal. The state holding circuit is
A data recovery circuit for generating intermediate received data based on the received signal;
A gating circuit that switches the logic level of the received data according to the logic level of the intermediate received data, and switches whether to fix the logic level of the received data according to the hold signal;
A state return circuit that sets a value of the received data output by the data recovery circuit based on an output of the gating circuit and the hold signal to a value of either a first logic level or a second logic level; Have
The state holding control circuit includes:
An edge detection circuit that detects a rising edge or a falling edge of the received data and generates an edge detection signal;
The receiving circuit according to claim 1, further comprising: a timer that enables the hold signal in the first period based on the edge detection signal. Reception of a reception circuit that operates in a power supply system different from that of the transmission circuit and switches the logical level of received data in accordance with a change in the signal level of the reception signal generated based on the transmission signal output from the transmission circuit via an insulating element. A method,
Detecting a change in the logic level of the received data;
Fixing the logical level of the received data in a period from when the logical level of the received data changes until a preset first period elapses;
A reception method of a reception circuit that switches a logic level of the reception data in accordance with a change in the reception signal after the first period has elapsed. A transmission circuit that outputs a transmission signal to the insulating element based on the transmission data;
A receiving circuit that operates in a power supply system different from the transmitting circuit and switches a logic level of received data in accordance with a change in a signal level of a received signal generated based on a transmission signal output from the transmitting circuit via an insulating element; Have
The receiving circuit is
A state holding circuit for switching the logic level of the received data in accordance with a change in the signal level of the received signal;
A state holding control circuit for generating a hold signal instructing the state holding circuit to hold the logical level of the received data in a first period set in advance from a first timing at which the logical level of the received data is switched;
A communication system.

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