JP2011211346A - Ultra-wideband wireless communication ranging device, ranging method, and time interval detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve ranging distance resolution without using a high-speed sampling signal.SOLUTION: The ultra-wideband wireless communication ranging device includes: a main counter 163 which is cleared at a first time, and counts up using a clock signal and stops it at a second time by obtaining the first time (Tr) at which a spectrum diffusion modulation signal is transmitted to the space in a reception system, and obtaining the second time (Ds) from a synchronization point of the spectrum diffusion modulation signal; and a sub-counter 162 which obtains k 1-bit signals by being latched at least at the second time and is supplied with clocks from a clock phase shifter 164.

Description

  The present invention relates to an ultra-wideband wireless communication ranging device using ultra-wideband wireless communication, a ranging method using ultra-wideband wireless communication, and a time interval detection device suitable for use in an ultra-wideband wireless communication ranging device. .

  A distance measurement technique for measuring a distance using wireless communication (more broadly, ultra-wideband wireless communication) using a spread spectrum modulation signal has been proposed. For example, Non-Patent Document 1 describes that wireless communication using a spread spectrum modulation signal can be used for distance measurement because the time required for radio wave propagation can be accurately calculated. Japanese Patent Application Laid-Open No. H10-260260 describes that when a PN code is used for spectrum spreading and distance measurement data is detected, sampling is performed using a high-speed sampling signal to obtain a differential signal. In Patent Document 2, a first spread spectrum modulation signal is transmitted from the own station to another station, and the time at which the other station receives the first spread spectrum modulation signal and the time at which the second spread spectrum modulation signal is transmitted. The time when the local station receives this second spread spectrum modulation signal and measures the distance between the local station and another station is included in the second spread spectrum modulation signal. Are listed. Patent Document 3 describes a technique using a chirp method in order to further improve the accuracy of distance measurement.

  However, in any of the techniques described in Non-Patent Document 1, Patent Document 1 to Patent Document 3, in order to improve distance resolution (distance resolution) in ranging, unless a high-speed sampling signal is used, I couldn't achieve that goal. In order to use a high-speed sampling signal, the circuit configuration becomes complicated and the apparatus becomes expensive. In addition, it has been difficult to provide an element that can withstand high-speed processing for using a high-speed sampling signal. For these reasons, there is a limit to the speed of the sampling signal that can be actually obtained.

Japanese Patent Laid-Open No. 10-234072 JP 2001-183447 A JP 2009-170968 A

Yukiji Yamauchi "Spread Spectrum Communication" Tokyo Denki University Press, November 20, 1994, first edition published

  In view of the above-described problems, the problem to be solved by the present invention is that an ultra-wideband wireless communication distance measuring apparatus and an ultra-wideband wireless communication capable of improving the distance resolution of distance measurement without using a high-speed sampling signal. It is to provide a distance measuring method using. It is another object of the present invention to provide a time interval detection device suitable for use in such an ultra-wideband wireless communication ranging device.

  An ultra-wideband wireless communication distance measuring device of the present invention includes a receiving unit that receives a spread spectrum modulation signal that is transmitted to a space and propagates through a measured object, and a time at which the spread spectrum modulation signal is transmitted to the space. A transmission timing generator for obtaining a first time, a synchronization point detector for obtaining a second time from a synchronization point of a spread spectrum modulation signal obtained from the receiver, and a time interval between the first time and the second time A time interval detecting means for detecting the time by digital processing, an arrival time detecting unit for obtaining an arrival time of the radio wave from the measured object to the receiving unit based on the time interval, and integrating the speed of light to the arrival time. Computing means for computing the distance between the object to be measured and the receiving unit, wherein the time interval detecting means comprises a first time detecting unit, a second time detecting unit, and the first time detecting unit. A combining unit that combines the first time interval obtained by the second time interval and the second time interval obtained by the second time detection unit, wherein the first time detection unit is cleared at the first time. An upper bit generator comprising a counter that counts up with a first clock signal of a predetermined period and stops counting up at the second time and outputs m-bit binary data as a count value; The second time detection unit is a first clock signal which is k clock signals whose phases are shifted by (180 degrees / k) with respect to the first clock signal based on the power k of 2 A clock phase shifter for generating the k-th clock signal and each of the first clock signal to the k-th clock signal are latched at least at the second time to obtain k 1-bit signals. From the latch circuit and k 1-bit signals obtained by the latch circuit, the smaller the time between the time when the first clock signal counts up the counter and the second time, the smaller the value. (K-1) a low-order bit generator that forms binary data, and the combining unit uses the m bits obtained from the high-order bit generator as high-order bits, and the above-mentioned obtained from the latch circuit. (K-1) bits are used as lower bits, and (m + n) bits of binary data are output.

  According to the distance measuring method of the present invention, the receiving unit receives a spread spectrum modulation signal that is transmitted to a space and propagates through an object to be measured, and is a time when the spread spectrum modulation signal is transmitted to the space. The time is obtained, the synchronization point detector obtains the second time from the synchronization point of the spread spectrum modulation signal obtained from the reception unit, and the counter of the first time detection unit is cleared at the first time, Counting up with the first clock signal of the period, stopping the counting up at the second time, outputting m-bit binary data as the count value, and the second time detecting unit based on the power k of 2 The first clock signal to the k-th clock signal, which are k clock signals whose phases are shifted by (180 degrees / k) with respect to the first clock signal, are generated. Each of the first clock signal to the kth clock signal is latched at least at the second time to obtain k 1-bit signals, and k 1-bit signals obtained by the latch circuit are obtained. From the signal, (k-1) -bit binary data is formed which has a smaller value as the time between the time when the first clock signal counts up the counter and the second time is shorter. The m bits are the upper bits, the (k-1) bits are the lower bits, and (m + n) bits of binary data are output, and the arithmetic means calculates the measured data based on the (m + n) bits of binary data. The distance between the distance object and the receiving unit is calculated.

  The time interval detection device of the present invention is a time interval detection device that detects the time interval between the first time and the second time by digital processing, and the time interval detection device includes a first time detection unit, a second time detection unit, and a second time detection unit. A time detection unit; and a synthesis unit that combines the first time interval obtained by the first time detection unit and the second time interval obtained by the second time detection unit. The unit is a high-order bit having a counter that is cleared at the first time, counted up with a first clock signal having a predetermined period, and stopped at the second time, and outputs m-bit binary data as a count value. And the second time detector includes k clock signals whose phases are shifted by (180 degrees / k) with respect to the first clock signal based on the power of 2 k. is there, A clock phase shifter for generating a first clock signal to a k-th clock signal, and a latch for latching each of the first clock signal to the k-th clock signal at least at the second time to obtain k 1-bit signals The shorter the time between the time when the first clock signal counts up the counter and the second time from the k 1-bit signals obtained by the circuit and the latch circuit, the smaller the value is ( k-1) a low-order bit generator that forms binary data, and the combining unit uses the m bits obtained from the high-order bit generator as high-order bits, and is obtained from the latch circuit ( k-1) Outputs (m + n) -bit binary data with the lower bits as bits.

  According to the ultra-wideband wireless communication distance measuring apparatus of the present invention and the distance measurement method using ultra-wideband wireless communication, the distance resolution of the distance measurement can be achieved without using a high-speed sampling signal, without using an element that can withstand high-speed processing. In addition, the price of the apparatus can be reduced. In addition, according to the time interval detection device of the present invention, it is possible to provide an ultra-wideband wireless communication ranging device that achieves such a purpose without using a high-speed sampling signal.

It is a figure which shows the principle of the ranging by an ultra wideband radio | wireless. It is a figure which shows three systems of ranging by an ultra wideband radio | wireless. It is a block diagram of the ultra-wideband wireless communication ranging device of the embodiment. It is a figure which shows the frame format of embodiment. It is a figure which shows the relationship between the frame format of embodiment, and ranging. It is a figure which shows each of the baseband data of embodiment, a PN series, and a spread spectrum modulation signal. It is a figure which shows typically the technique of the detection of the edge applicable to a synchronous point in the past. It is a figure which shows the principle of the technique of the synchronization point detection of embodiment with a time chart. It is a figure which shows the block diagram of the part which functions as the arrival time measurement means of the reception process block of embodiment. It is a figure which shows the principal part of embodiment by a specific Example. It is a figure which shows another Example of the subcounter which is the principal part of embodiment. It is a figure which shows operation | movement of the subcounter of an Example by a time chart. It is a figure which shows typically the case where noise is contained in a spread spectrum modulation signal. It is a figure which shows the block diagram of the subcounter which has the function of the majority process of embodiment, and an average value process. It is a figure which shows the circuit of the Example which operates a main counter with the clock signal different from the clock signal from a clock phase shifter. 16 is a time chart showing the relationship between a spread spectrum modulation signal and a clock signal in the circuit of the embodiment shown in FIG.

  The ultra wideband wireless communication distance measuring device of the embodiment, the distance measuring method of the embodiment, and the time interval detection device of the embodiment are characterized by the technique of time interval detection.

  In the time interval detection technique of the embodiment, the time interval between the first time and the second time is detected by digital processing, and the first time interval having a coarse time resolution obtained by the first time detection unit is used. The second time interval obtained by the second time detection unit and the fine time resolution is combined with the second time interval.

  The first time detection unit has a counter that is cleared at the first time, counted up by the first clock signal having a predetermined period, stopped at the second time, and outputs m-bit binary data as a count value. An upper bit generator is provided. The second time detection unit is a first clock signal to a first clock signal that are k clock signals whose phases are shifted by (180 degrees / k) based on the first clock signal based on the power of 2 k. a clock phase shifter for generating a k clock signal, a latch circuit for latching each of the first clock signal through the kth clock signal at least at a second time to obtain k 1-bit signals, and a latch circuit. From (k) 1-bit signals, (k-1) -bit binary data that has a smaller value is formed as the time between the time when the first clock signal counts up the counter and the second time is shorter. A low-order bit generator. The synthesizer outputs (m + n) bits of binary data with m bits obtained from the upper bit generator as upper bits and (k-1) bits obtained from the latch circuit as lower bits.

(Principle of distance measurement by wireless)
Prior to the description of the ultra-wideband wireless communication ranging apparatus of the embodiment, the principle of wireless ranging will be briefly described with reference to FIGS. 1 and 2.

  FIG. 1 is a diagram showing the principle of distance measurement by radio. The distance measurement by radio, that is, distance measurement, measures the arrival time Δt (unit: Sec: second), which is the time until the data transmitted from the transmitter TX is received by the receiver RX, and the electromagnetic wave is detected at the arrival time Δt. The distance is measured by multiplying the propagation speed (speed of light). Here, the speed of light is about 300,000 kilometers / second.

  FIG. 2 is a diagram showing three methods of wireless ranging. Ranging methods can be broadly classified as follows: reflection type ranging shown in FIG. 2 (a), one-way type ranging shown in FIG. 2 (b), and bidirectional type ranging shown in FIG. 2 (c). There is. In reflection-type ranging, the time at which data is transmitted from the transmitter TX and the time at which data is received by the receiver RX can be accurately detected by controlling the transmitter TX and the receiver RX with the same clock signal. Further, by sharing the antenna between the transmitter TX and the receiver RX, there is an advantage that it is not necessary to correct the distance due to the difference in the positions of the transmitter TX and the receiver RX. Here, the transmitter TX and the receiver RX are generally configured as a transmitter / receiver. However, it is difficult to measure the distance when the object for measuring the distance (object to be measured) is formed of a material that does not reflect electromagnetic waves.

  One-way distance measurement has an advantage that distance measurement is possible by providing the receiver RX even when the object to be measured is formed of a material that does not reflect electromagnetic waves. However, it is necessary to provide an absolute time generator capable of obtaining the same time in both the transmitter TX and the receiver RX, and the accuracy of the reference time largely dominates the accuracy of distance measurement. Become.

  In bidirectional ranging, a set of transmitter TX and receiver RX (first transmitter / receiver with reference (1)) having the same configuration as shown in FIG. , Another set of transmitter TX and receiver RX (second transmitter / receiver with reference (2)). Data is transmitted from the transmitter TX (first transmitter TX) of the first transmitter / receiver, and the data is received by the receiver RX (second receiver RX) of the second transmitter / receiver. Then, after the data is received by the second receiver RX, the data including the time received by the second receiver RX is transmitted again from the transmitter TX (second transmitter TX) of the second transmitter / receiver. The data is received by the receiver RX (first receiver RX) of the first transceiver. The second transmitter RX receives the data from the time difference between the time when the data is transmitted from the first transmitter TX and the time when the data is received by the first receiver RX. Ranging is performed based on the time obtained by subtracting the time from TX to transmission of data. In this way, distance measurement is possible even when the object whose distance is to be measured (object to be measured) is formed of a material that does not reflect electromagnetic waves.

  In the embodiments described below, the ultra-wideband wireless communication distance measuring device and the distance measurement method using ultra-wideband wireless communication are any of reflection type distance measurement, one-way type distance measurement, and bidirectional distance measurement. Can also be applied.

  Next, the distance resolution in distance measurement will be briefly described. The distance resolution is an index of how finely the distance can be measured in distance measurement. Here, the distance resolution depends on the transfer rate of data transmitted and received. This is because when the data transfer rate is low, the data delimitation cannot be determined at high speed, and as a result, a good distance resolution cannot be obtained.

  The distance measuring apparatus of the background art uses an ultra-wideband wireless communication system as a communication system suitable for increasing the data transfer rate. In addition, the clock frequency is increased in order to accurately measure the data arrival time Δt (see FIG. 1). Here, the distance measurement distance ΔL (unit m: meter) is obtained as expressed by Equation (1).

ΔL = 30 × 10 ⁷ × Δt (1)

  Assuming that the resolution of the arrival time Δt is the time resolution δt and the distance resolution of the ranging distance ΔL is the distance resolution δL, the time resolution δt is directly related to the distance resolution δL, as expressed by Equation (2). Here, the time resolution δt is an index of how short a time can be measured.

δL = 30 × 10 ⁷ × δt (2)

Here, since the arrival time Δt is generally measured using a digital counter, the time resolution δt is immediately reduced in the period that is the reciprocal of the counter clock frequency F _C (unit: Hz). I see, it improves. The relationship between the clock frequency F _C and the distance resolution δL is expressed by Equation (3).

δL = 30 × 10 ⁷ / F _C (3)

From equation (3), for example, when the clock frequency F _C is 100 MHz (megahertz), the distance resolution δL is 3 m. Accordingly, in order to obtain 0.3 m as the distance resolution δL, 1 GHz (gigahertz) is required as the clock frequency F _C.

Here, the technique of the embodiment, which will be described again with respect to the present embodiment, is greatly different from such a conventional technique. In the distance measuring method using the ultra-wideband wireless communication distance measuring device and the ultra-wideband wireless communication of the embodiment, the distance resolution depends not on the clock frequency but on the number of clock signals to be used. In the embodiment, for example, even when the clock frequency F _C is 100 MHz, for example, the same distance resolution as when the clock frequency F _C is 1 GHz can be obtained.

(Outline of ultra-wideband wireless communication rangefinder)
FIG. 3 is a diagram illustrating a block diagram of the ultra-wideband wireless communication distance measuring apparatus according to the embodiment. The ultra-wideband wireless communication ranging device 1 shown in FIG. 3 includes a transmission system and a reception system connected to an antenna 20, and controls the entire device as a control unit (CPU (central processing unit)) 19. Is going on. The ultra-wideband wireless communication distance measuring device 1 may have not only a distance measurement function but also a function of communicating with other ultra-wideband wireless communication distance measuring devices. In the description of the embodiment, only the portion related to the distance measuring function will be described, and the description of the portion related to the communication function will be omitted. The transmission system of the ultra-wideband wireless communication distance measuring device 1 of the embodiment corresponds to the transmitter TX shown in FIGS. 1 and 2, and the reception system of the ultra-wideband wireless communication distance measuring device 1 of the embodiment is shown in FIGS. This corresponds to the receiver RX shown in FIG.

  The transmission system includes a transmission unit 11, a transmission processing block 12, a data conversion unit 13, a buffer 14, and a CPU 19. The CPU 19 is connected to a user interface (user I / F) that is an interface with a user who uses the ultra-wideband wireless communication distance measuring device 1. The CPU 19 sends the original data from the user to the buffer 14 via the user I / F. The buffer 14 sends the original data to the data converter 13 at an appropriate timing. The data conversion unit 13 performs an encoding process for generating baseband data based on a predetermined data format based on the original data from the buffer 14. The transmission processing block 12 performs processing for performing spread spectrum modulation on the baseband data. The transmission unit 11 includes a power amplification unit and a frequency conversion unit, and performs frequency conversion on the spread spectrum modulation signal generated by the transmission processing block 12 to further convert the signal to a higher frequency, for example, 3.3 GHz. A high frequency is sent to the antenna 20.

  The transmission processing block 12 includes a transmission timing generator 121, and the transmission timing generator 121 generates a measurement start trigger signal Tr. In one-way ranging, two absolute time generators that generate an absolute time reference are used as transmission timing generators in order to inform both of the transmission system and the reception system separated from each other at the same time. 121 is used independently in both the transmission system and the reception system. In the reception system, the transmission timing generator 121 provided in the reception unit can detect the transmission time (first time) of the spread spectrum modulation signal generated from the transmission system at the time according to the predetermined agreement. .

  The reception system includes a reception unit 15, a reception processing block 16, a data conversion unit 17, a buffer 18, and a CPU 19. The receiving unit 15 tunes and amplifies the high-frequency signal obtained from the antenna 20, frequency-converts the 3.3 GHz high-frequency signal into a spectrum spread modulation signal in the baseband, and outputs it to the reception processing block 16. The reception processing block 16 performs processing for reproducing baseband data from the spread spectrum modulation signal. The data conversion unit 13 performs a decoding process for obtaining original data from the baseband data. The buffer 14 stores the original data in the buffer 18 and sends it to the CPU 19 at a predetermined timing designated by the CPU 19. The CPU 19 enables the user to use the original data via the user I / F.

  As the above-described original data, various data including measurement data, audio data, and video data from the measurement apparatus can be used.

  FIG. 4 is a diagram illustrating a data format (frame format) of one frame of baseband data processed by the data conversion unit 13 and the data conversion unit 17. The preamble is a pull-in area prior to the frame sync (FLM), and includes a preamble 1 (P1) and a preamble 2 (P2). Each of preamble 1 (P1), preamble 2 (P2), and frame sync (FLM) is composed of 8 bits. The frame sync is a signal for obtaining frame synchronization, has a unique pattern, and can be identified from other areas. That is, the frame sync serves to specify the position of each data in one frame.

  The preamble and frame sync are combined into 24-bit data. Data 1 (D1) and data 2 (D2) are obtained by using block data as original data exchanged via the user I / F. Data 1 (D1) and data 2 (D2) are each composed of predetermined bits. End code (END) is data indicating the end of one frame, and is composed of 8 bits.

  In the transmission system, data 1 (D 1) and data 2 (D 2) are supplied from the buffer 14, and the data converter 13 performs preamble 1 (P 1), preamble 2 (P 2), frame sync (FLM), end code ( END) is added. Then, the baseband data encoded according to the frame format shown in FIG. 4 is sent to the transmission processing block 12. Here, when the data 1 (D1) and the data 2 (D2) constituting the original data input from the user I / F are continuous time series data, the data conversion unit is connected via the CPU 19 and the buffer 18. The data output timing to 13 is adjusted.

  In the reception system, baseband data according to the frame format shown in FIG. 4 is output from the reception processing block 16 to the data converter 17. In the data converter 17, only data 1 (D 1) and data 2 (D 2) are transferred to the buffer 18 except for preamble 1 (P 1), preamble 2 (P 2), frame sync (FLM), and end code (END). Supplied. Here, when data 1 (D1) and data 2 (D2) constituting the original data are continuous time series data, they are output to the user I / F as continuous time series data via the buffer 18 and the CPU 19. Is done. Further, the reception processing block 16 can detect a detection time (second time) of a synchronization point described later.

  FIG. 5 is a diagram showing a relationship (ranging synchronization timing) between the frame format shown in FIG. 4 and distance measurement. 5 is a signal output from the transmission processing block 12 and input to the transmission unit 11. 5 is a signal output from the reception unit 15 and input to the reception processing block 16 in the middle part of FIG. The lower part of FIG. 5 shows the count value of the main counter which is a counter for distance measurement. The horizontal axis in FIG. 5 is time.

  The spread spectrum modulation in the transmission processing block 12 of the embodiment uses direct spreading (DS) that multiplies a PN sequence (pseudorandom sequence). In addition, the spectrum despread modulation in the reception processing block 16 of the embodiment uses the same PN sequence as that used at the time of transmission. Here, since the 1-bit section of the baseband data corresponds to the 7-chip section of the PN sequence, preamble 1 (P1), preamble 2 (P2) and frame sync (FLM) of the baseband data. The continuous 24-bit section is configured to have 168 chips.

  With reference to FIG. 5, the ranging using such a signal having a frame format will be described in more detail.

  The count of the main counter is started from the time (first time) at which the head of preamble 1 (P1) arranged at the head of one frame of the spread spectrum modulation signal generated in the transmission processing block 12 is transmitted. Regardless of reflection type distance measurement, one-way type distance measurement, or two-way type distance measurement, radio waves propagated through the space are received, and the reception processing block 16 uses the end of the frame sync (FLM) as a synchronization point. Detecting and stopping counting up of the main counter at the synchronization point detection time (second time). As an actual problem, since the internal processing time Ot occurs in the reception processing block 16, the main counter stops after the internal processing time Ot has elapsed. In the unidirectional distance measurement, the time at which the main counter starts counting (first time) is an absolute time generator (transmission timing generator) that generates a common absolute time that can be recognized by both the transmission side and the reception side. ) Is arranged in the receiving system and determined by this.

  Here, each time of the data transfer time Dt that is a time corresponding to a continuous 24-bit section of the preamble 1 (P1), the preamble 2 (P2), and the frame sync (FLM) and the internal processing time Ot is known. Yes, this time is stored in the reception system, actually in the CPU 19. The end of the frame sync (FLM) is detected as a synchronization point because the position in one frame can be specified when the detection of the frame sync (FLM) is completed. The time until the signal arrives from the transmission processing block 12 to the reception processing block 16 via radio waves is expressed by the following formula (4). Further, from the arrival time Δt, the distance measurement distance ΔL can be obtained as shown in the mathematical expression (1) already described. Here, the time delay in the transmission unit 11 and the reception unit 15 is a short time and is not considered. However, when the time delay in the transmission unit 11 and the reception unit 15 cannot be ignored, this can be subtracted from the right side of Equation (4) to further improve the distance measurement resolution.

Δt = T−Dt−Ot (4)

  Referring to FIG. 5, as is apparent, when the arrival time Δt is measured and the distance is measured in this way, a transmission signal denoted by reference numeral TX and a reception signal denoted by reference numeral RX are integrally configured. If they are from the same device, the head of preamble 1 (P1) can be easily detected by the measurement start trigger signal Tr (see FIG. 3). Therefore, in reflection-type distance measurement and bidirectional distance measurement, the measurement start trigger signal Tr can be effectively used as a trigger for starting counting (first time).

  FIG. 6 is a diagram showing each of baseband data, a PN sequence, and a spread spectrum modulation signal in the direct spreading method. The PN sequence is a variable length code whose code length changes in units of one chip. Further, it is a variable length constrained code (run length limited code) in which the maximum code length is constrained. For example, the example of the 1-bit section shown in FIG. 6 has information of 7 chips of 1010011. Baseband data is a code whose code length changes in units of 1 bit. Here, the 1-bit section is composed of a plurality of chip sections. As a result, the spread spectrum modulation signal is a variable length constrained code in which the length (inversion length) until 1 and 0 are inverted is changed in units of 1 chip. The spread spectrum modulation signal has information on the number of lines of 0 or the number of lines of 1, that is, the rising edge of the signal and the falling edge of the signal.

  In such a variable length constraint code, the detection accuracy of edge information where a synchronization point exists is directly related to the time resolution. In order to reduce the time resolution δt of the arrival time Δt shown in FIG. 5, it is necessary to accurately detect the synchronization point at the edge position of the spread spectrum modulation signal. If there is an error in the edge position detection time for the time Td (see FIG. 6), the distance resolution δL is directly affected as described above. Here, since the transmission processing block 12 manages the timing itself, the edge position of the spread spectrum modulation signal can be managed accurately. On the other hand, since the edge position of the spread spectrum modulation signal input to the reception processing block 16 changes according to the distance to be measured, the time Td is set to 0 unless counted with an infinitely small clock signal. I can't do it.

  Thus, if the main counter is operated with a clock signal having an infinitely small cycle, that is, an infinitely high frequency clock signal, the time resolution δt = 0 and the distance resolution δL = 0, and the distance measurement distance ΔL is accurate. Will be detected. That is, in order to make the distance resolution δL as small as possible, a clock signal having a frequency as high as possible should be used. However, as described above, it is difficult to realize hardware that operates with a high-frequency clock signal, for example, a 1 GHz clock signal. Hereinafter, how the time resolution is improved will be described in detail.

(Principle of the arrival time measuring circuit of the embodiment)
The principle of the arrival time measuring circuit, which is a main part of the ultra-wideband wireless communication distance measuring device of the embodiment, will be described. This arrival time measuring circuit measures the arrival time Δt. The arrival time Δt can be performed by transmitting at least one frame of the signal having the format shown in FIGS. 4 and 5 from the transmission system and receiving it by the reception system. Here, in the reception system, the synchronization point can be detected by decoding the frame sync. Here, since the formats shown in FIGS. 4 and 5 are one-frame completion formats, it is sufficient to transmit at least one frame of data in order to achieve the object of ranging. The proposition given to the edge detection circuit of the embodiment constitutes a circuit that can detect the position of the edge of the synchronization point of the spread spectrum modulation signal more accurately and obtain a smaller time resolution δt at a lower clock frequency. It is to be. In addition, when transmitting time-series continuous data, a plurality of frames are transmitted continuously. In this case, multipath effects occur, and the object to be measured has a very high transmission rate. Unless there is a situation of movement, synchronization points detected by the reception system are generated at regular time intervals.

  FIG. 7 is a diagram schematically showing a technique for detecting an inversion edge (abbreviated as an edge of a synchronization point) corresponding to a synchronization point in the prior art. A conventional technique for detecting the position of the edge will be briefly described with reference to FIG. Conventionally, the clock signal is counted by the main counter (see FIG. 5) at each rising edge timing, for example, at the rising edge timing until the synchronization point (see FIG. 5) of the received spread spectrum modulation signal is detected. . Only the count value of the main counter is used for distance measurement.

  Here, the head of preamble 1 (P1) and the synchronization point (see FIG. 5) of the spread spectrum modulation signal to be transmitted coincide with the rising edge of the clock signal. Also, the count value of the counter is cleared (set to 0) at the beginning of preamble 1 (P1) of the spread spectrum modulation signal to be transmitted. On the other hand, due to the propagation time delay corresponding to the length of the propagation path of the radio wave, the phase of the synchronization point of the received spread spectrum modulation signal is asynchronous with respect to the rising edge of the clock signal. Here, the phase is asynchronous means that there is no guarantee that the edge of the synchronization point and the edge of the clock signal are detected at the same time. Therefore, according to the conventional edge detection technique, an error occurs in the phase difference between the edge of the synchronization point and the edge of the clock signal, and the time resolution is reduced accordingly.

The resolution in the conventional method will be specifically described with reference to FIG. FIG. 7 shows two different phase signals of the spread spectrum modulation signal S ₁ and the spread spectrum modulation signal S ₂ . A description will be given by comparing either of the spread spectrum modulation signal S ₁ and the spread spectrum modulation signal S ₂ as input from the reception unit 15 to the reception processing block 16. The spread spectrum modulation signal S ₁ and the spread spectrum modulation signal S ₂ are counted at the rising edge of the clock signal φ. The time when the signal with the sign Q is 1 indicates the time of counting up. Further, the edge with a circle is a synchronization point that is the last edge of the frame sync. From the transmission system, the 0th rising edge of the clock signal φ is generated at the time when the head of preamble 1 (P1) of the spread spectrum modulation signal is transmitted, and the edge of the synchronization point and the edge of the clock signal are A synchronized signal is transmitted.

For the spread spectrum modulation signal S ₁ shown for comparison in FIG. 7, the synchronization point comes immediately after the jth rising edge of the clock signal φ (abbreviated as jth clock, the same applies hereinafter). Therefore, the j-th clock cannot detect this synchronization point, and the (j + 1) -th clock detects edge inversion and stops counting. The counter holds a value (j + 1).

On the other hand, the spread spectrum modulation signal S ₂ is synchronization point of the spread spectrum modulated signal S ₂ is (j + 1) -th so immediately precedes the clock, at j + 1 th clock, a count stop by detecting the synchronization point To do. The counter holds a value (j + 1).

In this way, the count value of the main counter for the spread spectrum modulation signal S ₁ indicates (j + 1), and the count value of the main counter for the spread spectrum modulation signal S ₂ also indicates (j + 1). Thus, even if the arrival time of both has a time difference T _C , the count value of the main counter is the same value as (j + 1). That is, according to the conventional method, the time, the processing on the cut at T _C units are made, than the actual time, time T as long (see Figure 5) is to be detected. As a result, the time resolution δt is expressed by Equation (5).

δt = T _C (5)

Here, the time resolution .DELTA.t = T _C, is intended to refer to become to be the maximum value of the time error caused by the count time error maximum value delta] max = T _C.

FIG. 8 is a time chart illustrating the principle of the edge detection (including synchronization point detection) method of the embodiment. FIG. 8 shows clock signals φ ₀ to φ ₃ , which are four clock signals different from 45 °, 90 °, and 135 °, where the clock signal φ ₀ is 0 ° (degrees). . Here, the length of 1 period and the length of 0 period of each clock signal are the same. Any one of the spread spectrum modulation signal S ₃ to the spread spectrum modulation signal S ₁₀ is compared as being input from the reception unit 15 to the reception processing block 16. As a synchronization point of rising edges by arrows is received, will be described by dividing the period T _C of the clock signal into eight regions, labeled 0-7.

Table 1 shows a post-latching signal Q ₀ to a post-latching signal Q ₃ . As shown in FIG. 8, the latched signal Q ₀ to the latched signal Q ₃ are obtained by latching the clock signal φ ₀ to the clock signal φ ₃ at the synchronization point of the spread spectrum modulation signal. In Table 1, the latched signal Q ₀ when the clock signal φ ₀ to the clock signal φ ₃ are latched at the respective synchronization points of the spread spectrum modulation signal S ₃ to the spread spectrum modulation signal S _10. polar each of ~ the latch after the signal Q ₃ of 1,0 is described. Here, 1 is a state where each of the clock signals φ ₀ to φ _{3 is at} the high level shown in FIG. 8, and 0 is a state where each of the clock signals φ ₀ to φ ₃ is at the low level shown in FIG. Corresponding to

Referring to Table 1, it can be understood that the time resolution of the synchronization point detection of the spread spectrum modulation signal can be improved in the embodiment. In other words, in the embodiment, the phase difference between the edge of the synchronization point and the edge of the clock signal is also measured, and the resolution is improved. For example. Latch the latch after the signal Q ₀ which is detected by latching the clock signal phi ₀ is 1, the latch after the signal Q ₁ that is detected by latching the clock signal phi ₁ is 0, it is detected by latching the clock signal phi ₂ When the post-signal Q ₂ is 0 and the post-latch signal Q ₀ detected by latching the clock signal φ ₃ is 0, it is a spread spectrum modulation signal S ₃ having a synchronization point at the edge with an arrow. It is detected. Then, referring to Table 1, depending on whether each state of the latched signal Q ₀ to the latched signal Q ₃ is 1 or 0, the other spread spectrum modulation signal S ₄ to spread spectrum modulation signal S for _ten, it is understood that the clock signal can be performed is less time resolution has been synchronization point detection than for one.

Here, the number of states that the post-latch signal Q ₀ to the post-latch signal Q ₃ can take will be described. In principle, the number of states that can be taken is 2 ^k = 2 ⁴ = 16 since the number of clock signals k = 4. However, each clock signal has a period T _C and is constrained to reverse its polarity at time T _C / 2, so that there are four consecutive times for a discrete time every clock signal period T _C / 4. Having 1 or 4 consecutive 0s is a weighting condition. Therefore, the number of states that can be taken, that is, the number that can divide one cycle T _C is expressed by Expression (6). The time resolution δt is expressed by Equation (7).

Number of possible states = 2 × 4 (6)

δt = T _C / (2 × 4) (7)

Here, the time resolution δt = T _C / (2 × 4) means that the time error maximum value δmax = T _C / (2 × 4), which is the maximum time error detected by the phase difference. Is what you say. The relationship between the number of clock signals and the time resolution will be described below using general formulas. The number of clock signals whose phases are sequentially shifted by 180 / k (degrees) at equal intervals is an integer k, and k continuous 1s or 0s are obtained for a discrete time every cycle T _C / k. When weighting conditions are taken into consideration, the relationship between the integer k and the integer n is expressed by Equation (8). If Equation (8) is solved for n, Equation (9) can be obtained. Further, when Equation (8) is solved for k, Equation (10) can be obtained. The time resolution at this time is represented by time resolution T _C / (2 ⁿ ).

2 ⁿ = 2 × k (8)

n = Log (2 × k) / Log (2) (9)

k = 2 ^n-1 (10)

  Therefore, when the number of clock signals k = 4, the number that can divide one cycle is 2 × k = 8, and n = 3, that is, a number that can be represented by 3 bits. Regarding the number of other clock signals, for example, when the number of clock signals k = 2, the number that can divide one cycle is 2 × k = 4, and n = 2, that is, a number that can be expressed by 2 bits. When the number of clock signals k = 8, the number that can divide one cycle is 2 × k = 16, and n = 4, that is, a number that can be represented by 4 bits. Here, of course, the above equation can also be applied when the number of clock signals k = 5. When the number of clock signals k = 5, the number that can divide one cycle is 2 × k = 10, and the time resolution can be improved by 10 times compared to the case where the number of clock signals is one. However, in this case, since 10 cannot be expressed by a power of 2, it is not suitable for digital processing, and is suitable for use in distance measurement processing using an addition operation of higher bits and lower bits, which will be described later. is not.

  That is, in Equation (8), it is desirable to select the number k of clock signals so that the number of n is an integer, k = 2, 4, 8, 16, 32. A number that is a power is desirable.

(Block diagram of the arrival time measuring circuit of the embodiment)
FIG. 9 is a block diagram centering on an arrival time measuring circuit functioning as arrival time measuring means in the reception processing block 16 (see FIG. 3). A block diagram centering on the arrival time measuring circuit of the embodiment will be described with reference to FIG. The reception processing block 16 includes a portion related to data decoding (decoding), but description of this portion is omitted.

The arrival time measurement circuit of the reception processing block 16 includes a correlator 161, a sub-counter 162, a main counter 163, a clock phase shifter 164, a data synchronizer 165, and a combiner 168 as main components. The correlator 161, the main counter 163, the clock phase shifter 164, and the data synchronizer 165 perform a synchronization process that operates in synchronization with a clock signal having a period _TC as a constant period. On the other hand, the sub-counter 162 operates in synchronization with the spread spectrum modulation signal S and performs asynchronous processing that operates asynchronously with the clock signal. The frequency of the clock signal for the synchronization processing is, for example, 100 MHz. The configuration of the synthesizer 168 will be described later.

The spread spectrum modulation signal S is input to the sub-counter 162 and the correlator 161. The correlator 161 generates the same PN sequence used for transmission and reproduces baseband data from the spread spectrum modulation signal S. Data synchronizer 165 for frame synchronization from the frame sync (FLM), detecting the synchronization point signal D _S generated in synchronization point. Synchronization point signal D _S, as described above, with use in ranging, used as a position reference for baseband data (time reference). For example, it is used for position detection of data 1 (D1) and data 2 (D2). Then, data 1 (D1) and data 2 (D2), which are data areas, are extracted from the baseband signal that has passed through the data synchronizer 165, and internal processing, that is, data decoding processing is performed. Yes.

The main counter 163 performs a counting operation in synchronization with the clock signal. The operation of the main counter is the same as the operation of the conventional main counter described with reference to FIG. The main counter 163 is outputted from the transmit timing generator 121 (see FIG. 3), when the measurement start trigger signal Tr is inputted by counting the start (first time), a synchronization point signal D _S is input However, as described above, the actual count stop time (second time) is delayed by a time T _{C at the} maximum. The time obtained by multiplying the count result by the period of the clock signal is time T (see FIG. 5). Here, the time resolution value of the time T measured by the main counter 163 becomes the time resolution T _C as expressed by the equation (5).

From the time T detected by the main counter 163, it is possible to obtain a rough amount of the arrival time Δt (rounded-up amount in units of time resolution T _C ) based on the equation (4). Here, the internal processing time Ot (see FIG. 5) is a time necessary for the data synchronizer 165 to detect a frame sync. The data transfer time Dt (see FIG. 5) is the time from the beginning of preamble 1 (P1) to the end of frame sync (FLM).

The sub-counter 162 is for measuring a time shorter than the clock signal period T _C based on the principle shown in FIG. 8 and obtaining a fine amount of the arrival time Δt (amount discarded by rounding up).

The sub-counter 162 performs an operation of latching a plurality of clock signals having different phases from the clock phase shifter 164 at the edge timing of the spread spectrum modulation signal S (inversion timing of the spread spectrum modulation signal S). Then, based on the latched levels of the plurality of clock signals, a time shorter than the cycle T _C is measured. The sub-counter 162 detects a time t shorter than the time T that cannot be detected by the main counter 163, and improves the time resolution to a time resolution T _C / (2 × k) that can be expressed by Equation (7).

That is, by using the time T measured by the main counter 163 and the time t measured by the sub-counter 162, the arrival time Δt is obtained by the following formula (11), and the time resolution T _C / (2 × k) It becomes possible to measure the distance. Here, the reason why the calculation of (T−T _C ) + t is performed is to improve the time resolution by correcting the round-up process in the process in the main counter 163. This calculation is performed by the CPU 19. Note that a time T _{C of} an error caused by rounding up may be included in advance in the time Ot. From Expression (11), Expression (12) for obtaining the distance measurement distance ΔL can be further obtained.

Δt = (T−T _C ) + t−Dt−Ot (11)

ΔL = 30 × 10 ⁷ × {(T−T _C ) + t−Dt−Ot} (12)

(Example)
FIG. 10 is a diagram illustrating a main part of the embodiment by a specific example.

The upper m bits of the arrival time Δt are obtained from the main counter 163 that functions as an upper bit generator. The main counter 163 is reset every time the measurement start trigger signal Tr is input, and every time a synchronization point (see FIG. 5) is detected, the synthesizer 168 receives m bits corresponding to time T (see FIG. 5). The count value represented by binary data is taken in. The timing for taking the binary data of m bits to the combiner 168 is controlled by a synchronization point signal D _S is the output signal of the NOR (NOR) gate 165b.

A predetermined unique pattern is stored in the frame sync pattern generator 165a. And unique pattern, when the pattern matches the baseband data time series, NOR gate 165b generates a synchronization point signal D _S. The same number of 1-bit shift registers 171 ₁ to 171 _{n as the} number of bits forming the frame sync are connected in series, and the bit shift operation is performed by the clock signal φ ₀ . Exclusive OR (EXOR) detects a match for each bit between the baseband data and the frame sync.

The sub-counter 162 has four de-flip flops (DFF), that is, flip-flops 162a to 162d. To Di input terminal of the flip-flop 162a (input terminal D) (see Figure 8) clock signal phi ₀ is input, (see Figure 8) clock signal phi ₁ to the D input terminal of the flip-flop 162b is input The clock signal φ ₂ (see FIG. 8) is input to the D input terminal of the flip-flop 162c, and the clock signal φ ₃ (see FIG. 8) is input to the D input terminal of the flip-flop 162d. A timing signal for notifying the time when the polarity of the spread spectrum modulation signal S obtained from the edge detector 174 is inverted (the time when the inverted edge occurs) is input to the clock terminals (CK terminals) of all flip-flops. . Note that the spread spectrum modulation signal S is directly input to the CK terminals of the flip-flops 162a to 162d, and only one of the rising edge and the falling edge is used as a trigger, and the clock signal A state of 1 or 0 of φ ₀ to clock signal φ ₃ may be latched. In this case, the edge detector 174 is not required.

  The low-order bit generator 166 receives 1 or 0 output from each of the output terminal (Q terminal) of the flip-flop 162a to the output terminal (Q terminal) of the flip-flop 162d as 4-bit data. Entered. The lower bit generator 166 outputs 3-bit binary data. Generally speaking, the low-order bit generator 166 receives k input signals from a number of de-flip flops equal to the number k of clock signals, and outputs n-bit binary data given by Equation (9). Is done.

Table 2 shows k data output from each of the output terminal (Q terminal) of the flip-flop 162a to the output terminal (Q terminal) of the flip-flop 162d (in this case, four data Q ₀ to data Q ₃ ). Is a table in which binary data of n bits (3 bits in this case) is associated. The column on the left side of Table 2 indicates the time corresponding to each of the n-bit data, and in order from the top, 0, (T _C / 2 ⁿ ), 2 × (T _C / 2 ⁿ ), ˜7 × (T _C / ²ⁿ ). The table shown in Table 1 is provided in the lower bit generator 166.

  The combiner 168 combines the upper m bits of binary data from the main counter 163 and the lower n bits of binary data from the lower bits generator 166 and outputs m + n bits of data to the CPU 19. At this time, the value of the m-bit binary data from the main counter 163 has an error of 1 LSB (1 LSB: Least Significant Bit) at the maximum due to rounding up as described above. The lower n bits from the lower bit generator 166 corresponding to this error are concatenated and output from the combiner 168.

  The operation of adding the m bits of the main counter 163 and the n bits of the lower bit generator 166 may be performed by the CPU 19 without being performed by the synthesizer 168. Further, as described above, the value of m-bit binary data is increased by 1 LSB by rounding up, but this correction may be performed at any stage. For example, the main counter 163 may ignore the first clock signal and substantially set −1 as the count initial value, may be corrected by a combiner 168 described later, As described above, the CPU 19 may perform correction.

  The lower n bits are signals to be detected at the timing of the inversion edge of the spread spectrum modulation signal S, but only the synchronization point edge may be used. As shown in FIG. Including all the inverted edges may be used. On the other hand, the upper m bits are signals for detecting baseband data in synchronization with the clock, and there is also a delay caused by a shift register for detecting frame sync. The point at which the spread spectrum modulation signal S, which is time series data, is sampled differs between the detection of the upper bits and the detection of the lower bits, and there is a shift in the detection position of the inverted edge on both formats. Yes.

However, the spread spectrum modulation signal transmitted from the transmission system is synchronized with the clock signal, and the same clock signal is involved in the reception system to detect the synchronization point. That is, both the transmission process and the reception process are performed based on the reference signal from the same crystal oscillator. Here, the oscillation accuracy of the crystal oscillator is as high as ± 50 ppm to ± 100 ppm (1 ppm = 1 × 10 ⁻⁶ ), and the detection time difference between the two (the upper bit detection time and the lower bit detection time) is a distance measurement. Has little effect on the distance resolution. Therefore, it is understood that the edge detection method of the embodiment has sufficient accuracy.

  In particular, in the reflection type distance measurement (see FIG. 2A), since the transmission processing and the reception processing are not involved except for the same clock signal, the influence of the oscillation accuracy of the crystal oscillator on the distance resolution is Furthermore, there are few. In addition, even when the distance between the DUT and the ultra-wideband wireless communication distance measuring device changes, if the distance changes according to time with a speed approximately equal to the normal vehicle speed, The difference in detection time has little effect on the distance resolution of ranging. Therefore, it is understood that the edge detection method of the embodiment has sufficient accuracy in the reflection type distance measurement.

  Although not described in detail, in the bidirectional distance measurement shown in FIG. 2C, even when different crystal oscillators are used on the transmission side and the reception side, the frequency error between the two crystal oscillators is When it falls within the range of ± 50 ppm to ± 100 ppm, there is almost no influence on the distance resolution of distance measurement. In the one-way distance measurement shown in FIG. 2B, if the deviation of the absolute time used in both the transmitter TX and the receiver RX can be ignored, a clock signal calibrated based on the absolute time is transmitted. By using both the machine TX and the receiver RX, there is almost no influence on the distance resolution of ranging. Therefore, it is understood that the edge detection method of the embodiment has sufficient accuracy even in the bidirectional distance measurement and the unidirectional distance measurement.

  The CPU 19 performs the following calculation based on the formula (12) to obtain the distance measurement distance ΔL. As described above, the count value (m + n) is a value after correcting the LSB of the upper bits and concatenating the upper m bits and the lower n bits.

^{ΔL = 30 × 10 7 × [} { count value ^{(m + n) / 2 n} } × T C -Dt-Ot] (13)

  The hardware configuration shown in FIG. 10 described above can be realized by, for example, an FPGA (Field Programmable Gate Array). In this case, for example, when the clock signal has a frequency of 100 MHz and four clock signals having different phases are used, this is equivalent to using an 800 MHz clock signal. The distance resolution obtained when the frequency of the clock signal is 100 MHz is 3 m, but the distance resolution is improved to 0.375 m by using clock signals having four different phases. Although a delay element is used to generate clock signals having different phases, a PLL (Phase Locked Loop) in the FPGA may be used, or a gate circuit in which a propagation delay amount is managed may be used. .

  In short, the ultra-wideband wireless communication distance measuring device of the embodiment has the following features.

  A receiver that receives a spread spectrum modulation signal that is transmitted to space and propagates through a measured object, and a first time that is the time at which the spread spectrum modulation signal is transmitted to space (for example, the first transmission time of the preamble) ), A synchronization point detector (for example, a data synchronizer) that obtains a second time (for example, frame sync end time) from the synchronization point of the spread spectrum modulation signal obtained from the receiver, and a first Time interval detection means for detecting the time interval between the time and the second time by digital processing, and an arrival time detection unit (for example, CPU) for determining the arrival time of the radio wave from the measured object to the reception unit based on the time interval And calculating means (for example, CPU) for calculating the distance between the object to be measured and the receiving unit by integrating the speed of light with the arrival time.

  The time interval detection means includes a first time obtained by the first time detector (for example, the upper bit generator), the second time detector (for example, the lower bit generator), and the first time detector. A combining unit (for example, a combiner) that combines the interval and the second time interval obtained by the second time detection unit. The first time detection unit has a counter that is cleared at the first time, counted up by the first clock signal having a predetermined period, stopped at the second time, and outputs m-bit binary data as a count value. An upper bit generator is provided. Here, the predetermined cycle which is the cycle of the first clock signal is, for example, the cycle of the system clock which is a repetitive signal having the shortest cycle, which is a reference for operating the apparatus.

  The second time detection unit is a first clock signal to a k-th clock signal that are k clock signals whose phases are shifted by (180 degrees / k) based on one clock signal based on the power of 2 k. A clock phase shifter for generating a clock signal, a latch circuit (for example, a sub-counter) for latching each of the first clock signal to the k-th clock signal at least at a second time and obtaining k 1-bit signals, From the k 1-bit signals obtained by the latch circuit, the shorter the time between the time when the first clock signal counts up the counter and the second time, the smaller the value becomes (k−1) -bit binary. And a lower bit generator for forming data.

  A synthesizer (for example, a synthesizer) outputs binary data of (m + n) bits, with m bits obtained from the upper bit generator as upper bits and (k−1) bits obtained from the latch circuit as lower bits. Is.

In the sub-counter 162 according to the embodiment described above, the inversion edge of the synchronization point of the spread spectrum modulation signal S is used as a trigger, and the state of 1 or 0 of the clock signal φ ₀ to the clock signal φ ₃ is latched at the trigger time. I made it. However, the sub-counter that generates low-order n-bit binary data detects the relative relationship between the inversion edge of the synchronization point of the spread spectrum modulation signal S and the edge of the clock signal. More specifically, the phase amount in one cycle of the clock signal is detected. However, as long as it can detect this relative relationship, it can function as a sub-counter and is not limited to the above-described embodiment.

FIG. 11 is a diagram illustrating another example of the sub-counter that is a main part of the embodiment. The sub-counter 262 has eight de-flip flops (DFF). Clock signals φ ₀ to φ ₇ are input to the clock terminals of the eight de-flip flops. The clock signals φ ₀ to φ ₇ are clocks generated by the clock phase shifter 264 and having phases different from each other by 45 degrees. A spread spectrum modulation signal S is applied to the de input terminal of each of the eight de-flip flops. Output signals Q ₀ to Q ₇ are output from the output terminals of the eight de-flip flops. The lower bit generator 266 generates 3-bit binary data from 8-bit signals of the output signal Q ₀ to the output signal Q ₇ .

FIG. 12 is a time chart showing the operation of the sub-counter 262. FIG. 12 corresponds to FIG. 8 and is a diagram showing a concept in the case of detecting each of the spread spectrum modulation signal S ₃ to the spread spectrum modulation signal S ₁₀ .

Table 3 is a table in which n-bit (3 bits in this case) binary data is associated with eight data Q ₀ to data Q ₇ output from each output terminal (Q terminal) of the flip-flop. . The columns S _{3 to} S ₁₀ on the left side of Table 3 mean each of the spread spectrum modulation signal S ₃ to the spread spectrum modulation signal S ₁₀ shown in FIG.

  By using Table 3 as a table in the lower bit generator 266, an 8-bit signal can be converted into 3-bit binary data. That is, the same resolution can be obtained by replacing the clock phase shifter 164 and the sub-counter 162 in the circuit shown in FIG. 10 with the clock phase shifter 264 and the sub-counter 262 shown in FIG. Compared with the circuit shown in FIG. 8, the number of clock signals is doubled, but half the clock signals can be generated by the inverter circuit.

(Modification of the embodiment)
A modification of the embodiment will be described with reference to FIGS. 13, 14, 4, and 5.

  When a signal out of the clock cycle is generated due to communication failure (noise, multipath, etc.), malfunction may occur in the sub-counter 162 (see FIG. 9) that performs asynchronous processing. The modification of the embodiment prevents such a malfunction.

  FIG. 13 is a diagram schematically showing a case where the spread spectrum modulation signal S includes noise.

Table 3 shows the positions of the rising and falling edges in the vicinity of the noise edges (pth edge and (p + 1) th edge) of the spread spectrum modulation signal S shown in FIG. is a table showing the output terminal (see FIG. 10), the relationship between the output signal Q ₀ ~ output signal Q _3.

As shown in Table 4, the values of the output signal Q ₀ to the output signal Q ₃ corresponding to the original edge are 1000. On the other hand, the values of the output signals Q ₀ to Q ₃ corresponding to the p-th latched by noise are 0111. Further, the value of the output signal Q ₀ to output signal Q ₃ corresponding to the (p + 1) th latched by noise is 0011.

Table 5 includes the edges of noise detected from the spread spectrum modulation signal S including the range not shown in FIG. 13, the positions of rising edges and falling edges in the vicinity thereof, and four flip-flops (see FIG. 10) is a table showing the relationship between the output signal Q ₀ to the output signal Q ₃ from the output terminal. Further, the majority of the output signals Q ₀ to Q ₃ at the current edge position and the output signals Q ₀ to Q ₃ at the positions of the four previous edges are majority. The output signal Q ₀ to the output signal Q ₃ at the positions of

As can be seen from Table 5, in this way, noise can be eliminated based on the output signals Q ₀ to Q ₃ at the positions of a plurality of previous edges. The algorithm for eliminating noise is not only the majority processing (occurrence frequency processing) of a plurality of edges before the edge for which it is determined whether or not it is noise, but also the majority of edges that are behind the edge. It can be the target of processing.

In addition to the majority process, a plurality of time-series output signals Q ₀ are added, divided by the added number to obtain an average value, and rounded off to determine whether it becomes 0 or 1 Similarly, the other output signals Q ₁ to Q ₃ may be similarly rounded off after obtaining an average value to remove noise. Such average value processing can also be employed. Then, based on the results of majority processing and average value processing, the edge data different from other parts caused by noise, multipath, etc. is replaced with the data of other parts, resulting in a ranging error for the lower bits. I can not.

Specifically, the sub-counter 362 to the synthesizer 168 shown in FIG 10 is connected, in synchronism with the sync point signal D _S, calculation result of the sub-counter 362 is taken to the synthesizer 168. Here, in the case without the noise remover 366c is, when the synchronization point signal D _S is output, the spread spectrum modulation signal S at the time of the edge P shown in Table 5 and was taken into the latch circuit 366a Therefore, information based on an erroneous phase difference is taken into the synthesizer 168. However, in the case of including the noise remover 366c, whether or not it is noise is detected for each edge of the spread spectrum modulation signal S, so that the phase difference signal detected by the noise is eliminated, n-bit information does not cause errors due to noise.

FIG. 14 is a block diagram of a sub-counter 362 that is a sub-counter having the above-described majority processing and average value processing functions. The latch circuit 366a has a de-flip flop circuit as shown in FIG. A plurality of signals (for example, Q _{1 to} Q ₃ ) equal to the number of clocks from the latch circuit 366a are sequentially stored in the memory 366b (for example, a 4-bit ring shift register) at each latch time. For example, when the signal at the storage position indicated by p is the signal to be processed, the previous signal (the signal at the position indicated by (p-4) to the signal at the position indicated by (p-1)), or Signals at positions indicated by subsequent signals (p + 1) to signals at positions indicated by (p + 4)), or signals before and after that can be used for the purpose of noise removal.

The noise remover 366c removes noise by the above-described majority process or average value process. The low-order bit generator 366d forms n-bit data using the conversion table for the signal after noise removal. Note that the processing performed by the noise remover 366c is not only performed at the stage of processing a plurality of signals (for example, Q _{1 to} Q ₃ ), but may be performed after conversion to n-bit data. For example, after taking (m + n) -bit binary data into the CPU 19, noise may be removed by arithmetic processing in the CPU 19.

(Another modification of the embodiment)
Another modification will be described with reference to FIGS. 15 and 16. In the circuit shown in FIG. 10, the same clock signal φ ₀ is input to the main counter 163 and the sub-counter 162a. Therefore, when the edge of the spread spectrum modulation signal S and the edge of the clock signal φ ₀ coincide with the clock terminal CK of the flip-flop of the subcounter 162, 0000 (111 in binary) is latched by the subcounter 162. At the same time, the main counter 163 is counted up, which may cause erroneous measurement.

FIG. 15 is a diagram showing a circuit for operating the main counter 163 with a clock signal different from the clock signal from the clock phase shifter 164. As shown in FIG. 15, by using the delay elements Dd, clock signals phi ₀ of the main counter 163 'is such delayed with respect to the clock signal phi _0. In this way, the main counter 163 is incremented when 0000 is generated in the sub-counter 162, and erroneous time measurement is not performed. FIG. 16 is a time chart showing the relationship between the spread spectrum modulation signal S, the clock signal φ ₀ ′, and the clock signal φ ₀ to clock signal φ ₃ in the circuit shown in FIG.

  Of course, it is possible to combine the above-described embodiment and examples to make a new embodiment, and the present invention is not limited to the above-described embodiment.

DESCRIPTION OF SYMBOLS 1 Ultra-wideband wireless communication ranging device, 11 Transmitter, 12 Transmission processing block, 13 Data conversion unit, 14 Buffer, 15 Reception unit, 16 Reception processing block, 17 Data conversion unit, 18 Buffer, 20 Antenna, 121 Transmission timing generation , 161 correlator, 162 sub-counter, 162a to 162d de-flip flop (DFF), 163 main counter, 164 clock phase shifter, 165 data synchronizer, 165a frame sync pattern generator, 165b NOR gate, 166 lower bit generator, 168 synthesizer, 171 ₁ ~171 _n shift register, 174 an edge detector, 262 sub-counter, 264 a clock phase shifter 266 lower bit generator, 362 sub-counter, 366a latch circuit, 366b memory, 3 6c noise remover, 366d lower bit generator, D1, D2 data, D _S synchronization point signal, Dt data transfer time, END end code, FLM frame sync, Ot internal processing time, P1, P2 preamble, Q ₀ to Q ₇ latch after the signal (output signal, data), RX receiver, S spread spectrum modulation signal, S ₁ to S ₁₀ spread spectrum modulation signal, TX transmitter, Tr measurement start trigger signal, [Delta] L measured distance, Delta] t arrival time, [delta] L Distance resolution, δt time resolution, φ clock signal, φ _{0 to} φ ₇ clock signal

Claims (7)

A receiving unit that receives a spread spectrum modulation signal that is transmitted to space and propagates through an object to be measured;
A transmission timing generator for obtaining a first time which is a time at which the spread spectrum modulation signal is transmitted to space;
A synchronization point detector for obtaining a second time from the synchronization point of the spread spectrum modulation signal obtained from the receiver;
Time interval detection means for detecting a time interval between the first time and the second time by digital processing;
An arrival time detection unit for obtaining an arrival time of radio waves from the object to be measured to the reception unit based on the time interval;
Calculating means for calculating the distance between the object to be measured and the receiving unit by integrating the speed of light with the arrival time;
The time interval detection means includes a first time detection unit, a second time detection unit, a first time interval obtained by the first time detection unit, and a second time interval obtained by the second time detection unit. And a synthesis unit that synthesizes
The first time detector is
An upper bit having a counter that is cleared at the first time, counted up with a first clock signal of a predetermined period, and stopped at the second time and outputs m-bit binary data as a count value Having a generator,
The second time detector is
Based on the power of 2 k, the first clock signal through the kth clock signal, which are k clock signals shifted in phase by (180 degrees / k) with respect to the first clock signal, are generated. A clock phaser,
A latch circuit that latches each of the first clock signal to the k-th clock signal at least at the second time to obtain k 1-bit signals;
From the k 1-bit signals obtained by the latch circuit, the smaller the time between the time when the first clock signal counts up the counter and the second time, the smaller the value (k− 1) a low-order bit generator that forms binary data of bits,
The synthesis unit is
(M + n) bits of binary data are output with the m bits obtained from the upper bit generator as upper bits, the (k-1) bits obtained from the latch circuit as lower bits,
Ultra-wideband wireless communication ranging device. The spread spectrum modulation signal is formed of a variable length code,
The latch circuit of the second time detector is
Obtaining the k 1-bit signals at the occurrence of an inversion edge of the spread spectrum modulation signal to be the variable length code;
The ultra-wideband wireless communication ranging apparatus according to claim 1. The spread spectrum modulation signal is formed of a variable length code,
The second time detection unit has a memory,
The k 1-bit signals obtained at the time when the edge of the variable length code is inverted are sequentially stored in the memory according to a time series,
Selecting k 1-bit signals having a high occurrence frequency from a plurality of sets of the k 1-bit signals stored in the memory, and outputting the selected signals to the lower bit generator;
The ultra-wideband radio communication ranging apparatus according to claim 1 or 2. The spread spectrum modulation signal is formed of a variable length code,
The second time detection unit has a memory,
The k 1-bit signals obtained at the time when the edge of the variable length code is inverted are sequentially stored in the memory according to a time series,
A plurality of sets of the k 1-bit signals stored in the memory are averaged for each bit, and k 1-bit signals obtained by rounding are selected, and the lower bit generator is selected. Output,
The ultra-wideband radio communication ranging apparatus according to claim 1 or 2. further,
Comprising a transmitter for transmitting a spread spectrum modulation signal;
Obtaining the first time from the transmitter;
The ultra-wideband wireless communication ranging apparatus according to claim 1. A receiving unit receives a spread spectrum modulation signal that is transmitted to space and propagates through an object to be measured, and obtains a first time that is a time at which the spread spectrum modulation signal is transmitted to space;
The synchronization point detector obtains the second time from the synchronization point of the spread spectrum modulation signal obtained from the receiving unit,
The counter of the first time detection unit is
Cleared at the first time, counted up with a first clock signal of a predetermined period, stopped at the second time, and output m-bit binary data as a count value,
The second time detection unit
Based on the power of 2 k, the first clock signal through the kth clock signal are generated which are k clock signals whose phases are shifted by (180 degrees / k) with respect to the first clock signal. Each of the first clock signal to the kth clock signal is latched at least at the second time to obtain k 1-bit signals, and k 1-bit signals obtained by the latch circuit are obtained. From this, the shorter the time between the time at which the first clock signal counts up the counter and the second time, the smaller the (k−1) -bit binary data is formed,
The synthesis unit
The m bits are upper bits, the (k-1) bits are lower bits, and (m + n) bit binary data is output,
An arithmetic means calculates a distance between the measured object and the receiving unit based on the binary data of (m + n) bits.
Ranging method. A time interval detection device for detecting a time interval between a first time and a second time by digital processing,
The time interval detection apparatus includes a first time detection unit, a second time detection unit, a first time interval obtained by the first time detection unit, and a second time interval obtained by the second time detection unit. And a synthesis unit that synthesizes
The first time detector is
An upper bit generator having a counter that is cleared at the first time, counted up with a first clock signal having a predetermined period, and stopped at the second time and outputs m-bit binary data as a count value. Equipped,
The second time detector is
Based on the power of 2 k, the first clock signal through the kth clock signal, which are k clock signals shifted in phase by (180 degrees / k) with respect to the first clock signal, are generated. A clock phaser,
A latch circuit that latches each of the first clock signal to the k-th clock signal at least at the second time to obtain k 1-bit signals;
From the k 1-bit signals obtained by the latch circuit, the smaller the time between the time when the first clock signal counts up the counter and the second time, the smaller the value (k−1). A lower bit generator that forms binary data of bits;
The synthesis unit is
(M + n) bits of binary data are output with the m bits obtained from the upper bit generator as upper bits, the (k-1) bits obtained from the latch circuit as lower bits,
Time interval detection device.

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