JP2011211120A - Solid-state imaging element, and imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging element capable of preventing image quality deterioration when an object has high luminance.SOLUTION: An output part 55 includes: a floating diffusion FD adjoiningly provided on a downstream side in the charge transfer direction of a transfer path 1; a source follower amplifier SFA outputting a signal according to a charge accumulated in the FD; and a transfer gate region 7 provided between the FD and the transfer path 1. In the transfer path 1, a width in the column direction Y narrows towards in the charge transfer direction at an end thereof. A drain region 5 is formed on a side of the transfer path 1. In at least a final transfer stage 4 disposed at a part where the width of the transfer path 1 narrows, a barrier region 6 forming a potential barrier between the drain region 5 and the transfer path 1 is formed in contact with the final transfer stage. A height of the potential barrier formed in the barrier region 6 relative to the final transfer stage 4 is lower than a height of a potential barrier formed in the transfer gate region 7 relative to the final transfer stage 4.

Description

  The present invention relates to a solid-state imaging device and an imaging apparatus.

  FIG. 10 is an enlarged view of the vicinity of an output portion of a conventional CCD (Charge Coupled Device) type solid-state imaging device.

  A horizontal charge transfer path 101 and a floating diffusion FD are formed in the semiconductor substrate. In the horizontal charge transfer path 101, the width in the direction orthogonal to the charge transfer direction becomes narrower toward the charge transfer direction at the end (termination) on the downstream side in the charge transfer direction. The floating diffusion FD is provided next to the end of the horizontal charge transfer path 101 whose width is narrowed.

  Above the horizontal charge transfer path 101, a plurality of transfer electrodes 105, each paired with the sub electrode 102 and the sub electrode 103, are arranged along the charge transfer direction.

  An output gate electrode OG is provided above the semiconductor substrate between the floating diffusion FD and the horizontal charge transfer path 101.

  In FIG. 10, among the plurality of transfer electrodes 105, the region of the horizontal charge transfer path 101 that overlaps with the transfer electrode 105 located on the most downstream side in the charge transfer direction of the horizontal charge transfer path 101 is the final transfer stage 104. The final transfer stage 104 is formed in a portion where the width of the horizontal charge transfer path 101 is narrowed.

  FIG. 11 is a diagram showing the potential in the semiconductor substrate in the cross section along line B-B ′ shown in FIG. 10. FIG. 11 shows a state where electrons are accumulated in the final transfer stage 104.

  Electrons transferred from a vertical charge transfer path (not shown) to the horizontal charge transfer path 101 are transferred to the final transfer stage 104. Since the final transfer stage 104 is narrow in width, when the amount of transferred electrons increases due to strong light, some of the electrons are transferred to the floating diffusion FD as shown by the arrows in FIG. Leak. As a result, after the floating diffusion FD is reset, before the electrons in the final transfer stage 104 are transferred to the floating diffusion FD, the electrons leaked from the final transfer stage 104 are accumulated in the floating diffusion FD. The feedthrough level of the signal waveform output from the solid-state imaging device will sink.

  In an imaging apparatus equipped with a solid-state imaging device, an imaging signal corresponding to subject light is obtained by subtracting the feedthrough level from the signal output level after the charge of the final transfer stage 104 is transferred to the floating diffusion FD. . For this reason, if the feedthrough level sinks, the level of the imaging signal also sinks. As a result, as shown in FIG. 12, the periphery 120 of the high-intensity subject H is darkened where it should originally be whitened, resulting in an unnatural image.

  Such a phenomenon has not been a problem so far. However, in recent solid-state imaging devices, noise charges (smear charges) generated in photodiodes and CCDs have increased due to miniaturization, and when there is a high-luminance subject, the final transfer stage 104 changes to the floating diffusion FD. The amount of charge that leaks is increasing. For this reason, the above-described black sun has become conspicuous, and improvement in image quality has been desired.

  In Patent Document 1, charge transfer paths are provided on both sides of a pixel column, and a charge discharge gate unit that discharges the charge transferred to the final transfer stage to the drain next to the final transfer stage of one of the charge transfer paths. There is disclosed a solid-state imaging device provided with the. In the low-resolution mode, this solid-state imaging device uses only a signal corresponding to the charge transferred on one of the two charge transfer paths, and discharges the charge read to the other charge transfer path to the drain. Thus, high-speed driving is realized while preventing image quality deterioration.

  However, the solid-state imaging device described in Patent Document 1 is intended to discharge all unnecessary charges to the drain in the low resolution mode, and is not intended to prevent the occurrence of the above-described black sink. . In the first place, the solid-state imaging device has a charge transfer capacity of the final transfer stage larger than that of the other transfer stages, and is not configured to cause the black sun.

  Patent Document 2 discloses a solid state in which charge transfer paths are provided on both sides of a pixel column, and an overflow drain for discharging charges transferred to the transfer stage is provided next to the transfer stage of one of the charge transfer paths. An image sensor is disclosed. This solid-state imaging device realizes expansion of the dynamic range by limiting the charge handling amount of one charge transfer path by an overflow drain.

  However, the solid-state imaging device described in Patent Document 2 is intended to expand the dynamic range, and is not intended to prevent the occurrence of the above-described black sun. Further, this solid-state imaging device also has a structure in which the charge storage capacity of the final transfer stage is larger than the charge storage capacity of the other transfer stages, and the above-described black sink occurs.

  In the solid-state imaging device shown in FIG. 10, if the width of the terminal end of the horizontal charge transfer path 101 is not reduced, the storage capacity of the final transfer stage 104 increases, so that charge leakage to the floating diffusion FD is reduced. I can. However, if this is done, the charge transfer rate decreases, and the frame rate cannot be improved.

JP 2005-217242 A JP 2002-343554 A

  The present invention has been made in view of the above circumstances, and provides a solid-state imaging device capable of preventing deterioration in image quality when there is a high-luminance subject while preventing a decrease in frame rate, and an imaging apparatus including the same. The purpose is to do.

  The solid-state imaging device of the present invention has a plurality of photoelectric conversion elements formed in a semiconductor substrate, a charge transfer path for transferring charges generated and accumulated in each of the photoelectric conversion elements, and the charge transfer path. A solid-state imaging device having an output unit that outputs a signal according to the charge, wherein the output unit includes a transfer gate region provided on the downstream side in the charge transfer direction of the charge transfer path, and the transfer gate region. And an output circuit that outputs a signal corresponding to the charge accumulated in the charge accumulation unit, and the end of the charge transfer path on the downstream side in the charge transfer direction has the charge The width in the direction orthogonal to the transfer direction becomes narrower toward the charge transfer direction, and the drain region formed on the side of the charge transfer path and at least the final transfer stage in the narrowed portion Provided in contact with A barrier region that forms a potential barrier between the drain region and the charge transfer path, and the height of the potential barrier formed by the barrier region relative to the final transfer stage in the charge accumulation state is determined by the transfer gate region. The potential barrier formed is lower than the height of the final transfer stage in the charge accumulation state.

  The imaging device of the present invention includes the solid-state imaging device.

  According to the present invention, it is possible to provide a solid-state imaging device capable of preventing deterioration in image quality when there is a high-luminance subject while preventing a decrease in frame rate, and an imaging apparatus including the same.

1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention. The figure which expanded the output part 55 vicinity in the solid-state image sensor shown in FIG. The figure which showed the potential in the semiconductor substrate in the A-A 'line cross section shown in FIG. The figure which showed the output signal waveform of the solid-state image sensor 50 when there existed a high-intensity subject. The figure which shows the 1st modification of the solid-state image sensor 50 shown in FIG. The figure which shows the 2nd modification of the solid-state image sensor 50 shown in FIG. The figure which shows the 3rd modification of the solid-state image sensor 50 shown in FIG. The figure which shows an example of the circuit mounted in the solid-state image sensor of the 3rd modification of the solid-state image sensor 50 shown in FIG. The figure which showed the relationship between resistance value Rv of the circuit shown in FIG. 8, and the potential of the barrier region 6 and the drain region 5 Enlarged view of the vicinity of the output part of a conventional CCD (Charge Coupled Device) type solid-state imaging device The figure which showed the potential in a semiconductor substrate in the B-B 'line cross section shown in FIG. Diagram showing black sun that occurs when shooting a high-intensity subject with a conventional solid-state image sensor

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings. This solid-state imaging device is used for an imaging module mounted on an imaging device such as a digital camera and a digital video camera, an electronic endoscope, a camera-equipped mobile phone, and the like.

  FIG. 1 is a schematic plan view showing a schematic configuration of a solid-state imaging device for explaining an embodiment of the present invention.

  The solid-state imaging device 50 shown in FIG. 1 is a plurality of two-dimensionally arranged in a row direction X on the semiconductor substrate and a column direction Y that intersects (orthogonal in the example in the figure) in a two-dimensional manner (square lattice in the example in the figure). Photoelectric conversion element 51, a plurality of vertical charge transfer units 53, a horizontal charge transfer unit 54, and an output unit 55.

  The vertical charge transfer unit 53 transfers charges generated in each photoelectric conversion element 51 in the column direction Y, and is configured by a CCD. One vertical charge transfer unit 53 is provided corresponding to each photoelectric conversion element column composed of a plurality of photoelectric conversion elements 51 arranged in the column direction Y. The charge generated and accumulated in each photoelectric conversion element 51 of the photoelectric conversion element array is read out to the vertical charge transfer unit 53 corresponding to each photoelectric conversion element 51 and transferred in the column direction Y.

  The horizontal charge transfer unit 54 transfers the charges transferred from the plurality of vertical charge transfer units 53 in the row direction X, and is composed of a CCD. Hereinafter, of the end portions in the row direction X of the horizontal charge transfer portion 54, the end portion on the side in which charges are transferred (the left end in the drawing) is referred to as the end portion on the downstream side in the charge transfer direction.

  The output unit 55 converts the charge transferred from the horizontal charge transfer unit 54 into a voltage signal corresponding to the charge amount, and outputs the voltage signal to the outside of the solid-state imaging device 50.

  FIG. 2 is an enlarged view of the vicinity of the output unit 55 in the solid-state imaging device shown in FIG. In the following description, it is assumed that the solid-state imaging device 50 outputs a signal corresponding to electrons accumulated in the photoelectric conversion device 51 to the outside.

  The horizontal charge transfer unit 54 includes a horizontal charge transfer path 1 that transfers charges in the row direction X and a plurality of transfer electrodes 8.

  The horizontal charge transfer path 1 is composed of an n-type impurity layer formed in a p-well layer on the surface of a semiconductor substrate (n-type silicon substrate). The horizontal charge transfer path 1 has a narrower width in the direction perpendicular to the charge transfer direction (column direction Y) at the end on the downstream side in the charge transfer direction.

  The transfer electrodes 8 are electrodes provided above the semiconductor substrate, and a plurality of transfer electrodes 8 are arranged in the row direction X above the horizontal charge transfer path 1.

  The transfer electrode 8 includes a sub electrode 2 and a sub electrode 3. The sub electrode 3 is arranged on the left side of the sub electrode 2 so as to partially overlap the sub electrode 2 in plan view. Further, the sub electrode 3 is formed above the sub electrode 2. The sub electrode 2 and the sub electrode 3 are connected to each other.

  The potential of the horizontal charge transfer path 1 below the sub electrode 2 is formed at a position shallower than the potential of the horizontal charge transfer path 1 below the sub electrode 3. That is, the impurity concentration below each of the sub-electrode 2 and the sub-electrode 3 is adjusted so that the potential of the horizontal charge transfer path 1 below the transfer electrode 8 is stepped in the charge transfer direction.

  Of the plurality of transfer electrodes 8, the odd-numbered transfer electrodes 8 and the even-numbered transfer electrodes 8 counted from the end side of the horizontal charge transfer path 1 are wired so that transfer pulses can be applied independently of each other. Has been made. In the horizontal charge transfer unit 54, a low-level transfer pulse is applied to the odd-numbered transfer electrodes 8, and a high-level transfer pulse is applied to the even-numbered transfer electrodes 8, and the odd-numbered transfer electrodes 8. The charge can be transferred in the row direction X by alternately applying a high-level transfer pulse to the even-numbered transfer electrode 8 and applying a low-level transfer pulse to the even-numbered transfer electrode 8. Although the horizontal charge transfer unit 54 is driven in two phases here, the present invention is not limited to this.

  Hereinafter, the region of the horizontal charge transfer path 1 that overlaps each transfer electrode 8 is referred to as a transfer stage. In each transfer stage, charges are stored in a region below the sub-electrode 3 in a charge storage state (a state where a high-level transfer pulse is applied to the transfer electrode 8). Therefore, this region is referred to as a charge storage region. Of the plurality of transfer stages, the transfer stage located on the most downstream side in the charge transfer direction of the horizontal charge transfer path 1 is referred to as a final transfer stage. In FIG. 2, reference numeral 4 is attached to the final transfer stage. In the example of FIG. 2, the final transfer stage 4 and the transfer stage adjacent thereto are formed in a portion where the width of the end portion of the horizontal charge transfer path 1 is narrowed.

  The output unit 55 includes a floating diffusion FD, a transfer gate region 7, an output gate electrode OG, a source follower amplifier SFA, and a reset transistor RT.

  The floating diffusion FD functions as a charge accumulation unit that accumulates charges transferred from the final transfer stage 4 of the horizontal charge transfer path 1. The floating diffusion FD is formed in the semiconductor substrate at a slight distance next to the end of the horizontal charge transfer path 1.

  The transfer gate region 7 forms a potential barrier between the charge accumulation region of the final transfer stage 4 and the floating diffusion FD, and is formed between the floating diffusion FD in the semiconductor substrate and the horizontal charge transfer path 1. And an impurity layer.

  The output gate electrode OG is an electrode provided above the semiconductor substrate, and is formed above the transfer gate region 7. A fixed voltage that forms a potential barrier in the transfer gate region 7 is applied to the output gate electrode OG.

  The source follower amplifier SFA is an output circuit that converts the charge accumulated in the floating diffusion FD into a voltage signal corresponding to the charge amount and outputs the voltage signal, and is configured by a MOS transistor.

  FIG. 2 shows only the first-stage MOS transistor among the MOS transistors constituting the source follower amplifier SFA.

  The first-stage MOS transistor includes a gate electrode G, a drain region D, and a source region S.

  The source region S and the drain region D are formed apart from each other in the semiconductor substrate. A power supply terminal (not shown) is connected to the drain region D via a contact portion Da.

  The gate electrode G is provided above the semiconductor substrate between the source region S and the drain region D, and is electrically connected to the floating diffusion FD through the contact portion Ga.

  The reset transistor RT includes a drain region RD provided on the side of the floating diffusion FD, and a reset gate electrode RG provided above the semiconductor substrate between the floating diffusion FD and the drain region RD.

  In the solid-state imaging device 50, when the amount of charge transferred to the final transfer stage 4 exceeds the storage capacity of the final transfer stage 4 due to a high-luminance subject or the like, the charge exceeding the storage capacity is transferred to the floating diffusion FD. The drain region 5 and the barrier region 6 are provided in the semiconductor substrate so as not to move.

  The drain region 5 is composed of an impurity layer provided on the side of the semiconductor substrate at a distance from the narrow portion of the horizontal charge transfer path 1 in the semiconductor substrate. In the example of FIG. 2, horizontal charge transfer is performed on the side opposite to the side where the photoelectric conversion element 51 is disposed, in the end portion in the column direction Y of the narrowed portion of the horizontal charge transfer path 1. A drain region 5 is formed along the narrow portion of the path 1.

  The barrier region 6 is composed of an impurity layer provided in contact with the final transfer stage 4 of the transfer stages in the narrowed portion of the horizontal charge transfer path 1 in the semiconductor substrate. In the example of FIG. 2, the end of the final transfer stage 4 in the column direction Y in the narrowed portion of the horizontal charge transfer path 1 is adjacent to the side opposite to the side where the photoelectric conversion element 51 is disposed. Thus, the barrier region 6 is formed.

  FIG. 3 is a diagram showing the potential in the semiconductor substrate in the cross section along the line A-A ′ shown in FIG. 2. FIG. 3 shows a state where electrons are accumulated in the final transfer stage 4.

  In FIG. 3, the range indicated by “FD” indicates the potential of the floating diffusion FD. The range indicated by “7” indicates the potential of the transfer gate region 7. The range indicated by “4” indicates the potential of the charge accumulation region of the final transfer stage 4. The range indicated by “6” indicates the potential of the barrier region 6. The range indicated by “5” indicates the potential of the drain region 5.

  As shown in FIG. 3, when the final transfer stage 4 is in the charge accumulation state, the height 30 of the potential barrier formed by the transfer gate region 7 with respect to the final transfer stage 4 (the bottom of the potential of the charge accumulation region) is the barrier region. The potential barrier formed by 6 becomes higher than the height 31 with respect to the final transfer stage 4. For this reason, the electrons that have overflowed without being accumulated in the final transfer stage 4 are discharged to the drain region 5 through the barrier region 6 and from there to the semiconductor substrate. Therefore, it is possible to prevent electrons from leaking into the floating diffusion FD.

  Thus, according to the solid-state imaging device 50, since the drain region 5 and the barrier region 6 are provided, even when the amount of charge accumulated in each transfer stage of the horizontal charge transfer path 1 is increased by a high-luminance subject, Charge leakage from the final transfer stage 4 to the floating diffusion FD can be prevented. As a result, sinking of the feedthrough level of the signal output from the solid-state imaging device 50 can be prevented, and image quality deterioration can be prevented.

  FIG. 4 is a diagram showing an output signal waveform of the solid-state imaging device 50 when there is a high brightness subject. In FIG. 4, “R” indicates a reset level, “F” indicates a feedthrough level, and “D” indicates a data level. A portion indicated by a broken line shows a signal waveform when the drain region 5 and the barrier region 6 are not provided in the solid-state imaging device 50.

  The output signal of the solid-state imaging device 50 becomes the reset level R after resetting the floating diffusion FD, and then becomes stable at the feedthrough level F. Thereafter, when charges are transferred from the final transfer stage 4 to the floating diffusion FD, the output changes to the data level D according to the amount of charges.

  In the solid-state imaging device 50, by providing the drain region 5 and the barrier region 6, as shown by the solid line waveform in FIG. (The broken line portion shows the output waveform when the drain region 5 and the barrier region 6 are not provided).

  In FIG. 4, “b” indicates the level of the imaging signal when the drain region 5 and the barrier region 6 are not provided, and “a” indicates the level of the imaging signal when the drain region 5 and the barrier region 6 are provided. Show. Thus, according to the solid-state imaging device 50, the drain region 5 and the barrier region 6 can prevent the level of the imaging signal from being lowered, and image quality deterioration when there is a high-luminance subject can be prevented. .

  Next, a modified example of the solid-state image sensor 50 will be described.

(First modification)
FIG. 5 is a diagram illustrating a first modification of the solid-state imaging device 50 illustrated in FIG. 1, and corresponds to FIG. The solid-state imaging device shown in FIG. 5 has the same configuration as the solid-state imaging device shown in FIG. 2 except that the formation range of the barrier region 5 and the drain region 6 is widened.

  The barrier region 6 shown in FIG. 5 is formed so as to be in contact with the final transfer stage 4 and the adjacent transfer stage among the transfer stages in the narrowed portion of the horizontal charge transfer path 1. Further, the drain region 5 is configured to extend in the direction in which the barrier region 6 extends.

  In this way, by forming the barrier region 6 adjacent to the transfer stage adjacent to the final transfer stage 4, the charges overflowing from the drain stage 6 are discharged to the drain area 6 even in the transfer stage before the final transfer stage 4. can do. For this reason, the amount of charge transferred to the final transfer stage 4 can be reduced, and charge leakage to the floating diffusion FD can be prevented more strongly.

(Second modification)
FIG. 6 is a diagram illustrating a second modification of the solid-state imaging device 50 illustrated in FIG. 1, and corresponds to FIG. The solid-state imaging device shown in FIG. 6 has the same configuration as the solid-state imaging device shown in FIG. 2 except that two pairs of the barrier region 5 and the drain region 6 are provided.

  In the solid-state imaging device shown in FIG. 6, the width of the horizontal charge transfer path 1 becomes narrower on the side of both ends in the column direction Y of the narrowed portion of the horizontal charge transfer path 1 in the semiconductor substrate. A drain region 5 is formed along the portion.

  In the solid-state imaging device shown in FIG. 6, in the semiconductor substrate, adjacent to both of the end portions in the column direction Y of the final transfer stage 4 in the narrowed portion of the horizontal charge transfer path 1, A barrier region 6 is formed.

  As described above, by providing the barrier regions 6 adjacent to both ends of the final transfer stage 4 in the column direction Y, it is possible to more strongly prevent charge leakage to the floating diffusion FD.

  In the configuration shown in FIG. 6, each barrier region 6 is extended so as to be adjacent to the transfer stage adjacent to the final transfer stage 4, and each drain region 5 is extended accordingly, thereby preventing charge leakage. The effect can be further enhanced.

(Third modification)
FIG. 7 is a diagram illustrating a third modification of the solid-state imaging device 50 illustrated in FIG. 1, and corresponds to FIG. The solid-state imaging device shown in FIG. 7 has the same configuration as the solid-state imaging device shown in FIG. 2 except that a power supply terminal is connected to the drain region 6.

  A wiring 9 is connected to the contact portion Da of the solid-state imaging device shown in FIG. A power source terminal for drain power source of the source follower amplifier circuit SFA (not shown) is connected to the wiring 9.

  A contact portion RDa is connected to the reset drain RD of the solid-state imaging device shown in FIG. A wiring 10 is connected to the contact portion RDa, and a power terminal for a reset drain power supply is connected to the wiring 10.

  A wiring 11 is connected to the drain region 5 of the solid-state imaging device shown in FIG. 7 via a contact portion 5a. The wiring 11 is connected to the power supply terminal for the drain power supply.

  With such a configuration, even if the voltage is applied to the drain region 5, the number of power supply terminals can be reduced, and the cost can be reduced.

  The wiring 11 may be connected to the power terminal for reset drain power instead of the power terminal for drain power. Even in this case, the number of power supply terminals can be similarly reduced.

  This configuration can also be applied to the configurations shown in FIGS.

  In the case of this configuration, a circuit that generates a voltage having a level different from the voltage supplied from the power supply terminal for the drain power supply or the power supply terminal for the reset drain power supply of the SFA is connected to the drain region 5. Is preferred.

  For example, the drain region 5 is connected to the power source terminal for the drain power source or the power source terminal for the reset drain power source of the SFA through a resistance voltage dividing circuit as shown in FIG.

  The resistance dividing circuit shown in FIG. 8 includes a resistor 81 having a resistance value Rv and a resistor 82 having a resistance value R.

  One end of the resistor 81 is an input terminal D1 of this circuit. The input terminal D1 is connected to a power supply terminal for drain power supply or a power supply terminal for reset power supply.

  One end of a resistor 82 is connected to the other end of the resistor 81. The other end of the resistor 82 is grounded.

  An output terminal D2 of this circuit is connected to the other end of the resistor 81 and one end of the resistor 82, and this output terminal D2 is connected to the drain region 5 through the wiring 11 and the contact portion 5a.

  This resistance dividing circuit generates a voltage having a level different from the voltage supplied from the input terminal D1, and outputs the voltage from the output terminal D2. The voltage level output from the output terminal D2 can be changed by changing the resistance value Rv. For this reason, the height of the potential barrier formed by the barrier region 6 can be adjusted by appropriately setting the resistance value Rv when manufacturing the solid-state imaging device.

  FIG. 9 is a diagram showing the relationship between the resistance value Rv of the circuit shown in FIG. 8 and the potentials of the barrier region 6 and the drain region 5, and corresponds to FIG.

  As shown in FIG. 9, as the resistance value Rv increases, the voltage level output from the output terminal D2 decreases accordingly, so that the potential of the drain region 5 changes in a shallow direction. When the potential of the drain region 5 changes in the shallow direction, the potential of the barrier region 6 also changes in the shallow direction. Thus, according to the solid-state imaging device provided with the circuit shown in FIG. 8, the height of the potential barrier in the barrier region 6 can be adjusted by the value of the resistance value Rv.

  The resistance value Rv can be changed simply by preparing a bleeder circuit and changing the contact mask, for example. Therefore, according to the solid-state imaging device provided with the circuit shown in FIG. 8, the height of the potential barrier in the barrier region 6 can be easily adjusted, and the height of the potential barrier is changed for each model of the solid-state imaging device. Even in such a case, an increase in manufacturing cost can be prevented.

  The arrangement of the photoelectric conversion elements 51 shown in FIG. 1 is not limited to this, and a known arrangement can be adopted. Further, the photoelectric conversion element array and the vertical charge transfer unit 53 shown in FIG.

  Further, in the portion where the width of the horizontal charge transfer path 1 is narrowed, there is the final transfer stage 4 and one transfer stage adjacent thereto, but at least the final transfer stage 4 is present here. That's fine. In addition to the final transfer stage 4, a plurality of transfer stages may exist.

  Further, the barrier region 6 may not be in contact with the entire final transfer stage 4 but may be provided in contact with a part or all of the charge accumulation region of the final transfer stage 4. Even when the barrier region 6 extends to the transfer stage adjacent to the final transfer stage 4, the barrier area 6 may be in contact with part or all of the charge accumulation region in the adjacent transfer stage. Since no charge is accumulated in the region below the sub-electrode 2, there is no problem even if the barrier region 6 is not in contact with this region.

  In the description so far, it is assumed that electrons generated in the photoelectric conversion element 51 are converted into signals and read out. However, the present invention can be similarly applied to the case where holes are converted into signals and read out.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device includes a plurality of photoelectric conversion elements formed in a semiconductor substrate, a charge transfer path that transfers charges generated and accumulated in each of the photoelectric conversion elements, and the charge transfer path. A solid-state imaging device having an output unit that outputs a signal according to the charge, wherein the output unit includes a transfer gate region provided on the downstream side in the charge transfer direction of the charge transfer path, and the transfer gate region. And an output circuit that outputs a signal corresponding to the charge accumulated in the charge accumulation unit, and the end of the charge transfer path on the downstream side in the charge transfer direction has the charge The width in the direction orthogonal to the transfer direction becomes narrower toward the charge transfer direction, and the drain region formed on the side of the charge transfer path and at least the final transfer stage in the narrowed portion Provided in contact with A barrier region that forms a potential barrier between the drain region and the charge transfer path, and the height of the potential barrier formed by the barrier region with respect to the final transfer stage in the charge accumulation state is the transfer gate region Is lower than the height of the final transfer stage in the charge accumulation state of the potential barrier formed by

  In the disclosed solid-state imaging device, the drain region is connected to a power supply terminal for drain power of a transistor of the output circuit.

  In the disclosed solid-state imaging device, the drain region is connected to a power source terminal for a drain power source of a reset transistor that resets the charge of the charge storage unit.

  The disclosed solid-state imaging device includes a circuit that generates and outputs a second voltage having a level different from the voltage from the first voltage supplied to the input terminal, and the input terminal is connected to the power supply terminal. The drain region is connected to the output terminal of the circuit.

  The disclosed solid-state imaging device has at least one transfer stage in addition to the final transfer stage in the narrowed portion, and the barrier region includes the final transfer stage and the adjacent transfer stage. It is provided in contact with.

  In the disclosed solid-state imaging device, the barrier region is provided in contact with both end portions in a direction perpendicular to the charge transfer direction of the narrow portion.

  The disclosed imaging device includes the solid-state imaging device.

DESCRIPTION OF SYMBOLS 1 Horizontal charge transfer path 4 Final transfer stage 5 Drain area | region 6 Barrier area | region 7 Transfer gate area | region 8 Transfer electrode 50 Solid-state image sensor 54 Horizontal charge transfer part 55 Output part FD Floating diffusion OG Transfer gate electrode

Claims (7)

A plurality of photoelectric conversion elements formed in a semiconductor substrate, a charge transfer path for transferring charges generated and accumulated in each of the photoelectric conversion elements, and a signal corresponding to the charges transferred through the charge transfer path are output. A solid-state imaging device having an output unit that
The output unit includes a transfer gate region provided on the downstream side in the charge transfer direction of the charge transfer path, a charge storage unit provided adjacent to the transfer gate region, and a charge stored in the charge storage unit. An output circuit that outputs a corresponding signal,
The end of the charge transfer path on the downstream side in the charge transfer direction is narrower as the width in the direction orthogonal to the charge transfer direction is toward the charge transfer direction,
A drain region formed on a side of the charge transfer path;
A barrier region that is provided in contact with at least the final transfer stage in the narrowed portion and forms a potential barrier between the drain region and the charge transfer path;
A solid-state imaging device, wherein a height of the potential barrier formed by the barrier region with respect to the final transfer stage in the charge accumulation state is lower than a height of the potential barrier formed by the transfer gate region with respect to the final transfer stage. The solid-state imaging device according to claim 1,
A solid-state imaging device, wherein the drain region is connected to a power supply terminal for drain power of a transistor of the output circuit. The solid-state imaging device according to claim 2,
A solid-state imaging device in which the drain region is connected to a power supply terminal for a drain power supply of a reset transistor that resets the charge in the charge storage unit. The solid-state imaging device according to claim 2 or 3,
A circuit for generating and outputting a second voltage having a level different from the voltage from the first voltage supplied to the input terminal;
A solid-state imaging device in which the input terminal is connected to the power supply terminal, and the drain region is connected to an output terminal of the circuit. The solid-state image sensor according to any one of claims 1 to 4,
The narrow portion has at least one transfer stage other than the final transfer stage,
A solid-state imaging device in which the barrier region is provided in contact with the final transfer stage and the adjacent transfer stage. The solid-state imaging device according to any one of claims 1 to 5,
A solid-state imaging device in which the barrier region is provided in contact with both end portions in a direction perpendicular to the charge transfer direction of the narrowed portion.   An imaging device provided with the solid-state image sensor of any one of Claims 1-6.

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