JP2011210364A - Thin-film magnetic body storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film magnetic body storage device having a magnetic body memory cell which is independent of the level of storage data to be written and whose magnetic characteristics are symmetrical.SOLUTION: In a magnetization free layer in a tunnel magneto-resistive element, a coupled magnetic field ΔHp between the magnetization free layer and a fixed magnetization layer acts in a direction along a magnetic field easy axis (EA). the coupled magnetic field being caused by magnetostatic connection. A data writing magnetic field H(WWL) is not applied in completely parallel to the magnetic hard axis (HA) of the magnetization free layer but is applied so as to form a predetermined angle α together with the magnetic hard axis HA. The uniform coupled magnetic field ΔHp is offset by a component in the direction along an easy magnetization axis (EA) of the H(WWL).

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Memory) device has attracted attention as a storage device capable of storing nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device will be dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

  FIG. 48 is a conceptual diagram showing the configuration and data read operation of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 48, the MTJ memory cell forms a tunnel magnetoresistive element TMR whose electric resistance value changes according to the data level of stored data, and a path of a sense current passing through tunnel magnetoresistive element TMR during data reading. And an access transistor ATR. Access transistor ATR is formed of a field effect transistor, for example, and is coupled between tunneling magneto-resistance element TMR and ground voltage VSS.

  The tunnel magnetoresistive element TMR includes a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed magnetic field in a certain direction, and a ferromagnetic material magnetized in a direction changed by a magnetic field applied from the outside. Layer (hereinafter also referred to simply as “free magnetic layer”) VL. A tunnel barrier TB formed of an insulator film is disposed between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in a different direction from fixed magnetic layer FL according to the level of stored data.

  For MTJ memory cells, write word line WWL for instructing data writing, read word line RWL for instructing data reading, and at the level of stored data at the time of data reading and data writing A bit line BL which is a data line for transmitting a corresponding electric signal is arranged.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, the sense current Is can flow through the current path of the bit line BL, the tunnel magnetoresistive element TMR, the access transistor ATR, and the ground voltage VSS.

  The electric resistance value of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of the pinned magnetic layer FL and the magnetization direction written in the free magnetic layer VL are aligned, the electrical resistance of the tunnel magnetoresistive element TMR is larger than when the magnetization directions of the two are different. The resistance value becomes smaller. Hereinafter, in this specification, the electrical resistance values of the tunnel magnetoresistive elements corresponding to the stored data “1” and “0”, respectively, are denoted by R1 and R0, respectively. However, it is assumed that R1> R0.

  Thus, the tunnel magnetoresistive element TMR changes its electric resistance value according to the magnetization direction. Therefore, data storage can be executed by associating the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR with the levels (“1” and “0”) of stored data. That is, the free magnetic layer VL corresponds to a storage node of the MTJ memory cell.

  The voltage change caused in the tunnel magnetoresistive element TMR by the sense current Is differs depending on the magnetization direction of the free magnetic layer VL, that is, the stored data level. As a result, if the sense current Is is passed through the tunnel magnetoresistive element TMR after the bit line BL is precharged to a constant voltage, the storage data of the MTJ memory cell is read by monitoring the voltage level change of the bit line BL. Can be put out.

FIG. 49 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 49, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in the direction corresponding to the write data is supplied to write word line WWL and bit line BL. The magnetization direction of free magnetic layer VL is determined by the combination of the directions of data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 50 is a conceptual diagram illustrating the relationship between the direction of data write current and the magnetization direction during data writing.

  Referring to FIG. 50, the horizontal axis Hx represents the direction of the data write magnetic field H (BL) generated by the data write current flowing through the bit line BL. On the other hand, the vertical axis Hy represents the direction of the data write magnetic field H (WWL) generated by the data write current flowing through the write word line WWL.

  The magnetization direction of the free magnetic layer VL is newly rewritten only when the sum of the data write magnetic fields H (BL) and H (WWL) reaches a region outside the asteroid characteristic line shown in the figure. Can do. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  Therefore, in order to update the stored contents of tunneling magneto-resistance element TMR by the data write operation, it is necessary to pass a current of a predetermined level or more to both write word line WWL and bit line BL. The magnetization direction once stored in tunneling magneto-resistance element TMR, that is, stored data is held in a nonvolatile manner until new data writing is executed.

  Even during the data read operation, sense current Is flows through bit line BL. However, since the sense current Is is generally set to be about 1 to 2 digits smaller than the data write current described above, the stored data in the MTJ memory cell is erroneously read at the time of data reading due to the influence of the sense current Is. The possibility of rewriting is small.

Roy Scheuerlein and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Using FET Switches and Magnetic Tunnel Junctions in Each Cell Junction and FET Switch in each Cell), (USA), 2000 IEICE International Solid Circuit Conference and Technical Papers TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129 D. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 International Solid State Circuit Conference / Technology of the Institute of Electrical and Electronics Engineers, 2000 Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131

  However, in the MRAM device using such a tunnel magnetoresistive element TMR, the following problems occur as the memory cell size is reduced.

  In the MTJ memory cell, stored data is stored according to the magnetization direction of the free magnetic layer VL. However, the magnetic field strength (hereinafter referred to as “reversing magnetic field strength”) that needs to be applied to rewrite the magnetization direction of the free magnetic layer. Is proportional to T / L, where T is the thickness of the magnetic layer and L is the length in the magnetization direction of the magnetic layer. Therefore, when the memory cell size is reduced, the switching magnetic field strength increases in accordance with the scaling of the planar size.

  As the memory cell size is reduced, magnetic field interference generated between the fixed magnetic layer and the free magnetic layer increases outside and inside the MTJ memory cell. Thereby, the threshold value of the data write magnetic field necessary for data writing (corresponding to the asroid characteristic line in FIG. 50) changes depending on the pattern of the write data or depends on the direction of the data write magnetic field. And become asymmetrical.

  Such a phenomenon makes it difficult to scale the MTJ memory cell, and causes problems such as an increase in current consumption as the memory cell size is reduced.

  In order to solve such problems, US Pat. No. 6,166,948 discloses that free magnetic layers of MTJ memory cells are formed by two ferromagnetic layers each having a different magnetic moment. Techniques to do this are disclosed. Hereinafter, such a structure in which a free magnetic layer is formed by two magnetic layers is also referred to as a “two-layer storage node structure”. On the other hand, the structure shown in FIGS. 48 and 49 in which the free magnetic layer is formed by a single magnetic layer is also referred to as a “single layer storage node structure”.

  FIG. 51 is a cross-sectional view showing a configuration of a conventional tunnel magnetoresistive element having a two-layer storage node structure.

  Referring to FIG. 51, the conventional tunnel magnetoresistive element includes an antiferromagnetic layer AFL, a fixed magnetic layer FL, free magnetic layers VL1 and VL2, and a fixed magnetic layer FL and a free magnetic layer VL1. It includes a tunnel barrier TB to be formed and an intermediate layer IML formed between free magnetic layers VL1 and VL2. The intermediate layer IML is formed of a nonmagnetic material. In the MTJ memory cell having the tunnel magnetoresistive element shown in FIG. 51, stored data is accumulated according to the relative relationship between the magnetization directions of the fixed magnetic layer FL and the free magnetic layer VL1.

  Free magnetic layers VL1 and VL2 are arranged with intermediate layer IML interposed therebetween. The magnetic moment of free magnetic layer VL1 is larger than that of free magnetic layer VL2. Therefore, the magnetization threshold value for changing the magnetization direction is larger in free magnetic layer VL1 than in free magnetic layer VL2.

  In addition, since the strength of the magnetic moment is applied, when the magnetization direction of the free magnetic layer VL1 changes, the magnetization direction of the free magnetic layer VL2 also forms a magnetization loop with the free magnetic layer VL1. It changes following.

  FIG. 52 is a hysteresis diagram for explaining the magnetization in the tunnel magnetoresistive element shown in FIG. In FIG. 52, the behavior of magnetization in the easy axis direction of free magnetic layers VL1 and VL2 by data write magnetic field H is shown.

  With reference to FIG. 52, first, the change in the magnetization direction when the data write magnetic field is increased in the negative direction will be described.

First, in the region of H> H ₀₁ (state 1A), free magnetic layers VL1 and VL2 are both magnetized in the positive direction (right direction). Next, when H <H ₀₁ is changed (state 2A), only the magnetization direction in the free magnetic layer VL2 having a small magnetic moment is reversed.

Further, when the magnetic field is changed in the negative direction to enter the region exceeding the threshold value −H ₀₂ (state 3A), the magnetization direction in the free magnetic layer VL1 having a large magnetic moment changes from the positive direction (right side) to the negative direction (left side). ). Following this, the magnetization direction in the free magnetic layer VL2 is also reversed from the state 2A.

Further, when data write magnetic field H increases in the negative direction and enters the region of H <−H ₀₃ (state 4A), the magnetization direction changes in the negative direction (left side) in both free magnetic layers VL1 and VL2. To do.

  Next, a change in the magnetization direction when the data write magnetic field H is increased in the positive direction will be described.

In the region of H <−H ₀₁ (state 4B), both free magnetic layers VL1 and VL2 are magnetized in the negative direction (left direction). Next, when H> −H ₀₁ is changed (state 3B), only the magnetization direction in the free magnetic layer VL2 having a small magnetic moment is reversed.

Further, when the magnetic field is changed in the positive direction to enter the region exceeding the threshold value H ₀₂ (state 2B), the magnetization direction in the free magnetic layer VL1 having a large magnetic moment changes from the negative direction (left side) to the positive direction (right side). To change. Following this, the magnetization direction in the free magnetic layer VL2 is also reversed from the state 3B.

Further, when data write magnetic field H increases in the positive direction and enters the region of H> H ₀₃ (state 1B), the magnetization direction changes in the positive direction (right side) in both free magnetic layers VL1 and VL2. .

  In this way, each free magnetic layer is formed of ferromagnetic layers having different magnetization threshold values (magnetic moments), and an intermediate layer that is a non-magnetized layer is sandwiched between them. By using a state in which the layers are inverted between the upper and lower layers as the data storage state, the reversal magnetic field strength of the free magnetic layer can be reduced. In addition, since the two free magnetic layers are magnetized in a loop shape in the data storage state, the magnetic flux does not spread outside the MTJ memory cell, and the adverse effect due to magnetic field interference can be suppressed.

  However, in the MTJ memory cell having the two-layer storage node structure shown in FIG. 51, each of the free magnetic layers VL1 and VL2 needs to have a different magnetization threshold (magnetic moment). It is necessary to deposit two different magnetic layers, which complicates the manufacturing apparatus and the manufacturing process.

  In particular, as shown in FIG. 52, since the difference in magnetic moment between free magnetic layers VL1 and VL2 has a great influence on the data storage state, the data storage characteristics of MTJ memory cells are affected by variations in the magnetic moment during manufacture. May change significantly.

  As shown in FIGS. 48, 49 and 52, in the MTJ memory cell, free magnetic layers VL, VL1 and VL2 which are magnetized in a direction corresponding to stored data, and a fixed magnetic layer having a fixed magnetization direction. Since the FL and the antiferromagnetic layer AFL are arranged close to each other, there is a problem that the magnetization characteristics in the free magnetic layer become non-uniform according to the level of stored data.

  FIG. 53 is a conceptual diagram illustrating non-uniformity of magnetization characteristics in an MTJ memory cell having a single-layer storage node structure.

  Referring to FIG. 53, fixed magnetic layer FL and antiferromagnetic material layer AFL have the same fixed magnetization direction. The antiferromagnetic material layer AFL is disposed in order to more strongly fix the magnetization direction of the fixed magnetization layer FL.

  The free magnetic layer VL functioning as a storage node is magnetized in either the positive direction (+ direction) or the negative direction (− direction) depending on the level of stored data. In FIG. 53, the magnetization direction in the same direction as the fixed magnetization layer FL is defined as a positive direction, and the magnetization direction opposite to the fixed magnetization layer FL is defined as a negative direction.

  Since the plurality of magnetic layers are provided close to each other in this way, the magnetic fields from the antiferromagnetic layer AFL and the fixed magnetization layer FL are magnetostatically coupled to each other in the direction of easy magnetization in the free magnetization layer VL. A uniform magnetic field ΔHp is applied. The uniform magnetic field ΔHp acts in the direction opposite to the magnetization direction of the fixed magnetization layer FL, that is, in the negative direction. Due to the presence of such a uniform magnetic field ΔHp, the magnetization characteristics in the free magnetic layer VL become asymmetric depending on the magnetic field direction.

  FIG. 54 is a hysteresis diagram for explaining the magnetization characteristics in free magnetic layer VL shown in FIG. FIG. 54 shows the magnetization behavior of free magnetic layer VL by data write magnetic field Hex in the easy axis direction.

  Referring to FIG. 54, in order to magnetize free magnetic layer VL magnetized in the negative direction in the positive direction, it is necessary to apply magnetic field Hex in the positive direction beyond + Hsp. Conversely, in order to magnetize the free magnetic layer VL magnetized in the positive direction in the negative direction, it is necessary to apply a magnetic field Hex in the negative and positive direction beyond -Hsn.

  Here, due to the influence of the uniform magnetic field ΔHp due to the magnetostatic coupling with the fixed magnetic layer FL, the magnetization threshold value Hsp in the positive direction is larger than the magnetization threshold value Hsn in the negative direction by ΔHp. As described above, the magnetization characteristics in the free magnetic layer VL become asymmetric according to the direction of the applied magnetic field. Therefore, the magnetic field that needs to be applied to the free magnetic layer VL depends on the level of the write data to the MTJ memory cell. Strength will be different. In order to use such a tunnel magnetoresistive element as a memory cell, it is necessary to apply a magnetic field that exceeds the larger magnetization threshold value when writing any data level. That is, it is necessary to apply a data write current for generating a magnetic field exceeding the magnetization threshold value Hsp even when the free magnetic layer VL is magnetized in the negative direction. Therefore, in such a case, the data write current is unnecessarily large. This may cause problems such as an increase in power consumption and a decrease in wiring reliability due to an increase in wiring current density.

  Such a phenomenon also occurs in a tunnel magnetoresistive element having a two-layer storage node structure.

  FIG. 55 is a conceptual diagram for explaining the non-uniformity of magnetization characteristics in an MTJ memory cell having a two-layer storage node structure.

  Referring to FIG. 55, also in the tunnel magnetoresistive element of the two-layer storage node structure, in the free magnetic layer VL1 between the antiferromagnetic layer AFL and the fixed magnetic layer FL, similarly to the single-layer storage node structure. Due to the magnetostatic coupling, a uniform magnetic field ΔHp is applied in the direction of the easy axis of magnetization. As a result, the magnetization behavior in the easy axis direction in the free magnetic layers VL1 and VL2 becomes asymmetric.

  FIG. 56 is a hysteresis diagram for explaining the magnetization characteristics in free magnetic layer VL shown in FIG.

Referring to FIG. 56, the magnetization behavior behavior of free magnetic layers VL1 and VL2 by data write magnetic field Hex in the direction of easy axis is described by the influence of uniform magnetic field ΔHp generated by magnetostatic coupling with fixed magnetic layer FL. Compared with the theoretical characteristic shown in FIG. 52, the characteristic is shifted by ΔHp. That is, the threshold + H ₀₁ for the positive direction of the applied magnetic field as shown in FIG. 52, + H _02, against + H _03, threshold -H ₀₁ for the negative direction of the magnetic field _{', -H 02', -H 03} ' Are shifted by ΔHp, and the magnetization characteristics become asymmetric with respect to the positive magnetic field and the negative magnetic field, respectively. That is, H ₀₁ − | −H ₀₁ ′ | = H ₀₂ − | −H ₀₂ ′ | = H ₀₃ − | −H ₀₃ ′ | = ΔHp.

  As described above, in any of the tunnel magnetoresistive elements of the single-layer storage node structure and the double-layer storage node structure, it is necessary to unnecessarily increase the level of the data write current due to the asymmetry of the magnetic field characteristics. It was.

  The present invention was made to solve such problems, and the object of the present invention is to provide a simple magnetization characteristic and a sufficient operating margin without complicating the manufacturing process. It is an object to provide a thin film magnetic memory device having an MTJ memory cell.

  Another object of the present invention is to provide a thin film magnetic memory device having MTJ memory cells having symmetrical magnetization characteristics independent of the level of stored data to be written.

  A thin film magnetic memory device according to the present invention includes a plurality of memory cells. Each of the plurality of memory cells includes a magnetic storage unit that performs data storage and an electrical resistance value changes in accordance with the stored data, and a read access element for passing a data read current through the magnetic storage unit when conducting. Including. The magnetic memory unit includes a first magnetic layer having a fixed magnetization direction, second and third magnetic layers that are magnetized in opposite directions according to an applied data write magnetic field, Formed between the nonmagnetic and conductive intermediate layer formed between the second and third magnetic layers, one of the second and third magnetic layers, and the first magnetic layer. And an insulating layer. At the time of data writing, at least a part of the data write magnetic field is generated by the first data write current flowing through the intermediate layer.

Preferably, the intermediate layer is shared by a part of the plurality of memory cells.
More preferably, the plurality of memory cells are arranged in a matrix, and the intermediate layer is formed to have a belt-like planar shape corresponding to any one of the memory cell rows and the memory cell columns.

  Alternatively, preferably, the plurality of memory cells are arranged in a matrix. The thin film magnetic memory device is formed using an intermediate layer, and is provided corresponding to one of the memory cell row and the memory cell column, each of which includes a plurality of first data flows for flowing a first data write current. A plurality of data write lines are provided in correspondence with the other of the memory cell row and the memory cell column, respectively, and a second data write current for generating a data write magnetic field is supplied during data writing. The second data write line is further provided. In both of the corresponding first and second data write lines, the magnetization directions of the second and third magnetic layers are rewritten in the memory cells through which the first and second data write currents flow, respectively. Is possible.

  In particular, the magnetic memory unit is formed in an upper layer of the read access element, and the data write wiring is formed in an upper layer than the magnetic memory unit.

  Alternatively, preferably, the access element electrically couples the magnetic storage unit with a fixed voltage during data reading, and the data read current is passed to the magnetic storage unit via the intermediate layer.

  Alternatively, preferably, the thin film magnetic memory device further includes a read data line for flowing a data read current during data reading. At the time of data reading, the read access element electrically couples the magnetic memory portion with the read data line, and the intermediate layer is set to a fixed voltage at the time of data reading.

  Preferably, the plurality of memory cells are arranged in a matrix, and the intermediate layer is formed to extend in the memory cell column direction as a plurality of data lines respectively corresponding to the memory cell columns. The thin-film magnetic memory device is configured to set one end of each of the two data lines forming a pair to one of the first voltage and the second voltage according to the level of the write data during data writing. A data write circuit and a current switch provided for each of the two data lines forming a pair and electrically coupling the other ends of the corresponding two data lines at the time of data writing .

  A thin film magnetic memory device according to another configuration of the present invention includes a plurality of memory cells, each of which executes data storage, and a data write wiring. Each memory cell includes a magnetic storage unit whose electrical resistance value changes in accordance with stored data, and an access element for passing a data read current through the magnetic storage unit when conducting. The magnetic storage unit includes a first magnetic layer having a fixed magnetization direction, and second and third magnetized in opposite directions according to an applied data write magnetic field, each having a different magnetic moment. A magnetic layer, a nonmagnetic intermediate layer formed between the second and third magnetic layers, one of the second and third magnetic layers, and the first magnetic layer And an insulating layer formed therebetween. The data write wiring passes a data write current for generating a data write magnetic field at the time of data writing.

  Preferably, the intermediate layer is formed in a planar shape so as to be shared by at least some of the plurality of memory cells.

  A thin film magnetic memory device according to still another configuration of the present invention includes a plurality of memory cells, a global data line, and a local data line. Each memory cell executes data storage, and a magnetic storage unit that changes its electric resistance value according to the magnetization direction rewritten in response to an applied magnetic field, and a data read current to the magnetic storage unit when conducting. And an access element for passing through. The global data line and the local data line are provided hierarchically in order to flow a data write current for magnetizing the magnetic storage unit in the direction corresponding to the write data during data writing.

  Preferably, at the time of data writing, the magnetic fields generated by the data write currents flowing through the global data line and the local data line reinforce each other in the magnetic memory unit.

  Preferably, the plurality of memory cells are arranged in a matrix, the global data line is arranged corresponding to one of the memory cell row and the memory cell column, and the local data line is connected to the same global data write line. It is arranged for each predetermined section of the corresponding memory cell group. The thin film magnetic memory device is a data for setting one end of each of the two global data lines forming a pair to one of the first voltage and the second voltage according to the level of the write data at the time of data writing. A first current switch portion provided for each of the two local data lines paired with the write circuit and for electrically coupling one end of the corresponding two local data lines at the time of data writing Provided for each of the two local data lines that form a pair, and a second for connecting each of the other ends of the corresponding two local data lines to the corresponding two global write data lines, respectively. And a current switch unit.

  Alternatively, preferably, the thin film magnetic memory device causes a data read current to flow through each of the two global data lines that make a pair, and responds to a voltage comparison between the two global data lines that make a pair. And a data read circuit for generating read data, and a reference voltage generator provided for each global data line and generating a reference voltage in response to passage of the data read current. A memory cell selected as a data read target is supplied with a data read current while being connected to a corresponding global data line via a corresponding local data line. At the time of data reading, the global data line paired with the global data line corresponding to the selected memory cell is connected to the reference voltage generating unit.

  Alternatively, preferably, the plurality of memory cells are arranged in a matrix, the global data line is arranged corresponding to one of the memory cell row and the memory cell column, and the local data line is connected to the same global data write line. It is arranged for each predetermined section of the corresponding memory cell group. The thin film magnetic memory device is a data for setting one end of each of the two global data lines forming a pair to one of the first voltage and the second voltage according to the level of the write data at the time of data writing. Current switch portion provided for each of two local data lines that make a pair with the write circuit, and for connecting one of the two local data lines that make a pair between the corresponding two global data lines And further comprising.

  More preferably, in the thin film magnetic memory device, at the time of data reading, a data read current is supplied to each of the two global data lines forming a pair, and a voltage comparison between the two global data lines forming a pair is performed. A data read circuit for generating read data and a reference voltage generation unit provided for each global data line and generating a reference voltage in response to passage of the data read current are further provided. The current switch unit connects one of the paired local data lines corresponding to the memory cell selected as a data read target to the corresponding global data line. At the time of data reading, the global data line paired with the corresponding global data line is connected to the reference voltage generator.

  Preferably, the plurality of memory cells are arranged in a matrix, the global data line is arranged for each of the plurality of memory cell columns, and the local data line is arranged for each predetermined section in each memory cell column.

  Alternatively, preferably, each memory cell has a write for selectively flowing the first data write current to the intermediate layer corresponding to the memory cell selected as the data write target among the plurality of memory cells. An access device.

  More preferably, the plurality of memory cells are arranged in a matrix, and the thin film magnetic memory device further includes first and second data lines provided for each memory cell column. At the time of data writing, the first and second data lines corresponding to the memory cell column including the selected memory cell are respectively connected to one of the first and second voltages according to the level of the write data. Each write access element is set and connected in series with the intermediate layer between corresponding first and second data lines and turned on in the memory cell row including the selected memory cell.

  In particular, in the read access element, in the data read operation, the magnetic storage portion of the memory cell selected as the data read target is connected to one of the first and second data lines supplied with the data read current and a predetermined voltage. A transistor for electrical coupling is provided between the transistors.

  Alternatively, in particular, the thin film magnetic memory device is provided for each memory cell row, and a read word line set to a voltage higher than a predetermined voltage in a memory cell row including a memory cell selected as a data read target Is further provided. The intermediate layer is coupled to a predetermined voltage via one of the first and second data lines during data reading. The read access element has a diode element provided between the corresponding read word line and the magnetic storage unit, with the direction from the corresponding read word line toward the magnetic storage unit as the forward direction.

  A thin film magnetic memory device according to still another configuration of the present invention includes a plurality of memory cells each for executing data storage. Each memory cell includes a magnetic storage unit whose electrical resistance value changes according to stored data. The magnetic storage unit includes a first magnetic layer having a fixed magnetization direction, a second magnetic layer that is magnetized in a direction corresponding to the level of stored data, and first and second magnetic layers. And an insulating layer formed therebetween. The thin film magnetic memory device includes a first data write magnetic field for magnetizing the second magnetic layer for at least one selected memory cell selected as a data write target among the plurality of memory cells. A first data write current line for generating. The first data write magnetic field has a component in a direction that cancels the coupling magnetic field that acts on the second magnetic layer from the first magnetic layer regardless of the level of the stored data.

  Preferably, the thin film magnetic memory device further includes a second data write current line for generating a second data write magnetic field for magnetizing the second magnetic layer for the selected memory cell. The first data write magnetic field mainly includes a component in a direction along the hard axis of the second magnetic layer, and the second data write magnetic field includes the easy axis of the second magnetic layer. The first data write current line mainly includes a component in the direction along the direction, and is arranged to form a predetermined angle with the easy axis direction.

  More preferably, each magnetic memory unit has a rectangular shape, and the first data write current line is arranged to form a predetermined angle with the long side direction of each magnetic memory unit.

  Alternatively, more preferably, the second data write current line is provided to be orthogonal to the easy axis direction. The second data write magnetic field has a direction corresponding to the level of stored data.

  More preferably, the first and second data write current lines are provided in directions orthogonal to each other.

  In particular, in such a configuration, the sum of the currents that flow through the first data write current line to write the storage data to at least one selected memory cell is the current that flows through the second data write current line. Smaller than the sum of

  Alternatively, more preferably, the first data write magnetic field is applied in the same direction regardless of the level of stored data, and the second data write magnetic field is applied in a direction according to the level of stored data.

  Preferably, the magnetic memory portion is formed on the side opposite to the insulating layer, and is magnetized in a direction opposite to the second magnetic layer, and the second and third magnetic bodies. And a nonmagnetic intermediate layer formed between the layers.

  2. The thin film magnetic memory device according to claim 1, wherein the two free magnetic layers are efficiently looped by a data write current flowing through an intermediate layer sandwiched between the second and third magnetic layers which are free magnetic layers. Can be magnetized. The magnetic flux generated by the magnetization of one free magnetic layer acts as a magnetic flux for magnetizing the other free magnetic layer. As a result, the data write current required for rewriting the magnetization direction of the free magnetic layer can be reduced, so that both reduction in memory cell size, reduction in power consumption, and suppression of magnetic noise can be achieved.

  The thin film magnetic memory device according to claims 2 and 3 can efficiently supply the data write current, in addition to the effect exhibited by the thin film magnetic memory device according to claim 1.

  5. The thin film magnetic memory device according to claim 4, wherein a plurality of memory cells are arranged in a matrix using first and second data write lines corresponding to one of each of a bit line and a write word line. Data writing can be executed by selecting one of these.

  According to a fifth aspect of the present invention, there is provided a thin film magnetic memory device comprising: a magnetic memory portion corresponding to a tunnel magnetoresistive element; and an access element corresponding to an access transistor, in addition to the effects exhibited by the thin film magnetic memory device according to the fourth aspect. Since there is no need to provide a wiring layer between them, it is easy to form a via hole for electrically coupling the two, and the manufacturing process can be simplified.

  The thin film magnetic memory device according to claim 6 can form a data read current supply line by using the intermediate layer in addition to the effect of the thin film magnetic memory device according to claim 1.

  The thin film magnetic memory device according to the seventh aspect can perform data reading by detecting the voltage of the read data line corresponding to the read bit line in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect.

  The thin-film magnetic memory device according to claim 8 can simplify the direction of the data write current in the data line according to the level of the write data, in addition to the effect exhibited by the thin-film magnetic memory device according to claim 1. Can be controlled.

  11. The thin film magnetic memory device according to claim 9, wherein in the second and third magnetic layers that are free magnetic layers, the magnetic flux generated by the magnetization of one free magnetic layer magnetizes the other free magnetic layer. It acts as a magnetic flux to do. Therefore, since the data write current required for rewriting the magnetization direction of the free magnetic layer can be reduced, it is possible to simultaneously reduce the memory cell size, reduce power consumption, and suppress magnetic noise. Furthermore, since it is not necessary to consider the electrical interference between the memory cells in the intermediate layer, the degree of freedom in shape increases. Therefore, the manufacturing process is facilitated and the yield is improved.

  The thin film magnetic memory device according to the eleventh aspect of the invention can efficiently perform data writing using the global / local data lines provided in a hierarchical manner.

  The thin film magnetic memory device according to claim 12 has a small data write current required for rewriting the magnetization direction of the magnetic memory portion in addition to the effect exhibited by the thin film magnetic memory device according to claim 11. Therefore, it is possible to reduce power consumption and suppress magnetic noise.

  The thin film magnetic memory device according to claim 13 has the effect of the thin film magnetic memory device according to claim 11 in addition to the direction of the data write current in the local data line according to the level of the write data. Easy to control.

  The thin film magnetic memory device according to claim 14 is a complementary type having a large operation margin based on a voltage comparison between two data lines forming a pair, in addition to the effect exhibited by the thin film magnetic memory device according to claim 11. Data reading can be executed.

  The thin film magnetic memory device according to claim 15 has the effect of writing data to a local data line arranged based on the open bit line configuration in addition to the effect exhibited by the thin film magnetic memory device according to claim 11. The direction of the current can be easily controlled according to the level of the write data.

  The thin film magnetic memory device according to claim 16 is a complementary type having a large operation margin based on a voltage comparison of two data lines forming a pair, in addition to the effect exhibited by the thin film magnetic memory device according to claim 15. Data reading can be executed.

  The thin film magnetic memory device according to claim 17 can secure the wiring pitch of the global data line and sufficiently secure the wiring width, that is, the cross-sectional area, in addition to the effect exhibited by the thin film magnetic memory device according to claim 11. . As a result, the current density of the global data line can be suppressed and the occurrence of electromigration or the like can be suppressed, so that the operational stability of the thin film magnetic memory device can be improved.

  In the thin film magnetic memory device according to the eighteenth and nineteenth aspects, the data write can be executed by selectively passing the data write current only to the intermediate layer corresponding to the selected memory cell. Therefore, occurrence of erroneous data writing in unselected memory cells can be prevented.

  The thin film magnetic memory device according to claim 20 has the selection memory by sharing the first and second data lines used for data writing in addition to the effect exhibited by the thin film magnetic memory device according to claim 19. Data can be read from the cell.

  The thin-film magnetic memory device according to claim 21 uses the diode as a read access element in addition to the effect exhibited by the thin-film magnetic memory device according to claim 19. Therefore, the MTJ memory cell can be reduced in size. .

  29. The thin film magnetic memory device according to claim 22, wherein the second magnetic layer (free magnetic layer) in the magnetic memory portion (tunnel magnetoresistive element) has a magnetization characteristic in a direction along the easy magnetization axis. Can be made symmetric without depending on the level of the write data. As a result, it is possible to suppress the data write current necessary for writing the stored data. As a result, it is possible to reduce the power consumption in the MRAM device and improve the operation reliability by reducing the current density in the data write current line.

  The thin film magnetic memory device according to claim 26 and 27 has a data write current required for writing stored data to the selected memory cell in addition to the effect exhibited by the thin film magnetic memory device according to claim 23. However, when the first and second data write current lines differ greatly, the power consumption in the MRAM device can be further reduced.

  The thin-film magnetic memory device according to claim 29 has the same effect as that of the thin-film magnetic memory device according to claim 22 in a two-layer storage node configuration capable of reducing a data write current required for rewriting the magnetization direction. It can also be enjoyed for MTJ memory cells.

It is a schematic block diagram which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. FIG. 2 is a conceptual diagram illustrating a configuration example of a memory array illustrated in FIG. 1. FIG. 3 is a conceptual diagram showing a configuration example of an MTJ memory cell having the two-layer storage node structure shown in FIG. It is a conceptual diagram explaining the magnetization direction of the free magnetic layer at the time of data writing. It is a conceptual diagram which shows the other structural example of the MTJ memory cell which has a two-layer storage node structure. 4 is a block diagram showing another configuration example of the memory array 10. FIG. 4 is a block diagram showing still another configuration example of the memory array 10. FIG. FIG. 8 is a structural diagram illustrating a configuration of a memory cell illustrated in FIG. 7. FIG. 11 is a structural diagram showing still another configuration of an MTJ memory cell having a two-layer storage node structure. FIG. 7 is a schematic diagram showing a configuration of a memory array according to a second embodiment. FIG. 11 is a circuit diagram showing a configuration of a memory block MBa shown in FIG. 10. FIG. 11 is a circuit diagram showing a configuration of a memory block MBb according to a first modification of the second embodiment. FIG. 14 is a conceptual diagram illustrating a state of generation of a data write magnetic field in a memory block according to a first modification of the second embodiment. FIG. 11 is a schematic diagram showing a configuration of a memory array according to a second modification of the second embodiment. FIG. 16 is a schematic diagram showing a configuration of a memory array according to a third modification of the second embodiment. FIG. 16 is a circuit diagram illustrating a configuration of a memory block MBb illustrated in FIG. 15. FIG. 22 is a block diagram showing a configuration of a memory array according to a fourth modification of the second embodiment. FIG. 18 is a circuit diagram illustrating a configuration of a memory block MBd shown in FIG. 17. FIG. 16 is a block diagram showing a configuration of a memory array 10 according to a fifth modification of the second embodiment. A configuration of an MTJ memory cell having a single-layer storage node structure is shown. It is a structural diagram showing a configuration of a conventional MTJ memory cell having a two-layer storage node structure. FIG. 14 is a circuit diagram showing a configuration of a memory block MBe according to the third embodiment. FIG. 16 is a circuit diagram showing a configuration of a memory block MBf according to a first modification of the third embodiment. FIG. 17 is a conceptual diagram illustrating a state of generation of a data write magnetic field in a memory block according to a first modification of the third embodiment. FIG. 16 is a circuit diagram showing a configuration of a memory block MBg according to a second modification of the third embodiment. FIG. 22 is a circuit diagram showing a configuration of a memory block MBh according to a third modification of the third embodiment. FIG. 16 is a conceptual diagram showing a configuration of an MTJ memory cell having a two-layer storage configuration according to the fourth embodiment. FIG. 28 is a conceptual diagram showing how a data write magnetic field is generated in the MTJ memory cell shown in FIG. 27. FIG. 28 is a block diagram showing a configuration of a memory array in which MTJ memory cells shown in FIG. 27 are arranged in a matrix. FIG. 16 is a circuit diagram showing a configuration of a memory array according to a first modification of the fourth embodiment. FIG. 22 is a conceptual diagram illustrating a hierarchical word line configuration according to a second modification of the fourth embodiment. FIG. 22 is a conceptual diagram illustrating a hierarchical word line configuration according to a third modification of the fourth embodiment. FIG. 10 is a block diagram showing a configuration of a memory array according to a fifth embodiment. FIG. 10 is a conceptual diagram illustrating the structure of an MTJ memory cell according to a fifth embodiment. FIG. 17 is an operation waveform diagram illustrating data reading and data writing operations for an MTJ memory cell according to the fifth embodiment. FIG. 22 is a block diagram showing a configuration of a memory array according to a first modification of the fifth embodiment. FIG. 16 is a conceptual diagram illustrating a structure of an MTJ memory cell according to a first modification of the fifth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array according to a second modification of the fifth embodiment. FIG. 16 is a conceptual diagram illustrating the structure of an MTJ memory cell according to a second modification of the fifth embodiment. FIG. 32 is an operation waveform diagram illustrating data read and data write operations on an MTJ memory cell according to the second modification of the fifth embodiment. FIG. 25 is a block diagram showing a configuration of a memory array according to a third modification of the fifth embodiment. FIG. 16 is a conceptual diagram illustrating a structure of an MTJ memory cell according to a third modification of the fifth embodiment. FIG. 29 is an operation waveform diagram illustrating data read and data write operations on an MTJ memory cell according to the third modification of the fifth embodiment. FIG. 17 is a conceptual diagram showing the direction of a data write magnetic field according to the sixth embodiment. It is a conceptual diagram which shows arrangement | positioning of the tunnel magnetoresistive element according to Embodiment 6. FIG. 22 is a conceptual diagram showing the direction of a data write magnetic field according to a modification of the sixth embodiment. FIG. 17 is a conceptual diagram showing the arrangement of tunnel magnetoresistive elements according to a modification of the sixth embodiment. 3 is a conceptual diagram showing a configuration of a MTJ memory cell and a data read operation. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the direction of the data write current and the magnetization direction at the time of data writing to the MTJ memory cell. It is sectional drawing which shows the structure of the conventional tunnel magnetoresistive element comprised with two free magnetic layers. FIG. 52 is a hysteresis diagram for explaining magnetization in the tunneling magneto-resistance element shown in FIG. 51. It is a conceptual diagram explaining the nonuniformity of the magnetization characteristic in the MTJ memory cell of a single layer storage node structure. FIG. 54 is a hysteresis diagram for explaining the magnetization characteristics in the free magnetization layer shown in FIG. 53. It is a conceptual diagram explaining the nonuniformity of the magnetization characteristic in the MTJ memory cell of a two-layer storage node structure. FIG. 56 is a hysteresis diagram for explaining the magnetization characteristics in the free magnetization layer shown in FIG. 55.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the same or an equivalent part.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT.

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix. The configuration of the memory array 10 will be described in detail later. A plurality of write word lines WWL and read word lines RWL are arranged corresponding to the MTJ memory cell rows (hereinafter also simply referred to as “memory cell rows”). The Bit lines BL and source lines SL are arranged corresponding to the MTJ memory cell columns (hereinafter also simply referred to as “memory cell columns”).

  The MRAM device 1 further includes a row decoder 20, a column decoder 25, a word line driver 30, a word line current control circuit 40, and read / write control circuits 50 and 60.

  Row decoder 20 performs row selection in memory array 10 in accordance with row address RA indicated by address signal ADD. Column decoder 25 performs column selection in memory array 10 in accordance with column address CA indicated by address signal ADD. The word line driver 30 selectively activates the read word line RWL or the write word line WWL based on the row selection result of the row decoder 20. A memory cell (hereinafter also referred to as “selected memory cell”) designated as a data read or data write target is indicated by row address RA and column address CA.

  The word line current control circuit 40 is provided for supplying a data write current to the write word line WWL during data writing. Read / write control circuits 50 and 60 are arranged in a region adjacent to memory array 10 in order to pass a data write current and a sense current (data read current) through bit line BL during data read and data write. This is a general term for circuit groups to be used.

FIG. 2 is a conceptual diagram showing the configuration of the memory array 10.
Referring to FIG. 2, memory array 10 includes MTJ memory cells MCa having a two-layer storage node structure arranged in n rows × m columns (n, m: natural numbers). Memory cell MCa includes an access transistor ATR and a tunnel magnetoresistive element 100a.

  Corresponding to the memory cell rows, read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are provided, respectively. Bit lines BL1 to BLm and source lines SL1 to SLm are provided corresponding to the memory cell columns, respectively. Each of source lines SL1 to SLm is coupled to the source side of access transistor ATR in the corresponding memory cell row and supplies ground voltage VSS.

  The word line current control circuit 40 couples each write word line WWL to the ground voltage VSS in a region opposite to the word line driver 30 across the memory array 10. Thereby, data write current Ip in a fixed direction can be supplied to the write word line selectively coupled to power supply voltage VDD by word line driver 30.

  FIG. 2 shows read word lines RWL1, RWL2, RWLn, write word lines WWL1, WWL2, WWLn, and bit lines BL1, BLm corresponding to the first, second and nth rows and the first and mth columns. In addition, source lines SL1 and SLm and a part of memory cells corresponding thereto are typically shown.

FIG. 3 is a conceptual diagram showing a configuration example of the MTJ memory cell MCa shown in FIG.
Referring to FIG. 3, tunneling magneto-resistance element 100 a includes an antiferromagnetic material layer 101, a fixed magnetization layer 102, free magnetization layers 103 and 104, a tunnel barrier 105, and an intermediate layer 107.

  The fixed magnetization layer 102 has a fixed magnetization direction and is formed on the antiferromagnetic material layer 101. The antiferromagnetic material layer 101 is disposed to more strongly fix the magnetization direction of the fixed magnetization layer 102. The tunnel barrier 105 is formed between the fixed magnetic layer 102 and the free magnetic layer 103. Free magnetic layers 103 and 104 are arranged so as to sandwich intermediate layer 107 having magnetically neutral characteristics. The intermediate layer 107 is formed of a nonmagnetic conductor.

  The shape and electrical characteristics of the intermediate layer 107 can be freely determined. In the structure according to the first embodiment, bit line BL is formed using intermediate layer 107. That is, the intermediate layer 107 is arranged as a metal wiring formed in a stripe shape extending in the column direction so that the intermediate layers 107 are electrically coupled to each other between MTJ memory cells belonging to the same memory cell column. As a result, the bit line BL is formed.

  At the time of data writing, a data write current ± Iw whose direction changes according to the level of the write data flows through the intermediate layer 107 (bit line BL). On the other hand, a data write current Ip in a certain direction flows through write word line WWL arranged along the row direction regardless of the level of the write data.

  A magnetic field in the easy axis (EA: Easy Axis) direction is applied to free magnetic layers 103 and 104 by a data write magnetic field generated by a write current ± Iw flowing through intermediate layer 107 (bit line BL). . On the other hand, a magnetic axis of a hard axis (HA) is applied by a data write magnetic field generated by the data write current Ip flowing through the write word line WWL.

  FIG. 4 is a conceptual diagram illustrating the magnetization direction of the free magnetic layer at the time of data writing. 4 corresponds to the PQ cross-sectional view in FIG.

  4A and 4B, the direction of data write current ± Iw flowing through intermediate layer 107 (bit line BL) varies depending on the level of write data.

  FIG. 4A shows a case where a positive data write current + Iw is passed through the intermediate layer 107 (bit line BL). When data write current Ip is also passed through corresponding write word line WWL, the magnetization directions of free magnetic layers 103 and 104 are rewritten in response to the data write magnetic field generated by data write current + Iw.

  At this time, the free magnetic layers 103 and 104 are formed in a layered shape with the nonmagnetic intermediate layer 107 interposed therebetween, so that both can be efficiently looped by the magnetic field generated by the data write current flowing through the intermediate layer 107. It can be magnetized. The magnetic flux generated by the magnetization of one free magnetic layer acts as a magnetic flux for magnetizing the other free magnetic layer.

  Thereby, the data write current required for generating the switching magnetic field strength of free magnetic layers 103 and 104 can be reduced. Further, since the magnetic flux does not spread to the outside, it is possible to suppress adverse effects on other memory cells.

  On the other hand, the magnetization direction of the fixed magnetization layer 102 is fixed in a certain direction. Therefore, as a result of data writing by the data write current + Iw, the magnetization directions of the fixed magnetic layer 102 and the free magnetic layer 103 are reversed, so that the electric resistance value of the tunnel magnetoresistive element 100a is increased.

  On the other hand, FIG. 4B shows a case where a negative data write current −Iw is supplied to the intermediate layer 107 (bit line BL). In this case, the free magnetic layers 103 and 104 are magnetized in the opposite direction to the case of FIG. Note that the data write current Ip flowing through the write word line WWL is maintained in a constant direction regardless of the level of the write data, as already described.

  Therefore, in the memory cell in which data writing is executed by the data write current −Iw, the magnetization directions of the fixed magnetic layer 102 and the free magnetic layer 103 are aligned. As a result, the electrical resistance value of the tunnel magnetoresistive element 100a becomes small.

  As described above, the magnetization directions of the free magnetic layers 103 and 104 can be changed only in the MTJ memory cell in which the data write current is supplied to both the corresponding write word line WWL and the intermediate layer 107 (bit line BL). In other words, the material and thickness of free magnetic layers 103 and 104 are determined so that data writing is executed.

  In the tunnel magnetoresistive element in the MTJ memory cell according to the first embodiment, unlike the conventional tunnel magnetoresistive element shown in FIG. 51, it is not necessary to increase or decrease the magnetic moment of free magnetic layers 103 and 104. . Accordingly, each of the free magnetic layers 103 and 104 can be formed with the same material and the same thickness. Thereby, complication of a manufacturing process can be avoided.

  Referring again to FIG. 3, access transistor ATR includes source / drain regions 111 and 112, which are n-type regions formed on P-type substrate 110, and gate electrode 113. Source / drain region 111 is electrically coupled to ground voltage VSS.

  The read word line RWL is arranged by extending the gate electrode 113 in the row direction so that the gate electrodes 113 are electrically coupled to each other between MTJ memory cells belonging to the same memory cell row. The That is, in response to activation (H level) of read word line RWL, access transistor ATR is turned on.

  Tunneling magneto-resistance element 100a and source / drain region 112 of access transistor ATR are electrically coupled through barrier metal 108 and via hole 115. The barrier metal 108 is a buffer material for obtaining an electrical contact with the antiferromagnetic material 101.

  At the time of data reading, by activating (H level) read word line RWL, bit line BL can be pulled down to ground voltage VSS via the electric resistance of tunneling magneto-resistance element 100a. As already described, since the electric resistance value of the tunnel magnetoresistive element 100a changes according to the relative relationship of the magnetization directions of the free magnetic layer 103 and the fixed magnetic layer 102, the bit is changed according to the storage data of the MTJ memory cell. The voltage change behavior of the line BL is different.

  Therefore, a voltage change corresponding to the storage data level of the MTJ memory cell MCa occurs in the bit line BL. Therefore, the storage data of the MTJ memory cell MCa is detected by detecting the voltage of the bit line BL when the sense current flows. Can be read out.

  As described above, the free magnetic layer 104 is provided to be magnetized in a loop with the free magnetic layer 103 at the time of data writing, but has no electrical effect at the time of data writing and data reading. . Therefore, the free magnetic layer 104 may be arranged as an isolated element for each MTJ memory cell as shown in FIG. 3, or may be arranged in a stripe pattern with the same pattern as the bit line BL.

  With such a configuration, in the memory array shown in FIG. 2, a data write current is supplied to each of the write word line WWL and bit line BL corresponding to the selected memory cell, and at the time of data reading, a selection is made. Data writing and data reading can be executed by activating the write word line RWL corresponding to the memory cell and detecting the voltage of the bit line BL.

  FIG. 5 is a conceptual diagram showing another configuration example of an MTJ memory cell having a two-layer storage node structure.

  Referring to FIG. 5, MTJ memory cell MCb having a two-layer storage node structure has write word line WWL from tunneling magneto-resistance element 100a and bit line BL as compared with MTJ memory cell MCa shown in FIG. Are different in that they are arranged in the upper layer. Since the configuration of other parts is the same as that of FIG. 3, detailed description will not be repeated. Therefore, data writing and data reading with respect to memory cell MCb can be performed in the same manner as memory cell MCa.

  With such a configuration, it is not necessary to provide a wiring layer between the tunnel magnetoresistive element 100a and the access transistor ATR, so that the distance between the two can be shortened. As a result, since the aspect ratio (vertical / horizontal dimension ratio) of the via hole 115 can be reduced, the formation of the via hole 115 is facilitated, and the manufacturing process can be simplified.

  FIG. 6 is a block diagram illustrating another configuration example of the memory array 10. 6 can be applied to any of the MTJ memory cells MCa and MCb shown in FIGS. 2 and 5, respectively.

  Referring to FIG. 6, a bit line pair is arranged corresponding to each memory cell column. The bit line pair BLP is composed of two complementary bit lines. In FIG. 6, bit line pairs BLP1 and BLPm in the first column and the m-th column are representatively shown. Bit line pair BLP1 includes bit lines BL1 and / BL1, and bit line pair BLPm includes bit lines BLm and / BLm. Hereinafter, the bit line pairs BLP1 to BLPm are also collectively referred to as bit line pairs BLP. Similarly, bit lines / BL1 to / BLm are also collectively referred to as bit lines / BL. Bit lines BL and / BL are formed using intermediate layer 107.

  MTJ memory cells are coupled to either one of bit lines BL and / BL every other row. For example, the memory cells belonging to the first column will be described. The memory cells in the first row are coupled to the bit line BL1, and the memory cells in the second row are coupled to the bit line / BL1. Similarly, each of the memory cells is connected to one of the bit line pairs BL1 to BLm in the odd-numbered row and is connected to each other of / BL1 to / BLm in the other bit line pair in the even-numbered row. As a result, when read word line RWL is selectively activated according to the row selection result, one of bit line pairs BL1 to BLm and the other of bit line pairs / BL1 to / BLm are either memory cells. Combined with.

  Column decoder 25 activates any one of column selection signals YS1 to YSm corresponding to each memory cell column to a selected state (H level) according to the decoding result of column address CA. Data bus pair DBP for transmitting read data and write data has complementary data buses DB and / DB.

  Read / write control circuit 50 includes column select gates CSG1 to CSGm, a data write circuit 51W, and a data read circuit 51R.

  Column selection gates CSG1 to CSGm are arranged between bit line pairs BLP1 to BLPm and data bus pair DBP, respectively. Each of column select gates CSG1-CSGm is electrically connected between a transistor switch electrically coupled between data bus DB and corresponding bit line BL, and between bit line / BL corresponding to data bus / DB. And a transistor switch coupled to the. These transistor switches are turned on in response to activation of the corresponding column selection signal.

  For example, column select gate CSG1 is electrically coupled between data bus DB and bit line BL1, and is turned on in response to activation of column select signal YS1, data bus / DB and bit line / And a transistor switch electrically coupled to BL1 and turned on in response to activation of column selection signal YS1.

  Corresponding to bit line pairs BLP1 to BLPm, short-circuit transistors EQT1 to EQTm and control signals EQS1 to EQSm for electrically coupling corresponding complementary bit lines are provided. Control signals EQS1 to EQSm are activated to H level when a corresponding memory cell column is selected as a data writing target during data writing. Hereinafter, the short-circuit transistors EQT1 to EQTm are collectively referred to as a short-circuit transistor EQT.

  Each short-circuit transistor EQT electrically couples corresponding bit lines BL and / BL when corresponding one of control signals EQS1-EQSm is activated to H level. Alternatively, instead of each of control signals EQS1 to EQSm, control signal WE activated (H level) at the time of data writing can be used.

  Data write circuit 51W sets data buses DB and / DB to one of power supply voltage VDD and ground voltage VSS according to write data DIN during data writing. Further, at the time of data writing, at least in the selected memory cell column, short circuit transistor EQT is turned on, so that the selected memory is selected according to the voltage difference between data buses DB and / DB set by data write circuit 51W. A data write current flows as a round trip current through bit lines BL and / BL of the cell column. On the other hand, data write current Ip in a fixed direction independent of the level of write data is supplied to write word line WWL corresponding to the selected memory cell row.

  With such a configuration, at the time of data writing, data writing that flows through the bit line BL (/ BL) can be performed simply by changing the voltage setting of the data buses DB and / DB in accordance with the level of the write data DIN. The direction of the current ± Iw can be easily controlled. That is, the configuration of the data write circuit 51W can be simplified.

Next, the data read operation will be described.
At the time of data reading, one of data buses DB and / DB can be pulled down to ground voltage VSS via corresponding bit line BL or / BL and tunneling magneto-resistance element 100a in the selected memory cell. . As a result, a voltage change corresponding to the storage data level of the selected memory cell occurs in the data bus DB or / DB connected to the selected memory cell. Data read circuit 51R generates read data DOUT according to the voltages of data buses DB and / DB.

  Alternatively, a dummy memory cell (not shown) having an intermediate value between the electrical resistance values R0 and R1 of the MTJ memory cell is arranged in memory array 10, and the selected memory is connected to data buses DB and / DB during data reading. One of the cells and the dummy memory cells may be connected. In this case, data read circuit 51R can execute complementary data reading based on the voltage comparison of data buses DB and / DB, and therefore the operation margin is improved.

FIG. 7 is a circuit diagram showing still another configuration example of the memory array 10.
In the configuration shown in FIG. 7, memory cells MCc having a two-layer storage node structure are arranged in n rows × m columns. Further, a write bit line WBL for data writing and a read bit line RBL for data reading are arranged separately. On the other hand, the arrangement of the source lines SL is omitted.

  Write bit line WBL and read bit line RBL are arranged corresponding to the memory cell columns, respectively. FIG. 7 shows write bit lines WBL1 and WBLm and read bit lines RBL1 and RBLm, which typically correspond to the first column and the m-th column. When generically referring to read bit lines RBL1 to RBLm and generically referring to write bit lines WBL1 to WBLm, symbols RBL and WBL are used, respectively.

FIG. 8 is a structural diagram showing the configuration of the memory cell shown in FIG.
Referring to FIG. 8, MTJ memory cell MCc having a two-layer storage node structure further includes a read bit line RBL provided extending in the column direction as compared with MTJ memory cell MCa shown in FIG. It is different in point to be arranged.

  A write bit line WBL is formed using the intermediate layer 107. Data write current ± Iw is applied to write bit line WBL during data writing. On the other hand, at the time of reading data, read / write control circuits 50 and 60 set each write bit line WBL to ground voltage VSS.

  Read bit line RBL is electrically coupled to source / drain region 111 of access transistor ATR through via hole 116. In data reading, source / drain region 112 functions as a source of access transistor ATR.

  As a result, in response to the turn-on of access transistor ATR, a sense current path can be formed in read bit line RBL, access transistor ATR, tunneling magneto-resistance element 100a, and write bit line WBL (ground voltage VSS).

  Referring again to FIG. 7, data writing is executed by flowing data write currents Ip and ± Iw to write word line WWL and write bit line WBL corresponding to the selected memory cell, respectively.

  At the time of data reading, in response to activation of the read word line RWL corresponding to the selected memory cell, the read bit line RBL corresponding to the selected memory cell is connected to the ground voltage VSS via the tunnel magnetoresistive element 100a in the selected memory cell. Can be pulled down to As a result, a voltage change corresponding to the storage data level of the selected memory cell occurs on read bit line RBL, so that the storage data of the selected memory cell can be read.

  FIG. 9 is a structural diagram showing still another configuration of an MTJ memory cell having a two-layer storage node structure.

  9, MTJ memory cell MCd does not form bit line BL in intermediate layer 107, but provides bit line BL in an independent metal wiring layer as compared with MTJ memory cell MCb shown in FIG. The point is different.

  That is, in the configuration of FIG. 9, intermediate layer 107 is fixed to a fixed voltage, for example, ground voltage VSS. As a result, it is not necessary to consider electrical interference between the MTJ memory cells, and the intermediate layer 107 can be formed in either a plain shape or a stripe shape. That is, since the degree of freedom of the shape of the intermediate layer 107 is increased, the manufacturing process is facilitated and the yield is improved.

  Bit line BL extends in the column direction, and is electrically coupled to source / drain region 111 of access transistor ATR via via hole 116. On the other hand, source / drain region 112 of access transistor ATR is electrically coupled to tunneling magneto-resistance element 100a through via hole 115 and barrier metal 108.

  In data writing, free magnetic layers 103 and 104 can be magnetized in a direction according to write data DIN by flowing data write currents ± Iw and Ip through bit line BL and write word line WWL, respectively. it can. In the MTJ memory cell MCd, the materials and thicknesses of the free magnetic layers 103 and 104 are made different so as to increase and decrease the magnetic moment (magnetization threshold value) of the free magnetic layers 103 and 104.

  In data reading, by activating read word line RWL, bit line BL can be pulled down to ground voltage VSS via the electric resistance of tunneling magneto-resistance element 100a. As a result, the bit line BL changes in voltage according to the electrical resistance value of the tunnel magnetoresistive element, that is, the storage data level of the MTJ memory cell, so that the storage data of the selected memory cell can be read.

  As described above, according to the MTJ memory cell having the two-layer storage node structure according to the first embodiment, even when the memory cell size is reduced, an increase in the amount of data write current for generating the switching magnetic field strength can be suppressed. The memory cell can be easily scaled.

  In addition, for memory cells of the same size, the amount of data write current for generating the reversal magnetic field strength can be suppressed, so that power consumption can be reduced. In particular, since the data write current flows through the intermediate layer sandwiched between the two free magnetic layers, the reversal magnetic field strength can be obtained efficiently, so that data can be written with a smaller data write current, The current consumption can be further reduced.

  In addition, since the bit line is formed using the intermediate layer in the tunnel magnetoresistive element, the number of metal wiring layers required is reduced. For this reason, in particular, when a system-on-chip device is configured by mixing MRAM devices and logic etc., the number of metal wiring layers that can be used in the region above the MRAM array increases. It is possible to increase the chip size.

[Embodiment 2]
In the first embodiment, the configuration in which the bit line is formed using the intermediate layer in the tunnel magnetoresistive element has been described. However, since the thickness of the intermediate layer must be designed to be somewhat thin, if the bit line BL is arranged with the intermediate layer extending in the column direction, the electrical resistance value may be relatively large. As a result, the data reading speed may be reduced, and it may be difficult to supply a sufficient data write current.

  Therefore, in the second embodiment, the hierarchical bit line configuration is applied to the memory array in which the MTJ memory cells having the two-layer storage node structure described in the first embodiment are arranged.

FIG. 10 is a schematic diagram showing a configuration of memory array 10 according to the second embodiment.
Referring to FIG. 10, in the configuration according to the second embodiment, main bit line MBL and sub bit line SBL are arranged hierarchically corresponding to each memory cell column. Further, a main bit line / MBL complementary to the main bit line MBL and a sub bit line / SBL complementary to the sub bit line SBL are further arranged corresponding to the memory cell columns, respectively. Sub-bit lines SBL and / SBL are formed using intermediate layer 107 of tunneling magneto-resistance element 100a, similarly to bit line BL shown in FIGS. On the other hand, main bit lines MBL and / MBL are formed using metal wirings having a small electric resistance. Main bit lines MBL and / MBL constitute main bit line pair MBLP, and sub bit lines SBL and / SBL constitute sub bit line pair SBLP.

  In FIG. 10, main bit lines MBL1, / MBL1 and MBLm, / MBLm in the first column and the m-th column are representatively shown. Main bit lines MBL1 and / MBL1 constitute a main bit line pair MBLP1, and main bit lines MBLm and / MBLm constitute a main bit line pair MBLPm. Hereinafter, when the main bit lines MBL1 to MBLm and / MBL1 to / MBLm are generically referred to, they are also simply referred to as main bit lines MBL and / MBL. Further, when the main bit line pairs MBLP1 to MBLPm are collectively referred to, they are also simply referred to as main bit line pairs MBLP.

  Read / write control circuit 50 functions as a supply source of data write current ± Iw for main bit lines MBL and / MBL corresponding to the selected memory cell column. For example, read / write control circuit 50 has a configuration similar to that of FIG. 6, and each of main bit lines MBL and / MBL corresponding to the selected memory cell column is set in accordance with the data level of write data DIN. Are coupled to one of the power supply voltage VDD and the ground voltage VSS.

  Each memory cell column is divided into k memory blocks along the row direction. For example, the MTJ memory cell group belonging to the first column is divided into memory blocks MBa11 to MBak1, and similarly, the memory cell group belonging to the mth column is divided into memory blocks MBa1m to MBakm. In the entire memory array 10, memory blocks MBa11 to MBakm are arranged in a matrix of k rows × m columns. Hereinafter, when the memory blocks MBa11 to MBakm are generically referred to, they are also simply referred to as memory blocks MBa.

  In each memory cell column, sub bit line SBL is arranged for each memory block MBa. Further, sub bit line / SBL complementary to sub bit line SBL is arranged in each of memory blocks MBa. Sub-bit lines SBL and / SBL complementary to each other constitute sub-bit line pair SBLP. For example, in memory block MBa11, sub bit lines SBL11 and / SBL11 constituting sub bit line pair SBLP11 are arranged.

  In the following, when each of sub bit lines SBL11 to SBLkm and / SBL11 to / SBLkm are generically referred to, they are also simply referred to as sub bit lines SBL and / SBL.

  Block selection signals BS1 to BSk are provided corresponding to the rows of the memory blocks, respectively. Hereinafter, the block selection signals BS1 to BSk are collectively referred to simply as a block selection signal BS. Block selection signal BS is activated in the row of the memory block including the selected memory cell.

  That is, a specific memory block including the selected memory cell can be selected by selecting the block selection signal BS and the memory cell column (main bit line pair MBLP).

  FIG. 11 is a circuit diagram showing a configuration of the memory block MBa. Since the configuration of each memory block MBa is the same, FIG. 11 representatively shows the configuration of the memory block MBa11. Sub-bit lines SBL11 and / SBL11 are arranged in memory block MBa11.

  Referring to FIG. 11, a plurality of (for example, 3 rows) × 1 column memory cell groups are arranged in memory block MBa11.

  Hereinafter, in the second embodiment and its modification, a configuration example in which the number of memory cell rows included in each memory block is three is shown, but the application of the present invention is not limited to such a configuration, The number of memory cell rows corresponding to the memory block can be arbitrarily plural.

  Similar to the configuration shown in FIG. 6, in each memory cell column, MTJ memory cell MCa is connected to one of sub bit lines SBL11 and / SBL11 for each row. For example, MTJ memory cells MCa corresponding to odd rows are coupled to sub bit line SBL11, and MTJ memory cells MCa corresponding to even rows are coupled to sub bit line / SBL11.

  Hereinafter, in the second embodiment and its modification, the configuration in which the MTJ memory cell MCa is arranged in each memory block will be exemplified. However, the MTJ memory shown in FIGS. Cells MCb and MCd can also be applied.

  MTJ memory cell MCa includes an access transistor ATR and a tunnel magnetoresistive element 100a. Access transistor ATR is electrically coupled between tunneling magneto-resistance element 100a and ground voltage VSS. Access transistor ATR has its gate coupled to read word line RWL of the corresponding memory cell row.

  Since each of sub bit lines SBL11 and / SBL11 is divided for each memory block MBa, the wiring is shortened. As a result, the electric resistance value of each sub-bit line SBL formed using the intermediate layer 107 of the tunnel magnetoresistive element 100a can be suppressed.

  Memory block MBa11 further includes current switch transistors SWTa and SWTb and a short-circuit transistor EQT11.

  Current switch transistor SWTa is electrically coupled between main bit line MBL1 and one end of sub-bit line SBL11 (side closer to read / write control circuit 50). Similarly, current switch transistor SWTb electrically couples main bit line / MBL1 and one end (side closer to read / write control circuit 50) of sub bit line / SBL11. Block selection signal BS1 is input to the gates of current switch transistors SWTa11 and SWTb11.

  Short-circuit transistor EQT11 electrically couples the other ends (side far from read / write control circuit 50) of sub-bit lines SBL11 and / SBL11 in response to write selection signal WMB11.

  Write selection signal WMB11 is activated to H level at least when block selection signal BS1 is activated during data writing. Alternatively, the column selection result is further added to activate H level when block selection signal BS1 is activated and the memory cell column corresponding to main bit line pair MBLP1 is selected at the time of data writing. .

  When memory block MBa11 is a data write target, each of short circuit transistor EQT11 and current switch transistors SWTa and SWTb is turned on. As a result, read / write control circuit 50 switches the voltage polarities (power supply voltage VDD and ground voltage VSS) of main bit lines MBL1 and / MBL1, thereby writing data in the direction corresponding to the level of write data DIN. Current ± Iw can be supplied as a round-trip current folded by short-circuit transistor EQT11 in sub-bit lines SBL11 and / SBL11. Therefore, the configuration of read / write control circuit 50 which is a supply source of data write current ± Iw can be simplified.

  Further, write word line WWL corresponding to the selected memory cell is selectively activated to receive supply of data write current Ip. Thereby, the write data DIN can be written to the selected memory cell.

  On the other hand, when memory block MBa11 is selected as a data read target, current switch transistors SWTa and SWTb are turned on, while short circuit transistor EQT11 is turned off. Thus, sub bit lines SBL11 and / SBL11 are electrically coupled to main bit lines MBL1 and / MBL1, respectively.

  In the configuration according to the second embodiment, so-called complementary data reading using dummy memory cell DMC is performed. Dummy memory cells DMC for executing complementary data reading are arranged corresponding to main bit lines MBL and / MBL. FIG. 11 representatively shows a dummy memory cell provided corresponding to main bit line MBL1, and a dummy memory cell provided corresponding to main bit line / MBL1.

  Each dummy memory cell DMC has an access transistor ATR and a dummy resistor Rd. The electric resistance value of the dummy resistor Rd is set to an intermediate value between the electric resistance values R1 and R0 of the MTJ memory cell corresponding to the stored data levels “1” and “0”, that is, R1 <Rd <R0.

  A dummy memory cell corresponding to main bit line MBL1 is electrically coupled between ground voltage VSS and main bit line MBL1 in response to activation of dummy word line DWL0. On the other hand, the dummy memory cell arranged corresponding to main bit line / MBL1 is electrically coupled between main bit line / MBL1 and ground voltage VSS in response to activation of dummy word line DWL1. .

  Dummy word lines DWL0 and DWL1 are selectively activated according to whether the selected memory cell belongs to an odd row or an even row. That is, when the selected memory cell belongs to an odd row, that is, when the selected memory cell is electrically coupled to main bit line MBL1, in order to electrically couple dummy memory cell DMC to main bit line / MBL1 The dummy word line DWL1 is activated. On the other hand, when the selected memory cell belongs to an even row, dummy word line DWL0 is activated to electrically couple dummy memory cell DMC with main bit line MBL.

  Thereby, at the time of data reading, one of each of the selected memory cell and dummy memory cell DMC is electrically coupled to complementary main bit lines MBL1 and / MBL1. Therefore, the data stored in the selected memory cell can be read by detecting the voltage difference between main bit lines MBL1 and / MBL1.

  Each sub-bit line SBL, / SBL has a short wiring and its electric resistance value is small. Therefore, the MTJ memory cell having the two-layer storage node structure according to the first embodiment is used to reduce power consumption during data writing. Even if it is the structure which aims at, the fall of a data reading speed is not caused.

[Modification 1 of Embodiment 2]
For the first modification of the second embodiment, a hierarchical sub-bit line configuration capable of efficiently supplying a data write current will be described.

FIG. 12 is a circuit diagram showing a configuration of a memory block according to the first modification of the second embodiment.
In the configuration according to the first modification of the second embodiment, memory blocks MBb11 to MBbkm are arranged instead of the memory blocks MBa11 to MBakm in the configuration of the memory array 10 shown in FIG. Since each of memory blocks MBb11-MBbkm has the same configuration, FIG. 12 representatively shows the configuration of memory block MBb11.

  Referring to FIG. 12, memory block MBb11 is different from memory block MBa11 shown in FIG. 11 in that the arrangement positions of short-circuit transistor EQT11 and current switch transistors SWTa and SWTb are interchanged.

  In memory block MBb11, short-circuit transistor EQT11 connects one ends of sub-bit lines SBL11 and / SBL11 closer to the read / write control circuit 50. Similarly, current switch transistor SWTa is electrically coupled between the other end of sub bit line SBL11 on the side far from read / write control circuit 50 and main bit line MBL1, and current switch transistor SWTb is connected to sub bit line SBLb. / SBL11 is electrically coupled between the other end (the side far from read / write control circuit 50) and main bit line / MBL1.

  With such a configuration, at the time of data writing, data write current ± Iw flows in the opposite direction in each of main bit line MBL1 and sub bit line SBL11. Similarly, data write current ± Iw flows in the opposite direction between main bit line / MBL1 and sub bit line / SBL11.

  FIG. 13 is a conceptual diagram illustrating a state of generation of a data write magnetic field in the memory block according to the first modification of the second embodiment.

  FIG. 13A shows the state of the data write magnetic field when the data write current + Iw in the positive direction is supplied to the sub bit line SBL (/ SBL). In this case, since the data write current flows through main bit line MBL (/ MBL) in the opposite direction, the data write current flowing through sub bit line SBL (/ SBL) and main bit line MBL (/ MBL) respectively. Thus, the data write magnetic fields generated thereby strengthen each other in the free magnetic layer 104. Since the magnetic flux generated by the magnetization of the free magnetic layer 104 acts as a magnetic flux for magnetizing the other free magnetic layer 103, the switching magnetic field strength can be generated by a smaller data write current.

  FIG. 13B shows the state of the data write magnetic field when the negative data write current −Iw is supplied to the sub bit line SBL (/ SBL). Also in this case, as in the case of FIG. 13A, the data write magnetic fields acting on the free magnetic layer 104 reinforce each other, so that data write to the MTJ memory cell can be performed with a smaller data write current. Can be executed.

  Referring to FIG. 12 again, the configuration of the other parts of memory block MBb11 is similar to that of memory block MBa11 shown in FIG. 11, and therefore details thereof will not be repeated. That is, the data read operation in the configuration according to the first modification of the second embodiment can be performed in the same manner as the memory block MBa according to the second embodiment.

[Modification 2 of Embodiment 2]
In the second modification of the second embodiment, a configuration in which a main bit line is arranged for each of a plurality of memory cell columns will be described.

FIG. 14 is a schematic diagram showing a configuration of a memory array according to the second modification of the second embodiment.
Referring to FIG. 14, in each of memory blocks MBb11-MBbkm arranged in a matrix, sub-bit lines SBL and / SBL constituting sub-bit line pair SBLP are independently provided. Each main bit line pair MBLP is arranged for each of a plurality of memory cell columns. FIG. 12 shows a configuration in which main bit line pair MBLP is arranged for every two memory cell columns as an example. Therefore, in the entire memory array 10, h (h: integer of h = m / 2) main bit line pairs MBLP1 to MBLPh are arranged. Arrangement of dummy memory cells DMC for each main bit line MBL is the same as that in FIG.

  Main bit line pair MBLP1 is shared by memory blocks MBb11-MBbk1 and memory blocks MBb12-MBbk2.

  In FIG. 12, block selection signal BS1 input to the gates of current switch transistors SWTa and SWTb is subdivided in order to select between a plurality of memory cells corresponding to the same main bit line pair.

  In the configuration of FIG. 14, block selection signal BS1 is divided into block selection signals BS1A and BS1B. The block selection signal BS1A is activated when the memory block in the first row is selected and the selected memory cell belongs to an odd column. On the other hand, the block selection signal BS1B is activated when the memory block in the first row is selected and the selected memory cell belongs to an even column. That is, one of block select signals BS1A and BS1B corresponding to the same memory block row is activated depending on whether the selected memory cell belongs to an even column or an odd column.

  Block selection signals BS1A to BSkA are transmitted to memory blocks MBa11 to MBak1, respectively, and block selection signals BS1B to BSkB are transmitted to memory blocks MBa12 to MBak2, respectively. A memory block including a selected memory cell can be designated by a combination of selection of the main bit line pair MBP and block selection signals BS1A, BS1B to BSkA, BSkB.

  With this configuration, the number of main bit lines arranged in the entire memory array 10 can be reduced. As a result, the wiring pitch of the main bit line can be secured.

  As a result, it is possible to sufficiently secure the wiring width, that is, the cross-sectional area of the main bit line through which a relatively large current flows during data writing, thereby reducing the current density. Therefore, the occurrence of electromigration or the like in the main bit line can be suppressed, and the operation reliability of the MRAM device can be improved.

  Furthermore, since the number of dummy memory cells can be reduced as the number of main bit lines is reduced, the chip area can be reduced.

[Modification 3 of Embodiment 2]
In the following modifications of the second embodiment, a case where each memory block has an open bit line configuration will be described.

FIG. 15 is a schematic diagram showing a configuration of a memory array according to the third modification of the second embodiment.
Referring to FIG. 15, in memory array 10 according to the third modification of the second embodiment, memory blocks MBc11 to MBckh are arranged in a matrix of k rows × h columns. Each of memory blocks MBc11-MBckh includes two memory cell columns. Therefore, if the number of memory cell rows and memory cell columns is the same as in the second embodiment, the number of memory blocks is half that in the second embodiment. In the following description, the memory blocks MBc11 to MBchk are collectively referred to simply as a memory block MBc.

  Main bit lines MBL1-MBLm are provided corresponding to the memory cell columns, respectively. In other words, each memory block MBc is associated with two main bit lines MBL that form a pair.

  In addition to block selection signals BS1 to BSk similar to those in FIG. 10, write selection signals WMB1A, WMB1B to WMBkA, WMBkB are provided. Write selection signals WMB1A, WMB1B to WMBkA, WMBkB are selectively activated according to which row of the memory block to which the selected memory cell belongs and whether the selected memory cell belongs to either the odd column or the even column. For example, write selection signal WMB1A is activated when the selected memory cell belongs to the row of the first memory block and belongs to the odd column. Similarly, write selection signal WMB1B is activated when the selected memory cell belongs to the row of the first memory block and belongs to the even column.

  FIG. 16 is a circuit diagram illustrating the configuration of memory block MBb shown in FIG. Since the configurations of the memory blocks MBc11 to MBckh are similar, the configuration of the memory block MBc11 is representatively shown in FIG.

  Referring to FIG. 16, memory block MBc11 has 3 × 2 memory cells. Sub-bit lines SBL11 and / SBL11 are arranged in memory block MBc11. MTJ memory cell MTa is arranged corresponding to both sub bit lines SBL11 and / SBL11 in each memory cell row.

  The memory block MBc11 further includes current switch transistors SWTa, SWTb, SWTc, and SWTd.

  Current switch transistor SWTa is electrically coupled between main bit line MBL1 and one end of sub bit line SBL11 on the side closer to read / write control circuit 50. Current switch transistor SWTb is electrically coupled between main bit line / MBL1 and one end of sub bit line / SBL11 (side closer to read / write control circuit 50). Block selection signal BS1 is input to the gates of current switch transistors SWTa and SWTb.

  Current switch transistor SWTc is electrically coupled between main bit line / MBL1 and the other end (side far from read / write control circuit 50) of sub-bit line SBL11. Current switch transistor SWTd is electrically coupled between main bit line MBL1 and the other end (the side far from read / write control circuit 50) of sub-bit line / SBL11. Write selection signals WMB1A and WMB1B are input to the gates of current switch transistors SWTc and SWTd, respectively.

Next, a data write operation in memory block MBc11 will be described.
When a memory cell connected to sub bit line SBL11 is selected as a data write target, block selection signal BS1 and write selection signal WMB1A are activated to H level, and current switch transistors SWTa, SWTb, SWTc are activated. Turn on. On the other hand, the current switch transistor SWTd is turned off. Thus, a current path is formed from main bit line MBL1 to current switch transistor SWTa to sub bit line SBL11 to current switch transistor SWTc to main bit line MBL2 (/ MBL1).

  Similarly, when a memory cell connected to sub bit line / SBL11 is selected as a data write target, block select signal BS1 and write select signal WMB1B are activated to H level, and current switch transistors SWTa, SWTb and SWTd are turned on. On the other hand, the current switch transistor SWTc is turned off. Thus, a current path is formed from main bit line MBL1 to current switch transistor SWTd to sub bit line / SBL11 to current switch transistor SWTb to main bit line MBL2 (/ MBL1).

  Further, the voltages of the paired main bit lines MBL1 and MBL2 corresponding to the memory block MBc11 are applied by the read / write control circuit 50 in the same manner as the complementary main bit lines MBL1 and / MBL1 in FIG. By setting, data write current ± Iw in the direction according to the data level of write data DIN can be supplied to sub bit line SBL11 or / SBL11.

  On the other hand, at the time of data reading, both current switch transistors SWTc and SWTd are turned off, while current switch transistors SWTa and SWTb are turned on. Therefore, a memory cell corresponding to the selected memory cell row is electrically coupled to each of main bit lines MBL1 and MBL2. As a result, the data stored in the selected memory cell can be read by detecting the voltage of the main bit line MBL corresponding to the selected memory cell column.

  By adopting such a configuration, even in a configuration in which sub bit lines and MTJ memory cells are arranged in each memory block based on an open bit line configuration, data writing and receiving effects similar to those of the second embodiment can be achieved. Data reading can be executed.

[Modification 4 of Embodiment 2]
FIG. 17 is a block diagram showing a configuration of memory array 10 according to the fourth modification of the second embodiment.

  Referring to FIG. 17, in the configuration according to the fourth modification of the second embodiment, memory blocks MBd11-MBdkh are arranged instead of memory blocks MBc11-MBckh, and the second embodiment shown in FIG. This is different from the configuration according to the third modification. Note that the memory blocks MBd11 to MBdkh are also collectively referred to as a memory block MBd.

  Further, the block selection signals BS1 to BSk are subdivided into block selection signals BS1A and BS1B to BSkA to BSkB reflecting the column selection results. Since the setting of block selection signals BS1A, BS1B to BSkA to BSkB has already been described, detailed description will not be repeated.

  FIG. 18 is a circuit diagram illustrating a configuration of memory block MBd shown in FIG. Since the configurations of the memory blocks MBd11 to MBdkh are the same, the configuration of the memory block MBd11 is also shown in FIG.

  Referring to FIG. 18, memory block MBd11 differs from memory block MBc11 shown in FIG. 16 in that it includes current switch transistors SWTc, SWTd, SWTe, and SWTf.

  Current switch transistor SWTc is electrically coupled between main bit line MBL2 and one end (side closer to read / write control circuit 50) of sub-bit line SBL1. Current switch transistor SWTd is electrically coupled between main bit line MBL1 and one end (side closer to read / write control circuit 50) of sub bit line / SBL1. Write selection signals WMB1A and WBM1B are applied to the respective gates of current switch transistors SWTc and SWTd.

  Current switch transistor SWTe is electrically coupled between main bit line MBL1 and the other end (side far from read / write control circuit 50) of sub-bit line SBL1. Current switch transistor SWTf is electrically coupled between main bit line MBL2 and the other end (side far from read / write control circuit 50) of sub-bit line / SBL1. Block selection signals BS1A and BS1B are applied to the respective gates of current switch transistors SWTe and SWTf.

Next, a data write operation in memory block MBd11 will be described.
When a memory cell connected to sub bit line SBL11 is selected as a data write target, block selection signals BS1A and WMB1A are activated, so that current switch transistors SWTc and SWTe are turned on. On the other hand, current switch transistors SWTd and SWTf are turned off. As a result, data write current ± Iw can be supplied to the current path of main bit line MBL1 through current switch transistor SWTe through sub bit line SBL11 through current switch transistor SWTc through main bit line MBL2 (/ MBL1).

  Therefore, in the configuration according to the fourth modification of the second embodiment, the data write magnetic field generated by the data write current ± Iw flowing in the opposite direction through each of main bit line MBL1 and sub bit line SBL11 is applied to the selected memory cell. .

  In this case, a data write magnetic field generated by data write current ± Iw flowing in the opposite direction through main bit line MBL2 (/ MBL1) and sub bit line / SBL11 is applied to the selected memory cell.

  Since the voltage setting of two main bit lines MBL1 and MBL2 corresponding to memory block MBd11 is the same as that of memory block MBc11 shown in FIG. 16, detailed description will not be repeated.

  As a result, at the time of data writing according to the fourth modification of the second embodiment, the data write magnetic field acting in the direction in which the free magnetic layer 104 in the tunnel magnetoresistive element 100a strengthens each other, as shown in FIG. Will be applied.

  Therefore, in addition to the effect enjoyed by the configuration according to the third modification of the second embodiment, the reversal magnetic field strength can be obtained in the free magnetic layer in the tunnel magnetoresistive element with a smaller data write current. It is possible to reduce power consumption by suppressing the incoming current.

  On the other hand, at the time of data reading, either one of block selection signals BS1A and BS1B is selectively activated according to which of the sub-bit lines SBL11 and / SBL11 corresponds to the selected memory cell. Write selection signals WMB1A and WMB1B are deactivated.

  Therefore, at the time of data reading, both current switch transistors SWTc and SWTd are turned off. On the other hand, current switch transistors SWTe and SWTf are selectively turned on according to whether the selected memory cell belongs to an odd column or an even column.

  By adopting such a configuration, one of the two main bit lines corresponding to the memory block including the selected memory cell corresponding to the selected memory cell is connected via the sub bit line SBL or / SBL. , The selected memory cell is electrically coupled.

  On the other hand, since the MTJ memory cell is not coupled to the other of the two main bit lines, the dummy memory cell DMC is coupled to form the complementary type as described in the second embodiment. Thus, the operation margin at the time of data reading can be improved. That is, as shown in FIG. 17, a dummy memory cell selected by dummy word line DWL0 and a dummy memory cell selected by dummy word line DWL1 corresponding to each of two adjacent main bit lines, By arranging each of them, complementary data reading can be executed.

[Modification 5 of Embodiment 2]
Modification 5 of the second embodiment shows a configuration in which one main bit line MBL is shared by a plurality of memory block columns.

  FIG. 19 is a block diagram showing a configuration of memory array 10 according to the fifth modification of the second embodiment.

  FIG. 19 shows a configuration in which two main bit lines MBL making a pair are shared by memory blocks for two columns. Therefore, two main bit lines MBL are arranged corresponding to four memory cell columns.

  Correspondingly, the block selection signals BS1 to BSk shown in FIG. 15 include a 4: 1 column selection result for the four memory cell columns associated with the two main bit lines forming a pair. Block selection signals BS1A, BS1B, BS1C, BS1D to BSkA, BSkB, BSkC, BSkD are subdivided.

  Similarly, the write selection signal activated at the time of data writing is also subdivided into WMB1A, WMB1B, WMB1C, WMB1D to WMBkA, WMBkB, WMBkC, and WMBkD.

  For example, in memory block MBd12, when a memory cell corresponding to sub bit line SBL12 is selected as a data write target, block selection signal BS1C and write selection signal WMB1C are activated. In contrast, when a memory cell corresponding to sub bit line / SBL11 is selected as a data read target, only block selection signal BS1D is activated.

  Since the configuration of memory blocks MBd11-MBdkm is similar to that of FIG. 18, detailed description thereof will not be repeated. However, the block selection signal and the write selection signal input to the gates of the current switch transistors SWTc, SWTd, SWTe, and SWTf respectively reflect the block selection signal shown in FIG. The only difference is that it is replaced by a write selection signal.

  With such a configuration, the number of main bit lines MBL arranged in the entire memory array 10 can be further suppressed to 1 (l: an integer represented by 1 = h / 2 = m / 4). That is, the number of main bit lines arranged may be half of the number of memory cell columns. As a result, the wiring pitch and the wiring width (that is, the cross-sectional area) of the main bit line can be secured, so that the current density is suppressed, the occurrence of electromigration and the like is avoided, and the operational stability of the MRAM device is improved. be able to.

[Embodiment 3]
In the third embodiment, a technique for applying the hierarchical bit line configuration described in the second embodiment to MTJ memory cells other than the two-layer storage node structure described in the first embodiment will be described.

FIG. 20 shows the configuration of an MTJ memory cell having a single-layer storage node structure.
Referring to FIG. 20, MTJ memory cell MCe having a single-layer storage node structure includes a tunnel magnetoresistive element 100b and an access transistor ATR. The tunnel magnetoresistive element 100 b includes an antiferromagnetic material layer 101, a fixed magnetic layer 102, a free magnetic layer 103, and a tunnel barrier 105. That is, tunneling magneto-resistance element 100b has the same configuration as tunneling magneto-resistance element TMR having the conventional configuration shown in FIGS. 48 and 49, and the free magnetic layer corresponding to the storage node is formed of a single layer.

  Since access transistor ATR has the same structure as MTJ memory cell MCa shown in FIG. 3, detailed description thereof will not be repeated. Access transistor ATR is electrically coupled to tunneling magneto-resistance element 100b through barrier metal 108 and via hole 115.

  Free magnetic layer 103 extends in the column direction and is electrically coupled to bit line BL formed in the metal wiring layer. Further, a write word line WWL is arranged in another metal wiring layer so as to extend in the row direction. Data for changing the magnetization direction of free magnetic layer 103 according to the combination of data write magnetic field generated by data write current Ip flowing through write word line WWL and data write current ± Iw flowing through bit line BL, respectively. A write magnetic field is generated.

  FIG. 21 is a structural diagram showing a configuration of a conventional MTJ memory cell having a two-layer storage node structure.

  Referring to FIG. 21, memory cell MCf includes a tunnel magnetoresistive element 100c and an access transistor ATR.

  The tunnel magnetoresistive element 100c includes an antiferromagnetic material layer 101, a fixed magnetic layer 102, free magnetic layers 103 and 104, a nonmagnetic intermediate layer 107 formed between the free magnetic layers 103 and 104, a tunnel And a barrier 105.

  That is, tunneling magneto-resistance element 100c has the same configuration as that of the tunneling magneto-resistance element according to the conventional technique shown in FIG.

  Since access transistor ATR has the same structure as MTJ memory cell MCa shown in FIG. 3, detailed description thereof will not be repeated. Access transistor ATR is electrically coupled to tunneling magneto-resistance element 100 c through barrier metal 108 and via hole 115.

  Data writing to memory cell MCf is performed in the same manner as described with reference to FIG.

  In the third embodiment, a hierarchical bit line configuration is applied to a memory array in which MTJ memory cells MCe or MCf shown in FIGS. 20 and 21 are arranged, respectively. Hereinafter, in the third embodiment and its modification, the configuration in which the MTJ memory cell MCe is arranged in each memory block is illustrated, but the MTJ memory cell MCf can be applied instead of the MTJ memory cell MCe. is there.

FIG. 22 is a circuit diagram showing a configuration of a memory block according to the third embodiment.
In the configuration according to the third embodiment, memory blocks MBe11 to MBekm are arranged in place of memory blocks MBa11 to MBakm in the configuration of memory array 10 shown in FIG. Since each of memory blocks MBe11-MBekm has the same configuration, FIG. 22 representatively shows the configuration of memory block MBe11. Hereinafter, the memory blocks MBe11 to MBekm are collectively referred to as a memory block MBe.

  FIG. 22 is compared with FIG. 11. In memory block MBe11, MTJ memory cell MCa is replaced with MTJ memory cell MCe in the configuration of memory block MBa11 shown in FIG. Data reading and data writing to these MTJ memory cells MCf are performed in the same manner as described with reference to FIG.

  In the third embodiment and its modification, a configuration example in which the number of memory cell rows included in each memory block is three is shown, but the application of the present invention is not limited to such a configuration, and each memory The number of memory cell rows corresponding to a block can be any number.

  By adopting such a configuration, the same effect as that of the second embodiment can be obtained by applying the hierarchical bit line configuration to the memory array in which the MTJ memory cells having the conventional configuration are arranged.

[Modification 1 of Embodiment 3]
FIG. 23 is a circuit diagram showing a configuration of a memory block according to the first modification of the third embodiment.

  In the configuration according to the first modification of the third embodiment, memory blocks MBf11 to MBfkm are arranged instead of memory blocks MBa11 to MBakm in the configuration of memory array 10 shown in FIG. Since each of memory blocks MBf11-MBfkm has the same configuration, FIG. 23 representatively shows the configuration of memory block MBf11. Hereinafter, the memory blocks MBf11 to MBfkm are collectively referred to simply as a memory block MBf.

  23, memory block MBf11 according to the first modification of the third embodiment has a current switch transistor SWTa, a main bit line MBL1, and a sub bit line / SBL11 compared to memory block MBb11 shown in FIG. And the current switch transistor SWTb is connected to one end of the main bit line / MBL1 and one end of the sub bit line SBL11 (read / write control). It is different in that it is electrically coupled to the side farther from the circuit 50. Further, a memory cell MCe is arranged instead of the memory cell MCa.

  With such a configuration, data write current ± Iw at the time of data writing is turned back by short-circuit transistor EQT11 and flows in the same direction through main bit line MBL1 and sub bit line SBL11. Similarly, data write current ± Iw flows in the same direction between main bit line / MBL1 and sub bit line / SBL11.

  FIG. 24 is a conceptual diagram illustrating a state of generation of a data write magnetic field in the memory block shown in FIG.

  FIG. 24A shows a case where a data write current + Iw in the positive direction is supplied to sub bit line SBL (/ SBL). In this case, a data write current in the same direction is also applied to the corresponding main bit line MBL (/ MBL). Therefore, the data write magnetic fields generated by these data write currents reinforce each other in free magnetic layer 103.

  FIG. 24B shows a case where negative direction data write current -Iw is caused to flow through sub-bit line SBL (/ SBL). Also in this case, the data write magnetic fields generated by the data write currents flowing through the sub bit line SBL (/ SBL) and the main bit line MBL (/ MBL) reinforce each other in the free magnetic layer 103.

  As a result, the reversal magnetization intensity in the free magnetic layer 103 can be obtained with a smaller data write current. As a result, the power consumption of the MRAM device can be reduced. Also, magnetic noise generated for data other than the selected memory cell during data writing can be reduced.

  With such a configuration, the hierarchical bit line configuration can be applied even to the MTJ memory cell having the conventional configuration to achieve high-speed data reading and low power consumption.

  When the MTJ memory cell MCf having the conventional two-layer storage node structure shown in FIG. 21 is applied, the data write magnetic field generated by the same data write current ± Iw is generated in the free magnetization layer 103 by the free magnetization. Larger than layer 104. Therefore, even if the magnetic moments (magnetization threshold values) of free magnetic layers 103 and 104 are similarly designed, free magnetic layer 104 can be magnetized following the magnetization of free magnetic layer 103. However, as described with reference to FIG. 51, if the magnetic moment (magnetization threshold) of free magnetic layer 103 is designed to be larger than that of free magnetic layer 104, the magnetization of free magnetic layers 103 and 104, that is, the data write operation Can be executed more reliably.

[Modification 2 of Embodiment 3]
FIG. 25 is a circuit diagram showing a configuration of a memory block according to the second modification of the third embodiment.

  In the configuration according to the second modification of the third embodiment, memory blocks MBg11 to MBgkm are arranged instead of memory blocks MBc11 to MBckm in the configuration of memory array 10 shown in FIG. Since each of memory blocks MBg11-MBgkm has the same configuration, FIG. 12 representatively shows the configuration of memory block MBg11. Hereinafter, the memory blocks MBg11 to MBgkm are collectively referred to as a memory block MBg.

  Referring to FIG. 25, memory block MBg11 according to the second modification of the third embodiment has the same configuration as memory block MBc11 shown in FIG. 16, and memory cell MCa is replaced with memory cell MCf. That is, sub bit lines SBL11 and / SBL11 are arranged according to an open bit line configuration, and in each memory cell column, MTJ memory cell MCe is arranged for each memory cell row.

  Since the connection relationship and on / off conditions of current control switches SWTa, SWTb, SWTc, and SWTd are the same as those described in FIG. 16, detailed description thereof will not be repeated.

  By adopting such a configuration, even in a memory array in which MTJ memory cells having a conventional configuration are arranged according to an open bit line configuration, the same effect as in the third modification of the second embodiment can be enjoyed, and data read and Data writing can be executed.

[Modification 3 of Embodiment 3]
FIG. 26 is a circuit diagram showing a configuration of a memory block according to the third modification of the third embodiment.

  In the configuration according to the third modification of the third embodiment, memory blocks MBh11 to MBhkm are arranged in place of memory blocks MBc11 to MBckm in the configuration of memory array 10 shown in FIG. Since each of memory blocks MBh11 to MBhkm has the same configuration, FIG. 26 representatively shows the configuration of memory block MBh11. In the following, the memory blocks MBh11 to MBhkm are collectively referred to simply as a memory block MBh.

  Referring to FIG. 26, memory block MBh11 according to the third modification of the third embodiment is different from memory block MBg11 shown in FIG. 25 in place of current switch transistors SWTa, SWTb, and current switch transistors SWTe, SWTf. Is different in that it is placed.

  Current switch transistor SWTe is electrically coupled between main bit line MBL1 and one end of sub bit line SBL11 on the side closer to read / write control circuit 50. Current switch transistor SWTf is electrically coupled between main bit line / MBL1 and one end of sub bit line / SBL11 (the side closer to read / write control circuit 50). Block selection signals BS1A and BS1B are input to the respective gates of current switch transistors SWTe and SWTf.

  With such a configuration, current switch transistors SWTc and SWTe can be turned on, and data write current ± Iw in the same direction as main bit line MBL1 can be supplied to sub bit line SBL11. Conversely, by turning on current switch transistors SWTd and SWTf, data write current ± Iw in the same direction as main bit line MBL2 (/ MBL1) can be supplied to sub bit line / SBL11.

  On the other hand, at the time of data reading, both current switch transistors SWTc and SWTd are turned off, and only one of current switch transistors SWTe and SWTf corresponding to the selected memory cell is turned on. As a result, like the memory block MBd11 shown in FIG. 18, one of the two main bit lines forming a pair that is not electrically coupled to the selected memory cell is coupled to the dummy memory cell, so that the complementary data Reading can be performed.

  Thus, according to the configuration according to the third embodiment, data writing and data reading can be executed by applying the hierarchical bit line configuration even in a memory array in which MTJ memory cells having a conventional structure are arranged. In particular, the data write magnetic fields generated by the data write currents flowing through the main bit line and the sub bit line, respectively, can be generated so as to strengthen each other in the free magnetic layer. As a result, the data write current can be reduced, so that magnetic noise can be suppressed and power consumption can be reduced.

[Embodiment 4]
In the fourth embodiment, another configuration example of the MTJ memory cell having the two-layer storage node structure described in the first embodiment will be described.

  FIG. 27 is a conceptual diagram showing a configuration of an MTJ memory cell having a two-layer storage node configuration according to the fourth embodiment.

  Referring to FIG. 27, MTJ memory cell MCg according to the fourth embodiment includes a tunnel magnetoresistive element 100d and an access transistor ATR. The tunnel magnetoresistive element 100d has an antiferromagnetic material layer 101, a fixed magnetic layer 102, free magnetic layers 103 and 104, a tunnel barrier 105, and an intermediate layer 107.

  In the configuration according to the fourth embodiment, intermediate layer 107 is arranged to extend in the row direction to form write word line WWL. On the other hand, the bit line BL extends in the column direction and is arranged in a metal wiring layer located in an upper layer or a lower layer of the tunnel magnetoresistive element 100d. FIG. 27 shows an example of a structure in which the bit line BL is disposed in the upper layer of the tunnel magnetoresistive element 100d.

  Access transistor ATR is electrically coupled between tunneling magneto-resistance element 100d and bit line BL. A write word line RWL extending in the row direction is formed at the gate of access transistor ATR.

  FIG. 28 is a conceptual diagram showing how a data write magnetic field is generated in MTJ memory cell MCg. 28A and 28B correspond to the cross-sectional view taken along the line RS in FIG.

  FIG. 28A shows a case where a positive direction data write current + Iw flows through bit line BL, and FIG. 28B shows a case where negative direction data write current −Iw flows through bit line BL. The case is shown. In both cases of FIGS. 28A and 28B, the direction of the data write current Ip flowing through the intermediate layer 107 (write word line WWL) is constant.

  Magnetization in the direction of hard axis (HA) in free magnetic layers 103 and 104 is executed by data write current Ip flowing through intermediate layer 107. With such a configuration, it is possible to suppress the amount of data write current required for generating the data write magnetic field of the hard axis (HA) in free magnetic layers 103 and 104. As a result, low power consumption and magnetic noise reduction of the MRAM device are realized.

  The magnetic field in the easy axis (EA) direction in free magnetic layers 103 and 104 is performed by data write current ± Iw flowing through bit line BL.

  In tunnel magnetoresistive element 100d, a magnetic axis in the direction of easy axis (EA) generated by a data write current flowing through bit line BL and a hard axis of magnetization generated by a data write current flowing through intermediate layer 107 (write word line WWL) ( Data writing is performed by superimposing the magnetic field in the direction HA). That is, the materials and thicknesses of the free magnetic layers 103 and 104 are made differently so that data writing with reversal of the magnetization direction is executed only in the memory cell to which both magnetic fields are applied in a superimposed manner. It is necessary to increase or decrease the magnetic moment (magnetization threshold).

  FIG. 29 is a block diagram showing a configuration of a memory array in which MTJ memory cells MCg are arranged in a matrix.

  Referring to FIG. 29, memory array 10 includes MTJ memory cells MCg having a two-layer storage node structure arranged in n rows × m columns (n, m: natural numbers). Memory cell MCg includes an access transistor ATR and a tunnel magnetoresistive element 100d.

  Corresponding to the memory cell rows, read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are provided, respectively. Bit lines BL1 to BLm are provided corresponding to the memory cell columns, respectively.

  The word line current control circuit 40 couples each write word line WWL to the ground voltage VSS in a region opposite to the word line driver 30 across the memory array 10. Thereby, data write current Ip in a fixed direction can be supplied to the write word line selectively coupled to power supply voltage VDD by word line driver 30.

  FIG. 29 shows read word lines RWL1, RWLn, write word lines WWL1, WWLn, and bit lines corresponding to the first and nth rows, the first, (m−1) th and mth columns. BL1, BLm-1, BLm and some of the memory cells corresponding thereto are typically shown.

  At the time of data reading, intermediate layer 107, that is, write word line WWL is fixed to ground voltage VSS. Further, by selectively activating read word line RWL corresponding to the selected memory cell, tunneling magneto-resistance element 100d can be electrically coupled between corresponding bit line BL and ground voltage VSS. . Thereby, the storage data of the selected memory cell can be read by detecting the voltage change of the bit line BL coupled to the selected memory cell.

  The intermediate layer 107 is formed of a nonmagnetic conductor between the free magnetic layers 103 and 104. The shape and electrical characteristics of the intermediate layer 107 can be freely determined. In the configuration according to the fourth embodiment, since write word line WWL is formed using intermediate layer 107, intermediate layers 107 are electrically coupled between MTJ memory cells belonging to the same memory cell column. Thus, the intermediate layer 107 extends in the column direction and is arranged in a stripe shape.

[Modification 1 of Embodiment 4]
FIG. 30 is a circuit diagram showing a configuration of memory array 10 according to the first modification of the fourth embodiment.

  Referring to FIG. 30, in the configuration according to the first modification of the fourth embodiment, write word lines WWL are arranged hierarchically. That is, main write word lines MWWL1 to MWWLn are further arranged corresponding to each of the memory cell rows. In the following, the main write word lines MWWL1 to MWWLn are also collectively referred to as main write word lines MWWL.

  In memory cell MCg according to the fourth embodiment, write word line WWL is formed using intermediate layer 107 of tunneling magneto-resistance element 100d, so that its electrical resistance value is relatively high. The main write word lines MWWL1 to MWWLn are formed using a metal wiring layer above the tunnel magnetoresistive element 100d.

  In each memory cell row, one end of the main write word line and the write word line are electrically coupled in a region opposite to the word line driver 30 (word line current control circuit 40). On the other hand, each write word line WWL, that is, the intermediate layer 107 is electrically coupled to the ground voltage VSS at one end on the word line driver 30 side. The word line driver 30 couples the main write word line MWWL corresponding to the selected memory cell to the power supply voltage VDD at the time of data writing according to the row selection result.

  With such a configuration, in the memory cell row corresponding to the selected memory cell, data write current Ip can flow in the opposite directions to main write word line MWWL and write word line WWL. As a result, the magnetic field in the hard axis (HA) direction generated in the free magnetic layer of the selected memory cell is strengthened by the data write current flowing through the main write word line MWWL and the data write current flowing through the write word line WWL. Fit. Therefore, data write current Ip can be further suppressed.

  Further, in the memory cell column corresponding to the selected memory cell, the data write current ± Iw in the direction corresponding to the data level of the write data DIN is supplied to the corresponding bit line BL to write data to the selected memory cell. Can be executed.

  On the other hand, at the time of data reading, each of main write word line MWWL and write word line WWL is set to ground voltage VSS, and read word line RWL corresponding to the selected memory cell is activated, thereby selecting memory cell. Tunnel magnetoresistive element 100d can be electrically coupled between corresponding bit line BL and ground voltage VSS.

[Modification 2 of Embodiment 4]
FIG. 31 is a conceptual diagram illustrating a hierarchical word line configuration according to the second modification of the fourth embodiment.

  Referring to FIG. 31, write word line WWL arranged for each memory cell row is divided into sub-write word lines for each predetermined region. For example, the write word line WWL1 corresponding to the first row is divided into k (k: natural number) sub-write word lines SWWL11 to SWWL1k. Similarly, sub write word lines SWWLn1 to SWWLnk are arranged in the nth memory cell row. In the following, the sub write word lines SWWL11 to SWWLnk are collectively referred to simply as the sub write word line SWWL. The sub word selection signals SW1 to SWk are respectively defined corresponding to regions where the sub write word lines SWWL are dividedly arranged.

  Thus, the hierarchical word line configuration of the main write word line MWWL and the sub write word line SWWL is applied to each memory cell row. As in the first modification of the fourth embodiment, each sub-write word line SWWL is arranged using the intermediate layer 107 of the tunnel magnetoresistive element 100d.

  Therefore, the sub-write word line SWWL formed in the intermediate layer having a small thickness and a relatively high electric resistance value per unit resistance can be shortened to reduce the electric resistance value.

  Each of main write word lines MWWL1 to MWWLn is activated by being selectively coupled to power supply voltage VDD by main word drivers MWD1 to MWDn arranged in word line driver 30. Sub word drivers SWD11 to SWDnk are arranged corresponding to the sub write word lines SWWL11 to SWWLnk, respectively. Hereinafter, the sub word drivers SWD11 to SWDnk are collectively referred to as a sub word driver SWD.

  Each of the sub word drivers SWD11 to SWDnk corresponds to the corresponding sub write word line SWWL when both are activated based on the corresponding main write word line MWWL and the sub word selection signal SWi (i: integer of 1 to k). One end of each is coupled with the power supply voltage VDD and activated.

  For example, the sub word driver SWD can be configured by a switch element connected between the corresponding main write word line MWWL and one end of the sub write word line SWWL and turned on / off in response to the corresponding sub word selection signal SWi. The other end of each sub-write word line SWWL opposite to the sub-word driver SWD is coupled to the ground voltage VSS.

  The sub word driver SWD generates a data write magnetic field generated by the data write current Ip flowing through the main write word line MWWL and the data write current Ip flowing through the sub write word line SWWL, in the free magnetic layer of the selected memory cell. Arranged so as to strengthen each other.

  That is, in the configuration shown in FIG. 31, the sub word driver SWD is arranged corresponding to one end of the sub write word line SWWL on the side farther from the main word driver MWD, and the other end (main word driver) of the sub write word line SWWL. The side closer to the MWD) is electrically coupled to the ground voltage VSS.

  With such a configuration, in MTJ memory cell according to the fourth embodiment, data write current Ip for generating a required magnetic field in the hard axis (HA) direction can be suppressed. In addition, the electrical resistance value of the write word line can be reduced as compared with the case where the write word line is configured using the intermediate layer extending in the row direction in the entire memory array 10, so that high speed operation is possible. It is.

[Modification 3 of Embodiment 4]
FIG. 32 is a conceptual diagram illustrating a hierarchical word line configuration according to the third modification of the fourth embodiment.

  Referring to FIG. 32, in the third modification of the fourth embodiment, the write word line WWL is hierarchically composed of the main write word line MWWL and the sub write word line SWWL as in the second modification of the fourth embodiment. Placed in. Further, the read word line RWL is also dividedly arranged in the same manner as the write word line. For example, read word line RWL1 corresponding to the first memory cell row is divided into sub read word lines SRWL11 to SRWL1k corresponding to sub write word lines SWWL11 to SWWL1k, respectively.

  As already described, read word line RWL is formed of a relatively high resistance material such as polysilicon using the gate electrode layer of access transistor ATR. Therefore, in each memory cell row, the electrical resistance value of each sub read word line SRWL can be reduced by arranging the sub read word line SRWL in a short wiring.

  Further, sub read drivers SRD11 to SRD1k corresponding to the sub read word lines SRWL11 to SRWL1k are arranged. Hereinafter, the sub read drivers SRD11 to SRD1k are also collectively referred to as a sub read driver SRD. The sub read driver SRD is connected between the corresponding main write word line MWWL and one end of the sub read word line SRWL at the time of data reading, and is turned on in response to the activation of the corresponding sub word selection signal SWi. It can be constituted by an element.

  Each of main word drivers MWD1-MWDn selectively activates main write word line MWWL corresponding to the selected memory cell in both data reading and data writing.

  With such a configuration, at the time of data writing, data write current Ip is caused to flow using both main write word line MWWL and sub write word line SWWL, similarly to the configuration shown in FIG. A data write magnetic field can be generated. Therefore, at the time of data writing, the same effect as that of the configuration according to the modification of the third embodiment shown in FIG. 31 can be emphasized.

  Further, at the time of data reading, sub read word line SRWL corresponding to the selected memory cell can be activated in response to activation of corresponding main write word line MWWL and turning on of sub read driver SRD. Thereby, data reading from the selected memory cell can be executed.

  Thus, by activating the sub read word line SRWL via the main write word line MWWL which is a metal wiring and has a small electric resistance value, the sub read word line SRWL corresponding to the selected memory cell is activated at high speed. Can be That is, it is possible to shorten the signal propagation time of sub read word line SRWL at the time of data reading, and to speed up the data reading operation.

[Embodiment 5]
In the first to fourth embodiments, an intermediate layer provided between two free magnetic layers is arranged extending in the row direction or the column direction to form the write word line WWL or the bit line BL. explained. In the fifth embodiment, a configuration in which a data write current can be supplied only to an intermediate layer corresponding to a selected memory cell by providing an intermediate layer independently for each memory cell will be described.

FIG. 33 is a block diagram showing a configuration of a memory array according to the fifth embodiment.
Referring to FIG. 33, MTJ memory cells MCp according to the fifth embodiment are arranged in a matrix over n rows × m columns in memory array 10 as a whole. Each MTJ memory cell MCp includes tunneling magneto-resistance element 100a and access transistors ATRr and ATRw which are access elements.

  Corresponding to the memory cell rows, write row selection lines WRSL1 to WRSLn are arranged in addition to read word lines RWL1 to RWLn and write word lines WWL1 to WWLn. Hereinafter, the write row selection lines WRSL1 to WRSLn are collectively referred to as a write row selection line WRSL.

  Bit lines BL and / BL are provided corresponding to each memory cell column. Therefore, in the entire memory array, read word lines RWL1 to RWLn, write word lines WWL1 to WWLn, write row selection lines WRSL1 to WRSLn, and bit lines BL1 to BLm, / BL1 to / BLm are arranged.

  Write row select line WRSL is activated to H level corresponding to the selected row at the time of data writing. Therefore, the word line driver 30 can drive each write row selection line WRSL according to the same decoding result as that of the corresponding write word line WWL. However, since the data write current Ip is supplied to the write word line WWL corresponding to the selected row, the write row selection line WRSL is provided to control the gate voltage of the corresponding access transistor ATRw. No current is passed through the circuit.

  In each MTJ memory cell MCp, tunneling magneto-resistance element 100a is electrically coupled to bit line / BL. Access transistors ATRr and ATRw are electrically coupled between bit line BL and tunneling magneto-resistance element 100a. The gate voltage of access transistor ATRr is controlled by the corresponding read word line RWL, and the gate voltage of access transistor ATRw is controlled by the corresponding write row selection line WRSL.

FIG. 34 is a conceptual diagram illustrating the structure of an MTJ memory cell according to the fifth embodiment.
Referring to FIG. 34, in the configuration according to the fifth embodiment, intermediate layer 107 formed of a nonmagnetic conductor is provided independently for each MTJ memory cell MCp. One end of intermediate layer 107 is electrically coupled to bit line / BL. Further, the other end of intermediate layer 107 is electrically coupled to bit line BL via access transistor ATRw. That is, access transistor ATRw is connected in series with intermediate layer 107 between corresponding bit lines BL and / BL, and has a function of selectively allowing a data write current to flow through intermediate layer 107.

  Data writing to the tunnel magnetoresistive element 100a is executed in the same manner as described with reference to FIGS. That is, by controlling the voltage at one end and the other end of the intermediate layer 107 so that the direction of the data write current flowing through the intermediate layer 107 is + Iw or −Iw depending on the write data, 104 can be magnetized according to the level of the write data.

  An access transistor ATRr is provided between the antiferromagnetic material layer 101 and the bit line BL. A write row selection line WRSL and a read word line RWL are connected to the gates of access transistors ATRw and ATRr, respectively.

  FIG. 35 is an operation waveform diagram illustrating data read and data write operations on MTJ memory cell MCp according to the fifth embodiment.

  Referring to FIG. 35, at the time of data reading, word line driver 30 activates read word line RWL corresponding to the selected row from L level to H level. As a result, the access transistor ATRr corresponding to the selected row is turned on. On the other hand, the voltages of each write row selection line WRSL and each write word line WWL are maintained at the L level (ground voltage VSS), so that each of access transistors ATRw is turned off.

  Read / write control circuits 50 and 60 couple bit line / BL to ground voltage VSS and supply sense current (data read current) Is to bit line BL. Therefore, tunnel magnetoresistive element 100a of the selected memory cell can be electrically coupled between bit line BL that receives supply of sense current Is and ground voltage VSS by turned on access transistor ATRr. As a result, a voltage change corresponding to the storage data of the selected MTJ memory cell occurs in the bit line BL. Therefore, data can be read from the selected MTJ memory cell by detecting the voltage of the bit line BL.

  At the time of data writing, write row selection line WRSL and write word line WWL corresponding to the selected row are coupled to H level (power supply voltage VCC) by word line driver 30. As a result, the data write current Ip flows through the write word line WWL corresponding to the selected row. In the selected row, access transistor ATRw is turned on.

  On the other hand, bit lines BL and / BL corresponding to the selected column are set to one of power supply voltage VCC and ground voltage VSS by read / write control circuits 50 and 60, respectively. For example, to write the stored data of “1”, in order to pass a data write current of + Iw, the bit line BL is set to the power supply voltage VCC while the bit line / BL is set to the ground voltage VSS. Is done. On the other hand, when a current of −Iw is passed through the intermediate layer 107 to write “0” stored data, the bit line / BL is set to the power supply voltage VCC, and the bit line BL is set to the ground voltage VSS. The On the other hand, the bit lines BL and / BL corresponding to the non-selected columns are set to the ground voltage VSS.

  As a result, the data write current flows only to the intermediate layer 107 corresponding to the selected memory cell, and the data write can be executed. That is, in the non-selected memory cell, even if it belongs to the same memory cell column or the same memory cell row as the selected memory cell, the data write current ± Iw is not passed through the intermediate layer 107. Since bit lines BL and / BL are arranged away from the tunnel magnetoresistive element, in the configuration according to the sixth embodiment, it is possible to prevent erroneous data writing in unselected memory cells. .

[Modification 1 of Embodiment 5]
FIG. 36 is a block diagram showing a configuration of a memory array according to the first modification of the fifth embodiment.

  Referring to FIG. 36, MTJ memory cells MCq according to the first modification of the fifth embodiment are arranged in a matrix over n rows × m columns in the entire memory array 10. Each MTJ memory cell MCq includes a tunnel magnetoresistive element 100a coupled to bit line BL, an access transistor ATRw provided between bit line / BL and tunnel magnetoresistive element 100a, a tunnel magnetoresistive element 100a and a ground voltage. And an access transistor ATRr provided between VSS. The gate voltage of access transistor ATRr is controlled by the corresponding read word line RWL, and the gate voltage of access transistor ATRw is controlled by the corresponding write row selection line WRSL.

  Since the arrangement of read word line RWL, write word line WWL, write row selection line WRSL, and bit lines BL, / BL is the same as in the sixth embodiment, detailed description will not be repeated.

  FIG. 37 is a conceptual diagram illustrating the structure of an MTJ memory cell according to the first modification of the fifth embodiment.

  Referring to FIG. 37, in MTJ memory cell MCq according to the first modification of the fifth embodiment, one end of intermediate layer 107 provided independently for each MTJ memory cell is coupled to bit line BL. The end is coupled to bit line / BL via access transistor ATRw. Therefore, as in the fifth embodiment, access transistor ATRw is connected in series with intermediate layer 107 between corresponding bit lines BL and / BL, and selectively applies a data write current to intermediate layer 107. Has the function of flowing. Access transistor ATRr is provided between antiferromagnetic material layer 101 and ground voltage VSS.

  The access transistor ATRw is turned on when the corresponding write row selection line WRSL is set to H level (power supply voltage VCC), and is turned on when it is set to L level (ground voltage VSS). Similarly, the access transistor ATRr is turned on when the corresponding read word line RWL is set to H level (power supply voltage VCC), and is turned off when it is set to L level (ground voltage VSS).

  The operation waveforms of read word line RWL, write word line WWL, write row selection line WRSL, and bit lines BL and / BL at the time of data reading and data writing in the configuration according to the first modification of the fifth embodiment are shown in FIG. It is the same as shown in. That is, in the configuration according to the first modification of the fifth embodiment, the voltages and currents of read word line RWL, write word line WWL, write row selection line WRSL and bit lines BL and / BL are controlled in the same manner as in the fifth embodiment. Thus, data reading and data writing operations can be executed. As in the fifth embodiment, this causes data write current ± Iw to flow only in intermediate layer 107 corresponding to the selected memory cell during data writing, so that erroneous data writing occurs in unselected memory cells. Can be prevented.

[Modification 2 of Embodiment 5]
FIG. 38 is a block diagram showing a configuration of a memory array according to the second modification of the fifth embodiment.

  Referring to FIG. 38, MTJ memory cells MCr according to the second modification of the fifth embodiment are arranged in a matrix of n rows × m columns in the entire memory array 10. MTJ memory cell MCr includes tunneling magneto-resistance element 100a coupled to bit line / BL, access transistor ATRw electrically coupled between bit line BL and tunneling magneto-resistance element 100a, and read word line RWL. It includes an access diode ADr coupled as an access element between the two with the direction toward tunneling magneto-resistance element 100a as the forward direction.

  Since the arrangement of read word line RWL, write word line WWL, write row selection line WRSL and bit lines BL, / BL is the same as in the fifth embodiment, detailed description will not be repeated.

  FIG. 39 is a conceptual diagram illustrating the structure of an MTJ memory cell MCr according to the second modification of the fifth embodiment.

  Referring to FIG. 39, MTJ memory cell MCr according to the second modification of the fifth embodiment has an access diode in place of access transistor ATRr, as compared with MTJ memory cell MCp according to the fifth embodiment shown in FIG. It differs in that it includes ADr. Access diode ADr is electrically coupled between the read word line RWL and the antiferromagnetic layer 101 as a forward direction. Since the structure of other parts is similar to that of MTJ memory cell MCp according to the fifth embodiment, detailed description will not be repeated.

  FIG. 40 is an operation waveform diagram illustrating data read and data write operations on MTJ memory cell MCr according to the second modification of the fifth embodiment.

  Referring to FIG. 40, at the time of data reading, word line driver 30 activates read word line RWL corresponding to the selected row from L level to H level (power supply voltage VCC). Read / write control circuits 50 and 60 connect bit line / BL to ground voltage VSS to supply a sense current (data read current) -Is in the negative direction. As a result, the access diode ADr corresponding to the selected row is forward biased and turned on.

  On the other hand, the voltages of each write row selection line WRSL and each write word line WWL are maintained at the L level (ground voltage VSS), so that each of access transistors ATRw is turned off. Read / write control circuits 50 and 60 set bit line BL to ground voltage VSS.

  Therefore, a sense current can be passed through tunnel magnetoresistive element 100a of the selected memory cell by access diode ADr that is turned on. Thus, data can be read from the selected MTJ memory cell by detecting the voltage of the bit line BL.

  In contrast, read word line RWL corresponding to the non-selected row is maintained at the L level (ground voltage VSS), and thus corresponding access diode ADr is maintained in the OFF state without being forward biased.

  Since the operation waveform at the time of data writing is similar to that shown in FIG. 35, detailed description will not be repeated. That is, also in the configuration according to the second modification of the fifth embodiment, the data write current is supplied only to the intermediate layer corresponding to the selected memory cell at the time of data writing. Therefore, in the same manner as in the fifth embodiment and its modification example 1, it is possible to prevent erroneous data writing in unselected memory cells. Further, since the diode is used as the access element instead of the access transistor, the MTJ memory cell can be reduced in size.

[Modification 3 of Embodiment 5]
FIG. 41 is a block diagram showing a configuration of a memory array according to the third modification of the fifth embodiment.

  Referring to FIG. 41, MTJ memory cells MCs according to the third modification of the fifth embodiment are arranged in a matrix of n rows × m columns in the entire memory array 10. MTJ memory cell MCs includes a tunnel magnetoresistive element 100a coupled to bit line BL, an access transistor ATRw electrically coupled between bit line / BL and tunnel magnetoresistive element 100a, and read word line RWL. It includes an access diode ADr coupled as an access element between the two with the direction toward tunneling magneto-resistance element 100a as the forward direction. Since the arrangement of read word line RWL, write word line WWL, write row selection line WRSL, and bit lines BL, / BL is the same as in the sixth embodiment, detailed description will not be repeated.

  FIG. 42 is a conceptual diagram illustrating the structure of an MTJ memory cell according to the third modification of the fifth embodiment.

  Referring to FIG. 42, MTJ memory cell MCs according to the third modification of the fifth embodiment has access transistor ATRw formed of bit layer intermediate layer 107 and bit compared with MTJ memory cell MCr according to the fifth embodiment shown in FIG. It differs in that it is provided between the line / BL. Intermediate layer 107 is electrically coupled to bit line BL. Since the configuration of other parts is similar to that of MTJ memory cell MCr according to the second modification of the fifth embodiment, detailed description will not be repeated.

  FIG. 43 is an operation waveform diagram illustrating data reading and data writing operations for the MTJ memory cell according to the third modification of the fifth embodiment.

  Referring to FIG. 43, in the data write operation and data read operation according to the third modification of the fifth embodiment, the data write operation and the data read operation according to the second modification of the fifth embodiment shown in FIG. Is different from the above in that the voltage settings of the bit lines BL and / BL are interchanged. Since the other points are the same as in the second modification of the fifth embodiment, detailed description will not be repeated.

  As described above, in the configuration according to the third modification of the fifth embodiment as well, the diode is used as an access element, similarly to the configuration according to the second modification of the fifth embodiment. Therefore, the MTJ memory cell can be reduced in size. It becomes possible.

[Embodiment 6]
In the sixth embodiment, a configuration example in which the magnetization characteristics in each MTJ memory cell can be made symmetric without depending on the level of stored data to be written will be described.

  As will be apparent from the following description, the configuration according to the sixth embodiment can be applied to any of the tunnel magnetoresistive elements 100a, 100b and 100c described in the first to fifth embodiments. Therefore, in the sixth embodiment, these tunnel magnetoresistive elements are collectively referred to simply as tunnel magnetoresistive element 100. The free magnetic layers in each type of tunnel magnetoresistive element are also collectively referred to as free magnetic layer VL.

FIG. 44 is a conceptual diagram showing the direction of the data write magnetic field according to the sixth embodiment.
Referring to FIG. 44, at the time of data writing, data write magnetic field H (BL) generated by data write current ± Iw flowing through bit line BL and write word line WWL are applied to tunneling magneto-resistance element 100. And a data write magnetic field H (WWL) generated by the data write current Ip flowing through is applied. In the free magnetic layer VL in the tunnel magnetoresistive element 100, the coupling magnetic field ΔHp between the fixed magnetic layer due to the magnetostatic coupling acts in the direction along the magnetic easy axis (EA).

  The data write magnetic field H (BL) mainly includes a component along the easy axis (EA) direction of the free magnetic layer VL, and the data write magnetic field H (WWL) is a hard magnetization axis (free magnetization layer VL). HA) mainly contains components along the direction. That is, the data write magnetic field H (BL) is applied to magnetize the free magnetic layer VL in the easy axis (EA) direction, and the data write magnetic field H (WWL) applies the hard magnetic layer VL to the hard axis. Applied to magnetize in the (HA) direction.

  In the configuration according to the sixth embodiment, the data write magnetic field H (WWL) is not applied completely parallel to the hard axis (HA) of the free magnetic layer VL, but between the hard axis HA. Is applied at a predetermined angle α. As a result, the data write magnetic field H (WWL) is decomposed into a component HWWL (e) in the easy axis direction and a component HWWL (h) in the hard axis direction.

Here, each component is shown as the following formulas (1) and (2).
HWWL (e) = H (WWL) · sin α (1)
HWWL (h) = H (WWL) · cos α (2)
Further, the predetermined angle α is set so as to satisfy the following expression (3).

H (WWL) · sin α + ΔHp = 0 (3)
Thereby, the uniform coupling magnetic field ΔHp is canceled by the component along the easy axis (EA) direction of H (WWL). In other words, the data write magnetic field H (WWL) has a component in a direction that cancels the coupling magnetic field ΔHp.

On the other hand, in the configuration according to the sixth embodiment, data write magnetic field H (BL) is applied along the easy axis (EA) in a direction according to the level of write data.
As a result, magnetization along the easy magnetization axis direction can be performed with only the data write magnetic field H (BL) acting.

  With this configuration, the magnetization characteristics in the direction along the easy axis (EA) can be made symmetric without depending on the level of the write data, that is, the direction of the data write current ± Iw. it can. As a result, it is possible to suppress the data write current ± Iw necessary for data writing. As a result, it is possible to obtain effects such as reduction in power consumption in the MRAM device and improvement in operation reliability due to reduction in the current density of the bit line BL.

  In addition, about the predetermined angle (alpha) mentioned above, in order to perform magnetization along a hard magnetization axis | shaft HA direction, it is necessary to satisfy the following Formula (4).

H (WWL) · cos α> HSWh (4)
Here, HSWh indicates the magnetization threshold value in the magnetization characteristic along the hard magnetization axis HA direction, and HSWh corresponds to the value on the vertical axis of the asteroid characteristic line shown in FIG.

FIG. 45 is a conceptual diagram showing the arrangement of tunneling magneto-resistance elements according to the sixth embodiment.
Referring to FIG. 45, in order to realize the relationship between the magnetic fields shown in FIG. 44, bit line BL is arranged to extend in a direction perpendicular to the easy axis (EA) of free magnetic layer VL. . When tunneling magneto-resistance element 100 (free magnetic layer VL) has a rectangular shape, the easy axis (EA) corresponds to the long side direction.

  On the other hand, the write word line WWL extends in a direction that forms a predetermined angle α with the easy axis (EA). That is, the write word line WLL and the bit line BL are not provided orthogonal to each other, but are arranged at an angle of (90−α) degrees.

  Appropriately design the formation pattern and polishing pattern by CMP (Chemical Mechanical Polishing) etc. for at least the free magnetic layer VL of the tunnel magnetoresistive element 100 and the metal wiring layers of the write word line WWL and the bit line BL. As a result, the arrangement shown in FIG. 46 can be realized. With such an arrangement, the data write magnetic field according to the sixth embodiment shown in FIG. 45 can be applied to the MTJ memory cell.

[Modification of Embodiment 6]
In the modification of the sixth embodiment, a configuration capable of obtaining the same effect as that of the sixth embodiment under the configuration in which the bit line BL and the write word line WWL are arranged in directions orthogonal to each other will be described. .

FIG. 46 is a conceptual diagram showing the direction of the data write magnetic field according to the modification of the sixth embodiment. Referring to FIG. 46, in the configuration according to the modification of the sixth embodiment, data write magnetic field H (BL ) Is arranged such that the tunnel magnetoresistive element 100 forms a predetermined angle α with the easy axis (EA) direction of the free magnetic layer VL. Data write magnetic field H (WWL) and H (BL) are applied in directions orthogonal to each other. That is, the bit line BL and the write word line WWL are arranged orthogonally. Therefore, data write magnetic field H (WWL) forms a predetermined angle α with hard magnetization axis (HA) of free magnetic layer VL, similarly to the configuration according to the sixth embodiment. Similarly, data write magnetic field H (BL) is set in the opposite direction depending on the level of write data.

  Therefore, the magnetic field H (e) applied in the easy axis (EA) direction in the tunnel magnetoresistive element 100 (free magnetic layer) is expressed by the following equation (5).

H (e) = H (WWL) · sin α ± H (BL) · cos α + ΔHp (5)
Further, similarly to the configuration according to the sixth embodiment, if the predetermined angle α is set so as to satisfy the expression (3), the same effect as the sixth embodiment can be obtained.

  Similarly, the magnetic field H (h) in the hard axis HA direction in the tunnel magnetoresistive element 100 (free magnetic layer) is expressed by the following equation (6).

H (h) = H (WWL) · cos α ± H (BL) · sin α (6)
At this time, in order to update the magnetization direction of the free magnetic layer VL in the MTJ memory cell to be written, it is necessary to satisfy the following expressions (7) and (8).

| ± H (BL) · cosα |> HSWe (7)
| H (WWL) · cosα ± H (BL) · sinα |> HSWh (8)
HSWh and HSWe are threshold values for magnetization along the hard axis and easy axis, respectively, and correspond to the values on the vertical and horizontal axes of the asteroid characteristic line shown in FIG. To do.

  The predetermined angle α and the data write magnetic fields H (WWL) and H (BL) may be set so that such a relational expression is satisfied. In the configuration according to the modification of the sixth embodiment, as can be understood from the equation (8), compared with the normal configuration in which the predetermined angle α is 0 degree, the direction along the easy axis (EA) direction. In order to make the magnetization characteristics symmetrical, it is necessary to set H (WWL) larger. That is, it is necessary to set the data write current Ip flowing through the write word line WWL large.

  Therefore, such a configuration suppresses current consumption in the case where Ip <| ± Iw | is satisfied for data write currents Ip and ± Iw necessary for writing stored data to the selected memory cell. it can. For example, a configuration in which data writing is executed in parallel corresponding to a plurality of memory cell columns corresponding to one selected row in one data writing operation corresponds to such a case.

  Typically, in order to process data with high speed and low power consumption, it is applied to a system LSI (Large Scale Integrated Circuit) integrated on the same semiconductor chip as logic such as a processor, and between other circuits. Thus, data writing according to the above-described configuration is effective for MRAM devices that are required to exchange data in multiple bits in parallel.

  FIG. 47 is a conceptual diagram showing an arrangement of tunneling magneto-resistance elements according to the modification of the sixth embodiment.

  Referring to FIG. 47, in order to realize the relationship between the magnetic fields shown in FIG. 46, write word line WWL has a predetermined angle α with easy axis (EA) of tunneling magneto-resistance element 100 (free magnetic layer). It is arranged extending in the forming direction. When tunneling magneto-resistance element 100 has a rectangular shape, write word line WWL is arranged to form a predetermined angle α with the long-side direction of tunneling magneto-resistance element 100. Further, the bit line BL and the write word line WWL are arranged extending in a direction orthogonal to each other.

  Such an arrangement can also be realized by appropriately designing the formation pattern and polishing pattern of the magnetic layer and the metal wiring layer. With such an arrangement, it is possible to apply the data write magnetic field according to the modification of the sixth embodiment shown in FIG. 46 to the MTJ memory cell.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 40 word line current control circuit, 50, 60 read / write control circuit, 51W data write circuit, 51R data read circuit, 100a, 100b, 100c , 100d tunnel magnetoresistive element, 101 antiferromagnetic layer, 102 pinned magnetic layer, 103, 104 free magnetic layer, 105 tunnel barrier, 107 intermediate layer, 108 barrier metal, ADr access diode, ATR, ATRw, ATRr access transistor, BL, / BL bit line, DB, / DB data bus, DMC dummy memory cell, EQT short-circuit transistor, Is sense current, ± Iw, Ip data write current, MBa, MBb, MBc, MBd, MBe, MBf, MBg memory block, Ca, MCb, MCd, MCe, MCf, MCg, MCp, MCq, MCr, MCs MTJ memory cell, MBL, / MBL main bit line, MWD main word driver, MWWL main write word line, RBL read bit line, SBL, / SBL sub-bit line, SRD sub-read driver, SRWL sub-read word line, SWD sub-word driver, SWTa, SWTb, SWTc, SWTd, SWTe, SWTf Current switch transistor, SWWL sub-write word line, WRSL write row select line.

Claims (8)

Comprising a plurality of memory cells each for performing data storage;
Each of the memory cells
Including a magnetic storage unit whose electrical resistance value changes in accordance with stored data,
The magnetic storage unit
A first magnetic layer having a fixed magnetization direction;
A second magnetic layer magnetized in a direction according to the level of stored data;
An insulating layer formed between the first and second magnetic layers,
A first data write magnetic field for magnetizing the second magnetic layer is generated for at least one selected memory cell selected as a data write target among the plurality of memory cells. The data write current line of
The first data write magnetic field cancels a coupling magnetic field that acts on the second magnetic layer from the first magnetic layer in the second magnetic layer regardless of the level of the stored data. A thin-film magnetic memory device having the following components: A second data write current line for generating a second data write magnetic field for magnetizing the second magnetic layer with respect to the selected memory cell;
The first data write magnetic field mainly includes a component in a direction along the hard axis of the second magnetic layer,
The second data write magnetic field mainly includes a component in a direction along the easy axis direction of the second magnetic layer,
2. The thin film magnetic memory device according to claim 1, wherein the first data write current line is disposed so as to form a predetermined angle with the easy axis direction. Each of the magnetic storage units has a rectangular shape,
3. The thin film magnetic memory device according to claim 2, wherein the first data write current line is arranged so as to form the predetermined angle with a long side direction of each of the magnetic memory units. The second data write current line is provided to be orthogonal to the easy axis direction of magnetization,
3. The thin film magnetic memory device according to claim 2, wherein the second data write magnetic field has a direction corresponding to a level of the stored data.   3. The thin film magnetic memory device according to claim 2, wherein the first and second data write current lines are provided in directions orthogonal to each other.   The sum of currents that flow through the first data write current line to write the stored data to the at least one selected memory cell is greater than the sum of currents that flow through the second data write current line. The thin film magnetic memory device according to claim 5, which is small. The first data write magnetic field is applied in the same direction regardless of the level of the stored data,
3. The thin film magnetic memory device according to claim 2, wherein the second data write magnetic field is applied in a direction corresponding to a level of the stored data. The magnetic storage unit
A third magnetic layer formed on the opposite side of the insulating layer and magnetized in the opposite direction to the second magnetic layer;
2. The thin film magnetic memory device according to claim 1, further comprising a non-magnetic intermediate layer formed between the second and third magnetic layers.

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