JP2011205471A - Gain variable circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the distribution wiring of a gain control signal, to achieve a high frequency/broadband of a circuit, and to increase a gain variable width in a negative direction.SOLUTION: The gain variable circuit includes: a variable gain amplifier (VGA) 1 for amplifying an input signal In; a fixed gain amplifier (Amp) 2 for amplifying an output signal Out 1 of the VGA 1; and an automatic gain control circuit (AGC) 3 for detecting an amplitude of an output signal Out 2 of the Amp 2, and controlling a gain of the VGA 1 so that the detected amplitude may be the same as a predetermined set value of an amplitude. The VGA 1 is a Gilbert cell type variable gain amplifier.

Description

  The present invention relates to a variable gain circuit which is an amplifier circuit having a variable gain function.

  Conventionally, there has been proposed a gain variable circuit in which a plurality of variable gain amplifiers (hereinafter, abbreviated as VGA) are connected in cascade to expand a gain variable width (see, for example, Patent Document 1). FIG. 8 is a block diagram showing the configuration of the variable gain circuit disclosed in Patent Document 1. In FIG. The gain variable circuit shown in FIG. 8 includes a VGA 100 that amplifies an input signal In, a VGA 101 that amplifies an output signal Out1 of the VGA 100, and an automatic gain adjustment circuit that outputs a gain control signal VGC to control the gains of the VGAs 100 and 101. (Auto Gain Control Circuit, hereinafter abbreviated as AGC) 102.

  The AGC 102 generates the gain control signal VGC so that the amplitude of the output signal Out2 of the second-stage VGA 101 is equal to the amplitude setting value preset in the AGC 102. The gains of the two VGAs 100 and 101 are set in advance so that the gain of the preceding VGA 100 is smaller than the gain of the subsequent VGA 101. Due to the characteristics related to the gain setting of the VGAs 100 and 101, the amplitude of the input signal input to the VGA 101 is not excessively increased, and as a result, the low distortion performance of the variable gain circuit can be obtained.

  FIG. 9 shows a specific circuit configuration of the transistor levels of the VGAs 100 and 101 of the variable gain circuit shown in FIG. The VGA 100 supplies the transistors xt11 and xt12 that constitute the upper differential pair, the transistors xt21 and xt22 that also constitute the upper differential pair, the transistors xt5 and xt6 that constitute the lower differential pair, and the power supply voltage VCC supplied to one end. A collector resistor RL1 whose other end is connected to the collectors of the transistors xt11 and xt21, a power supply voltage VCC supplied to one end, a collector resistor RL2 whose other end is connected to the collectors of the transistors xt12 and xt22, and one end a transistor The emitter resistors RE11 and RE12 are connected to the emitters of xt11 and xt12, the other end is connected to the collector of the transistor xt5, one end is connected to the emitters of the transistors xt21 and xt22, and the other end is connected to the collector of the transistor xt6. Emitter resistance RE21 And RE22, one end is connected to the emitter of the transistor XT5, XT6, composed of a current source CS1 Metropolitan power supply voltage VEE is supplied to the other end.

  The VGA 101 includes transistors xt31 and xt32 constituting the upper differential pair, transistors xt41 and xt42 constituting the upper differential pair, transistors xt7 and xt8 constituting the lower differential pair, and a power supply voltage VCC at one end. , A collector resistor RL3 whose other end is connected to the collectors of the transistors xt31 and xt41, a power supply voltage VCC is supplied to one end, and a collector resistor RL4 whose other end is connected to the collectors of the transistors xt32 and xt42, and one end Is connected to the emitters of the transistors xt31 and xt32, the other end is connected to the emitters of the transistors xt41 and xt42, and the other end is connected to the collector of the transistor xt8. Emitter resistance R 41, and RE42, one end is connected to the emitter of the transistor XT7, XT8, composed of a current source CS2 Metropolitan power supply voltage VEE is supplied to the other end.

  Differential input signals DUT and DUC corresponding to the input signal In in FIG. 8 are input to the VGA 100. The AGC 102 detects the amplitudes of the differential output signals QT and QC corresponding to the output signal Out2 in FIG. 8, and outputs the differential control signals DLT and DLC corresponding to the gain control signal VGC in FIG.

  The VGAs 100 and 101 shown in FIG. 9 are VGAs called gain addition type, and two upper differential pairs having different gains due to different emitter resistance values are continuously switched by the lower differential pair to vary the gain. Is.

Here, VGA100 and VGA101 have a gain G (VGA100) and VGA101 gain G (VGA101) so that G (VGA100) <G (VGA101) satisfies the emitter resistance RE11 of the upper differential pair of VGA100 and VGA101. The resistance values of RE12, RE21, RE22, RE31, RE32, RE41, and RE42 are set as follows.
RE11 = RE12> RE31 = RE32 (1)
RE21 = RE22> RE41 = RE42 (2)

  That is, by making the emitter resistance value of the VGA 100 larger than the emitter resistance value of the VGA 101, the relationship of G (VGA100) <G (VGA101) can be obtained. From the relationship between the gains of the VGAs 100 and 101, similarly to the configuration of FIG. 8, the amplitude of the input signal to the VGA 101 need not be excessively increased, and as a result, the low distortion performance of the gain variable circuit can be obtained.

JP 2008-306613 A

  When the variable gain circuit shown in FIG. 8 is used, a distribution wiring for distributing the gain control signal VGC, which is the output of the AGC 102, to each of the VGAs 100 and 101 is required. This distribution wiring has a problem of increasing the circuit area required for the variable gain circuit. Further, in the variable gain circuit shown in FIG. 8, when the signal amplified by the VGAs 100 and 101 is a high frequency signal, there is a possibility that an adverse effect such as coupling due to the intersection of the high frequency signal wiring and the distribution wiring may be caused.

  When the variable gain circuit shown in FIG. 9 is used, there is a problem that it is difficult to extend the bandwidth of the variable gain circuit. In view of the operation principle of the gain addition type VGA, two transistors for receiving the input signal are required. For example, in the case of the VGA 100, two transistors xt11 and xt21 that receive the normal phase input signal DUT and two transistors xt12 and xt22 that receive the negative phase input signal DUC are provided. In the case of the VGA 101, two transistors xt32 and xt42 that receive a normal phase output signal output from the VGA 100 and two transistors xt31 and xt41 that receive a negative phase output signal output from the VGA 100 are provided. The reason why it is difficult to extend the bandwidth of the variable gain circuit is that two transistors are required for the input, and the input capacitance becomes large.

  Further, the variable gain circuit shown in FIG. 9 has a problem that it is difficult to increase the variable gain width, particularly in the negative direction (= loss direction). In order to increase the gain variable width in the negative direction with the circuit shown in FIG. 9, the emitter resistors RE21, RE22, RE41, 42 of the low-gain differential pair of the two upper differential pairs in each of the VGAs 100, 101 are used. The value needs to be increased. However, when the emitter resistance value is excessively increased, the collector potentials of the transistors xt6 and xt8, which are the constituent elements of the lower differential pair, are greatly reduced, and the current switching operation of the transistors xt6 and xt8 becomes impossible. VGA itself falls into impossibility. That is, in the gain variable circuit shown in FIG. 9, there is a great limitation on the increase of the gain variable width in the negative direction.

  The present invention has been made to solve the above-described problems, and can simplify the distribution wiring of the gain control signal, can increase the frequency and bandwidth of the circuit, increase the gain variable width, particularly in the negative direction. An object of the present invention is to provide a gain variable circuit capable of increasing the gain variable width.

  The variable gain circuit of the present invention includes a variable gain amplifier that amplifies an input signal, a fixed gain amplifier that amplifies an output signal of the variable gain amplifier, and an amplitude detected by detecting the amplitude of the output signal of the fixed gain amplifier. And an automatic gain adjustment circuit that controls the gain of the variable gain amplifier so that a preset amplitude setting value becomes equal, and the variable gain amplifier is a Gilbert cell type variable gain amplifier. To do.

  In one configuration example of the variable gain circuit according to the present invention, the variable gain amplifier includes an amplifying unit including a first amplifying transistor having a differential configuration to which the input signal is input, and the first amplifying transistor. Output signal of the first amplifying transistor according to gain control signals GCT and GCC inputted from the automatic gain adjusting circuit to the amplitude adjusting transistor. A constant current is supplied to the amplitude adjusting unit, the first output emitter follower including the first output transistor that receives the output signal of the amplitude adjusting transistor, and the amplifying unit and the amplitude adjusting unit. And a second current source for supplying a constant current to the first output emitter follower.

  Further, in one configuration example of the variable gain circuit according to the present invention, the fixed gain amplifier receives at least one differential amplifier that receives an output signal of the variable gain amplifier and an output signal of the differential amplifier at the final stage. A second output emitter follower including a second output transistor as an input; a third current source for supplying a constant current to the differential amplifier; and a second current source for supplying a constant current to the second output emitter follower. 4 and a parallel feedback resistor, and the differential amplifier is composed of a pair of second amplification transistors that receive the output signal of the variable gain amplifier, and the parallel feedback resistor. Thus, the output of the second output transistor is resistance-parallel fed back to the collector output of the second amplifying transistor constituting the first stage differential amplifier.

  Further, in one configuration example of the variable gain circuit according to the present invention, the amplifying unit of the variable gain amplifier has a positive phase input signal input to the base, and an emitter on the positive phase input side connected to the first current source. The variable gain comprises: the first amplification transistor; and the first amplification transistor on the negative phase input side having a negative phase input signal input to a base and an emitter connected to the first current source. The amplifier amplitude adjuster has the gain control signal GCT input to the base, the emitter connected to the collector of the first amplification transistor on the negative phase input side, and the collector connected to the first collector resistance on the positive phase output side The first amplitude adjusting transistor for positive phase output to which the power supply voltage is supplied via the first input transistor, the gain control signal GCT being input to the base, and the emitter being the first amplification transistor on the positive phase input side The gain control signal GCC is input to the first anti-phase output transistor for negative phase output, which is connected to the collector and supplied to the collector via the first collector resistor on the negative phase output side. A positive-phase output second transistor whose emitter is connected to the collector of the first amplification transistor on the negative-phase input side and whose collector is connected to the collector of the first amplitude-adjusting transistor for negative-phase output. The gain control signal GCC is input to the amplitude adjustment transistor and the base, the emitter is connected to the collector of the first amplification transistor on the positive phase input side, and the collector is the first for the positive phase output. A first output emitter follower of the variable gain amplifier, the second amplitude adjusting transistor for negative phase output connected to the collector of the amplitude adjusting transistor. , Output from a connection point between the collector of the first amplitude adjusting transistor for positive phase output, the collector of the second amplitude adjusting transistor for negative phase output, and the first collector resistor on the positive phase output side. The first output transistor for positive phase output that receives a normal phase output signal to be input, the collector of the first amplitude adjustment transistor for negative phase output, and the second amplitude for positive phase output A first output transistor for negative phase output that receives a negative phase output signal output from a connection point between the collector of the adjustment transistor and the first collector resistor on the negative phase output side. It is a feature.

  In one configuration example of the variable gain circuit of the present invention, the differential amplifier of the fixed gain amplifier has a base that receives a positive phase output signal output from the variable gain amplifier or the differential amplifier in the previous stage, The second amplifying transistor for negative phase output connected to the third current source and supplied with a power supply voltage via a second collector resistor on the negative phase output side to the collector, and the variable gain at the base A negative phase output signal output from the amplifier or the differential amplifier in the previous stage is input, the emitter is connected to the third current source, and the power supply voltage is supplied to the collector via the second collector resistor on the positive phase output side And a second output emitter follower of the fixed gain amplifier for the second amplification for the positive phase output of the differential amplifier at the final stage. Trang The second output transistor for positive phase output, which receives a positive phase output signal output from the connection point between the collector of the star and the second collector resistor on the positive phase output side, and the difference in the final stage A negative phase output signal having a negative phase output signal output from a connection point between the collector of the second amplification transistor for negative phase output of the dynamic amplifier and the second collector resistor on the negative phase output side as an input. And a second output transistor.

  According to the present invention, since the second-stage amplifier is a fixed gain amplifier, it is not necessary to distribute the gain control signal to the second-stage amplifier, so that the distribution wiring of the gain control signal can be simplified. In addition, the circuit area required for the variable gain circuit can be reduced. In addition, the possibility of adverse effects such as coupling due to the intersection of the high-frequency signal wiring and the distribution wiring can be reduced. In the present invention, since the number of amplification transistors for receiving an input signal can be reduced to one by using a Gilbert cell type variable gain amplifier, the input capacitance can be suppressed, and the gain variable circuit High frequency and wide band can be realized. Further, by using a Gilbert cell type variable gain amplifier, the gain variable width in the negative direction of the gain variable circuit can be increased. Further, in the present invention, by increasing the gain variable width in the negative direction of the first stage variable gain amplifier, the output signal of the variable gain amplifier is controlled not to be excessively large even if the amplitude of the input signal is large. As a result, the low distortion characteristics of the variable gain circuit can be realized.

  Further, the present invention includes an amplifying unit including a first amplifying transistor having a differential configuration to which an input signal is input, and an amplitude adjusting transistor having a differential configuration cascode-connected to the first amplifying transistor, An amplitude adjustment unit that adjusts the amplitude of the output signal of the first amplification transistor according to the gain control signals GCT and GCC input to the amplitude adjustment transistor from the automatic gain adjustment circuit, and an output signal of the amplitude adjustment transistor A first output emitter follower including a first output transistor, a first current source for supplying a constant current to the amplifying unit and the amplitude adjusting unit, and a first current source for supplying a constant current to the first output emitter follower. By providing two current sources, a Gilbert cell type variable gain amplifier can be realized.

  In the present invention, the fixed gain amplifier includes at least one differential amplifier that receives the output signal of the variable gain amplifier, and a second output transistor that receives the output signal of the differential amplifier at the final stage. A variable gain amplifier comprising a second output emitter follower and a parallel feedback resistor, and a differential amplifier comprising a pair of second amplification transistors that receive the output signal of the variable gain amplifier. Since the number of second amplifying transistors that receive the output signal can be reduced to one, the input capacitance can be suppressed, and the gain variable circuit can be increased in frequency and bandwidth. In the present invention, since the parallel feedback resistor is provided, the output of the second output transistor is fed back in parallel to the collector output of the second amplification transistor constituting the first-stage differential amplifier. Can be realized.

It is a block diagram which shows the structure of the gain variable circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the concrete circuit structure of the gain variable circuit which concerns on embodiment of this invention. It is a figure explaining operation | movement of the variable gain amplifier of the gain variable circuit which concerns on embodiment of this invention. It is a figure which shows the simulation result of the gain variable width and gain band of the conventional gain variable circuit. It is a figure which shows the simulation result of the gain variable width and gain band of the gain variable circuit which concerns on embodiment of this invention. It is a figure which shows the simulation result of the distortion characteristic of the conventional gain variable circuit. It is a figure which shows the simulation result of the distortion characteristic of the gain variable circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the conventional variable gain circuit. FIG. 9 is a circuit diagram showing a specific circuit configuration of the variable gain circuit of FIG. 8.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a variable gain circuit according to an embodiment of the present invention. The variable gain circuit according to the present embodiment includes a VGA 1 that amplifies an input signal In, a fixed gain amplifier (hereinafter abbreviated as Amp) 2 that amplifies an output signal Out 1 of the VGA 1, and a gain control signal that outputs a gain control signal. And AGC 3 for controlling the gain.

VGA1 amplifies input signal In and outputs output signal Out1. Amp2 amplifies the output signal Out1 of VGA1 and outputs an output signal Out2. The reason why the VGA 1 and Amp 2 are cascaded in this way is to obtain a high gain.
The AGC 3 detects the amplitude of the output signal Out2 of the Amp 2, and generates a gain control signal so that the detected amplitude becomes equal to the amplitude set value preset in the AGC 3, thereby controlling the gain of the VGA 1.

  8 and FIG. 9 is different from the conventional gain variable circuit shown in FIGS. 8 and 9 in that the second-stage amplifier has a fixed gain Amp2 and that the first-stage VGA1 has a large gain variable width in the negative direction. . In the present embodiment, since the second-stage amplifier is set to Amp 2 having a fixed gain, it is not necessary to distribute the gain control signal to the second-stage amplifier, thereby simplifying the distribution wiring of the gain control signal. Therefore, the circuit area required for the variable gain circuit can be reduced. In addition, the possibility of adverse effects such as coupling due to the intersection of the high-frequency signal wiring and the distribution wiring can be reduced.

Further, in the present embodiment, by increasing the gain variable width in the negative direction of the first-stage VGA1, the signal Out1 that is the output of the VGA1 and the input of the Amp2 is not excessively large even if the amplitude of the input signal In is large. As a result, the low distortion characteristic of the variable gain circuit can be obtained in the present embodiment as in the conventional case.
In the present embodiment, when the gain of the VGA1 -G ₁₁ ~ + G _12, the gain of Amp2 + G _{2 to, | G 11 |> | G} 2 |> | G 12 | relationship of.

  FIG. 2 shows a specific circuit configuration of transistor levels of VGA1 and Amp2 of the variable gain circuit according to the present embodiment. The circuit configuration of the VGA 1 is a so-called Gilbert cell. For example, the document “PR Gray, PJ Furst, SH Levis, RG Mayer, Kunihiro Asada, and Director Nagata , “Analog Integrated Design Technology for System LSI (Part 2)”, Fourth Edition, Bafukan, p.263-264, 2003 ”.

  As shown in FIG. 2, the VGA 1 according to the present embodiment is for amplitude adjustment that constitutes an upper differential pair (amplitude adjustment unit) that adjusts output amplitude in accordance with gain control signals GCT and GCC input to the base. Transistors Q1 and Q2, amplitude adjusting transistors Q3 and Q4 that also form an upper differential pair (amplitude adjusting unit), and a lower differential pair (a positive phase input signal DT and a negative phase input signal DC are input to the base) Amplifying transistors Q5 and Q6 constituting the amplifying part), an output transistor Q7 whose base is connected to the collectors of the amplifying transistors Q2 and Q4, and whose power supply voltage VCC is supplied to the collector, and whose base is the amplifying transistor Q1, The output transistor Q8 is connected to the collector of Q3, the power supply voltage VCC is supplied to the collector, and one end is connected to the emitter of the amplifying transistor Q5 A current source IS1 to which the power supply voltage VEE is supplied to the other end, one end connected to the emitter of the amplifying transistor Q6, a current source IS2 to which the other end is supplied with the power supply voltage VEE, and one end to the emitter of the output transistor Q7 Is connected to the other end, and the other end is supplied with the power source voltage VEE, one end is connected to the emitter of the output transistor Q8, the other end is supplied with the power source voltage VEE, and the other end is supplied with the power source voltage VEE. VCC is supplied, the other end is connected to the collector of the amplitude adjusting transistors Q1 and Q3, the collector resistor R1 is connected to one end, the power supply voltage VCC is supplied to one end, and the other end is connected to the collectors of the amplitude adjusting transistors Q2 and Q4. The collector resistor R2 has one end connected to the emitter of the amplifying transistor Q5 and the other end connected to the emitter of the amplifying transistor Q6. A resistor R3 Metropolitan.

  The collector of the amplifying transistor Q5 is connected to the emitters of the amplitude adjusting transistors Q1 and Q2, and the collector of the amplifying transistor Q6 is connected to the emitters of the amplitude adjusting transistors Q3 and Q4. The output transistor Q7 and the current source IS3 constitute an output emitter follower, and similarly, the output transistor Q8 and the current source IS4 constitute an output emitter follower. Then, a normal phase output signal OT is output from the emitter of the output transistor Q7, and a negative phase output signal OC is output from the emitter of the output transistor Q8.

  As shown in FIG. 2, the Amp 2 according to the present embodiment includes amplifying transistors Q9 and Q10 constituting a differential amplifier in which the differential output signals OT and OC of the VGA1 are input to the base, and an amplifying transistor Q9 at the base. , Q10, amplifying transistors Q11 and Q12 constituting a differential amplifier to which a differential signal output from the collector is input, and a base is connected to the collector of the amplifying transistor Q11, and a power supply voltage VCC is supplied to the collector. The output transistor Q13, the base is connected to the collector of the amplifying transistor Q12, the output transistor Q14 to which the power supply voltage VCC is supplied to the collector, one end connected to the emitters of the amplifying transistors Q9 and Q10, and the other end Current sources IS5 and IS6 to which the power supply voltage VEE is supplied, and one end of the amplifying transistor Q1 , Q12, a current source IS7 connected to the emitter of Q12, the other end being supplied with the power supply voltage VEE, a current source IS8 having one end connected to the emitter of the output transistor Q13 and the other end supplied with the power supply voltage VEE, One end is connected to the emitters of the amplifying transistors Q11 and Q12, the other end is connected to the power supply voltage VEE, and the other end is connected to the emitter of the output transistor Q14, and the other end is supplied with the power supply voltage VEE. Current source IS10, a power source voltage VCC supplied to one end, a collector resistor R4 connected to the collector of the amplifying transistor Q9 at the other end, a power source voltage VCC supplied to one end, and the other end of the amplifying transistor Q10 The collector resistor R5 connected to the collector, the power supply voltage VCC is supplied to one end, and the other end is a collection of the amplifying transistor Q11. Is connected to the collector resistor R6, one end is supplied with the power supply voltage VCC, the other end is connected to the collector of the amplifying transistor Q12, the other end is connected to the emitter of the output transistor Q13, and the other end Is connected to the collector of the amplifying transistor Q9, the parallel feedback resistor R8 is connected to the collector of the amplifying transistor Q10, and the other end is connected to the collector of the amplifying transistor Q10. Composed.

  The output transistor Q13 and the current source IS8 constitute an output emitter follower, and similarly, the output transistor Q14 and the current source IS10 constitute an output emitter follower. Then, a normal phase output signal QT is output from the emitter of the output transistor Q13, and a negative phase output signal QC is output from the emitter of the output transistor Q14.

  FIG. 3 is a diagram for explaining the operation of the VGA 1 of the present embodiment. In VGA1, the positive phase input signal DT and the negative phase input signal DC corresponding to the input signal In of FIG. 1 are input to the amplifying transistors Q5 and Q6 constituting the lower differential pair, and the amplitude constituting the upper differential pair. The gain control signals GCT and GCC are input to the adjustment transistors Q1 and Q2, and the gain control signals GCT and GCC are input to the amplitude adjustment transistors Q4 and Q3 that also form the upper differential pair. Then, a negative phase output signal OC is output via the output transistor Q8 from the connection point between the collectors of the amplitude adjusting transistors Q1 and Q3 and the collector resistor R1, and the collectors and collector resistors R2 of the amplitude adjusting transistors Q2 and Q4 The positive phase output signal OT is output from the connection point via the output transistor Q7. The normal phase output signal OT and the negative phase output signal OC correspond to the output signal Out1 in FIG.

As shown in FIG. 3, when the collector current flowing through the amplifying transistor Q5 is + Ic, the collector current flowing through the amplifying transistor Q6 is -Ic.
The differential current (Ic, −Ic) generated by the lower differential pair is distributed to the two amplitude adjusting transistors constituting the upper differential pair with a distribution ratio α. That is, of the collector current + Ic flowing through the amplification transistor Q5, a current of + αIc is distributed to the amplitude adjustment transistor Q1, and a current of + (1−α) Ic is distributed to the amplitude adjustment transistor Q2. Of the collector current (-Ic) flowing through the amplifying transistor Q6, a current -αIc is distributed to the amplitude adjusting transistor Q4, and a current-(1-α) Ic is distributed to the amplitude adjusting transistor Q3. The

  The distributed currents are combined in a combination that is in an opposite phase relationship to each other. That is, αIc and-(1-α) Ic are synthesized, and -αIc and (1-α) Ic are synthesized. As a result, a current of + (2α-1) Ic flows through the collector resistor R1, and a current of-(2α-1) Ic flows through the collector resistor R2.

  The distribution ratio α is determined by the magnitude relationship between the voltage values of the gain control signals GCT and GCC. For example, α = 1 if GCT >> GCC, α = 0.5 if GCT = GCC, and α = 0 if GCT << GCC. Note that α is not limited to 1,0.5,0 but can take a continuous value of 1 to 0.5 in the region of GCT> GCC and 0.5 to 0 in the region of GCT <GCC. .

  Here, assuming that the potential rise is positive, the potential drop is negative, and the resistance values of the collector resistors R2 and R1 are RL, the amplitude of the positive phase output signal OT output from the VGA1 is (2α-1) IcRL, The amplitude of the output signal OC is − (2α−1) IcRL, and the differential output amplitude is expressed as 2 (2α−1) IcRL.

  Therefore, the differential output amplitude is 2IcRL when GCT >> GCC, 0 when GCT = GCC, and −2IcRL when GCT << GCC (the negative sign of the amplitude indicates phase inversion). Thus, according to the VGA 1 of the present embodiment, the differential output amplitude can be varied in the range of 2IcRL to 0 to −2IcRL.

  The VGA 1 of the present embodiment distributes the current generated by the lower differential pair to the two amplitude adjustment transistors that constitute the upper differential pair. Further, in addition to such a distribution function, a synthesis function for synthesizing a normal phase signal and a negative phase signal is provided. That is, the combined result of the positive phase signal output from the collector of the amplitude adjusting transistor Q3 and the negative phase signal output from the collector of the amplitude adjusting transistor Q1 is output as the negative phase output signal OC, and the amplitude adjusting transistor Q2 is output. The combined result of the negative phase signal output from the collector of the positive phase signal and the positive phase signal output from the collector of the amplitude adjusting transistor Q4 is output as the positive phase output signal OT. Thus, the VGA 1 of the present embodiment changes the output amplitude by the distribution function and the synthesis function.

  In the VGA 1 configured as described above, the number of amplifying transistors that receive the differential input signals DT and DC is one each, and the number of transistors that receive the input signals is two compared to the conventional VGA 100 that has two transistors. Since the number is small, the input capacitance can be suppressed, and the high frequency and wide band of the variable gain circuit can be realized. In addition, when the gain control signals GCT and GCC are GCT = GCC, the Gilbert cell type VGA has a gain of −∞ (dB) in principle, so that the gain variable width in the negative direction of the gain variable circuit is increased. Can be realized.

  Amp2 of the present embodiment amplifies differential output signals OT and OC output from VGA 1 and outputs differential output signals QT and QC. This Amp2 is composed of two differential amplifiers and an output emitter follower, and the outputs of the output transistors Q13 and Q14 constituting the output emitter follower are the collector outputs of the amplification transistors Q9 and Q10 constituting the first stage differential amplifier. The circuit configuration is such that resistance parallel feedback is performed. Needless to say, Amp2 does not have a variable gain function, and is a fixed gain amplifier. However, since two differential amplifiers are used, the gain is high, which contributes to an increase in gain variable width on the high gain side of the gain variable circuit of the present embodiment.

  In Amp2, the number of amplifying transistors that receive the differential output signals OT and OC output from the VGA1 is one, compared with the conventional VGA101 that has two transistors that receive the input signal. Since the number of transistors is small, the input capacitance can be suppressed, and the high frequency and wide band of the variable gain circuit can be realized. Further, in the present embodiment, since resistance parallel feedback is used, it is possible to further widen the bandwidth by the feedback effect.

  The AGC 3 detects the amplitude of the differential output signals QT and QC output from the Amp 2 and generates gain control signals GCT and GCC based on the difference between the amplitude and a preset amplitude setting value. Thus, the AGC 3 controls the gain of the VGA 1 so that the amplitudes of the differential output signals QT and QC are equal to the amplitude setting value.

  4A shows a simulation result of the gain variable width of the conventional gain variable circuit shown in FIG. 9, and FIG. 4B shows a simulation result of the gain band of the conventional gain variable circuit. 5A and 5B are diagrams showing simulation results of the variable gain width of the variable gain circuit according to the present embodiment, and FIG. 5C is a simulation of the gain band of the variable gain circuit according to the present embodiment. It is a figure which shows a result. FIG. 5B is an enlarged view of FIG.

  GC in FIGS. 4A, 5A, and 5B indicates the value of the differential voltage that is the difference between the gain control signals GCT and GCC. 4A, 5A, and 5B, the horizontal axis represents frequency, and the vertical axis represents gain. 4B and 5C, the horizontal axis represents the differential voltage, and the vertical axis represents the cutoff frequency. The conventional variable gain circuit and the variable gain circuit of the present embodiment use InP heterojunction transistors (HBT) having the same characteristics. Also, VCC = + 3.3V and VEE = 0V (ground potential) are applied as power sources in both the conventional gain variable circuit of FIG. 9 and the gain variable circuit of the present embodiment of FIG.

  According to FIG. 4A, the gain variable width is 18.9 dB in the conventional gain variable circuit, whereas in this embodiment, the gain variable width is 100 dB or more as shown in FIG. 5A. It is possible to obtain in simulation. Further, even if the band of the conventional gain variable circuit shown in FIG. 4B and the band of the present embodiment shown in FIG. 5C are compared, the conventional gain variable circuit has only a band of 20 GHz or less. In contrast, in the present embodiment, it can be seen that a band of 20 GHz or more can be secured for all gain control signals.

  6A and 6B are diagrams showing simulation results of distortion characteristics of the conventional gain variable circuit shown in FIG. 9, and FIGS. 7A and 7B are gains of this embodiment. It is a figure which shows the simulation result of the distortion characteristic of a variable circuit. 6A and 7A are diagrams showing frequency spectra at the output of the variable gain circuit, where the horizontal axis represents frequency and the vertical axis represents signal intensity. 6B and 7B are diagrams showing output signal waveforms of the variable gain circuit, in which the horizontal axis represents time and the vertical axis represents voltage. 6 (A) and 6 (B) are reprinted results disclosed in Patent Document 1. FIG. In both the conventional and the present embodiment, the input signal amplitude to the gain variable circuit is 300 mVpp and the input signal frequency is 3 GHz.

  From FIG. 6 (A) and FIG. 7 (A), the ratio of the component of the third harmonic 9 GHz to the component of the input signal frequency 3 GH can be obtained. In the conventional gain variable circuit, the ratio of the third harmonic 9 GHz component to the input signal frequency 3 GHz component is −22.7 dB, whereas in the present embodiment, the ratio is −53.1 dB. It can be seen that a good suppression ratio of 30 dB or more can be obtained.

  The present invention can be applied to an amplifier circuit having a variable gain function.

  DESCRIPTION OF SYMBOLS 1 ... Variable gain amplifier, 2 ... Fixed gain amplifier, 3 ... Automatic gain adjustment circuit, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14 ... Transistor, IS1 IS2, IS3, IS4, IS5, IS6, IS7, IS8, IS9, IS10 ... current source, R1, R2, R3, R4, R5, R6, R7, R8, R9 ... resistance, In ... input signal, Out1, OutT2 ... Output signal, DT ... Normal phase input signal, DC ... Negative phase input signal, OT, QT ... Normal phase output signal, OC, QC ... Negative phase output signal, GCT, GCC ... Gain control signals GCT, GCC.

Claims (5)

A variable gain amplifier for amplifying the input signal;
A fixed gain amplifier that amplifies the output signal of the variable gain amplifier;
An automatic gain adjustment circuit that detects the amplitude of the output signal of the fixed gain amplifier and controls the gain of the variable gain amplifier so that the detected amplitude is equal to a preset amplitude setting value;
The variable gain circuit according to claim 1, wherein the variable gain amplifier is a Gilbert cell type variable gain amplifier. The gain variable circuit according to claim 1, wherein
The variable gain amplifier includes:
An amplifying unit including a first amplifying transistor having a differential configuration to which the input signal is input;
The first amplifying transistor includes a differential amplitude adjusting transistor cascode-connected, and the first gain control signal is input to the amplitude adjusting transistor from the automatic gain adjusting circuit according to the gain control signals GCT and GCC. An amplitude adjustment unit for adjusting the amplitude of the output signal of the amplification transistor;
A first output emitter follower including a first output transistor that receives the output signal of the amplitude adjusting transistor;
A first current source for supplying a constant current to the amplification unit and the amplitude adjustment unit;
And a second current source for supplying a constant current to the first output emitter follower. The gain variable circuit according to claim 1 or 2,
The fixed gain amplifier is:
At least one differential amplifier that receives the output signal of the variable gain amplifier;
A second output emitter follower including a second output transistor that receives the output signal of the differential amplifier at the final stage;
A third current source for supplying a constant current to the differential amplifier;
A fourth current source for supplying a constant current to the second output emitter follower;
Consisting of parallel feedback resistors,
The differential amplifier includes a pair of second amplifying transistors that receive the output signal of the variable gain amplifier,
A variable gain circuit, wherein the parallel feedback resistor provides resistance parallel feedback of the output of the second output transistor to the collector output of the second amplifying transistor constituting the first stage differential amplifier. The gain variable circuit according to claim 2 or 3,
The amplification unit of the variable gain amplifier includes:
A positive phase input signal is input to the base, an emitter is connected to the first current source, the first amplification transistor on the positive phase input side, a negative phase input signal is input to the base, and the emitter is the first The first amplifying transistor on the negative phase input side connected to the current source of 1;
The amplitude adjustment unit of the variable gain amplifier is:
The gain control signal GCT is input to the base, the emitter is connected to the collector of the first amplifying transistor on the negative phase input side, and the power supply voltage is supplied to the collector via the first collector resistor on the positive phase output side A first amplitude adjusting transistor for a positive phase output,
The gain control signal GCT is input to the base, the emitter is connected to the collector of the first amplification transistor on the positive phase input side, and the power supply voltage is supplied to the collector via the first collector resistor on the negative phase output side The first amplitude adjusting transistor for reverse phase output,
The gain control signal GCC is input to the base, the emitter is connected to the collector of the first amplification transistor on the negative phase input side, and the collector is connected to the collector of the first amplitude adjusting transistor for negative phase output. The second amplitude adjusting transistor for positive phase output,
The gain control signal GCC is input to the base, the emitter is connected to the collector of the first amplification transistor on the positive phase input side, and the collector is connected to the collector of the first amplitude adjustment transistor for the positive phase output. Second amplitude adjusting transistor for reverse phase output,
The first output emitter follower of the variable gain amplifier includes a collector of the first amplitude adjusting transistor for the positive phase output, a collector of the second amplitude adjusting transistor for the negative phase output, and the positive phase output side. Of the first output transistor for positive phase output that receives the positive phase output signal output from the connection point of the first collector resistor and the first amplitude adjustment transistor for negative phase output. A negative phase output signal having a negative phase output signal output from a connection point between a collector and a collector of the second amplitude adjusting transistor for positive phase output and the first collector resistor on the negative phase output side as an input. A variable gain circuit comprising: the first output transistor. The gain variable circuit according to claim 3 or 4,
The differential amplifier of the fixed gain amplifier has a base to which a positive phase output signal output from the variable gain amplifier or the differential amplifier of the previous stage is input, an emitter is connected to the third current source, and a collector has a negative phase The second amplifying transistor for anti-phase output to which the power supply voltage is supplied via the second collector resistor on the output side, and the anti-phase output output from the variable gain amplifier or the previous-stage differential amplifier to the base The second amplifying transistor for positive phase output in which a signal is input, the emitter is connected to the third current source, and the power supply voltage is supplied to the collector via the second collector resistor on the positive phase output side And
The second output emitter follower of the fixed gain amplifier is connected to the collector of the second amplification transistor for positive phase output of the differential amplifier in the final stage and the second collector resistor on the positive phase output side. A second output transistor for positive phase output that receives a positive phase output signal output from a point, and a collector of the second amplification transistor for negative phase output of the differential amplifier at the final stage; A gain variable circuit comprising: the second output transistor for negative phase output that receives a negative phase output signal output from a connection point with the second collector resistor on the negative phase output side. .

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