JP2011205040A - Semiconductor substrate and photoelectric conversion element, and method of manufacturing them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance electron recovery efficiency and to achieve improvement in sensitivity in a long-wavelength range and fast electron recovery.SOLUTION: An electron transfer speed in a semiconductor substrate is increased by giving an impurity concentration of the semiconductor substrate a concentration gradient from a standard concentration to a high concentration with depth, to quickly transfer electrons at a part deeper than a depletion part in a surface direction, and electron recovery is made to be fast by shortening a lifetime of a stray electron, thereby a time resolution is improved.

Description

  The present invention relates to a semiconductor substrate, a photoelectric conversion element, and a method for manufacturing the same, and more particularly, a semiconductor substrate and a photoelectric conversion element suitable for use in manufacturing a solid-state image sensor or a solid-state image sensor integrated circuit in which the solid-state image sensor is integrated. And a manufacturing method thereof.

  Conventionally, a photoelectric conversion element is manufactured using a semiconductor substrate, and a solid-state imaging element integrated circuit in which a solid-state imaging element and a solid-state imaging element are integrated using a photoelectric conversion element is manufactured.

  However, in such a solid-state imaging device, particularly a solid-state imaging device that requires high-speed electron recovery, in a semiconductor substrate having a uniform impurity concentration that has been conventionally used, electron recovery is performed by electrons straying in the semiconductor substrate. It has been pointed out that there is a problem that the time resolution is lowered and the temporal resolution is lowered.

  In particular, when a solid-state imaging device is irradiated with near infrared light in a long wavelength region (wavelength 750 nm to 900 nm), light that is transmitted without being absorbed deeply into the semiconductor substrate is generated. The light transmitted deeply is absorbed deep in the semiconductor substrate, and electrons are generated deep in the semiconductor substrate. Thus, electrons generated deep in the semiconductor substrate are strayed.

  Therefore, when the solid-state imaging device is irradiated with near-infrared light in a long wavelength region (wavelength 750 nm to 900 nm), the influence of delay of electron recovery due to electrons straying in the semiconductor substrate is large, and the time resolution is mainly reduced. It was the cause.

  In addition, since some of the electrons straying in the semiconductor substrate recombine with holes, the sensitivity of near-infrared light is drastically lowered in the solid-state imaging device.

Here, in a photoelectric conversion element such as a PN junction photodiode or photogate manufactured using a semiconductor substrate, the electron recovery efficiency is increased, the sensitivity in a long wavelength region is increased, and the electron recovery speed is increased. As an improvement method for this purpose, a method mainly aimed at expanding the depletion layer has been adopted.

  As a conventional technique for expanding such a depletion layer, for example, in Japanese Patent Laid-Open No. 7-86543 presented as Patent Document 1, intrinsic silicon which is an insulating layer is provided between a P-type semiconductor layer and an N-type semiconductor layer. A technique for integrating pinned PIN structures is disclosed, and Japanese Patent Application Laid-Open No. 2008-34836 presented as Patent Document 2 discloses a low-concentration N-type semiconductor layer and a low-concentration P-type semiconductor layer that are close to intrinsic. Is disclosed by controlling the epitaxial crystal growth.

  However, the former of the two methods described above has a problem in that it has poor technical stability during manufacturing because a semiconductor substrate having a very low impurity concentration is used.

  In addition, the latter of the above two methods requires a crystal growth process controlled with extremely high precision, and is consistent with the design method and manufacturing method that have been performed so far in the manufacture of semiconductor substrates. There is a problem that it is low and resources that have been used in the manufacture of semiconductor substrates cannot be used effectively.

On the other hand, as disclosed in Japanese Patent Application Laid-Open No. 2009-180659 presented as Patent Document 3 as a technique for increasing electron recovery efficiency, light is irradiated from the back side of a solid-state imaging device configured using a semiconductor substrate. Backside illumination techniques have been proposed.

Although this backside irradiation technology seems to be improved in terms of increasing electron recovery efficiency, it is not easy to shorten the electron recovery time, and it is insufficient in terms of improving time resolution. It was.
Japanese Unexamined Patent Publication No. 7-86543 JP 2008-34836 A JP 2009-180659 A

  The present invention has been made in view of the various problems of the prior art as described above, and its object is to increase the efficiency of electron recovery and increase sensitivity in a long wavelength region. It is an object of the present invention to provide a semiconductor substrate and a photoelectric conversion element that can increase the speed of electron recovery.

  Further, the object of the present invention is to achieve an electron recovery efficiency by a relatively minor process change that is highly compatible with conventionally used photoelectric conversion technologies such as photodiodes and photogates, and CMOS image sensor technology. Semiconductor substrate manufacturing method and photoelectric conversion element manufacturing method capable of manufacturing a semiconductor substrate and a photoelectric conversion element capable of increasing the sensitivity in the long wavelength region and increasing the speed of electron recovery Is to provide a method.

  In order to achieve the above object, the present invention provides an electron transfer rate in a semiconductor substrate by providing a concentration gradient in which the impurity concentration of the semiconductor substrate shifts to a higher concentration than the standard concentration as the depth increases. In addition, by moving electrons deeper than the depletion layer toward the surface quickly, and shortening the lifetime of the stray electrons, the electron recovery speed is increased and the time resolution is improved.

  More specifically, for example, the epitaxial crystal growth layer constituting the semiconductor substrate is provided with a concentration gradient so that the impurity concentration becomes higher than the standard concentration as the depth from the surface of the semiconductor substrate increases. Yes, this increases the electron transfer speed in the epitaxial crystal growth layer, moves electrons deeper than the depletion layer to the surface quickly, and shortens the lifetime of stray electrons, thereby speeding up electron recovery. This improves the time resolution.

  Therefore, according to the present invention, for example, on the surface on which a device is formed using a mask with respect to a semiconductor substrate and the surface layer at a depth of 2 μm from the surface, the standard impurity concentration conventionally used by the device is used as it is. Since it can be used, it can be designed and manufactured without changing the conventional method, and the electron recovery efficiency can be improved, the sensitivity in the long wavelength region can be increased, and the electron recovery speed can be increased. It becomes like this.

  In other words, according to the present invention, the time resolution of the photoelectric conversion element manufactured on the semiconductor substrate can be increased only by changing the manufacturing process of the semiconductor substrate without changing the design and manufacturing process of the existing standard CMOS integrated circuit. Can be improved.

That is, the semiconductor substrate according to the present invention is a semiconductor substrate constituting a photoelectric conversion element structure having a depletion layer on the front surface side, and has an impurity concentration gradient from the front surface side to the back surface side of the semiconductor. Is doped.

  The semiconductor substrate according to the present invention is the above-described semiconductor substrate according to the present invention, wherein the impurity is a P-type impurity, and the concentration gradient increases from the front surface side to the back surface side. It is intended to be.

  Further, the semiconductor substrate according to the present invention is the above-described semiconductor substrate according to the present invention, wherein the concentration on the surface side in the concentration gradient is a concentration capable of constituting the photoelectric conversion element structure, and the concentration gradient is on the surface side. The P-type impurity concentration is monotonously increased from the above toward the back side.

  The semiconductor substrate according to the present invention is the above-described semiconductor substrate according to the present invention, wherein the concentration gradient is an exponentially increasing concentration gradient, and the average increase rate of the concentration is 1.05 times or more per 1 μm in the depth direction. It is what you have.

  In the photoelectric conversion device according to the present invention, an N-type semiconductor layer is formed on the surface of the semiconductor substrate according to the present invention, and the depletion layer is formed on the surface side of the semiconductor substrate.

  The method for producing a semiconductor substrate according to the present invention is a method for producing a semiconductor substrate comprising a photoelectric conversion element structure having a depletion layer on the surface side, wherein the concentration is higher than the concentration capable of constituting the photoelectric conversion element structure. On the bulk silicon substrate by supplying a raw material having a concentration of the P-type impurity fixed to a concentration capable of constructing the photoelectric conversion element structure by epitaxial growth on the bulk silicon substrate that has been heat-treated after doping with the P-type impurity in A concentration in which a P-type epitaxial layer is formed by epitaxial growth, and the concentration of the P-type impurity in the P-type epitaxial layer monotonously increases in the direction from the surface of the P-type epitaxial layer to the bulk silicon substrate due to diffusion of the P-type impurity. A semiconductor substrate having a gradient is formed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate, comprising: controlling the heat treatment time of the bulk silicon substrate in the method for manufacturing a semiconductor substrate according to the present invention; The gradient of the impurity concentration gradient is controlled.

  The method for producing a semiconductor substrate according to the present invention is a method for producing a semiconductor substrate comprising a photoelectric conversion element structure having a depletion layer on the surface side, wherein the concentration is higher than the concentration capable of constituting the photoelectric conversion element structure. In the initial stage of epitaxial growth, the concentration of the P-type impurity is set higher than the concentration at which the photoelectric conversion element structure can be formed on the bulk silicon substrate that has been heat-treated after being doped with the P-type impurity in step 1. The concentration of the P-type impurity is lowered according to the above, and in the final stage of the epitaxial growth, the raw material is supplied while controlling the concentration of the P-type impurity so as to be a concentration that can constitute the photoelectric conversion element structure. And the concentration of the P-type impurity in the P-type epitaxial layer is the P-type epitaxial layer. From the surface of the Kisharu layer is obtained so as to form a semiconductor substrate having a concentration gradient that increases monotonically in the direction towards the bulk silicon substrate.

  According to another aspect of the present invention, there is provided a method for manufacturing a photoelectric conversion element comprising: forming an N-type semiconductor layer on a surface of a P-type epitaxial layer of a semiconductor substrate manufactured by the method of manufacturing a semiconductor substrate according to the present invention; The depletion layer is formed.

  Since the present invention is configured as described above, it provides a semiconductor substrate and a photoelectric conversion element that can increase electron recovery efficiency, increase sensitivity in a long wavelength region, and increase the speed of electron recovery. There is an excellent effect of being able to.

  Further, since the present invention is configured as described above, it is a relatively light process that is highly compatible with conventional photoelectric conversion technologies such as photodiodes and photogates, and CMOS image sensor technology. Semiconductor substrate manufacturing method and semiconductor substrate manufacturing method capable of increasing electron recovery efficiency and improving sensitivity in a long wavelength region and speeding up electron recovery by the change And the outstanding effect that it comes to be able to provide the manufacturing method of a photoelectric conversion element is produced.

FIG. 1 is an explanatory diagram of a cross-sectional structure of a conventional photodiode. FIG. 2 is an explanatory diagram showing a state of movement of electrons and holes in the photodiode shown in FIG. FIG. 3 is an explanatory diagram showing the impurity concentration and the electrostatic potential with respect to the depth of the semiconductor substrate corresponding to the cross-sectional structure of the photodiode in the photodiode shown in FIG. FIG. 4 shows a cross-sectional structure of a photodiode, which is a photoelectric conversion element manufactured using a semiconductor substrate according to the present invention, and the impurity concentration and electrostatic potential with respect to the depth of the semiconductor substrate according to the present invention corresponding to the cross-sectional structure of the photodiode. FIG. 3 is an explanatory diagram corresponding to FIG. FIG. 5 is an explanatory view showing the state of movement of electrons and holes in the photodiode according to the present invention shown in FIG. FIG. 6 is a chart showing the relationship between the concentration gradient of the P-type impurity, the electrostatic potential gradient, and the time resolution realized by the electrostatic potential gradient. FIG. 7 is an explanatory view of a first manufacturing method in the method of manufacturing a semiconductor substrate according to the present invention. 8A and 8B are explanatory views of a second manufacturing method in the method of manufacturing a semiconductor substrate according to the present invention. FIG. 9 is a graph showing a doping profile obtained by the method for manufacturing a semiconductor substrate according to the present invention. FIGS. 10A and 10B are explanatory diagrams showing conditions and results of simulation performed by the inventor of the present application. FIG. 11A is a simulation result of a trajectory of electrons that freely move by phonon scattering, and FIG. 11B is a graph showing a moving speed of electrons in an electric field.

  Hereinafter, an example of an embodiment of a semiconductor substrate, a photoelectric conversion element, and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

  In the drawings of the accompanying drawings and the following description, the same or corresponding components are denoted by the same reference numerals.

I. Description for Easily Understanding the Present Invention First, a method for producing a solid-state imaging device using a semiconductor substrate will be described. The solid-state imaging device is formed on the surface of a bulk silicon substrate thinly cut from a silicon ingot. A semiconductor substrate (wafer) is formed by forming an epitaxial crystal growth layer (hereinafter referred to as an “epi layer” as appropriate) having few crystal defects, and a desired method is applied by implanting various ions into the wafer according to a mask. It is known that it is manufactured by forming a semiconductor element such as a photoelectric conversion part or FET.

  Conventionally, one of widely used wafers is doped with impurities such as boron forming a P-type semiconductor as impurities to be added to silicon (about 1 to the 15th power atom per cubic centimeter). In order to simplify the description, the notation of “the 15th power atom” is appropriately indicated as “1e15” in the following.)

  In such a wafer manufacturing method, an impurity is doped in a bulk silicon substrate so that the impurity concentration is 1e15, and an epitaxial layer having the same concentration is grown on the bulk silicon by 7 to 20 μm. A wafer is manufactured as an epitaxial substrate in which impurities are uniformly doped.

  The wafer, that is, the surface layer region having a depth of about 2 μm from the surface of the semiconductor substrate is doped with various impurities to achieve the purpose of the integrated circuit, thereby forming various semiconductor elements. However, among these semiconductor elements, those suitable for manufacturing using the semiconductor substrate according to the present invention are photoelectric conversion elements called photodiodes or photogates.

Therefore, in the following description, only the case where the photoelectric conversion element is formed as the semiconductor element formed on the semiconductor substrate according to the present invention will be described, and in the case where other semiconductor elements other than the photoelectric conversion element are formed. The explanation is omitted by using the following explanation.

  In addition, regarding the photodiode and the photogate which are photoelectric conversion elements, when both are formed on the semiconductor substrate according to the present invention, the effect of the semiconductor substrate according to the present invention on both is the same. Only that will be described.

  Furthermore, depending on the semiconductor substrate manufacturing method, wafers having different impurity concentrations may be used. In this case, the standard impurity concentration used by the manufacturing method (for example, the P-type impurity concentration is 2.5e15). Of course, the present invention can be applied to the present invention on the basis of the above, but in the following description of the embodiments, the impurity concentration of the reference wafer will be described as 1e15 in order to avoid complicated explanation.

Here, FIG. 1 shows an explanatory diagram of a cross-sectional structure of a conventional photodiode. The photodiode 100 includes a P-type epitaxial crystal growth layer (P) containing a P-type impurity on a P-type bulk silicon substrate 102. N-type impurities such as phosphorus are implanted from the surface of the semiconductor substrate (wafer) 106 on which the type epi layer 104 is formed to form an N-type semiconductor layer (N-type doped layer) 108 to form a so-called PN junction. A depletion layer 110 in which neither electrons nor holes are present is formed in the vicinity of the PN junction. In FIG. 1, the depletion layer 110 is indicated by a broken line.

  The photodiode 100 moves electrons and holes generated when light is absorbed by silicon atoms in the depletion layer 110 according to the electrostatic potential, and collects electrons in the N-type doped layer 108 near the surface. The photoelectric conversion element performs photoelectric conversion by collecting holes in the P-type epi layer 104 in the wafer 106 deeper than the surface.

Here, when the P-type epitaxial layer 104 of the wafer 106 contains P-type impurities at an impurity concentration of 1e15, the thickness T1 of the depletion layer 110 (distance measured in the depth direction from the surface where the N-type impurities are implanted). Is generally 2 to 3 μm.

  That is, the thickness T1 of the depletion layer 110 varies depending on the bias voltage 112 applied to the N-type doped layer 108 and the N-type impurity concentration of the N-type doped layer 108, but 2V to 5V used by a general image sensor. And a N-type impurity concentration (1e17 to 1e20) of about 3 μm at the maximum.

  In order to further increase the thickness T1 of the depletion layer 110, it is most effective to lower the P-type impurity concentration of the P-type epi layer 104 of the wafer 106, but it is necessary to mix various semiconductor devices. The integrated circuit is designed on the premise of a wafer containing about 1e15 of the P-type impurity, and it is not practical to set the impurity concentration to 1e14 or less.

  If an N-type impurity can be implanted at a high speed and the N-type impurity can be doped in a deeper portion of the wafer 106 with an impurity concentration close to 1e15, in principle, it is possible to expand a region equivalent to intrinsic silicon. It is known that N-type impurity atoms have a relatively heavy mass and are difficult to implant into the deep portion of the wafer 106, and this method is also impractical.

  That is, in a manufacturing process compatible with at least a standard CMOS integrated circuit manufacturing process, N-type impurity doping with a thickness exceeding several μm, a low concentration, and faithful to the mask layout cannot be realized.

  That is, the thickness T1 of the depletion layer 110 having high sensitivity to light has a limit of 2 to 3 μm as long as a manufacturing method close to the standard CMOS integrated circuit manufacturing process is used, and it is not easy to widen this.

Next, FIG. 2 shows an explanatory diagram showing the state of movement of electrons and holes in the photodiode 100 shown in FIG. 1, and with reference to FIG. A description will be given of how the generated electrons and holes move.

  Here, the light absorption of silicon depends on the wavelength, and light having a wavelength shorter than 600 nm is efficiently absorbed by the depletion layer 110 having a thickness T1 of 2 to 3 μm, and the generated electrons 200 and holes 202 are depleted. Moving according to the electrostatic potential inside layer 110, electrons 200 are attracted to N-type doped layer 18 (see arrow A in FIG. 2) and holes 202 escape in the opposite direction (see arrow B in FIG. 2). To do.)

  However, part of the light having a wavelength longer than 600 nm reaches the deep part of the wafer 106 without being absorbed by the depletion layer 110. For example, it is known that the depth at which 50% light with a wavelength of 700 nm is absorbed is 3.0 μm, and the depth at which 50% light with a wavelength of 800 nm is absorbed is about 9.0 μm.

  That is, more than half of the near-infrared light having a wavelength longer than 700 nm is not absorbed by the depletion layer 110 having a thickness T1 of 2 to 3 μm, but is transmitted to the deep part of the wafer 106.

  The light beam transmitted through the depletion layer 110 is absorbed by silicon atoms in the deep part of the wafer 106 to generate electrons 204 and holes 206.

  The holes 206 generated in the deep part of the wafer 106 are collected in the P-type epi layer 104, but the P-type impurity concentration of the P-type epi layer 104 is uniform at about 1e15 (impurities with respect to the depth of the semiconductor substrate shown in FIG. 3). (See the explanatory diagram showing the concentration and electrostatic potential corresponding to the cross-sectional structure of the photodiode.), And the electrostatic potential is almost uniform (the impurity concentration and electrostatic potential shown in FIG. Therefore, the electron 204 strays through the wafer 106 while undergoing free motion due to phonon scattering.

  Such stray electrons 204 are allowed to exist for a short time as minority carriers in the P-type epilayer 104, but disappear with recombination with holes with a certain probability, and with a certain probability with a depletion layer due to the photodiode 100 near the surface. 110 is reached.

  The electrons 204 that reach the depletion layer 110 by the photodiode 100 near the surface with a certain probability are immediately attracted to the N-type doped layer 108 and collected, thereby contributing to photosensitivity. Since it is collected with a delay, the time resolution of the photodiode 100 with respect to the light is reduced.

  Here, it is known that electrons due to phonon scattering move about 10 nm on average in a random direction at a rate of about once every 1 psec.

  When the stochastic process is simulated (refer to the simulation result of the trajectory of free-moving electrons by phonon scattering shown in FIG. 11A), it is expected to stray in the range of about 2 to 3 μm in 1 μsec.

  That is, if the P-type epi layer 104 of the wafer 106 has a completely uniform concentration, a stray time of at least several μsec will occur if the thickness is 7 to 20 μm.

  On the other hand, it is known that the frequency of recombination is proportional to the product of the hole concentration and the electron concentration, but the average electron lifetime in the Pe type epi layer 104 of 1e15 is about several μsec. It is known that electrons straying longer than that are expected to disappear.

  As a result, the near-infrared light in the photoelectric conversion element typified by the photodiode 100 constructed in the conventional CMOS integrated circuit in which the P-type impurity concentration of the wafer 106 is uniform as shown in FIGS. The time resolution is several μsec, and the frequency is several hundreds KHz. It can be seen that the optical signal having a faster frequency causes a sharp attenuation of the amplitude.

II. Description of Semiconductor Substrate According to the Present Invention The semiconductor substrate according to the present invention has been devised in view of the above-described knowledge, and increases the P-type impurity concentration with a moderate gradient from the surface of the semiconductor substrate toward the deep portion. It is a thing.

  FIG. 4 shows the cross-sectional structure of a photodiode, which is a photoelectric conversion element manufactured using a semiconductor substrate according to the present invention, and the impurity concentration and electrostatic potential with respect to the depth of the semiconductor substrate according to the present invention corresponding to the cross-sectional structure of the photodiode. An explanatory diagram corresponding to FIG. 2 is shown.

  This photodiode 10 is a semiconductor in which a P-type epitaxial crystal growth layer (P-type epilayer) 14 doped with P-type impurities with a concentration gradient is formed on a P-type bulk silicon substrate 12 doped with P-type impurities at a high concentration. An N-type impurity such as phosphorus is implanted from the surface of the substrate (wafer) 16 to form an N-type semiconductor layer (N-type doped layer) 108 to form a so-called PN junction. A depletion layer 110 in which neither electrons nor holes are present is formed. In FIG. 4, the depletion layer 110 is indicated by a broken line.

  More specifically, the P-type epi layer 14 has a concentration gradient such that the P-type impurity concentration increases from the surface of the wafer 16 toward the deep part.

  Specifically, the P-type impurity concentration of the P-type epi layer 14 is about 1e15 at a depth of 2 to 3 μm from the surface of the wafer 16 to maintain consistency with the existing process, and at a deeper portion, the concentration is about 1e16 to 1e20. To increase the concentration.

  For example, the P-type impurity concentration of the P-type epi layer 14 is 1e16 at a depth of 4 μm from the surface of the wafer 16, 1e17 at a depth of 6 μm, and 1e18 at a depth of 8 μm. It is something that attaches.

  The increase in the concentration of the P-type impurity with respect to this depth is about three times per 1 μm depth, in other words, about one digit per 3 μm depth, which is suitable for speeding up electron recovery from the viewpoint of the electrostatic potential gradient described later.

  However, if the increase in the concentration of the P-type impurity with respect to the depth is about 1.5 times per 1 μm depth, in other words, about one digit per 6 μm depth, sufficient electron recovery speed can be increased compared to the conventional technology. Even if the depth is about 1.05 times per 1 μm depth, the electron recovery speed can be increased to some extent as compared with the conventional technique.

Here, the above-mentioned concentration gradient needs to increase monotonously, and preferably increases exponentially at a constant rate.

  Further, since the thickness T2 of the P-type epi layer 14 from the surface of the wafer 16 is generally 7 to 20 μm, the deeper portion becomes the P-type bulk silicon substrate 12 cut out thinly from the silicon ingot. The P-type impurity concentration of the P-type bulk silicon substrate 12 is preferably higher than the P-type impurity concentration in the deepest part of the P-type epi layer 14.

  Note that the P-type impurity concentration in the planar direction of the wafer 16 is preferably uniform, but strict uniformity is not required.

  However, it is preferable to exclude extreme localization of impurity concentration and discontinuous steps in both the depth direction and the planar direction.

Next, FIG. 5 shows an explanatory view showing the state of movement of electrons and holes in the photodiode 10 according to the present invention shown in FIG. 4, and referring to FIG. How electrons and holes generated by light irradiation move will be described.

  As described above, the light absorption of silicon depends on the wavelength, and light having a wavelength shorter than 600 nm is efficiently absorbed by the depletion layer 110 having a thickness T1 of 2 to 3 μm, and the generated electrons 20 and holes 22 moves according to the electrostatic potential inside the depletion layer 110, the electrons 20 are attracted to the N-type doped layer 108 (see arrow C in FIG. 5), and the holes 22 escape in the opposite direction (in FIG. 2). (See arrow D).

  However, part of the light having a wavelength longer than 600 nm reaches the deep part of the wafer 16 without being absorbed by the depletion layer 110.

  For example, more than half of near-infrared light having a wavelength longer than 700 nm is not absorbed by the depletion layer 110 having a thickness T1 of 2 to 3 μm, but is transmitted to the deep part of the wafer 16.

  The light beam transmitted through the depletion layer 110 is absorbed by silicon atoms in the deep portion of the P-type epi layer 14 of the wafer 16 to generate electrons 24 and holes 26.

Conventionally, it is known that the electrostatic potential increases by about 59 mV when the P-type impurity concentration becomes 10 times, and the P-type impurity concentration has a gradient according to the depth as in the P-type epi layer 14 of the present invention. If the concentration gradient of the P-type impurity increases from 1e15 to 1e20, for example, the electrostatic potential has a gradient of about 300 mV (see FIG. 4).

  Therefore, as described above, some of the electrons (stray electrons 204) generated in the conventional wafer 106 stray, recombine with holes with a certain probability, and disappear. Electrons 24 generated in the semiconductor substrate (wafer) 16 having a P-type impurity concentration gradient in the vertical direction move in the surface direction (see arrow E in FIG. 5) without stray according to the gradient of the electrostatic potential. Have the speed to do.

  For this reason, compared with the case where electrons stray in the conventional photodiode 100, according to the photodiode 10 of the present invention, the electrons reach the depletion layer 110 of the photodiode 10 near the surface with a high probability.

  As a known fact, it is known that the electron moving speed is orders of magnitude higher when there is a gradient in the electrostatic potential than when electrons stray through a uniform concentration.

  Specifically, the average speed of electrons in an electric field of 1 kV / cm is about 15 km / sec (refer to the graph showing the moving speed of electrons in an electric field shown in FIG. 11B).

  Therefore, in terms of conversion, when there is an electrostatic potential gradient of 30 mV per 1 μm depth, the travel time of 1 μm is about 0.2 nsec.

  In other words, if there is an electrostatic potential gradient of this level, electrons generated at a depth of 10 μm from the surface of the wafer 16 do not stray and reach the depletion layer 110 due to the photodiode 10 near the surface of the wafer 16 within about 2 nsec. It arrives or recombines with holes in the middle of movement and disappears.

  Here, since P-type impurities are present in the P-type epi layer 14 at a high concentration of 1e16 to 1e21, the probability that electrons existing in the P-type epi layer 14 recombine with holes is higher than that in the case of 1e15. On the other hand, since electrons pass through the P-type epi layer 14 in a very short time due to the electrostatic potential gradient, it is expected that the possibility of reaching the depletion layer 110 without recombination with holes is high.

On the other hand, the holes 26 generated in the P-type epi layer 14 move in the deeper direction of the wafer 16 (see arrow F in FIG. 5) according to the electrostatic potential gradient.

  Since the speed is about 1/3 of the moving speed of electrons, it is expected to be several nsec. However, the P-type impurity concentration in the P-type epi layer 14 around the generated holes 24 is high, and considering that a large amount of holes are present, the P-type impurity layer propagates in a form that maintains concentration equilibrium rather than migration. It will be in a state.

If the light further proceeds through the wafer 16 without being absorbed by the P-type epi layer 14, the light transmitted through the P-type epi layer 14 is absorbed in the bulk silicon substrate 12 deeper than the P-type epi layer 14. As a result, electrons 28 and holes 30 are generated.

  Since the electrons 28 thus generated are not affected by the gradient of the electrostatic potential, they stray according to phonon scattering.

  However, in a high impurity concentration P-type semiconductor, the probability of contact with holes is high, and the stray electrons have a very high probability of disappearing by recombination.

  Accordingly, when the P-type impurity concentration of the bulk silicon substrate 12 is a high concentration of 1e20 or more, the average recombination time is generally expected to be about 1 nsec or less, so that it is deeper than the P-type epi layer 14. The electrons 28 generated in the deep part of the bulk silicon substrate 12 disappear in a short time without straying.

  On the other hand, the holes 30 generated in the bulk silicon substrate 12 are collected in the bulk silicon substrate 12.

Therefore, the semiconductor substrate (wafer) 16 having the impurity concentration gradient in the depth direction according to the present invention, that is, the P-type epitaxial layer 14 having the concentration gradient in which the P-type impurity concentration becomes higher as the depth increases and the P-type In a semiconductor substrate (wafer) 16 including a bulk silicon substrate 12 doped with impurities at a high concentration, a depletion layer 110 of the photodiode 10 is formed by conventional impurity doping at a depth of 2 to 3 μm from the surface of the wafer 16. The photosensitivity is as usual.

  Electrons generated in the P-type epi layer 14 deeper than the depletion layer 110 move to the surface of the wafer 16 without straying according to a gentle electrostatic potential gradient, and reach the surface of the wafer 16 in a very short time, or are moving. It disappears by recombination with holes.

  Electrons generated in the bulk silicon substrate 12 deeper than the P-type epi layer 14 disappear by recombination in a short time.

  Therefore, according to the photodiode 10 formed using the semiconductor substrate (wafer 16) according to the present invention, the time resolution is greatly improved as compared with the conventional photodiode 100 formed using the conventional semiconductor substrate 106. .

The P-type impurity concentration gradient described above indicates the maximum concentration gradient that can be realized by the current semiconductor manufacturing technology. For example, the P-type impurity concentration is 1e15 on the surface of the wafer 16, and If the concentration gradient is about 1e17 at the deepest part of the P-type epitaxial layer 14, the effect of the present invention can be sufficiently obtained.

  In this case, the difference in electrostatic potential is about 120 mV, and it has a gentler gradient.

  Even in this case, the time resolution is 5 to 10 nsec, which is a significant improvement over the case where a semiconductor substrate having a uniform concentration is used.

  Further, when the concentration gradient of the P-type impurity is such a gentle concentration gradient, the photosensitivity can be improved.

  That is, the P-type impurity concentration is 10 to 100 times higher than the conventional one, and the frequency of recombination increases with the concentration. However, the electrons are converted into minority carriers by the high-speed electron transfer due to the electrostatic potential gradient. 14 stays in 1/100 to 1/1000.

  Therefore, the possibility that the electrons survive without being recombined is several times higher than the conventional case, and the electron recovery efficiency is improved and the photosensitivity is improved.

Next, FIG. 6 shows a chart showing the relationship between the concentration gradient of the P-type impurity, the electrostatic potential gradient, and the time resolution realized by the electrostatic potential gradient.

  Note that the concentration of the P-type impurity on the surface of the wafer 16 is fixed at 1e15, the thickness T2 of the P-type epitaxial layer 14 in the wafer 16 having a concentration gradient of the P-type impurity is 10 μm, and the gradient of the P-type impurity concentration is Is assumed to increase exponentially from the surface of the wafer 16 at a constant rate.

  The actual time resolution of a solid-state image sensor is not determined solely by the photodiode's electron recovery time, but is reduced by factors such as the parasitic capacitance of the photodiode, the speed of the peripheral electronic circuit, and the parasitic resistance and parasitic capacitance of the signal wiring. Therefore, it is not necessary to make the concentration gradient of the P-type impurity more than 4 times, and the average increase rate of the concentration is 2 per 1 μm in the depth direction even in an ultrahigh-speed application requiring a time resolution of 100 MHz or more. ~ 3 times is appropriate.

  In many high-speed applications, an average density increase rate of 2 to 1.5 times per 1 μm in the depth direction is sufficient, and in so-called high-speed camera applications, the average density increase rate is 1.2 per 1 μm in the depth direction. Even at ˜1.05 times, a much better time resolution can be obtained compared to the conventional case.

  If the average concentration increase rate is 1.05 to 1.01 times per 1 μm in the depth direction, which is a lower concentration gradient, the effectiveness in terms of speeding up the electron recovery is not so great, but there is no concentration gradient at all. Compared to conventional technologies that do not, the electron recovery speed is increased and the electron recovery rate is improved.

  6 illustrates the case where the thickness T2 of the P-type epi layer 14 is 10 μm. However, when the thickness T2 of the P-type epi layer 14 is different, the required time resolution and the P-type are shown. An appropriate impurity concentration gradient may be determined from the thickness T2 of the epi layer 14.

III. Description of Method for Manufacturing Semiconductor Substrate According to the Present Invention As a method for manufacturing a semiconductor substrate having an impurity concentration concentration gradient according to the present invention, there are a first manufacturing method and a second manufacturing method described below.

  Hereinafter, the first manufacturing method and the second manufacturing method will be described, respectively. In order to facilitate understanding of the semiconductor substrate manufacturing method according to the present invention, the surface of the P-type epi layer 14, that is, the wafer 16 is formed. The case where the P-type impurity concentration on the surface is 1e15 and the concentration of the deepest part of the P-type epilayer 14 in the depth direction is 1e20 will be described as an example.

[First production method]
The first manufacturing method will be described with reference to an explanatory diagram of the first manufacturing method shown in FIG. 7. This first manufacturing method is a bulk silicon substrate in which the concentration of P-type impurities is fixed and a raw material is supplied by an epitaxial growth method. In this manufacturing method, a P-type epi layer is formed on the top by epitaxial growth, and the concentration of P-type impurities is given a concentration gradient by diffusion.

  As an epitaxial growth method, it is preferable to use a vapor phase epitaxial growth method.

  More specifically, in the first manufacturing method, for example, a P-type impurity is implanted into a bulk silicon substrate before the epitaxial growth at a high concentration such that the concentration exceeds 1e21 from the surface to be epitaxially grown, and then a heat treatment is performed. Impurities are introduced into the bulk silicon substrate at a high concentration exceeding 1e21.

  A P-type epi layer is formed on the surface of such a bulk silicon substrate under the vapor phase film forming conditions for performing epitaxial growth with a conventional P-type impurity concentration of 1e15.

  The high-concentration P-type impurity introduced into the bulk silicon substrate has a low molecular weight such as boron, so that it is easily diffused in the gas phase.

  Therefore, as the crystal grows, the P-type impurities ooze out from the surface of the bulk silicon substrate and evaporate, and the P-type impurity concentration contained in the gas used for vapor phase growth is actually higher than that even if the concentration is 1e15. A high concentration of crystals will be created.

  And since the transpiration due to the seepage of the P-type impurities decreases exponentially with respect to the growth film thickness, it may be difficult to control the concentration gradient of the P-type impurities very precisely. A concentration gradient can be formed at a constant rate with good reproducibility.

  In the first manufacturing method, as a method of controlling the gradient of the concentration gradient of the P-type impurity, there is a method of adjusting the heat treatment time of the bulk silicon substrate.

  That is, according to the conventional manufacturing method, high-concentration impurities are implanted into the bulk silicon substrate, and then the impurities are diffused by a long thermal diffusion process until the impurity concentration in the bulk silicon substrate becomes sufficiently uniform, and then epitaxial growth is performed. It will move to the process.

  By doing so, the impurity atoms implanted in the bulk silicon substrate are evenly dispersed and stabilized with respect to the silicon atoms.

  On the other hand, in order to have a positive concentration gradient as in the first manufacturing method, high concentration impurities are implanted into the bulk silicon substrate, the subsequent thermal diffusion process is completed in a shorter time than usual, and then epitaxial growth is performed. It is effective to move to this process.

  In this case, the uniformity of the impurities in the bulk silicon substrate becomes insufficient, and excess P-type impurities implanted into the surface of the bulk silicon substrate are unevenly distributed near the surface and are unstable. The atoms will diffuse in the gas phase (transpiration: out diffusion).

  Therefore, by adjusting the time of the thermal diffusion process after implanting high-concentration impurities into the bulk silicon substrate, it is possible to control the extent of vapor phase diffusion in epitaxial growth.

  At the same time, excessive P-type impurities unevenly distributed near the surface of the bulk silicon substrate are evaporated, and at the same time, the diffusion of impurities also proceeds in the bulk silicon substrate, so that the impurity concentration near the surface is lowered and the impurities are uniform in the bulk silicon substrate. When it becomes, it stabilizes and the exudation of the P-type impurity from the surface of the bulk silicon substrate ends.

  That is, by combining the total amount of P-type impurity concentration implanted into the bulk silicon substrate and the heat treatment time after implantation, the P-type impurity concentration finally doped into the bulk silicon substrate and the impurities diffused in the vapor phase during the growth. The concentration gradient can be intentionally designed, and if the impurity is doped in a large amount and the heat treatment is performed for a short time, the final concentration of the bulk silicon substrate at the completion of the growth is high and a P-type epi layer can be formed. The concentration gradient takes a long form of relaxation (see the curve B of the graph representing the doping profile obtained by the method of manufacturing a semiconductor substrate according to the present invention shown in FIG. 9).

  On the other hand, if the heat treatment is sufficiently performed after doping impurities corresponding to the same concentration as in the above case, the relaxation is steep and immediately reaches a certain concentration (the curve of the graph showing the doping profile shown in FIG. 9). See C).

  Further, if the total amount of impurities is suppressed and the heat treatment time is adjusted in the same manner, a concentration gradient having profiles like curves D and E in the graph representing the doping profile shown in FIG. 9 is obtained. Curve D shows the case of short-time heat treatment, and curve E shows the case of long-time heat treatment.

[Second production method]
The second manufacturing method will be described with reference to the explanatory diagrams of the second manufacturing method shown in FIGS. 8 (a) and 8 (b). This second manufacturing method is a material supply while controlling the concentration of P-type impurities by an epitaxial growth method. Thus, a P-type epi layer is formed by epitaxial growth.

  As an epitaxial growth method, it is preferable to use a vapor phase epitaxial growth method.

  More specifically, in the second manufacturing method, for example, the P-type impurity concentration in the gas introduced into the vapor deposition apparatus that performs epitaxial growth is positively controlled, so that 1e20, Next, as in 1e19, the P-type impurity concentration is lowered for a while as the growth progresses, and finally a P-type impurity concentration gradient is created so that the P-type impurity concentration reaches 1e15. The impurity concentration is adjusted (see FIG. 8B).

  As a result, a P-type epitaxial layer having a concentration gradient in which the P-type impurity concentration is reduced to 1e20 and then 1e19 and finally the P-type impurity concentration is 1e15 is formed on the bulk silicon substrate. (See FIG. 8 (a)).

  According to the second manufacturing method, it is possible to obtain a concentration gradient of P-type impurities whose concentration is increased exponentially at a constant ratio (see curve A of the graph representing the doping profile shown in FIG. 9). This is advantageous in that the concentration gradient can be accurately controlled.

  In the case of using the second manufacturing method, it is preferable to feed back a measurement result such as a growth film thickness measurement to the control of the P-type impurity concentration and to feedback control the management of gas supply.

[Summary of Manufacturing Method of Semiconductor Substrate According to the Present Invention]
What is necessary in the method of manufacturing a semiconductor substrate according to the present invention is to form a monotonous concentration gradient that increases from the surface toward the deep portion with respect to the concentration of impurities.

  Therefore, even if the shape of the doping profile is greatly different as shown by curves A to E in FIG. 9 or there is a slight non-uniformity in the plane direction of the wafer, the electron recovery time is, for example, 2 nsec. Or 5 nsec, and there is almost no influence on the actual performance in practical use.

  If a device manufactured from a semiconductor substrate is required to have reproducibility of 1 nsec unit or strict variation accuracy, as shown by curve A in FIG. It is preferable to control to have a sufficiently monotonous gradient.

  On the other hand, as shown in FIG. 6, if the time resolution required for a device manufactured from a semiconductor substrate is about 10 to 20 nsec, the electrostatic potential gradient in the entire P-type epi layer is several tens of times. mV is sufficient. Therefore, if a bulk silicon substrate before epitaxial growth is preliminarily doped with an impurity equivalent to about 1e17 to 1e18, and the P-type epitaxial layer is grown under growth conditions with a concentration of 1e15, a sufficient concentration gradient (1.2 μm per 1 μm) is obtained. (See curve D in FIG. 9).

  Such a wafer having a gentle concentration gradient can improve both time resolution and sensitivity, and is therefore advantageous for manufacturing a device.

In the description of the first manufacturing method and the second manufacturing method described above, the case where the thickness T2 of the P-type epi layer is 10 μm is shown as an example for convenience of description. If desired, since a thicker P-type epi layer is suitable, for example, the P-type epi layer may be laminated so that the thickness T2 is about 20 μm.

  Whether to select the first manufacturing method or the second manufacturing method described above may be determined as appropriate in consideration of necessary accuracy and time resolution with respect to the manufacturing cost.

  Each of the first manufacturing method and the second manufacturing method described above is a manufacturing method using a conventional semiconductor manufacturing process, and any change is made to the integrated circuit manufacturing process excluding the conventional epitaxial manufacturing method of a semiconductor substrate. There is no need to add.

  In addition, the first manufacturing method and the second manufacturing method described above have good consistency with the technology for scraping off the bulk silicon substrate portion by polishing and manufacturing a back-illuminated solid-state imaging device, and the back-illuminated solid There is no inconvenience in producing the image sensor.

  However, when fabricating a semiconductor manufacturing substrate for fabricating a back-illuminated solid-state imaging device, in order to obtain short wavelength sensitivity, the impurity concentration gradient is slightly steeper on the back surface rather than being a constant ratio. Specifically, it is preferable to set the average value of the P-type impurity concentration of the P-type epi layer to 2e15 or less by about 1.05 times per μm.

  With such a P-type impurity concentration, recombination of electrons and holes is infrequent, and the possibility that electrons derived from short wavelengths generated in the vicinity of the back surface survive to the vicinity of the surface increases.

  In addition, if it is an application that only requires sensitivity at long wavelengths, the time resolution can be increased to about 10 nsec by increasing the concentration gradient to about 1.5 times per 1 μm and increasing the concentration on the back surface to about 5e17. .

IV. Simulation Results by the Inventor The simulation results performed by the inventor will be described below with reference to FIGS. 10 (a) and 10 (b).

  That is, in FIGS. 10A and 10B, a P-type epi layer having a depth of 10 μm is doped with boron, which is a P-type impurity, at a concentration of 1e20 from the deepest portion, and decreases exponentially toward the surface. The simulation result is shown when boron is doped with a concentration gradient and the boron concentration on the surface is 1e15.

  The concentration gradient of the P-type epi layer was set to be 10 times per 1.5 μm (6.7 times per 1 μm).

  Specifically, the P-type impurity concentration of the P-type epilayer is 1e20 when the depth from the surface of the semiconductor substrate is 10 μm, 1e19 when the depth is 8.5 μm, 1e18 when the depth is 7 μm, and the depth is 5.5 μm. 1e17 at a depth of 4 μm, and 1e16 from a depth of 2.5 μm to the surface.

  After setting the P-type epitaxial layer having the P-type impurity concentration gradient described above, phosphorus, which is an N-type impurity, is implanted from the surface of the semiconductor substrate, the surface concentration is 1e18, the depth is 1 μm, and the concentration is 1e15. As described above, an N-type semiconductor layer was formed by Gaussian distribution of N-type impurities, thereby forming a PN junction.

  A tungsten electrode was ohmically connected to the surface of the N-type semiconductor layer and the end face of the deepest part of the P-type epi layer, that is, the portion corresponding to the back surface of the bulk silicon substrate, and biased with a direct current of 2.5V ( Reference is made to FIG.

  The graph of FIG. 10A shows the result of repeatedly calculating and converging the Poisson equation and the current continuity equation under the above-described concentration conditions.

  As shown in the legend of FIG. 10A, the electrostatic potential, the electron density, and the hole density are shown with respect to the depth.

  Here, the unit of the electrostatic potential is V (volt), and the rightmost electrode surface corresponding to the bulk silicon substrate is shown as 0 V with respect to the voltage in the semiconductor substrate. Note that the left axis is referred to for the numerical axis of the graph shown in FIG.

  Further, the electron density and the hole density are logarithmic axes, and refer to the numerical value on the right axis of the graph shown in FIG. 10A. For example, “1e20” means that the carrier density per cubic centimeter is 1 to the 20th power. It is a notation that means individual, and the same applies to the other numerical values on the right axis.

  First, referring to the electrostatic potential (solid curve in FIG. 10A), it is understood that there is a potential gradient of about 3 V from a depth of 0.8 μm to a depth of 3 μm, and this portion is a depletion layer. . Thereafter, a gentle and linear potential gradient is observed from 4 μm to 10 μm in depth, and this portion is caused by the boron concentration gradient in the P-type epilayer, and the gradient is about 40 mV / μm.

  Next, referring to the electron density (dashed curve in FIG. 10A), it can be seen that 1e18 is shown at a depth of 0.8 μm from the surface and does not exist deeper than that.

  Since this simulation is a steady state calculation, it is impossible to calculate the behavior when electrons are generated deep due to light absorption, but it is expected from this result that all electrons follow the electrostatic potential gradient. It means to move to an N-type semiconductor or to disappear by recombination with holes in a P-type semiconductor.

  Next, referring to the hole density (the dashed-dotted line curve in FIG. 10A), there are very few holes in the N-type semiconductor and the depletion layer at a depth of 3 μm from the surface, and impurities from a depth of 3 μm to a deep portion. Increasing with increasing concentration. Unlike the case of electrons, holes exist in a wide range, and it can be seen that all of them are provided from boron, which is a tomato, in a steady state.

  When electrons and holes are generated by light absorption in this wide range, it is considered that electrons follow the gradient of electrostatic potential in the initial stage, and electrons start moving to the deeper part on the surface.

  Since the probability of existence of holes is high, some electrons will recombine with the holes, but if the moving speed is faster than the recombination speed, the recombination is avoided and is attracted to the potential of the depletion layer. Reach the type semiconductor.

  The time required for the electrons generated at the deepest part, that is, at a depth of 10 μm, to reach the 3 μm depletion layer from the surface is 1.2 nsec or less in calculation, and this is considered to be a measure of time resolution.

  Slower electrons are also present stochastically, but they should be more affected by scattering and are more likely to recombine with holes during scattering, so the probability of reaching the depletion layer is lower. .

V. Other Embodiments The embodiments described above can be modified as shown in the following (1) to (5).

  (1) Although the P-type semiconductor substrate has been described in the above-described embodiment, it is needless to say that the present invention can be applied to an N-type semiconductor by substituting a P-type impurity and an N-type impurity. It is.

  (2) The numerical values used in the above-described embodiments are merely examples, and it goes without saying that the numerical values may be appropriately selected according to various design conditions.

  (3) In the above-described embodiment, the first manufacturing method and the second manufacturing method are shown as the semiconductor substrate manufacturing method according to the present invention. What are the first manufacturing method and the second manufacturing method? Of course, the semiconductor substrate according to the present invention may be manufactured by different manufacturing methods.

  (4) In the above embodiment, the depletion layer is formed by the PN junction. However, the present invention is not limited to this, and the depletion layer is formed by the Schottky junction or the MOS junction. It may be.

  (5) You may make it combine suitably the embodiment shown above and the modification shown in said (1) thru | or (4).

  INDUSTRIAL APPLICABILITY The present invention can be used as a semiconductor substrate for forming a solid-state imaging device that requires a high-speed response, for example, a TOF (optical time-of-flight measurement) type distance image sensor, or a manufacturing method thereof.

10, 100 Photodiode 12, 102 P-type bulk silicon substrate 14, 104 P-type epitaxial crystal growth layer (P-type epi layer)
16, 106 Wafer 20, 24 Electron 22, 26, 30 Hole 28 Electron (stray electron)
108 N-type semiconductor layer (N-type doped layer)
110 depletion layer 112 bias voltage 200 electrons 204 electrons (stray electrons)
202, 206 holes

Claims (9)

A semiconductor substrate constituting a photoelectric conversion element structure having a depletion layer on the surface side,
A semiconductor substrate, wherein impurities are doped with a concentration gradient of impurity concentration from the front side to the back side of the semiconductor. The semiconductor substrate according to claim 1,
The impurity is a P-type impurity,
The semiconductor substrate according to claim 1, wherein the concentration gradient is a concentration gradient in which a P-type impurity concentration increases from the front surface side toward the back surface side. The semiconductor substrate according to claim 2,
The concentration on the surface side in the concentration gradient is a concentration capable of constituting the photoelectric conversion element structure,
The semiconductor substrate, wherein the concentration gradient monotonously increases a P-type impurity concentration from the front side toward the back side. The semiconductor substrate according to claim 2, wherein:
The semiconductor substrate, wherein the concentration gradient is an exponentially increasing concentration gradient, and an average concentration increase rate is 1.05 times or more per 1 μm in the depth direction. An N-type semiconductor layer is formed on the surface of the semiconductor substrate according to any one of claims 2, 3 and 4, and the depletion layer is formed on the surface side of the semiconductor substrate. element. A method of manufacturing a semiconductor substrate constituting a photoelectric conversion element structure having a depletion layer on the surface side,
On a bulk silicon substrate that has been heat-treated after being doped with a P-type impurity at a concentration higher than that capable of constituting the photoelectric conversion element structure,
An epitaxial growth method is used to supply a raw material in which the concentration of P-type impurities is fixed to a concentration that can constitute the photoelectric conversion element structure, and a P-type epitaxial layer is formed on the bulk silicon substrate by epitaxial growth.
Forming a semiconductor substrate having a concentration gradient in which the concentration of the P-type impurity in the P-type epitaxial layer monotonously increases in a direction from the surface of the P-type epitaxial layer toward the bulk silicon substrate by diffusion of the P-type impurity; A method for manufacturing a semiconductor substrate. In the manufacturing method of the semiconductor substrate according to claim 6,
A method of manufacturing a semiconductor substrate, comprising: controlling a heat treatment time of the bulk silicon substrate to control a concentration gradient of P-type impurities in the P-type epitaxial layer due to diffusion of P-type impurities. A method of manufacturing a semiconductor substrate constituting a photoelectric conversion element structure having a depletion layer on the surface side,
On a bulk silicon substrate that has been heat-treated after being doped with a P-type impurity at a concentration higher than that capable of constituting the photoelectric conversion element structure,
By the epitaxial growth method, the concentration of the P-type impurity is set higher than the concentration capable of constructing the photoelectric conversion element structure in the initial stage of the epitaxial growth, and the concentration of the P-type impurity is lowered according to the progress of the epitaxial growth, and in the final stage of the epitaxial growth. The raw material is supplied while controlling the concentration of the P-type impurity so that the photoelectric conversion element structure can be configured, and a P-type epitaxial layer is formed by epitaxial growth.
A semiconductor substrate having a concentration gradient in which the concentration of P-type impurities in the P-type epitaxial layer monotonously increases in a direction from the surface of the P-type epitaxial layer toward the bulk silicon substrate is formed. Production method. An N-type semiconductor layer is formed on a surface of a P-type epitaxial layer of a semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate according to claim 6, 7, or 8, and the surface of the semiconductor is the surface of the semiconductor substrate. A method for producing a photoelectric conversion element, comprising forming a depletion layer.