JP2011204873A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a rising characteristic of an optical current output when light is shielded in a PIN diode without causing an increase of a leak current of an optical current output control transistor of the PIN diode.SOLUTION: A type P+ type embedded layer 2 is formed at a type P- type semiconductor substrate 1. Next, a type P- type epitaxial layer 3 is formed at the type P- type semiconductor substrate 1 and a type P+ type embedded contact layer 5 is formed in the type P- type epitaxial layer 3. Next, a type P+ type up-diffusing layer 2b that is coupled with the type P+ type embedded contact layer 5 in the P- type epitaxial layer 3 from the P+ type embedded layer 2 is formed. Thereby, the electric resistance of a route in which a positive hole generated by light which is incident to the PIN diode flows up to an anode electrode can be reduced. In this case, a dose of a boron ion required to form the type P+ type embedded layer 2 is adjusted to a range not causing the increase of the leak current between the collector and an emitter of the NPN transistor 60 in the control part.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same that can improve the characteristics of a PIN diode while preventing an increase in leakage current of a transistor.

  In recent years, in a data reading device for an optical disc such as a compact disc, the market demand for high-speed reading of an optical disc and short wavelength light has been increasing. In order to meet this demand, in an optoelectronic integrated circuit in which a PIN diode as a light receiving element and a control circuit composed of a transistor for amplifying and controlling the output from the PIN diode irradiated with light are integrated, both the PIN diode and the transistor Improvement of characteristics is desired.

  Patent Document 1 describes the following contents regarding a method of forming a high-concentration P + type buried layer on a P− type semiconductor substrate in order to realize a high speed PIN diode and a structure of an epitaxial layer for realizing a high voltage PNP transistor. Has been. The outline of the content will be described below with reference to FIG.

  FIG. 9 is a cross-sectional view of a semiconductor device having a PNP transistor 80 as a representative of the PIN diode 70 and an element for controlling its output. When light enters the PIN diode 70, a photocurrent flows between the anode electrode 69 and the cathode electrode 68, and the output is amplified and controlled by a control circuit including the PNP transistor 80 and the like.

  The disclosed invention includes a P + type buried layer 62 having an impurity concentration of two orders of magnitude or more higher than that of the semiconductor substrate 61 on the P− type semiconductor substrate 61, and a P− type one-stage or two-stage epitaxial layer formed thereon. The layers 63 and 64 and an N− type epitaxial layer 65 formed thereon are formed. By making the concentration of the N− type epitaxial layer 65 one digit higher than the concentration of the P− type epitaxial layer 64, the depletion layer due to the reverse bias applied to the PIN diode 70 extends to the P− type epitaxial layer 64 side. .

  Further, by thinning the N− type epitaxial layer 65, it becomes possible to reduce carriers composed of electron-hole pairs generated by light irradiated on the portion, and the diffusion current due to the carriers is reduced, so that the PIN diode is reduced. 70 can be speeded up. Furthermore, since the film thicknesses of the N− type epitaxial layer 65 and the P− type epitaxial layer 64 can be set independently, the film thickness of the second P− type epitaxial layer 64 can be set to a predetermined breakdown voltage if the film thickness is 1.5 μm or more. The PNP transistor 80 of the control unit can be realized.

  Further, since the P + type buried layer 62 is connected to the high-concentration anode contact layer 66, the path of the photocurrent can be made low, and the PIN diode 70 can be speeded up. When it corresponds to infrared light, the total thickness of the first and second P− type epitaxial layers 63 and 64 is increased to a maximum of about 10 μm, but the thickness of the second P− type epitaxial layer 64 is several μm. In this way, the film thickness of the first P − type epitaxial layer 63 can be made 5 μm or less. Therefore, the formation of the P + type anode contact buried layer 67 can be easily realized from the surface of the first P− type epitaxial layer 63 by ion implantation.

  In the case of infrared light, since the silicon semiconductor layer penetrates about 30 μm in the depth direction, it penetrates into the P− type semiconductor substrate 61 and generates electron-hole pairs serving as carriers in that region. Such carriers have a potential barrier due to a difference in impurity concentration between the high concentration P + type buried layer 62 and the P− type semiconductor substrate 61, and therefore cannot enter the P + type buried layer 62 and recombine and disappear. Does not constitute the diffusion current component. Therefore, the PIN diode 70 can be speeded up also from this point.

JP 2006-41432 A

  Although Patent Document 1 describes the effect of increasing the speed of the PIN diode 70 by forming the P + type buried layer 62, the impurity concentration of the buried layer 62 and the incident light to the PIN diode 70 are blocked. No detailed mention is made regarding the relationship between the photocurrent output falling characteristics and the effect of the formation of the buried layer 62 on the leakage current of the transistor 80 of the control unit. In addition, there is no mention of short-wave blue light applied to Blu-ray discs that have been highly demanded in recent years.

  However, depending on the intended use and the DVD set used, the photocurrent output falling characteristic when the incident light of the PIN diode 70 is blocked becomes a problem. Therefore, it is a problem to form an appropriate P + type buried layer 62 for improving the photocurrent output falling characteristic of the PIN diode 70 without increasing the leakage current of the transistor of the control unit. In addition, the realization of the PIN diode 70 that can cope with blue light, red light, and infrared light using the P + type buried layer 62 is also a problem.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first conductive type high-concentration buried layer by ion implantation in a semiconductor substrate having a PIN diode and a transistor; Forming a first conductivity type low-concentration first epitaxial layer on the surface of the buried layer; and embedding the first conductivity type in a region of the first epitaxial layer excluding the light irradiation portion of the PIN diode. A step of forming a contact layer; a step of forming a second conductivity type buried layer in a transistor formation region of the first epitaxial layer; and a second epitaxial layer having a low concentration on the surface of the first epitaxial layer. Forming a layer, and a first conductivity type buried isolation layer extending from the first epitaxial layer to the second epitaxial layer. Forming a first conductive type separation layer connected to the buried isolation layer and extending to a surface of the second epitaxial layer; and scooping from the buried layer in the first epitaxial layer. A step of forming a first conductivity type rising layer connected to the buried contact layer; and a step of forming a second conductivity type cathode layer and a first conductivity type anode layer on the surface of the second epitaxial layer. It is characterized by having.

  In the method of manufacturing a semiconductor device according to the present invention, a depletion layer extending in the first and second epitaxial layers by a predetermined reverse bias applied between the cathode layer and the anode layer of the PIN diode extends to the rising layer. It is characterized by extending.

  Further, the method of manufacturing a semiconductor device of the present invention improves the falling characteristic at the time of light blocking of the PIN diode until the dose characteristic at the time of ion implantation for forming the buried layer satisfies a predetermined standard, and The present invention is characterized in that the leakage current of the transistor is not increased.

  In the method of manufacturing a semiconductor device according to the present invention, the transistor is a bipolar transistor.

  In the semiconductor device manufacturing method of the present invention, the leakage current of the bipolar transistor is a collector-emitter leakage current or a collector-semiconductor substrate leakage current.

  In the semiconductor device manufacturing method of the present invention, the impurity concentration of the buried layer is lower in the transistor formation region than in the PIN diode formation region.

  In the semiconductor device manufacturing method of the present invention, the buried layer is formed by ion implantation of an impurity through an insulating film mask having an opening or thin on the PIN diode formation region and a thick on the transistor formation region. It is characterized by that.

  According to another aspect of the present invention, there is provided a semiconductor device having a PIN diode and a transistor, a first conductivity type high-concentration buried layer formed by ion implantation in a first conductivity type semiconductor substrate, and a surface of the buried layer. A first conductivity type low-concentration first epitaxial layer formed on the first conductivity type; a first conductivity type buried contact layer formed in a region of the first epitaxial layer excluding the light irradiation portion of the PIN diode; The second conductivity type buried layer formed in the transistor formation region, the low-concentration second epitaxial layer formed on the surface of the first epitaxial layer, and the first epitaxial layer, A buried isolation layer of a first conductivity type formed extending from one epitaxial layer to the second epitaxial layer, and connected to the buried isolation layer. A first conductivity type isolation layer formed extending to the surface of the second epitaxial layer, and a buried contact layer formed in the first epitaxial layer so as to rise from the buried layer. A first conductivity type scooping layer, a second conductivity type cathode layer and a first conductivity type anode layer formed on the surface of the second epitaxial layer, and the cathode of the PIN diode. A depletion layer that extends into the first and second epitaxial layers by a predetermined reverse bias applied between the layer and the anode layer extends to the scooping layer, and during ion implantation for forming the buried layer The amount of impurity impurities improves the falling current characteristic of the photocurrent when the PIN diode is light-blocked until a predetermined standard is satisfied, and the leakage current of the transistor Characterized in that it is a range never increase.

  In the semiconductor device of the present invention, the buried layer is formed by ion implantation of an impurity through an insulating film mask having an opening or thin on the PIN diode formation region and a thick transistor formation region. The layer concentration is lower in the transistor formation region than in the PIN diode formation region.

  According to the semiconductor device and the manufacturing method thereof of the present invention, a semiconductor device having a PIN diode having a good photocurrent output falling characteristic when light is blocked and a high speed and a transistor with no increase in leakage current is manufactured. I can do it. Further, it is possible to realize a PIN diode that can cope with blue, red, and infrared light while improving characteristics with respect to blue light.

It is sectional drawing which shows the semiconductor device in the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device in the 2nd Embodiment of this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is a circuit diagram which measures the fall characteristic of a photocurrent output when the incident light with respect to the PIN diode of the semiconductor device of embodiment of this invention is interrupted | blocked. It is drawing which shows the relationship between the waveform of incident light with respect to the PIN diode of the semiconductor device of embodiment of this invention, and a photocurrent output. In this embodiment, the relationship between the ion implantation dose amount to the P + type buried layer and the photocurrent output falling characteristic of the PIN diode expressed by the residual voltage, the ion implantation dose amount to the P + type buried layer, and the collector-emitter of the transistor It is a graph which shows the relationship of the leakage current defect rate between. It is sectional drawing of the semiconductor device which has the conventional PIN diode and transistor.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIG. First, the configuration of the PIN diode 50 will be described. The PIN diode 50 of this embodiment can be used in common for blue light, red light, and infrared light. A P + type buried layer 2 is formed on a P− type semiconductor substrate 1, a P− type epitaxial layer 3 and a P− type epitaxial layer 4 are formed thereon, and an N + type cathode layer 11 c is formed in the P− epitaxial layer 4. It is formed.

  The P + type buried isolation layer 7b extending from the inside of the P− type epitaxial layer 3 to the inside of the P− type epitaxial layer 4 and the P + type anode layer 16 formed on the surface of the P− type epitaxial layer 4 are a P− type epitaxial layer. 4 are connected by a P + type separation layer 10b. The P + type buried layer 2 forms a P + type buried diffusion layer 2a on the P− type semiconductor substrate 1 side and a P + type creeping layer 2b on the P− type epitaxial layer 3 side. The P + type creeping layer 2b and the P + type buried isolation layer 7b are connected by a P + type buried contact layer 5 formed inside from the surface of the P− type epitaxial layer 3.

  By applying a reverse bias between the cathode electrode 14d and the anode electrode 14e of the PIN diode 50 such that the cathode electrode 14d side is a positive potential and the anode electrode 14e side is a ground potential, a P− type epitaxial layer is formed from the bottom surface of the N + type cathode layer 11c. 4. A depletion layer extending to the skirt portion of the P− type epitaxial layer 3 and the P + type scooping layer 2b is formed. When the PIN diode 50 is irradiated with light in this state, electron-hole pairs are generated in the depletion layer, and the electrons immediately flow into the cathode electrode 14d via the N + type cathode layer 11c.

  On the other hand, holes flow into the P + type buried layer 2 and pass through the P + type anode layer 16 from the P + type creeping layer 2b through the P + type buried contact layer 5, the P + type buried isolation layer 7b, and the P + type isolation layer 10b. It flows to the anode electrode 14b. The above-mentioned path through which holes flow is formed of a high concentration P + type scooping layer 2b and the like, and contributes to speeding up of the PIN diode because of its relatively low resistance. In particular, one of the features of this embodiment is to reduce the resistance of the path through which holes flow by connecting the P + type scooping layer 2b and the P + type buried contact layer 5.

Next, a configuration for sharing the blue light, the red light, and the infrared light, which is the second feature of the present embodiment, will be described below. The semiconductor device of this embodiment is for pickup, and the voltage applied between the cathode electrode 14d and the anode electrode 14e of the PIN diode 50 is 2V. The P-type epitaxial layer 3 and the P-type epitaxial layer 4 are composed of non-doped or low-concentration P-type layers, and the specific resistance is about 100 Ω · cm so that the depletion layer can easily spread. / cm ³ or less.

In this case, the depletion layer extending from the bottom surface of the N + type cathode layer 11c to the P− type epitaxial layer 4 and the P− type epitaxial layer 3 side is determined by the impurity concentration Na of the low concentration P− type epitaxial layers 3 and 4. The width of the depletion layer≈√ (2εV / qNa), the dielectric constant ε = 12 × 8.85 × 10 ⁻¹² F / m when the semiconductor substrate is a silicon substrate, and the electron charge q = 1.6 × 10 ^{− When 19} C, applied voltage V = 2 V, and impurity concentration Na = 1E14 / cm ³ (1E20 / m ³ ) are substituted and approximated, the depletion layer width is approximately 5 to 6 μm.

On the other hand, the incident light having the intensity F0 to the PIN diode 50 has the intensity F = F0exp (−αx) of the light indicated by the position of the distance x in the semiconductor layer. In the case of blue light, α is in the lower half of 10 ⁴ / cm, so that most of the incident light is absorbed in the vicinity of 0.4 μm from the surface of the P− type epitaxial layer 4, and the P− type epitaxial layer on the back side. 4 cannot enter.

  Therefore, the N + type cathode layer 11 c is formed in a region shallower than 0.2 μm from the surface of the P− type epitaxial layer 4, and an extremely shallow region of the depletion layer extending from the bottom surface of the N + type cathode layer 11 c to the P− type epitaxial layer 4. Electron-hole pairs are generated only at. For this reason, in the PIN diode corresponding to blue light, the depletion layer extending downward is an extra path for holes to reach the P + type buried layer 2. Therefore, it is preferable to form the P + type scooping layer 2b as close to the N + type cathode layer 11c as possible.

On the other hand, in the case of red light, α is on the order of 10 ³ / cm, so that incident light travels from the surface of the P− type epitaxial layer 4 to a depth of about 9 μm and is absorbed. Therefore, the depletion layer that extends to the bottom of the P− type epitaxial layer 4, the P− type epitaxial layer 3 and the P + type creeping layer 2b with a reverse voltage of 2V applied between the cathode electrode 14d and the anode electrode 14e is used. Therefore, it is necessary to generate as many electron-hole pairs as possible to ensure sensitivity. The same applies to infrared light.

  Therefore, in consideration of the relationship with the transistor 60, when a reverse voltage 2V is applied between the cathode electrode 14d and the anode electrode 14e, the tip portion of the P + type scooping layer 2b that scoops up from the P + type buried layer 2 and the N + type. The amount of rising of the P + type rising layer 2b is determined so that a depletion layer of 5 to 6 μm spreads between the cathode layers 11c.

  If the amount of creeping of the P + type creeping layer 2b is increased in order to suppress the spread of an unnecessary depletion layer with respect to blue light, a low breakdown voltage is generated between the P + type creeping layer 2b and the N + buried layer 6 of the transistor 60. This is because a Zener diode may be formed. In this case, the P + type buried contact layer 5 plays an effective role in order to connect the P + type creeping layer 2b and the P + type buried isolation layer 7b having a small amount of creeping up with low resistance.

  Next, the NPN bipolar transistor 60 will be described as an example on behalf of a control unit that amplifies and controls the photocurrent output of the PIN diode 50. P− type semiconductor substrate 1, P + type buried layer 2, P + type creeping layer 2 b, P− type epitaxial layer 3, P− type epitaxial layer 4, P + type buried contact layer 5, P + type buried isolation layer 7 a, P + type The configuration employing the isolation layer 10 a and the element isolation insulating film 12 is the same as that of the PIN diode 50. By connecting the P + type scooping layer 2b and the P + type buried isolation layer 7a with the P + type buried contact layer 5, the potential between the P + type isolation layers 10a separating the devices is set to the potential of the P type semiconductor substrate 1. Fixed in common.

  The difference from the configuration of the PIN diode 50 is that the N + type buried layer 6 straddling the P− type epitaxial layer 3 and the P− type epitaxial layer 4, and the surface of the P− type epitaxial layer 4 connected to the N + type buried layer 6. N + type contact layer 9 extending to N + type contact layer 9, N + type collector layer 11a connected to N + type contact layer 9, and N type collector layer formed in P− type epitaxial layer 4 and connected to N + type buried layer 6 8, and a P-type base layer 15 formed in the N-type collector layer 8 and an N + -type emitter layer 11 b formed in the P-type base layer 15. The emitter electrode 14b, collector electrode 14a, and base electrode 14c are formed in the same manner as the cathode electrode 14d.

  The most significant features of this embodiment will be described below with reference to FIGS. FIG. 6 is a circuit diagram for measuring the falling state of the photocurrent output when red light having a wavelength of 780 nm is incident on the PIN diode 50 and the photocurrent output is generated in the PIN diode 50 and then the light is blocked. . When light is incident on the PIN diode 50, a photocurrent I flows through the PIN diode 50 through the resistance of the voltage generator 51 toward the ground line. As a result, a photocurrent output is generated in the voltage generator 51. The output is adjusted by the output attenuator 52, and the photocurrent output unit 53 adds the forward and reverse outputs to detect a minute falling residual voltage.

  When the pulsed red light shown in FIG. 7A was incident on the PIN diode 50 in the measurement circuit, a photocurrent output voltage waveform as shown in FIG. 7B was obtained. In this case, the frequency of light was 10 MHZ. Despite the fact that incident light is cut off sharply, the output voltage shows a shape that has a trailing edge that decreases with the elapsed time from the time when the light was cut off, and does not show a sharp waveform. Assuming that the output voltage at an elapsed time td = 30 ns from the time when the light is blocked is the remaining voltage Vd, the smaller the remaining voltage Vd, the sharper the fall and the better the fall characteristics. If the residual voltage Vd exceeds a predetermined value, a harmful effect occurs depending on the DVD set.

  FIG. 8 shows the relationship between the residual voltage Vd and the dose amount of boron ions when the P + type buried layer 2 is formed as a normalized value. As shown in the figure, the residual voltage Vd of the photocurrent output decreases exponentially as the dose of the P + type buried layer 2 increases. As the dose increases, the electrical resistance of the P + type buried layer 2 decreases and passes from the P + type creeping layer 2b to the P + type buried contact layer 5, P + type buried isolation layer 7b, P + type isolation layer 10b, and P + type anode layer 16. This is because the resistance to the flow of holes reaching the anode electrode 14b is reduced.

  Next, the leakage current flowing from the collector electrode 14a to the emitter electrode 14b of the NPN transistor 60 shown in FIG. 1 will be described. Since the leakage current is very small, several hundred transistors of the same size as the actual element or several times larger are connected in parallel, 7V is applied to the collector electrode 14a, and the emitter electrode 14b is grounded. It was measured. The base electrode 14c and the P-type semiconductor substrate 1 were in an open state. When a current of 100 pA or more flows, it was determined to be defective.

  The result is as shown by the collector-emitter leakage current defect rate in FIG. When the dose of boron ions for forming the P + buried layer 2 is equal to or less than a predetermined amount, the collector-emitter leakage current failure rate is low and close to a constant value. However, when the standardized dose exceeds 1, the leakage current failure rate significantly increases. This is because crystal defects are generated in the P-type semiconductor substrate 1 as the dose increases and transferred to the P− type epitaxial layer, or the high concentration region of the P + type scooping layer 2b is N + type buried. It is conceivable that a low withstand voltage Zener diode is formed close to the layer 6.

  The feature of the present embodiment is that the remaining voltage Vd at the fall of the photocurrent output when the incident light of the PIN diode 50 is blocked is prevented within a predetermined standard while preventing the increase of the collector-emitter leakage current of the NPN transistor 60. It is in that. Therefore, a specific feature is that the dose amount of boron ions for forming the P + type buried layer 2 is determined under the optimum condition based on the balance between the transistor 60 characteristics and the PIN diode 50 characteristics. In the present embodiment, the dose amount of boron ions in the P + type buried layer 2 is set to 0.6 as a normalized value.

  Now, the manufacturing process of the semiconductor device of this embodiment will be described with reference to the schematic steps based on FIG. 1 and FIG. First, as shown in FIG. 2, a P-type semiconductor substrate 1 is prepared, and boron ions are implanted into the entire surface thereof. As described above, the amount of dose is such that the residual voltage Vd indicating the falling delay of the photocurrent output when the incident light of the PIN diode 50 is blocked is within a predetermined standard, and between the collector and emitter of the transistor 60 of the control circuit. In view of the range where the leakage current does not increase and safety, the standardized dose amount 0.6 shown in FIG. 8 is set.

  Thereafter, annealing and activation of the ion implantation layer are performed in a high temperature furnace to form the P + type buried layer 2. The P + type buried layer 2 into which boron ions are implanted is formed into a P + type buried diffusion layer 2a on the P− type semiconductor substrate 1 side by annealing in this step and heat treatment in the subsequent step, and the subsequent P− type epitaxial layer. A P + type scooping layer 2 b is formed in the substrate 3.

  Next, after cleaning the P-type semiconductor substrate 1, a non-doped or P-type epitaxial layer 3 is formed thereon by a predetermined epitaxial method. Next, boron ions are ion-implanted from the surface of the P − type epitaxial layer 3 into a predetermined region using an oxide film or the like as a mask, and then heat treatment is performed to form the P + type buried contact layer 5. At this stage, the P + type scooping layer 2a and the P + type buried contact layer 5 are separated from each other in FIG. 2, but the P + type scooping layer 2a is also considerably scooped up and is in contact with the P + type buried contact layer 5. It can also be done.

  Next, a predetermined antimony-doped spin-on glass or the like is applied to the formation region of the NPN transistor 60 and diffused in a high temperature furnace as a diffusion source to form the N + type buried layer 6. Next, a P + type buried isolation layer 7a and a P + type buried isolation layer 7b for extracting the anode of the PIN diode are formed in a predetermined region by ion implantation of boron ions using a resist mask or the like.

  Next, as shown in FIG. 1, a P− type epitaxial layer 4 is formed on the P− type epitaxial layer 3. An NPN transistor 60 is formed in the P − type epitaxial layer 4. First, phosphorus ions are ion-implanted into a region where the N + type contact layer 9 is formed using a predetermined resist mask. Subsequently, phosphorus ions are ion-implanted into a region where the N-type collector layer 8 is formed using a predetermined resist mask. Boron ions are ion-implanted into a region where the P + type separation layers 10a and 10b are formed using a predetermined resist mask, and then annealing and diffusion of impurities implanted in a high temperature furnace are performed. Thereafter, the element isolation insulating film 12 is formed by a predetermined LOCOS (Local Oxidation of Silicon) method.

  As a result, as shown in the figure, the P + type scooping layer 2b is connected to the P + type buried isolation layers 7a and 7b through the P + type buried contact layer 5 and further connected to the P + type isolation layers 10a and 10b. . In the NPN transistor 60 part, the N + type contact layer 9 and the N type collector layer 8 are connected to the N + type buried layer 6.

  Next, in the NPN transistor 60 part, a P-type base layer 15 is formed in the N-type collector layer 8 by ion implantation of boron ions, and an N + -type emitter layer 11b is formed in the P-type base layer 15 by ion implantation of arsenic ions. At the same time, an N + type collector layer 11 a is formed in the N + type contact layer 9. At this time, the N + type cathode layer 11c is also formed in the PIN diode 50 part. Further, boron ions or the like are ion-implanted into the P + type separation layer 10b of the PIN diode 50, thereby forming the P + type anode layer 16.

  Next, an interlayer insulating film 13 is deposited on the entire surface of the P− type semiconductor substrate 1 on which the N + type cathode layer 11c and the like are formed by a CVD method or the like, and a contact hole is formed through a predetermined photoetching process. Thereafter, aluminum or the like is deposited by a predetermined method, and after a predetermined photoetching process, a collector electrode 14a connected to the N + type collector layer 11a in the NPN transistor 60 part, an emitter electrode 14b connected to the N + type emitter layer 11b, a P type A base electrode 14c connected to the base layer 15 is formed, and a cathode electrode 14d connected to the N + type cathode layer and an anode electrode 14e connected to the P + type anode layer 16 are formed in the PIN diode 50 part.

  Finally, a desired semiconductor device is manufactured by covering the entire surface of the P-type semiconductor substrate 1 on which each electrode is formed with a protective film (not shown).

[Second Embodiment]
A second embodiment will be described with reference to FIG. The difference between this embodiment and the first embodiment is that the ion implantation amount of boron ions into the P − type semiconductor substrate 1 immediately below the PIN diode 50 is made larger than the ion implantation amount directly below the NPN transistor 60. This is because the impurity concentration of the P + type buried layer 21 immediately below the diode 50 part is made higher than that of the P + type buried layer 22 of the NPN transistor 50 part.

  As a result, as shown in the figure, the amount of rise of the P + type creeping layer 2b from the P + type buried layer 21 immediately below the PIN diode 50 part is represented by P + from the P + type buried layer 22 immediately below the NPN transistor 60. It can be made larger than the amount of scooping of the mold scooping layer 2c.

  In this way, the concentration of the P + type buried layer 22 in the NPN transistor 60 part is made lower than the concentration of the P + type buried layer 21 immediately below the PIN diode 50 part, and the amount of rise of the P + type rising layer 2c is reduced. Are effective in preventing an increase in leakage current of the NPN transistor.

  Therefore, from the relationship shown in FIG. 8, while the dose of boron ions to the P + type buried layer 22 of the NPN transistor 60 part is set to a standardized dose of about 0.6, an increase in leakage current is prevented, When the dose of boron ions to the P + type buried layer 21 of the PIN diode 50 part is set to a standardized dose of 1 or more, the falling residual voltage Vd of the photocurrent output at the time of light interruption is compared with the case of the first embodiment. Can be a small value.

  A method for manufacturing the semiconductor device of this embodiment will be briefly described below with reference to FIGS. First, as shown in FIG. 4, boron ions are ion-implanted for forming P + -type buried layers 21 and 22 in a P − -type semiconductor substrate 1 as shown in FIG. This is performed through the insulating film 17 having a larger film thickness immediately below 50 parts.

  By adjusting the film thickness of the insulating film 17 shown in the figure to an appropriate film thickness, the impurity concentration of the P + type buried layer 21 immediately below the PIN diode 50 is made higher than the impurity concentration of the P + type buried layer 22 immediately below the NPN transistor 60. be able to. As a result, the photoelectric current output when the incident light to the PIN diode 50 is blocked without increasing the collector-emitter leakage current failure rate of the NPN transistor 60 in the P-type semiconductor substrate 1 in each region. It becomes possible to form the P + type buried layers 22 and 21 that make the remaining falling voltage Vd a desired value.

  Next, as shown in FIG. 5, as in the case of the first embodiment, the P − type epitaxial layer 3 is formed on the P − type semiconductor substrate 1 on which the P + type buried layers 21 and 22 are formed, Subsequently, a P + type buried contact layer 5, an N + type buried layer 6, and P + type buried isolation layers 7a and 7b are formed. As a result, a P + type scooping layer 2b having a large scooping amount is formed in the PIN diode 50 part, and a P + type scooping layer 2d having a small scooping amount is formed in the NPN transistor 60 part. Further, P + type buried diffusion layers 2a and 2c are formed in the P− type semiconductor substrate 1 from the P + type buried layers 21 and 22, respectively.

  Thereafter, through the same process as in the first embodiment, the configuration of the semiconductor device shown in FIG. 3 is obtained. Finally, a semiconductor device is completed by forming a protective film (not shown) on the P-type semiconductor substrate 1 on which various laminates are formed.

  Note that the P-type and the N-type in the first and second embodiments are interchanged to form the PIN diode 50, the PNP transistor 60, etc., or even if the NPN transistor 60 is a MOS transistor, the technical idea is the same. Needless to say, it is included in the scope of the present invention.

1 P-type semiconductor substrate 2, 21, 22 P + type buried layer
2a, 2c P + type buried diffusion layer 2b, 2d P + type creeping layer
3 P-type epitaxial layer 4 P-type epitaxial layer
5 P + type buried contact layer 6 N + type buried layer
7a, 7b P + type buried isolation layer 8 N type collector layer 9 N + type contact layer 10a, 10b P + type isolation layer 11a N + type collector layer
11b N + type emitter layer 11c N + type cathode layer 12 Element isolation insulating film 13 Interlayer insulating film 14a Collector electrode 14b Emitter electrode
14c Base electrode 14d Cathode electrode 14e Anode electrode 15 P type base layer 16 P + type anode layer 17 Insulating film 50 PIN diode 51 Voltage generator 52 Output booster
53 Photocurrent output unit Vd Residual voltage td Residual voltage detection time 60 NPN transistor 61 P-type semiconductor substrate 62 P + type buried layer
63 P-type epitaxial layer 64 P-type epitaxial layer
65 N-type epitaxial layer 66 Anode contact layer
67 Anode contact buried layer 68 Cathode electrode
69 Anode electrode 70 PIN diode 80 PNP transistor

Claims (9)

In a method for manufacturing a semiconductor device having a PIN diode and a transistor,
Forming a high-concentration buried layer of the first conductivity type by ion implantation on a semiconductor substrate of the first conductivity type;
Forming a first conductivity type low-concentration first epitaxial layer on the surface of the buried layer;
Forming a first conductive type buried contact layer in a region of the first epitaxial layer excluding the light irradiation portion of the PIN diode;
Forming a second conductivity type buried layer in a transistor formation region of the first epitaxial layer;
Forming a low-concentration second epitaxial layer on the surface of the first epitaxial layer;
Forming a buried isolation layer of a first conductivity type extending from the first epitaxial layer to the second epitaxial layer;
Forming a first conductivity type separation layer connected to the buried separation layer and extending to a surface of the second epitaxial layer;
Forming a rising layer of a first conductivity type that rises from the buried layer and is connected to the buried contact layer in the first epitaxial layer;
Forming a second conductivity type cathode layer and a first conductivity type anode layer on the surface of the second epitaxial layer. A method of manufacturing a semiconductor device, comprising:   The depletion layer extending in the first and second epitaxial layers by a predetermined reverse bias applied between the cathode layer and the anode layer of the PIN diode extends to the rising layer. 2. A method for manufacturing a semiconductor device according to 1.   Improve the photocurrent output falling characteristics when the light of the PIN diode is blocked by light when the ion dose for forming the buried layer satisfies a predetermined standard, and increase the leakage current of the transistor 3. The method of manufacturing a semiconductor device according to claim 1, wherein the manufacturing method is within a range where there is no problem.   The method of manufacturing a semiconductor device according to claim 1, wherein the transistor is a bipolar transistor.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the leakage current of the bipolar transistor is a collector-emitter leakage current or a collector-semiconductor substrate leakage current.   6. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity concentration of the buried layer is lower in a formation region of the transistor than in a formation region of the PIN diode.   7. The semiconductor according to claim 6, wherein the buried layer is formed by ion implantation of an impurity through an insulating film mask having an opening or thin on the PIN diode formation region and a thick transistor formation region. Device manufacturing method. In a semiconductor device having a PIN diode and a transistor,
A first conductivity type high-concentration buried layer formed by ion implantation in a first conductivity type semiconductor substrate;
A first conductivity type low-concentration first epitaxial layer formed on the surface of the buried layer;
A buried contact layer of a first conductivity type formed in a region excluding the light irradiation portion of the PIN diode in the first epitaxial layer;
A buried layer of a second conductivity type formed in the transistor formation region of the first epitaxial layer;
A low-concentration second epitaxial layer formed on the surface of the first epitaxial layer;
A buried isolation layer of a first conductivity type formed extending from the first epitaxial layer to the second epitaxial layer;
A first conductivity type separation layer connected to the buried separation layer and extending to the surface of the second epitaxial layer;
A first conductivity type scooping layer connected to the buried contact layer formed scooping up from the buried layer in the first epitaxial layer;
A second conductivity type cathode layer and a first conductivity type anode layer formed on the surface of the second epitaxial layer, and a predetermined voltage applied between the cathode layer and the anode layer of the PIN diode. A depletion layer extending into the first and second epitaxial layers due to reverse bias extends to the rising layer, and an impurity dose during ion implantation for forming the buried layer is the light of the PIN diode. A semiconductor device characterized in that the photocurrent output falling characteristic at the time of cutoff is improved until a predetermined standard is satisfied, and the leakage current of the transistor is not increased.   The buried layer is formed by ion implantation of an impurity through an insulating film mask having an opening or thin on the PIN diode formation region and a thick transistor formation region, so that the concentration of the buried layer is the transistor formation region. 9. The semiconductor device according to claim 8, wherein the semiconductor device is lower than a formation region of the PIN diode.

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