JP2011204770A - Semiconductor device and logic circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is reduced in area and improved in the yield, and to provide a logic circuit which uses the device.SOLUTION: A first transistor Tr1 and a second transistor Tr2 are formed; the first transistor Tr1 includes a first diffusion layer group 103 functioning as a source and a drain, a first gate electrode 102, and a second gate electrode 104, and the second transistor Tr2 includes a second diffusion layer group 201 functioning as a source and a drain, a floating gate 202 capable of accumulating electric charge, and a third gate electrode 200, wherein the second gate electrode 200 controls a threshold Vth of the first transistor Tr1; and the potential of the second gate electrode 104 has a value corresponding to the amount of electric charges accumulated in the floating gate 202.

Description

  The present invention relates to a semiconductor device and a logic circuit using the same.

  Conventionally, there is a circuit (for example, a field programmable gate array (FPGA)) that can be rewritten by a control signal. These FPGAs are composed of, for example, a plurality of transistors. For example, variations in device performance such as a threshold value occur between the plurality of transistors (see Non-Patent Documents 1 and 2).

  Therefore, there is a problem that the circuit scale becomes enormous if a structure that eliminates variations in the element characteristics is taken. Further, as the power supply voltage is lowered, there is a problem that the on / off ratio cannot be obtained due to the variation in the element performance, and the yield is lowered.

Shinichi Ouchi, 4 others, “Successfully prototyped a new SRAM circuit that solved the variation factors of fin-type transistors”, [online], December 18, 2008, [Search March 9, 2010], Internet <URL: // http: //www.aist.go.jp/aist_j/press_release/pr2008/pr20081218_2/pr20081218_2.html> Shinichi Ouchi, 3 others, “Contrived a new circuit configuration of SRAM using fin-type transistors”, [online], September 18, 2007, [March 9, 2010 search], Internet <URL : Http://www.aist.go.jp/aist_j/press_release/pr2007/pr20070918/pr20070918.html>

  An object of the present invention is to provide a semiconductor device capable of reducing the element area and improving the yield, and a logic circuit using the semiconductor device.

  A semiconductor device according to an aspect of the present invention includes a first transistor formed on a first region of a semiconductor substrate, and a second transistor formed on a second region of the semiconductor substrate. The transistor is provided on the semiconductor substrate and has a fin-shaped first semiconductor layer in which a first source, a region where a first channel is formed, and a first drain are sequentially formed, and the first semiconductor layer A first gate electrode adjacent to the region where the first channel is formed with a first gate insulating film interposed therebetween, and a second gate electrode opposed to the first gate electrode with the first semiconductor layer interposed The second transistor is provided on the semiconductor substrate, and a second semiconductor having a fin shape in which a second source, a region where a second channel is formed, and a second drain are sequentially formed layer The charge storage layer adjacent to the second semiconductor layer in the region where the second channel is formed with a second gate insulating film interposed therebetween, and relative to the second semiconductor layer with the charge storage layer interposed And the second gate electrode and the charge storage layer are electrically connected.

  A logic circuit according to an aspect of the present invention includes a writable logic circuit including a plurality of the first transistor and the second transistor, and a threshold adjustment circuit that enables the logic circuit to be written. The logic circuit includes: And a plurality of transistor units in which the first semiconductor layers of the first transistors are commonly connected so that current paths are connected in series, and the threshold adjustment circuit is provided in each of the plurality of transistor units. By controlling the amount of charge accumulated in the floating gate of the second transistor constituting the transistor group with the first transistor according to the threshold value of one transistor, and adjusting the threshold voltage of the first transistor, The logic circuit is writable.

  According to the present invention, it is possible to provide a semiconductor device capable of reducing the element area and improving the yield and a logic circuit using the semiconductor device.

1 is a perspective view of a semiconductor device according to an embodiment of the present invention. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 1 is a side view of a semiconductor device according to an embodiment of the present invention. The circuit diagram concerning one embodiment of this invention. 1 is a configuration table of a logic circuit according to an embodiment of the present invention, in which (a) and (b) constitute a NAND, and (c) and (d) constitute a NOR.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

<1. Configuration example>
A semiconductor device and a logic circuit using the same according to an embodiment of the present invention will be described. The semiconductor device 1 according to this embodiment includes a Fin-type four-terminal transistor and a floating gate electrically connected to the second gate electrode of the Fin-type four-terminal transistor, and controls charges accumulated in the floating gate. Thus, the threshold value of the Fin-type four-terminal transistor is controlled.

  1 is a perspective view showing a structure of a semiconductor device 1 according to the present embodiment, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is a plan view of FIGS. 1 and 2 (a-a direction in the drawing). A cross-sectional view is shown. 1 and 2, the first direction and the second direction are substantially orthogonal.

  As shown in FIGS. 1 to 3, the semiconductor device 1 according to the present embodiment includes a control transistor Tr <b> 1 and a Fin-type four-terminal transistor Tr <b> 2 formed on a semiconductor substrate 100 with an insulating film 101 interposed therebetween. The control transistor Tr1 is formed in the region 1 on the semiconductor substrate 100, and the Fin-type four-terminal transistor is formed in the region 2 on the semiconductor substrate 100.

  First, the control transistor Tr1 will be described. As shown in FIGS. 1 to 3, the control transistor Tr <b> 1 includes a Fin-type conductive layer 204, a floating gate 202 (also referred to as a charge storage portion 202), and a gate electrode 200.

  The Fin-type conductive layer 204 includes an impurity diffusion layer 201 that functions along the second direction and functions as a source and a drain, and a conductive layer 203 sandwiched between the impurity diffusion layers 201. The conductive layer 203 is doped with, for example, a p-type impurity, and functions as a channel as necessary. That is, when a predetermined voltage is applied to the gate electrode 200, electrons are induced on the surface of the conductive layer 203, and function as a channel that electrically connects the impurity diffusion layer 201 that functions as a drain and a source.

  The floating gate 202 is formed adjacent to the conductive layer 203 through an insulating film (not shown). The floating gate 202 is formed in the first direction with respect to the conductive layer 203.

  The gate electrode 200 is formed adjacent to the floating gate 202 via an insulating film (not shown). The gate electrode 200 is formed in the first direction with respect to the floating gate 202. The gate electrode 200 is formed so as to cover the control transistor Tr1 and the Fin-type four-terminal transistor Tr2.

  Next, an operation for injecting (accumulating) electrons into the floating gate 202 of the control transistor Tr1 and an operation for extracting electrons from the floating gate 202 will be described. In the configuration of the semiconductor device 1 shown in FIGS. 1 to 3, the control transistor Tr <b> 1 is formed on the semiconductor substrate 100 with the insulating film 101 interposed therebetween. Therefore, injection of electrons into the floating gate electrode 202 and extraction of electrons from the floating gate electrode 202 are performed by a transistor including the Fin-type conductive layer 204, the floating gate 202, and the gate electrode 200.

  First, when electrons are accumulated in the floating gate 202, a predetermined voltage (a positive voltage with respect to the conductive layer 203) is applied to the gate electrode 200, and the potential of the drain (impurity diffusion layer 201) is set to the source. A voltage is applied to the impurity diffusion layer 201 so as to be higher (positive potential) than the potential of the (impurity diffusion layer 201). As a result, some of the electrons accelerated from the source toward the drain are attracted to the gate electrode 200 side, tunnel through an insulating film (not shown), and injected into the floating gate 202. As a result, electrons in the floating gate 202 accumulate (increase).

  On the other hand, when electrons are extracted from the floating gate 202, a predetermined voltage (for example, 0V) is applied to the gate electrode 200, and further, for example, 20V is applied to the drain 201 (either one or both of the impurity diffusion layers 201). Apply high voltage. Thereby, electrons accumulated in the floating gate 202 are extracted to the drain region. As a result, electrons accumulated in the floating gate 202 are reduced.

  Next, the Fin type 4-terminal transistor Tr2 will be described. As shown in FIGS. 1 to 3, the Fin type four-terminal transistor Tr <b> 2 includes a first gate electrode 102, a Fin type conductive layer 106, and a second gate formed on the semiconductor substrate 100 with an insulating film 101 interposed therebetween. An electrode 104 is provided.

  The first gate electrode 102 has an L shape. That is, as shown in FIG. 3, the bottom surface of the first gate electrode 102 is along the surface of the insulating film 101, and the apex p is formed to extend in the direction perpendicular to the first direction and the second direction. In addition, the electrode is formed such that the side surface is along the side wall of the Fin-type conductive layer 106.

  The Fin-type conductive layer 106 is formed along the second direction, and includes an impurity diffusion layer 103 that functions as a source and a drain, and a conductive layer 105 sandwiched between the impurity diffusion layers 103. The conductive layer 105 is formed adjacent to the first gate electrode 102 through an insulating film (not shown). The impurity diffusion layer 103 and the conductive layer 105 are formed in the first direction with respect to the first gate electrode 102. The conductive layer 105 is doped with, for example, a p-type impurity and functions as a channel as necessary. That is, when a voltage equal to or higher than a predetermined voltage (threshold voltage) is applied to the first gate electrode 102, electrons are induced on the surface of the conductive layer 105, and the impurity diffusion layer 103 functioning as a drain and a source is electrically connected. To function as a channel. Further, the threshold voltage of the Fin-type four-terminal transistor Tr2 can be controlled by the voltage (potential) of the second gate electrode 104 described later.

  The second gate electrode 104 is formed adjacent to the conductive layer 105 through an insulating film (not shown). The second gate electrode 104 is formed in the first direction with respect to the conductive layer 105. As described above, the semiconductor device 1 according to this embodiment has a configuration in which the threshold voltage of the Fin-type conductive layer 106 can be controlled by applying a voltage (potential) to the gate electrode 200. Details will be described later.

  As shown in FIGS. 1 and 3, the second gate electrode 104 is electrically connected to the floating gate 202 described above. As shown in FIGS. 1 and 3, the second gate electrode 104 is electrically connected to the floating gate 202 on the insulating film 101, for example. Hereinafter, the floating gate 202 and the second gate electrode 104 that are electrically connected to each other are collectively referred to as a gate group 205.

  In the above configuration, the gate group 205 functions as a charge storage layer on the control transistor Tr1 side, and functions as a second gate electrode for controlling the threshold value of the Fin-type four-terminal transistor Tr2 on the Fin-type four-terminal transistor Tr2.

<About the threshold value of the semiconductor device 1>
Next, the threshold voltage of the Fin type 4-terminal transistor Tr2 described above will be described.

First, a case where the threshold voltage of the Fin-type four-terminal transistor Tr2 is lowered will be described. As described above, by applying a predetermined voltage to the gate electrode 200, the impurity diffusion layer 201, and the conductive layer 203 of the control transistor Tr1, the electrons accumulated in the floating gate 202 are extracted, thereby being accumulated in the floating gate 202. Reduce the electrons. As a result, the negative charge accumulated in the floating gate 202 decreases, and the potential of the second gate electrode 104 rises. As a result, the threshold voltage of the Fin-type four-terminal transistor Tr2 decreases. Therefore, even when the voltage applied to the first gate electrode 102 is a low value, the Fin type four-terminal transistor Tr2 is in an on state (a state in which a channel is formed in the conductive layer 105). Note that the threshold when the on state is set at this low voltage is, for example, Vth _L (<0 V). That is, the Fin-type four-terminal transistor Tr2 is always turned on when, for example, a voltage larger than zero potential is applied to the first gate electrode.

  Next, a case where the threshold voltage of the Fin-type four-terminal transistor Tr2 is increased will be described. As described above, by applying a predetermined voltage to the gate electrode 200 and the impurity diffusion layer 201 of the control transistor Tr1, electrons are injected into the floating gate 202, whereby the electrons accumulated in the floating gate 202 are increased. As a result, the negative charge accumulated in the floating gate 202 increases in the floating gate 202, so that the potential of the second gate electrode 104 decreases. Thereby, the threshold voltage of the Fin type 4-terminal transistor Tr2 increases. Therefore, the first gate electrode 102 is not turned on unless a voltage higher than at least the above case (when the threshold voltage of the Fin-type four-terminal transistor Tr2 is lowered) is applied. This is because the depletion layer width of the Fin-type conductive layer 105 located under the first gate electrode 102 is widened to maintain electrical equilibrium with the increased fixed charge and achieve the inversion condition. For this reason, a high voltage is required for the voltage applied to the first gate electrode 102.

  The above-described threshold voltage value is caused by the amount of electrons accumulated in the floating gate 202. The threshold voltage of the Fin-type four-terminal transistor Tr2 becomes higher as the number of electrons accumulated in the floating gate 202 increases. In order to increase the amount of electrons stored in the floating gate 202, for example, there is a method of extending the time of the voltage applied to the gate electrode 200.

  In other words, by adjusting the time of the voltage applied to the gate electrode 200, the amount of electrons accumulated in the floating gate 202 can be adjusted to obtain the target threshold voltage.

For example, when it is desired to set the threshold voltage to a threshold Vth _C higher than the threshold Vth _L , a predetermined voltage is applied to the gate electrode 200, for example, for a time t1.

Further, when it is desired to set the threshold voltage to a threshold Vth _H higher than the threshold Vth _C , a predetermined voltage is applied to the gate electrode 200 for, for example, time t2 (> time t1).

Note that (0V <) Vth _C (<voltage VDD), Vth _H (> voltage VDD). That is, when the threshold voltage is Vth _C , the Fin-type four-terminal transistor Tr2 is turned on when a voltage higher than at least 0 V (more than the threshold Vth _C ) is applied to the first gate electrode.

When the threshold voltage is Vth _H , the Fin type four-terminal transistor Tr2 is turned off even when the voltage VDD is applied to the first gate electrode, and a voltage equal to or higher than the voltage VDD is applied to the first gate electrode. It is turned on for the first time.

  In this way, by controlling the charge accumulated in the floating gate 202 of the control transistor Tr1, the potential of the second gate electrode 104 of the Fin type four-terminal transistor Tr2 is controlled. As a result, the threshold voltage of the Fin-type four-terminal transistor Tr2 can be controlled.

<Application Examples Using Semiconductor Device 1>
Next, an application example of the semiconductor device 1 including the control transistor Tr1 and the Fin-type transistor Tr2 shown in FIGS. 1 to 3 will be described with reference to FIG.

  FIG. 4 shows an example of a circuit formed by disposing the control transistor Tr1, the Fin-type four-terminal transistor Tr2, and, for example, four semiconductor devices 1 on the semiconductor substrate 100. As shown in FIG. 4, the circuit configured from the semiconductor device 1 includes a threshold adjustment circuit 400, a control unit 500, and a system circuit 600. In the following, the threshold voltage of the Fin-type four-terminal transistor included in the semiconductor device is referred to as the threshold voltage of the semiconductor device.

First, the semiconductor device 1 will be described.
These semiconductor devices 1 shown in FIG. 4 are referred to as semiconductor devices TG11 to TG22, respectively. Here, the Fin-type four-terminal transistor Tr2 and the second gate electrode (floating gate 202) included in the semiconductor device TG11 are referred to as a Fin-type four-terminal transistor Tr11 and a second gate electrode (floating gate 202) G11, respectively. Note that the control transistor Tr1 electrically connected to the second gate electrode G11 is omitted.

  Similarly, in the semiconductor devices TG12 to TG22, the Fin type 4-terminal transistors Tr12 to Tr22 and the second gate electrodes G12 to G22, respectively, are used.

  As shown in FIG. 4, the node N1 (voltage VDD) is connected to one end of the current path of the resistance element 300, and the other end is connected to the node N2. The node N2 is assumed to be an output terminal of a NAND circuit and a NOR circuit described in the following example.

One end of the current path of the Fin type four-terminal transistor Tr11 is connected to the other end of the resistance element 300 via the node N2, and the signal line S1 is connected to the first gate electrode 102 via the node N3. An input signal Sig1 is transferred to the signal line S1 from a system circuit 600 described later. The input signal Sig1 corresponds to the “H” level, for example, the voltage VDD or the “L” level, for example, a zero potential. In addition, a predetermined voltage is written into the second gate electrode G11 of the semiconductor device TG11 by the threshold adjustment circuit 400. This is because the threshold adjustment circuit 400 described later applies a predetermined voltage to the impurity diffusion layer 210 and the gate electrode 200, respectively, and thereby the amount of electrons accumulated in the floating gate 202 electrically connected to the second gate electrode. Is adjusted. Note that the threshold value of the semiconductor device TG11 having the Fin-type four-terminal transistor Tr11 is Vth11. Then, the semiconductor device TG11 takes one of the threshold voltages Vth11 _L , Vth11 _C , and Vth11 _H as the threshold Vth11. _Further, it is assumed that holds the relationship _{Vth11 L <Vth11 C <Vth11 H} , are (0V>) Vth11 L, ( 0V <) V11th C (< voltage VDD), V11th _H (> voltage VDD).

That is, when the threshold voltage of the semiconductor device TG11 is the threshold value Vth11 _L, is always turned on. Therefore, the semiconductor device TG11 can be regarded as a wiring.

Further, when the threshold voltage of the semiconductor device TG11 is a threshold Vth11 _C, the semiconductor device TG11 functions as a transistor. That is, the input signal Sig1 transferred to the signal line S1 is turned on or off according to the voltage level (“L” or “H” level).

Further, when the threshold voltage of the semiconductor device TG11 is the threshold value Vth11 _H, the semiconductor device TG11 is always turned off. Therefore, the semiconductor device TG11 can be regarded as being in an open (disconnected) state.

One end of the current path of the Fin-type four-terminal transistor Tr21 is connected to the other end of the resistance element 300 via the node N2, and the signal line S1 is connected to the first gate 102 via the node N3. As described above, the input signal Sig1 of “L” or “H” level is transferred to the signal line S1. Further, the threshold adjustment circuit 400 writes the second gate electrode G21 of the Fin-type four-terminal transistor Tr21 to a predetermined voltage. As described above, the threshold adjustment circuit 400 applies a predetermined voltage to the impurity diffusion layer 210 and the gate electrode 200, respectively, so that electrons stored in the floating gate 202 electrically connected to the second gate electrode are accumulated. This is because the amount is adjusted. Note that the threshold value of the semiconductor device TG21 having the Fin-type four-terminal transistor Tr21 is Vth21. The semiconductor device TG21 is assumed to take any one of the threshold voltages Vth21 _L , Vth21 _C , and Vth21 _H as the threshold Vth21. Further, it is assumed that the relationship of Vth21 _L <Vth21 _C <Vth21 _H is established, and (0V>) Vth21 _L , (0V <) Vth21 _C (<voltage VDD), Vth21 _H (> voltage VDD).

That is, when the threshold voltage of the semiconductor device TG21 is the threshold value Vth21 _L, is always turned on. Therefore, the semiconductor device TG21 can be regarded as a wiring.

Further, when the threshold voltage of the semiconductor device TG21 is a threshold Vth21 _C, the semiconductor device TG21 functions as a transistor. That is, the input signal Sig1 transferred to the signal line S1 is turned on or off according to the voltage level (“L” or “H” level).

Further, when the threshold voltage of the semiconductor device TG21 is the threshold value Vth21 _H, the semiconductor device TG21 is always turned off. Therefore, the semiconductor device TG21 can be regarded as being in an open (disconnected) state.

  The signal line S1 functions as one input terminal of a NAND circuit and a NOR circuit described in the following example.

  One end of the current path of the Fin type 4-terminal transistor Tr12 is connected to the other end of the current path of the Fin type 4-terminal transistor Tr11, the other end is grounded, and the first gate electrode 102 is connected to the signal line S2 via the node N4. Connected to. The input signal Sig2 is transferred to the signal line S2. The input signal Sig2 is equivalent to an 'H' level, for example, a voltage VDD or an 'L' level, for example, a zero potential.

In addition, the threshold adjustment circuit 400 writes the second gate electrode G12 of the semiconductor device TG12 to a predetermined voltage. This is because the threshold adjustment circuit 400 applies a predetermined voltage to the impurity diffusion layer 210 and the gate electrode 200 as described above, and thereby the amount of electrons accumulated in the floating gate 202 electrically connected to the second gate electrode. It is because it adjusts. Note that the threshold value of the semiconductor device TG12 having the Fin-type four-terminal transistor Tr12 is Vth12. Then, the semiconductor device TG12 takes one of the threshold voltages Vth12 _L , Vth12 _C , and Vth12 _H as the threshold Vth12. _Further, it is assumed that holds the relationship _{Vth12 L <Vth12 C <Vth12 H} , are (0V>) Vth12 L, ( 0V <) Vth12 C (< voltage VDD), Vth12 _H (> voltage VDD).

That is, when the threshold voltage of the semiconductor device TG12 is the threshold value Vth12 _L, is always turned on. Therefore, the semiconductor device TG12 can be regarded as a wiring.

Further, when the threshold voltage of the semiconductor device TG12 is a threshold Vth12 _C, the semiconductor device TG12 functions as a transistor. That is, the input signal Sig2 transferred to the signal line S2 is turned on or off according to the voltage level ('L' or 'H' level).

Further, when the threshold voltage of the semiconductor device TG12 is the threshold value Vth12 _H, the semiconductor device TG12 is always turned off. Therefore, the semiconductor device TG12 can be regarded as being in an open (disconnected) state.

  One end of the current path of the Fin type 4-terminal transistor Tr22 is connected to the other end of the current path of the Fin type 4-terminal transistor Tr21, the other end is grounded, and the first gate is connected to the signal line S2 via the node N4. Is done. As described above, the ‘L’ or ‘H’ level input signal Sig <b> 1 is transferred to the signal line S <b> 1.

Further, the threshold adjustment circuit 400 writes the second gate electrode G22 of the Fin-type four-terminal transistor Tr22 to a predetermined voltage. This is because the threshold adjustment circuit 400 adjusts the amount of electrons accumulated in the floating gate 202 by applying predetermined voltages to the impurity diffusion layer 210 and the gate electrode 200, respectively, as described above. The threshold value of the semiconductor device TG22 having the Fin-type four-terminal transistor Tr22 is Vth22. Then, the semiconductor device TG22 takes one of the thresholds Vth22 _L , Vth22 _C , and Vth22 _H as the threshold Vth22. _Further, it is assumed that holds the relationship _{Vth22 L <Vth22 C <Vth22 H} , are (0V>) Vth22 L, ( 0V <) Vth22 C (< voltage VDD), Vth22 _H (> voltage VDD).

That is, when the threshold voltage of the semiconductor device TG22 is the threshold value Vth22 _L, is always turned on. Therefore, the semiconductor device TG22 can be regarded as a wiring.

Further, when the threshold voltage of the semiconductor device TG22 is a threshold Vth22 _C, the semiconductor device TG22 functions as a transistor. That is, the input signal Sig2 transferred to the signal line S2 is turned on or off according to the voltage level ('L' or 'H' level).

Further, when the threshold voltage of the semiconductor device TG22 is the threshold value Vth22 _H, the semiconductor device TG22 is always turned off. Therefore, the semiconductor device TG22 can be regarded as being in an open (disconnected) state.

  The signal line S2 functions as the other input terminal of the NAND circuit and NOR circuit described in the following example.

  Note that one end and the other end of the current path of the Fin type four-terminal transistor Tr2 provided in each of the semiconductor devices TG11 to TG22 described above are the impurity diffusion layers 103 in FIG.

  Next, the threshold adjustment circuit 400 will be described. The threshold adjustment circuit 400 applies a predetermined voltage to the impurity diffusion layer 201 and the gate electrode 200, thereby causing the semiconductor devices TG11 to TG22 to apply voltages having values corresponding to the target thresholds Vth11 to Vth22 to the second gate electrodes G11 to G11. Write to G22. In other words, the threshold adjustment circuit 400 adjusts the amount of electrons accumulated in the floating gate 202 to change the potential of the second gate electrode to reach the target threshold potential.

Threshold adjustment circuit 400, each of the threshold voltage Vth11~Vth22 is zero _potential> Vth11 _{L ~Vth22} L, zero potential _{<Vth11 C ~Vth22} C _<voltage VDD or Vth11 _H ~Vth22 _H,> voltage such voltage satisfying the VDD Is transferred to each of the impurity diffusion layer 210 and the gate electrode 200 of the semiconductor devices TG11 to TG22. As described above, the threshold adjustment circuit 400 adjusts the time of the voltage applied to the gate electrode 200 in order to satisfy these threshold potentials. Thus, even if the threshold characteristics of the Fin-type four-terminal transistor Tr2 vary after manufacturing, the threshold adjustment circuit 400 applies a predetermined voltage to the Fin-type four-terminal transistor Tr2 and the gate electrode 200 constituting the semiconductor device 1. This is a circuit that can obtain the on / off ratio of the four semiconductor devices TG11 to TG22 by changing the time to be performed. That is, even variations in the threshold voltage was between the semiconductor device TG11～T22, be by adjusting the amount of electrons accumulated in the respective floating gates 202 for example _{Vth11 H = Vth12 H = Vth21 H} = Vth22 H Is a possible circuit. The same applies likewise _{Vth11 C = Vth12 C = Vth21 C} = Vth22 C, and _{Vth11 L = Vth12 L = Vth21 L} = Vth22 L.

  Next, the control unit 500 will be described. The control unit 500 controls the threshold adjustment circuit 400. That is, the magnitude of the voltage transferred by the threshold adjustment circuit 400 to the gate electrode 200, the length of time for applying the voltage, and the timing for applying the voltage are controlled.

  Next, the system circuit 600 will be described. The system circuit 600 outputs signals as input signals Sig1 and Sig2 to the signal lines S1 and S2, respectively. As described above, the input signals Sig1 and Sig2 are zero potential ('L' level) or voltage VDD ('H' level).

<Circuit logic rewriting method>
Next, an example of a method for rewriting the logic of the circuit described with reference to FIG. 4 will be described with reference to FIGS.
As an example, a case where the circuit shown in FIG. 4 functions as a NAND circuit or a NOR circuit according to the correspondence table shown in FIGS. As described above, from the semiconductor device 1 (not shown), the signals Sin1 and Sing2 that are set to either the voltage VDD or the zero potential are applied to the first gate electrodes 102 of the semiconductor devices TG11 to TG22 via the signal lines S1 and S2. .

  Further, the threshold adjustment circuit 400 applies a voltage corresponding to the target threshold value to each of the semiconductor devices TG11 to TG22 to the gate electrode 200. As described above, the threshold adjustment circuit 400 applies a predetermined voltage to the impurity diffusion layer 201 functioning as a source and a drain to adjust the amount of electrons in the floating gate 202. A description will be given focusing on the voltage application. Note that the timing at which the threshold adjustment circuit 400 transfers the voltage is controlled by the control unit 500.

First, the case of functioning as a NAND circuit will be described.
As shown in FIGS. 5A and 5B, the threshold adjustment circuit 400 is applied to the gate electrodes 200 of the semiconductor devices TG21 and 22 so that the potentials of the second gate electrodes G21 and G22 drop (L level in the figure). A predetermined voltage (a positive voltage with respect to the conductive layer 203) is applied. In other words, so that the threshold voltage of the semiconductor device TG21, TG 22 is the threshold value _Vth H 21, _Vth H 22 respectively, (make injecting electrons (increase).) Storing electrons in the floating gate 202 causes.

That is, the threshold adjustment circuit 400 applies a predetermined voltage to the gate electrode 200, whereby the thresholds Vth21 and Vth22 of the semiconductor devices TG21 and TG22 become (voltage VDD <) Vth21 _H and (voltage VDD <) Vth22 _H , respectively. Such a voltage is written to the floating gate 202.

Therefore, even when the voltage VDD is transferred as the input signals S1 and S2 to the first gate electrodes 102 of the semiconductor devices TG21 and TG22, the semiconductor devices TG21 and TG22 are turned off (FIG. 5 ( b)). At this time, if Vth21 _H (> voltage VDD) and Vth12 _H (> voltage VDD), Vth21 _H = Vth22 _H may or may not be.

On the other hand, the threshold adjustment circuit 400 applies a predetermined voltage (conductive layer) to the gate electrodes 200 of the semiconductor devices TG11 and TG12 so that the potentials of the second gate electrodes G11 and G12 rise ((a) in the figure, C level). 203 is applied to the negative voltage). In other words, so that the threshold voltage of the semiconductor device TG11, TG12 is a threshold Vth11 _C, Vth12 _C respectively to adjust the electrons stored in the floating gate 202 (to emit electrons). Specifically, for example, a predetermined voltage (negative voltage with respect to the conductive layer 203) is applied to the gate electrode 200 for a time t1, and electrons in the floating gate 202 are emitted, thereby setting the threshold voltage of the semiconductor devices TG11 and TG12. Raise.

That is, in the threshold adjustment circuit 400, for example, the thresholds Vth11 and Vth12 of the semiconductor devices TG11 and TG12 are (zero potential <) Vth11 _C (<voltage VDD) and (zero potential <) Vth12 _C (<voltage VDD), respectively. An appropriate voltage is written to the floating gate 202 for a time t1.

  When the voltage VDD is applied as the input signals Sig1 and Sig2, the semiconductor devices TG11 and TG12 are turned on (see FIG. 5A). That is, the potential of the node N2 (OUT) is set to the ground potential (zero potential, “L” as the logic level) at the other end of the current path of the Fin-type four-terminal transistor Tr12 in the semiconductor device TG12 (see FIG. 4).

  On the other hand, when any combination of (Sig1, Sig2) = (voltage VDD, zero potential), (zero potential, voltage VDD) and (zero potential, zero potential) is applied as the input signals Sig1, Sig2. Either the semiconductor device TG21 or TG22 is turned off (see FIG. 5A). Therefore, the node N2 functioning as an output terminal outputs a value (logical level ‘H’) obtained by subtracting the voltage dropped by the resistance element 300 from the voltage VDD (see FIG. 4).

From the above, by setting the threshold values of the semiconductor devices TG11 and T12 to Vth11 _C and Vth12 _C , the circuit illustrated in FIG. 4 functions as a NAND.

At this time, Vth11 _C = Vth12 _C may or may not be as long as at least (zero potential <) Vth11 _C and Vth12 _C (<voltage VDD).

Next, a case where the circuit shown in FIG. 4 functions as a NOR circuit will be described.
The threshold adjustment circuit 400 applies a predetermined voltage (negative with respect to the conductive layer 203) to the gate electrode 200 of the semiconductor devices TG21 and 12 so that the potentials of the second gate electrodes G21 and G12 rise (FIG. 5D, C level). Voltage). That is, the amount of electrons stored in the floating gate 202 is adjusted so that the threshold voltages of the semiconductor devices TG21 and TG12 become the threshold values Vth21 _C and Vth12 _C , respectively. Specifically, for example, by applying a predetermined voltage (negative voltage with respect to the conductive layer 203) to the gate electrode 200 for a time t1, electrons are emitted from the floating gate 202, and the threshold voltage of the semiconductor devices TG21, 12 is obtained. To raise.

Specifically, in the threshold adjustment circuit 400, for example, the thresholds Vth12 and Vth21 of the semiconductor devices TG12 and TG21 are (zero potential <) Vth12 _C (<voltage VDD) and (zero potential <) Vth21 _C (<voltage VDD), respectively. Is written to the floating gate 202 for a time t1, for example.

Therefore, when the voltage VDD is applied as the input signals Sig1 and Sig2, the semiconductor devices TG12 and TG21 are turned on, and when the zero potential is applied, the semiconductor devices TG12 and TG21 are turned off. . That is, the semiconductor devices TG12 and TG21 function as transistors. At this time, if (zero potential <) Vth21 _C (<voltage VDD) and (zero potential <) Vth12 _C (<voltage VDD), Vth21 _C = Vth22 _C may or may not be.

The threshold adjustment circuit 400 applies a predetermined voltage (with respect to the conductive layer 203) to the gate electrode 200 of the semiconductor devices TG11 and TG22 so that the potentials of the second gate electrodes G11 and G22 rise (FIG. 5C, H level). Apply a negative voltage. In other words, adjusting the amount of electrons threshold voltage of the semiconductor device TG11, TG 22 are injected respectively into the floating gate 202 so as to be Vth11 _L, Vth22 _L. Specifically, for example, by applying a predetermined voltage (negative voltage with respect to the conductive layer 203) to the gate electrode 200 for a longer time t2, electrons in the floating gate 202 are emitted, and the semiconductor devices TG21, 12 Increase the threshold voltage.

That is, the threshold adjustment circuit 400, for example, a semiconductor device TG11, threshold TG 22 Vth11, Vth22, respectively (zero potential>) Vth11 _L, the (zero potential>) Vth22 _L become such a voltage is written into the floating gate 202.

  Accordingly, at least zero potential is transferred to each of the input signals Sig1 and Sig2, so that the semiconductor devices TG11 and TG22 are always turned on (see FIG. 5C).

  From the above, when any combination of (Sig1, Sig2) = (voltage VDD, zero potential) or (zero potential, voltage VDD) is applied as the input signals Sig1, Sig2, any of the semiconductor devices TG12 or TG21 is turned on. State (see FIG. 5D). Since the semiconductor device TG11 or TG22 is always on, the node N2 functioning as the output terminal is connected to the ground potential (zero) at the other end of the current path of the Fin type four-terminal transistor Tr12 or Tr21 in the semiconductor device TG12 or TG21. The potential and logic level are set to “L” (see FIG. 4).

  On the other hand, when (Sig1, Sig2) = (zero potential, zero potential) is applied as the input signals Sig1, Sig2, the semiconductor devices TG12, TG21 are turned off, and thus function as output terminals. The node N2 outputs a value (the logic level is “H”) obtained by subtracting the voltage dropped by the resistance element 300 from the voltage VDD (see FIG. 4D).

With Vth12 _C, Vth21 _C a semiconductor device TG11, Vth11 the threshold T22 _L, Vth22 _L, TG12, threshold TG21 from above, the circuit shown in FIG. 4 functions as a NOR.

<Effects according to this embodiment>
The semiconductor device according to the present embodiment and the logic circuit using the semiconductor device can achieve the following effects (1) to (3).
(1) The variation in threshold value can be controlled.
Even if the semiconductor device according to the present embodiment has a variation in element performance, such as a threshold value, which each semiconductor device 1 has, for example, between a plurality of semiconductor devices 1 after manufacturing, By controlling the amount of electrons accumulated in the floating gate, individual threshold voltages can be controlled, and variations in threshold voltages can be reduced. For this reason, in the circuit as shown in FIG. 4, the threshold characteristics of the semiconductor devices TG11 to TG22 can be made equal to, for example, Vth _H or Vth _L as necessary. That is, even if the voltage by the threshold adjustment circuit 400 is a low voltage, the thresholds of these semiconductor devices 1 to TG22 can be controlled, so that it is not unstable and a sufficient on / off ratio can be obtained. I can do it.

(2) The operational reliability can be improved.
As described above, when the circuit configuration shown in FIG. 4 is changed to a NAND circuit, a NOR circuit, or the like by the control unit 500, the on / off ratio of the semiconductor devices TG11 to TG22 can be obtained. That is, when the voltage VDD or zero potential is transferred to the first gate via the signal lines S1 and S2, respectively, the semiconductor device 1 can be turned on or off as necessary.

(3) The element area can be reduced.
Conventionally, the same voltage is transferred to the back gate electrodes of a plurality of four-terminal transistors functioning as switching elements, as in the example of SRAM, for example. That is, if the threshold value varies between the plurality of four-terminal transistors after manufacturing, these switch elements may become unstable at the time of reading or writing. In some cases, a sufficient on / off ratio may not be obtained.

  Therefore, in order to make it possible to apply different voltages to these back gate electrodes in accordance with the thresholds of the individual four-terminal transistors, if an FG type memory cell transistor structure is simply adopted, the area becomes enormous. That is, the normal FG transistor has a configuration in which a floating diffusion layer, a second gate insulating film, and a gate electrode are sequentially formed on a semiconductor substrate with a first inter-gate insulating film interposed therebetween. If an attempt is made to connect the floating gate of the FG type transistor to the back gate of the four-terminal transistor, the number of wires increases more than necessary, and the occupied area increases accordingly.

  However, the semiconductor device according to the present embodiment and the transfer circuit using the semiconductor device have the configurations shown in FIGS. That is, the charge storage layer 202 and the second gate electrode 104 are electrically connected on the semiconductor substrate 100, so that necessary wiring can be eliminated. That is, even after the manufacture and even if the threshold values vary individually among the plurality of semiconductor devices TG11 to TG22, the semiconductor devices TG11 to TG22 can be individually controlled with the configuration according to the present embodiment. It is possible to suppress an increase in element area (circuit area).

  The semiconductor device and the logic circuit using the semiconductor device according to the above embodiment have been described by focusing on the Fin type 4-terminal transistor Tr as an example, but the structure is not limited thereto. In other words, the transistor structure is not limited to the Fin type as long as it is not a Fin type four-terminal transistor Tr but a transistor having four terminals.

  Further, the semiconductor device according to the embodiment and the logic circuit using the semiconductor device are the semiconductor device 1 formed on the SOI, but are not limited thereto. That is, a bulk fin transistor in which an element isolation film is formed on a semiconductor substrate may be used. In this case, the Fin-type conductive layers 106 and 204 in FIG. 1 are element regions that are processed into a protruding shape from the semiconductor substrate 100.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 101 ... Insulating film, 102, 104, 200 ... Gate electrode, 103 ... Impurity diffusion layer, 104 ... Second gate electrode, 201 ... Impurity diffusion layer, 202 ... Floating (FG) gate, 203, 105 ... Conductive layer, 400 ... threshold adjustment circuit, 500 ... control unit

Claims (5)

A first transistor formed on a first region of a semiconductor substrate;
A second transistor formed on a second region of the semiconductor substrate, the first transistor comprising:
A first semiconductor layer provided on the semiconductor substrate and having a fin shape in which a first source, a region where a first channel is formed, and a first drain are sequentially formed;
A first gate electrode adjacent to a region where the first channel of the first semiconductor layer is formed via a first gate insulating film;
A second gate electrode facing the first gate electrode with the first semiconductor layer interposed therebetween, and the second transistor comprises:
A second semiconductor layer having a fin shape, provided on the semiconductor substrate, wherein a second source, a region in which a second channel is formed, and a second drain are sequentially formed;
A charge storage layer adjacent to a region where the second channel is formed in the second semiconductor layer with a second gate insulating film interposed therebetween;
A third gate electrode facing the second semiconductor layer with the charge storage layer interposed therebetween,
The semiconductor device, wherein the second gate electrode and the charge storage layer are electrically connected. The second gate electrode is provided along a sidewall of the first semiconductor layer;
The charge storage layer is provided along a sidewall of the second semiconductor layer;
A conductive layer provided along the surface of the semiconductor substrate and connecting the second gate electrode and the charge storage layer;
The semiconductor device according to claim 1, wherein the third gate electrode is provided in a space sandwiched between the second gate electrode and the charge storage layer. 3. The semiconductor device according to claim 1, wherein a threshold voltage of the first transistor is a value corresponding to a charge amount in the charge storage layer. The first transistor includes:
3. The semiconductor device according to claim 1, wherein the semiconductor device is a Fin-type four-terminal transistor including the first and second gate electrodes and the Fin-shaped first semiconductor layer. A rewritable logic circuit comprising a plurality of semiconductor devices according to claim 1;
A threshold adjustment circuit capable of adjusting a threshold of the logic circuit;
The logic circuit is:
A plurality of transistor units in which the first semiconductor layers of the first transistors are commonly connected so that current paths are connected in series;
The threshold adjustment circuit includes:
A logic circuit comprising: adjusting a threshold value of the first transistor included in each of the plurality of transistor units, and rewriting logic of the logic circuit.

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