JP2011204081A - Semiconductor design program, semiconductor design method and semiconductor design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor design program, a semiconductor design method and a semiconductor design device, for facilitating calculation for predicting separation of a wiring layer.SOLUTION: The semiconductor design device 1 for predicting separation between wiring layers of a semiconductor integrated circuit includes an energy calculation part 5a and a conversion part 5b. The energy calculation part 5a calculates energy for closing a crack generated by virtually separating the wiring layers of a target part of a circuit model formed by modeling the semiconductor integrated circuit to be designed. The conversion part 5b converts the energy calculated by the energy calculation part 5a to energy per unit area of the crack.

Description

  The present invention relates to a semiconductor design program, a semiconductor design method, and a semiconductor design apparatus.

A large number of LSI (Large Scale Integration) packages are mounted in electronic devices such as PCs (Personal Computers) and mobile phones.
The layers of the LSI chip wiring layer may be peeled off due to thermal stress, temperature cycle, or the like during reflow heating when the LSI chip included in these LSI packages is mounted on the package.

In particular, in recent years, the dielectric constant of the interlayer insulating film has been reduced with the increase in the speed of LSI, and the decrease in peel strength (average load necessary for peel per unit width) has become remarkable.
As a factor that affects the peel strength between layers of LSI chips, it is known that the adhesion strength changes depending on the process during the production of the wiring layer.

  It is also known that whether or not the layers are actually peeled off is greatly influenced by structural factors such as the dimensions of the LSI chip. Factors of the structure include, for example, the chip size of the LSI chip, the thickness of the chip, the configuration in which wiring layers are stacked, the thickness of each layer, the placement of solder bumps on the LSI chip, the pitch, the solder joint electrode pad diameter, the pad thickness, and the reflow The temperature profile such as heating, the cooling rate, the material of the package substrate to be joined, the package thickness, the presence or absence of underfill reinforcement at the solder joint, and the like.

As a method for predicting such delamination in advance, a finite element analysis is known in which thermal stress generated in an LSI chip is verified by a temperature profile applied to the LSI chip.
However, when the LSI chip size is on the order of several millimeters to several tens of millimeters and the thickness of the thin film wiring or the insulating layer is on the order of several nanometers, the wiring layer of the entire LSI chip is based on finite element analysis. Modeled, the total number of meshes may be on the order of tens of billions. For this reason, the scale is not easy to realize the calculation.

  For this reason, a method for simplifying LSI chip models using physical property values of composite materials and analyzing stress, and a method for facilitating calculations by analyzing separation prediction in multiple steps Etc. have been proposed.

  In addition, in order to evaluate the peel strength at a specific location on an LSI chip, a method for calculating the energy release rate between wiring layers and predicting the peel strength has been proposed.

JP 2007-213269 A

Guotao Wang, Steven Groothuis and Paul S. Ho, `` Effect of Packaging on Interfacial Cracking in Cu / Low k Damascene Structures '', 2003 Electronic Components and Technology Conference, USA, Laboratory for Interconnect and Packaging, 2003 IEEE, p.727 −732 Nobuhiro Mochizuki and three others, “Prediction Method of Peelability of Low-k Material Interface during CMP”, Ebara Times, Ebara Research Institute, No. 219, April 2008, p.21-27

However, in order to calculate the energy release rate, a special analysis model or program is required, and it is difficult to predict the separation of the wiring layer.
The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor design program, a semiconductor design method, and a semiconductor design apparatus that facilitate calculation of wiring layer separation prediction.

  In order to achieve the above object, a semiconductor design program for predicting occurrence of peeling between wiring layers of a semiconductor integrated circuit is provided. This semiconductor design program causes a computer to execute an energy calculation procedure and a conversion procedure.

  In the energy calculation procedure, an energy for closing a crack generated by virtually peeling a wiring layer of a measurement target portion of a circuit model obtained by modeling a semiconductor integrated circuit to be designed is calculated.

  In the conversion procedure, the energy calculated by the energy calculation procedure is converted into energy per unit area of the crack.

  According to the disclosed semiconductor design program, it is possible to easily calculate the separation prediction of the wiring layer.

It is a figure which shows the outline | summary of the semiconductor design apparatus of 1st Embodiment. It is a figure which shows the hardware structural example of the semiconductor design apparatus of 2nd Embodiment. It is a block diagram which shows the function of the semiconductor design apparatus of 2nd Embodiment. It is a figure which shows an example of a whole structure analysis model. It is a figure which shows the graph used for prediction of peeling incidence. It is a figure (graph) which shows the relationship between peeling incidence prediction value and the measured peeling incidence. It is a figure which shows the change of the largest principal stress distribution of LSI chip accompanying arrangement | positioning of a solder bump. It is a figure explaining the cause that the stress of an outermost peripheral part falls. It is a figure which shows the example of arrangement | positioning of the solder bump which suppresses peeling in the case of filling an underfill. It is a figure which shows the example of arrangement | positioning of the solder bump which suppresses peeling when not filling an underfill. It is a figure which shows a part of detailed analysis model. It is a figure which shows a cracked analysis mesh model. It is a figure which shows a mode that a difference arises in the displacement of a node. It is a figure which shows the graph which shows the relationship between an energy release rate and peeling incidence. It is a figure which shows an example of the information which a result output part displays on a monitor. It is a flowchart which shows the whole process of a semiconductor design apparatus. It is a flowchart which shows a 1st determination process. It is a flowchart which shows a 2nd determination process. It is a flowchart which shows the calculation process of peeling incidence rate prediction value.

Hereinafter, embodiments will be described in detail with reference to the drawings.
First, the semiconductor design apparatus according to the embodiment will be described, and then the embodiment will be described more specifically.

<First Embodiment>
FIG. 1 is a diagram showing an outline of the semiconductor design apparatus according to the first embodiment.
The semiconductor design apparatus (computer) 1 according to the embodiment evaluates the influence of the layout of solder bumps, which are input / output terminals of an LSI chip (semiconductor integrated circuit), on the peel strength between the layers of the LSI chip wiring layer. This device provides an LSI package with a strong solder bump layout.

The semiconductor design apparatus 1 includes a stress distribution calculation unit 2, a determination unit 3, a detailed analysis model creation unit 4, an energy release rate calculation unit 5, a determination unit 6, and an output unit 7.
The stress distribution calculation unit 2 adds a load condition such as temperature to each component of the LSI package, for example, an LSI chip, a substrate, and an entire finite element analysis model including solder bumps that electrically connect the LSI chip to the substrate. Then, the stress distribution acting on the LSI chip is obtained.

  The determination unit 3 determines the pass / fail of the entire finite element analysis model by determining the possibility of peeling of the wiring layer of the entire finite element analysis model based on the stress distribution obtained by the stress distribution calculation unit 2. As a determination method, for example, an evaluation formula that combines each stress acting on a specific portion of the LSI chip (hereinafter, as an example, a joint portion with a solder bump of the wiring layer (solder joint portion)) is applied to the specific portion of the LSI chip. Substituting various acting stresses, the predicted value of the occurrence rate of peeling is obtained.

As the stress to be combined, for example, it is preferable to combine the maximum principal stress and the stress in the stacking direction of the wiring layer. Thereby, the accuracy of the predicted value of the peeling occurrence rate is improved.
And the determination part 3 determines whether the acquired predicted value is below a predetermined value. The determination unit 3 determines that the entire finite element analysis model is “good” when the predicted value is equal to or less than a predetermined value for all the solder joints. On the other hand, if there is a solder joint having a predicted value larger than the predetermined value, it is determined that the entire finite element analysis model is “NO”.

  The determination unit 3 changes the placement position of the solder bumps according to the user's designation for the solder joint portion that is determined as “No” for the entire finite element analysis model. In this case, the determination unit 3 again determines pass / fail for the entire finite element analysis model in which the solder bump placement position is changed. The semiconductor design apparatus 1 repeats this operation until it is determined that the entire finite element analysis model is “good”.

  The detailed analysis model creation unit 4 creates a detailed analysis model in which a part of the entire finite element analysis model is modeled in detail for the entire finite element analysis model determined by the determination unit 3 to be “good”.

  Here, the part for creating the detailed analysis model includes, for example, a solder joint that is predicted to have the largest predicted value acquired by the determination unit 3, that is, the highest possibility of occurrence of peeling, and the solder joint on the solder joint The wiring layer.

  Then, the detailed analysis model creation unit 4 virtually separates the wiring layers of the created detailed analysis model. Specifically, a mesh model in which the wiring layers are separated by a mesh is created. Then, one node of the mesh shared between the wiring layers is separated.

  Here, the detailed analysis model creation unit 4 preferably adds conditions such as temperature change and load obtained from the result of the entire finite element analysis to the detailed analysis model. Thereby, the precision of prediction can be improved more.

The energy release rate calculation unit 5 includes an energy calculation unit 5a and a conversion unit 5b.
The energy calculation unit 5a calculates the energy for closing a crack generated by virtually separating the wiring layers with respect to the detailed analysis model created by the detailed analysis model creating unit 4.

  The conversion part 5b calculates the energy release rate which converted the energy calculated by the energy calculation part 5a into the energy per unit area of a crack. Specifically, the energy per unit area of the crack is calculated by dividing the energy calculated by the energy calculation unit 5a by the area of the crack. The area of the crack is calculated as, for example, the area of a circle having a radius on one side of the mesh as the total area of the crack.

The determination unit 6 determines pass / fail of the entire finite element analysis model by substituting the energy release rate converted by the conversion unit 5b into the prepared evaluation formula.
The output unit 7 outputs various types of information such as the energy release rate of the whole finite element analysis model determined to be “good” by the determination unit 6.

  According to such a semiconductor design apparatus 1, the stress distribution calculating unit 2 calculates the stress distribution acting on the LSI chip. Based on the stress distribution obtained by the stress distribution calculation unit 2, the determination unit 3 determines the quality of the finite element overall analysis model. When it is determined that the entire finite element analysis model is “NO”, the placement position of the solder bumps is changed according to the user's designation.

  Further, the detailed analysis model creation unit 4 creates a detailed analysis model for the entire finite element analysis model determined to be “good” by the determination unit 3, and virtually separates the wiring layers of the detailed analysis model. . The energy calculation unit 5a calculates the energy for closing the cracks generated by virtually separating the wiring layers in the created detailed analysis model. The conversion unit 5b calculates an energy release rate obtained by converting the calculated energy into energy per unit area of the crack.

And the determination part 6 determines the quality of the whole finite element analysis model based on the energy release rate converted by the conversion part 5b.
The output unit 7 outputs various types of information such as the energy release rate of the whole finite element analysis model determined to be “good” by the determination unit 6.

  According to this semiconductor design device 1, the energy release rate can be easily calculated by the processing of the energy release rate calculation unit 5. Accordingly, it is possible to facilitate calculation of the wiring layer peeling prediction.

  The stress distribution calculation unit 2, the determination unit 3, the detailed analysis model creation unit 4, the energy release rate calculation unit 5, the determination unit 6, and the output unit 7 are provided by a CPU (Central Processing Unit) included in the semiconductor design apparatus 1. It can be realized by the function provided.

  In the present embodiment, the semiconductor design apparatus 1 includes a stress distribution calculation unit 2, a determination unit 3, a detailed analysis model creation unit 4, an energy release rate calculation unit 5, an energy calculation unit 5a, a conversion unit 5b, and a determination unit 6. And the function of the output unit 7. However, the present invention is not limited to this, and functions other than the energy release rate calculation unit 5 may be provided outside the semiconductor design apparatus 1.

Hereinafter, the embodiment will be described more specifically.
<Second Embodiment>
FIG. 2 is a diagram illustrating a hardware configuration example of the semiconductor design apparatus according to the second embodiment.

  The entire semiconductor design apparatus 100 is controlled by the CPU 101. A random access memory (RAM) 102, a hard disk drive (HDD) 103, a graphic processing device 104, an input interface 105, an external auxiliary storage device 106, and a communication interface 107 are connected to the CPU 101 via a bus 108. Yes.

  The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data necessary for processing by the CPU 101. The HDD 103 stores an OS and application programs. A program file is stored in the HDD 103.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits a signal transmitted from the keyboard 105 a and the mouse 105 b to the CPU 101 via the bus 108.

  The external auxiliary storage device 106 reads information written on the recording medium and writes information on the recording medium. Examples of the recording medium that can be read and written by the external auxiliary storage device 106 include a magnetic recording device, an optical disc, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include an HDD, a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). Examples of the magneto-optical recording medium include MO (Magneto-Optical disk).

  The communication interface 107 is connected to the network 30. The communication interface 107 transmits and receives data to and from other computers via the network 30.

  With the hardware configuration as described above, the processing functions of the present embodiment can be realized. The following functions are provided in the semiconductor design apparatus 100 having such a hardware configuration.

FIG. 3 is a block diagram illustrating functions of the semiconductor design apparatus according to the second embodiment.
The semiconductor design apparatus 100 includes a finite element analysis model DB 110, a finite element whole analysis unit 120, an evaluation DB 130, a solder bump layout information DB 140, a determination unit 150, a detailed analysis model DB 160, and an LSI detailed model placement unit 170. The finite element detailed analysis unit 180, the displacement extraction unit 190, the finite element detailed analysis unit 200, the energy release rate calculation unit 210, the determination unit 220, and the result output unit 230 are included.

  The finite element analysis model DB 110 stores a model for whole structure analysis (hereinafter referred to as “whole structure analysis model”) for investigating a macro stress distribution that acts when an LSI chip is mounted on a printed circuit board. Has been.

This overall structural analysis model has an LSI chip, solder bumps, a mounting board, and their attached members (solder resist, electrodes, etc.).
The overall structural analysis model has solder joint layout information.

The wiring layer of the LSI chip of the overall structural analysis model has a plurality of layers in the thickness direction.
Hereinafter, an example of the entire structural analysis model stored in the finite element analysis model DB 110 will be described.

FIG. 4 is a diagram illustrating an example of the entire structural analysis model.
In an overall structural analysis model 10 shown in FIG. 4, an LSI chip model 13 is placed on a substrate model 11 via a plurality of solder bump models 12.

The size of the substrate model 11 is 47.5 mm × 47.5 mm × 1.32 mm.
The size of the LSI chip model 13 is 10 mm × 10 mm × 0.55 mm.
The lower right part of FIG. 4 represents the entire structural analysis model 10 obtained by cutting out the upper right quarter of the entire entire structural analysis model 10. Therefore, the side length of the LSI chip model 13 shown in FIG. 4 is 5 mm.

  The solder bump model 12 is a model of a solder bump having, for example, an alloy of tin and silver (Sn—Ag) as a constituent element. The solder bump models 12 are arranged at all arrangement positions of the LSI chip model 13 (full grid), and the pitch of each solder bump model 12 is 0.176 mm.

  The finite element whole analysis unit 120 executes finite element analysis of the whole structure analysis model stored in the finite element analysis model DB 110. Specifically, the finite element whole analysis unit 120 adds a load condition such as temperature to the finite element whole analysis model, and obtains distributions of various stresses acting on the LSI chip. At this time, a plurality of stresses are extracted for the elements on the wiring layer surface of the LSI chip divided in the thickness direction of the wiring layer.

Examples of factors extracted by the finite element analysis include the following (a) to (d).
(A) Maximum, intermediate and minimum principal stresses σ1, σ2, σ3, maximum Mises stress σm, and stress components (XYZ normal stress σx, σy, σz, shear stress τxy, τyz, τzx) of the entire LSI chip.

  (B) Strain corresponding to these stresses, maximum, intermediate, minimum principal stress ε1, ε2, ε3, equivalent strain εm, each strain component (XYZ vertical strain εx, εy, εz, shear strain γxy, γyz, γzx) .

  (C) The above-mentioned (a) in a specific part of the LSI chip (joint part between the wiring layer and the solder bump (hereinafter referred to as “solder joint part”) and the surface (circuit element surface) where the LSI chip is connected to the solder bump. ) And (b), various maximum stresses or maximum strains.

(D) Maximum equivalent plastic strain at the solder joint.
Note that the finite element overall analysis unit 120 may display the analysis results of these factors on the monitor 104a.

  The evaluation DB 130 stores a graph having a relationship of an evaluation formula (formula (1) described later) having various stresses as variables. This evaluation expression is an expression for predicting the occurrence rate of peeling of the wiring layer of the LSI chip.

  In addition, in the evaluation DB 130, there are other graphs showing the relationship between the predicted value of the peeling occurrence rate obtained by the above evaluation formula and the actually measured peeling occurrence rate, and the graph showing the relationship between the energy release rate and the peeling occurrence rate. May be stored.

Solder bump layout information DB 140 stores solder bump arrangement position information (layout information).
The determination unit 150 extracts stress that seems to directly or indirectly affect the separation occurrence rate from the factors analyzed by the finite element overall analysis unit 120.

  Then, the determination unit 150 extracts the stress at the center coordinate of each solder joint based on the extracted stress and the solder bump placement position information stored in the solder bump layout information DB 140. And the determination part 150 calculates | requires the predicted value of peeling generation | occurrence | production about the wiring layer on the center coordinate of each solder joint part by substituting the extracted stress for the evaluation formula stored in evaluation DB130.

Here, the wiring layer on the center coordinate means each wiring layer located on the straight line when the straight line is extended in the thickness direction of the wiring layer (Z-axis direction) from the central coordinate of the solder joint. To do.
And the determination part 150 determines the quality of the whole structure analysis model based on the obtained predicted value. This will be described in detail below.

  The rate of occurrence of peeling of the wiring layer on the center coordinates of each solder joint has a correlation with a specific stress of the LSI chip. Specifically, it has a low correlation with Mises equivalent stress and the like, and the maximum principal stress of the LSI chip on the element surface of the LSI chip (hereinafter referred to as “LSI chip maximum principal stress”) and the Z of the element surface of the LSI chip There is a high correlation with the stress in the direction (stacking direction) (hereinafter referred to as “LSI chip Z direction stress”).

The following shows the results of investigation by multiple regression analysis of the LSI chip maximum principal stress, the LSI chip Mises equivalent stress, and the correlation between the LSI chip Z-direction stress and the separation occurrence rate.
The LSI chip maximum principal stress (MPa) has a coefficient of 0.119828 and a t value of 0.653806.

The Mises stress (MPa) is a coefficient: 0.018603, t value: 0.487123.
The LSI chip Z direction stress (MPa) is a coefficient: 0.16817 and a t value: 1.48594.

  Therefore, hereinafter, the operation of the determination unit 150 will be described by taking as an example the case where the determination unit 150 extracts the LSI chip maximum principal stress and the LSI chip Z direction stress that are highly correlated with the separation occurrence rate from the finite element analysis result.

The determination unit 150 calculates a predicted value of the occurrence rate of peeling by the following equation (1) that linearly combines the LSI chip maximum principal stress and the LSI chip Z direction stress.
Predicted peeling rate Y (%) = A × LSI chip maximum principal stress + B × LSI chip Z direction stress + C (1)
However, A, B, and C are coefficients obtained by regression analysis with an actual peeling occurrence rate.

FIG. 5 is a diagram illustrating a graph used for predicting the occurrence rate of peeling.
The X-axis of the graph 141 shown in FIG. 5 is the LSI chip maximum principal stress (Mpa) (corresponding to A above), and the Y-axis is the predicted delamination rate Y (%).

A graph 141 shows a straight line obtained by Expression (1) when the LSI chip Z-direction stress is set to 0 to 3, respectively.
In the graph 141, A = 0.075292 (MPa). B = −0.06384 (MPa).

  For example, in Equation (1), the predicted peeling rate Y when LSI chip maximum principal stress = 1, LSI chip Z-direction stress = 0, and C = 0 is 0.075292 × 1 − (− 0.06384). X0 = 0.075292.

  In Formula (1), when the LSI chip maximum principal stress = 1, LSI chip Z-direction stress = 1, and C = 0, the predicted peeling occurrence rate Y is 0.075292 × 1 − (− 0.06384). X1 = 0.139132.

Note that the determination unit 150 may display the graph 141 on the monitor 104a.
Next, the reliability of the predicted occurrence rate of peeling Y in Equation (1) will be described.
FIG. 6 is a diagram (graph) showing the relationship between the predicted peeling occurrence rate and the actually measured peeling occurrence rate.

FIG. 6A is a graph showing the relationship between the predicted peeling occurrence value Y (combining the LSI chip maximum principal stress and the LSI chip Z direction stress) according to the above equation (1) and the actually measured peeling occurrence rate. In graph 142a, the coefficient of determination R ² indicating the true condition of the model is 0.9946.

On the other hand, FIG.6 (b) is a graph which shows the relationship between the peeling incidence rate prediction value by Mises stress, and the measured peeling incidence rate. In graph 142b, the coefficient of determination R ² indicating the true condition of the model is 0.0525.

  Thus, by calculating the peeling occurrence rate prediction value Y using the equation (1), when calculating the peeling occurrence rate prediction value using Mises stress, or using only a single stress. The accuracy of the peeling prediction can be increased as compared with the case where the predicted peeling occurrence rate is calculated.

  Then, the determination unit 150 determines pass / fail of the overall structural analysis model based on the predicted peeling rate Y of the wiring layer on the center coordinates of each solder joint obtained as a result of the calculation. The quality of the overall structural analysis model can be determined as follows, for example.

  A threshold value (hereinafter referred to as “allowable value P1”) is provided in advance to the predicted peeling occurrence value Y. When the predicted peeling rate Y of the wiring layer on the center coordinates of a certain solder joint exceeds this allowable value P1, the wiring layer on the center coordinates of this solder joint is determined as “No”. . For example, when the allowable value P1 is set to 0%, when the peeling occurrence rate prediction value Y is 0%, it is determined as “good”. If it is greater than 0%, it is determined as “No”.

  The determination unit 150 performs the above determination for all solder joints of the LSI chip model. If there is a location determined as “NO”, the fact is displayed on the monitor 104a and the identification information of the solder joint determined as “NO” is notified to the user. As this notification method, for example, as shown in FIG. 7 to be described later, an LSI chip model is displayed on the screen, and the solder bump model of the solder joint portion determined to be “No” is displayed in a different color or blinked. Or the like.

  The user can select the coordinates (candidate point coordinates) of the candidate point for moving the solder bump from the part where the solder bump is not arranged by operating the keyboard 105a and the mouse 105b.

At this time, the user can try to decrease the peeling occurrence rate prediction value Y by selecting the candidate point coordinates as follows.
Hereinafter, a method for selecting candidate point coordinates will be described. First, a change in the maximum principal stress distribution of the LSI chip accompanying the solder bump arrangement will be described, and then an example of the solder bump arrangement movement will be described.

<Selection method of candidate point coordinates>
FIG. 7 is a diagram showing a change in the maximum principal stress distribution of the LSI chip accompanying the arrangement of the solder bumps.

  Here, FIG. 7A to FIG. 7F show a case where the upper left quarter of the LSI chip model 13 is cut out when the solder bump model 12 is arranged at all the arrangement positions on the LSI chip model 13. It is a figure which shows the wiring surface. That is, the upper left of the LSI chip model 13 shown in FIGS. 7A to 7F corresponds to the corner of the LSI chip model 13, and the lower right corresponds to the center of the LSI chip model 13.

FIG. 7B is a diagram showing the stress distribution of the maximum principal stress of the LSI chip when the LSI chip model 13 in FIG. 7A is simulated.
A dark portion (portion close to black) indicates that the stress is larger than a light portion (portion close to white).

As described above, the maximum principal stress of the LSI chip does not simply occur at the outermost peripheral portion of the LSI chip, but occurs to some extent inside.
FIGS. 7C and 7E show wiring surfaces of the LSI chip model 13 when the number of solder bump models 12 is reduced compared to the LSI chip model 13 shown in FIG. FIG. FIG. 7D is a diagram showing the stress distribution of the maximum principal stress of the LSI chip when the LSI chip model 13 in FIG. 7C is simulated. FIG. 7F is a diagram showing the stress distribution of the maximum principal stress of the LSI chip when the LSI chip model 13 in FIG. 7E is simulated.

The LSI chip model 13 shown in FIGS. 7B, 7D, and 7F shows the stress distribution when the underfill is filled.
As can be seen from the models shown in FIGS. 7B, 7D, and 7F, the maximum principal stress of the LSI chip varies depending on the number of solder bumps.

  However, in any arrangement, in the case of a structure filled with underfill, the maximum principal stress of the LSI chip is generated to some extent from the outer peripheral portion where the solder bumps are arranged. Further, the outermost peripheral portion is rather subjected to stress reduction or compressive stress.

FIG. 8 is a diagram for explaining the cause of a decrease in stress at the outermost periphery.
In the LSI package 20 shown in FIG. 8, an LSI chip 23 is arranged on a substrate 21 via solder bumps 22. An underfill 24 is disposed so as to reinforce the bonding strength of the portion indicated by the oblique lines, that is, the bonding surface of the LSI chip 23 and the solder bump 22.

  When the temperature is decreased, the underfill 24 and the outer peripheral portion of the LSI chip 23 are pulled following the warp of the substrate 21 as shown in FIG. For this reason, compressive stress acts near the outermost periphery of the LSI chip 23. Accordingly, the stress at the outermost peripheral portion is reduced.

FIG. 9 is a diagram illustrating an arrangement example of solder bumps for suppressing peeling when filling with underfill.
From the above results, when the LSI package 20 is filled with the underfill 24, it is preferable that the solder bumps 22 inside the outermost peripheral portion of the corner portion of the LSI chip 23 be moved to another position.

  For example, as shown in FIG. 9A, all of the solder bumps 22 in the portion adjacent to the outermost peripheral portion of the corner portion of the LSI chip 23 (the portion surrounded by the dotted line) are moved to another position. Is preferred.

  In another example, as shown in FIG. 9B, a part of the solder bump 22 in a portion (a portion surrounded by a dotted line) adjacent to the outermost peripheral portion of the corner portion of the LSI chip 23 is placed at another position. It is preferable to displace the solder bumps at this portion to reduce the density.

Thereby, the stress of the LSI chip 23 generated at this location can be reduced.
FIG. 10 is a diagram illustrating an example of the arrangement of solder bumps for suppressing peeling when the underfill is not filled.

  In the LSI chip 23 of the LSI package 20 that is not filled with the underfill 24, a portion where the stress is maximum occurs at the center of the side of the LSI chip 23. For this reason, it is preferable that the arrangement of the solder bumps 22 at the center of the side of the LSI chip 23 is moved to another position.

  For example, as shown in FIG. 10A, all the solder bumps 22 in the outermost row (the portion surrounded by the dotted line) at the center of the side of the LSI chip 23 are moved to other positions. Is preferred.

  In another example, as shown in FIG. 10B, a part of the solder bump 22 in the outermost row portion (the portion surrounded by the dotted line) at the center of the side of the LSI chip 23 is placed at another position. It is preferable to displace the solder bumps at this portion to reduce the density.

Thereby, the stress of the LSI chip 23 generated at this location can be reduced.
Returning to FIG. 3, the description will be continued.
When the determination unit 150 receives the coordinates of an alternative candidate point input by the user, the determination unit 150 temporarily arranges the entire structural analysis model in which the solder bumps are arranged and moved at the coordinates. Here, the provisional assumption is that solder bumps are not arranged at the coordinates of candidate points of the LSI chip model. Then, various stresses of the temporarily placed overall structural analysis model are approximated and calculated from the analysis result of the finite element overall analysis unit 120. Since this calculation method can be obtained by a known method, detailed description thereof is omitted.

Then, the determination unit 150 substitutes the extracted stress into Expression (1), and determines pass / fail for the entire structural analysis model temporarily arranged by repeating the above-described method.
Note that when there are a plurality of candidate point coordinates, the determination unit 150 provisionally arranges the entire structural analysis model for all candidate point coordinates. Then, the quality of the overall structural analysis model is determined by calculating the peeling occurrence rate prediction value Y for all the temporarily placed overall structural analysis models. Then, candidate point coordinates (excellent candidate point coordinates) of the overall structural analysis model determined as “good” are extracted.

Then, the determination unit 150 creates an overall structural analysis model in which the solder bumps are arranged and moved at the excellent candidate point coordinates.
Further, when there are a plurality of excellent candidate point coordinates, the determination unit 150 further selects the candidate point coordinates (the best candidate point coordinates) with the smallest peeling occurrence rate prediction value Y from the extracted excellent candidate point coordinates. Create an overall structural analysis model with solder bumps placed and moved.

The finite element whole analysis unit 120 performs a finite element whole analysis using the whole structure analysis model created by the determination unit 150.
The determination unit 150 repeatedly executes the above finite element overall analysis and result determination until the determination result becomes “good” at the center coordinates of all the solder joints.

  When the determination unit 150 determines “good” at the center coordinates (all placement points of the solder bumps) of the solder joints of all the LSI chips by the above determination method, that is, the separation occurrence rate at all the center coordinates. When the predicted value falls below the allowable value P1, the following processing is performed.

  The determination unit 150 obtains the coordinates of the solder joint where peeling is most likely to occur from Equation (1), that is, the coordinates of the solder joint where the maximum stress is generated, and places the obtained coordinates in the LSI detailed model arrangement. To the unit 170.

The detailed analysis model DB 160 stores a detailed analysis model in which the details of the solder joint and the wiring layer are modeled out of the entire structural analysis model.
The LSI detailed model placement unit 170 refers to the detailed analysis model DB 160 and acquires a detailed analysis model. Then, the LSI detailed model placement unit 170 moves the center coordinates of the detailed analysis model to the center coordinates of the solder joint determined by the determination unit 150 that the maximum stress is generated.

The center coordinates can be designated by the user operating the keyboard 105a and the mouse 105b.
The finite element detailed analysis unit 180 adds conditions such as temperature change and load obtained from the analysis result of the overall structural analysis model to the detailed analysis model at the coordinate of the moved position, that is, the coordinate of the solder joint where the maximum stress occurs. And perform a detailed analysis.

FIG. 11 is a diagram illustrating a part of the detailed analysis model.
The detailed analysis model 10a includes a solder bump model 12a having a rotationally symmetric shape with the substrate model 11a, an LSI chip model 13a having a detailed wiring layout of the wiring layer, and these accessories and materials such as resists and electrode pads. Yes.

  The finite element detailed analysis unit 180 is a mesh model (analysis mesh with cracks) for analysis in the wiring layer of the LSI chip model 13a located directly above the rotation center (on the central axis 12b) of the solder bump model 12a of the detailed analysis model 10a. Model). The joint between the solder bump model 12a and the LSI chip model 13a on the central axis 12b is the center coordinate of the solder joint. This will be described below with reference to the drawings.

FIG. 12 is a diagram showing a cracked analysis mesh model.
The cracked analysis mesh model is a model that assumes a crack that occurs due to separation between wiring layers.

  The finite element detailed analysis unit 180 vertically separates (releases) one central node between wiring layers where separation is predicted, and creates a cracked analysis mesh model having a crack model with two independent nodes.

  For example, the mesh model 15 shown in FIG. 12A is a model obtained by meshing a plurality of wiring layers of the LSI chip model 13a of the detailed analysis model 10a in a matrix. The size of one mesh (mesh length R) can be arbitrarily determined by the user.

  The mesh model 15 illustrates one node 131 located between the two wiring layer models 13b and 13c indicated by the highlighted thick frame in FIG. 12A. In a state where no peeling occurs, the two wiring layer models 13b and 13c share one node 131.

  As illustrated in FIG. 12B, the finite element detailed analysis unit 180 is formed between the two independent nodes 132 and 133, the node 132, and the node 133 by separating the node 131 in the vertical direction. A cracked analysis mesh model having a crack 134 (a portion indicated by a hatched portion in FIG. 12B) is created.

Returning to FIG. 11, the description will be continued.
Further, the finite element detailed analysis unit 180 calculates the area (crack area) S of the crack 134.
Here, when calculating the crack area S, the shape of the crack 134 is a regular polygon in plan view. The number of corners of the polygon is preferably 16 or more (16 or more). By doing so, since the shape of the crack can be regarded as a substantially circular shape, the crack area S can be regarded as equal to the area of the circle.

In addition, since one node is separated in the vertical direction, the radius of the crack 134 is equal to the mesh length R. Therefore, it can be approximately calculated by the crack area S = πR ² . In FIG. 11, the area of half (S / 2) of the crack area S is indicated by hatching. The finite element detailed analysis unit 180 sends the calculated crack area S to the energy release rate calculation unit 210.

Furthermore, the finite element detailed analysis unit 180 gives a load condition such as a temperature change and a load to the mesh model. Due to the applied load, a difference occurs in the displacement of the nodes 132 and 133.
FIG. 13 is a diagram illustrating a state in which a difference occurs in the displacement of the nodes.

The displacement extraction unit 190 extracts a displacement difference (displacement difference ΔU) between the nodes 132 and 133.
Specifically, if the displacement of the node 132 is u1 (u1x, u1y, u1z) and the displacement of the node 133 is u2 (u2x, u2y, u2z), the displacement difference ΔU = u1 (u1x, u1y, u1z) −u2 ( u2x, u2y, u2z).

  When the displacement extraction unit 190 extracts the displacement difference ΔU, the finite element detailed analysis unit 200 cancels the displacement difference ΔU and extracts a reaction force F that equalizes the displacements of both nodes from the finite element analysis result.

  Specifically, as shown in FIG. 13B, displacement (forced displacement) in the direction of closing the crack 134 is added, and the reaction force F generated when closing between the nodes 132 and 133 is determined from the finite element analysis result. Extract. Then, the extracted reaction force F is applied to the node 132. Thereby, the displacement between the nodes 132 and 133 becomes equal, and the displacement of the node 132 coincides with the displacement of the node 133. By doing so, the crack 134 is closed.

  The energy release rate calculation unit 210 uses the displacement difference ΔU obtained from the displacement extraction unit 190 and the reaction force F obtained from the finite element detailed analysis unit 200 to calculate the crack closing energy E (= ΔU × F / 2). calculate.

  Further, the energy release rate calculation unit 210 calculates the energy per unit area by dividing the crack closing energy E obtained by the calculation by the crack area S acquired from the finite element detailed analysis unit 200, and calculates the energy release rate ERR. And Specifically, the energy release rate ERR = E / S = (ΔU × F / 2) / S.

The energy release rate calculation unit 210 may display the obtained energy release rate ERR on the monitor 104a.
The determination unit 220 substitutes the energy release rate ERR obtained by the energy release rate calculation unit 210 into a graph showing the relationship between the energy release rate ERR stored in the evaluation DB 130 and the separation occurrence rate, and Judge the quality.

FIG. 14 is a graph showing a relationship between the energy release rate and the separation occurrence rate.
In the graph 143 in FIG. 14, the horizontal axis indicates the energy release rate ERR (J / mm ² ), and the vertical axis indicates the separation occurrence rate.

The quality of the overall structural analysis model can be determined as follows, for example.
A threshold value (hereinafter referred to as “allowable value P2”) is provided in advance to the peeling occurrence rate. Then, when the peeling occurrence rate obtained by substituting the energy release rate ERR into the graph 143 exceeds the allowable value P2, “No” is determined. For example, when the allowable value P2 is set to 0%, when the energy release rate ERR is 0%, it is determined as “good”. If it is greater than 0%, it is determined as “No”.

  If the determination unit 220 determines “No”, the determination unit 220 determines whether there are other candidate point coordinates. In the present embodiment, it is determined whether or not there are other above-described excellent candidate point coordinates, and if they are present, it is determined that other candidate point coordinates are further present.

  Further, as another example, a candidate point that the monitor 104a displays “not determined” and the identification information of the solder joint determined to be “not” is notified to the user and input by the user You may make it receive a coordinate (coordinate of the site | part in which the solder bump is not arrange | positioned).

  Then, when there are other candidate point coordinates, that is, other excellent candidate point coordinates, the determination unit 220 determines an excellent candidate point coordinate having the smallest peeling occurrence rate prediction value Y as a solder bump arrangement position candidate.

Then, the determination unit 220 creates an overall structural analysis model in which the solder bumps are arranged and moved to the decided arrangement position candidates.
In this case, the semiconductor design apparatus 100 repeatedly performs the process from the finite element overall analysis unit 120 to the process of the determination unit 220 again using the created overall structure analysis model.

If the determination unit 220 determines that the overall structural analysis model is “good”, the determination unit 220 transfers the energy release rate ERR of the overall structural analysis model determined to be “good” to the result output unit 230.
The result output unit 230 digitizes and graphs the transferred energy release rate ERR and displays it on the monitor 104a.

FIG. 15 is a diagram illustrating an example of information displayed on the monitor by the result output unit.
On the monitor 104a, the transferred energy release rate ERR is displayed as a numerical value and a graph.

  In FIG. 15, “Model 1”, “Model 2”, and “Model 3” indicate different LSI chip models. “G-1 (X direction)” indicates the energy release rate ERR in the X direction of the LSI chip model 13. “G-2 (Y direction)” indicates the energy release rate ERR in the Y direction of the LSI chip model 13. “G-3 (Z direction)” indicates the energy release rate ERR in the Z direction of the LSI chip model 13. The X direction, the Y direction, and the Z direction correspond to the directions shown in FIG.

“G-1 (X direction)” of “Model 1” can be obtained as follows, for example.
If u1x = −0.0088311 and u2x = −0.0088309, then ΔUx = 2.00E-07.

When the reaction force F = −9.25E-06, the crack closing energy E (= ΔUx × F / 2) = 2.00E−07 × (−9.25E-06) /2=−9.25E-13 Become.
Further, if the mesh length R is 0.002690315, the crack area S is 2.27E-05.

Therefore, “G-1 (X direction)” of “Model 1” is | E / (R × S) | = | −1.5113E−05 | = 1.5113E−05.
Similarly, “G-2 (Y direction)” of “Model 1” is 1.5521E-05. “G-3 (Z direction)” of “Model 1” is 5.9757E-05.

Therefore, the energy release rate ERR of “Model 1” is 1.5113E−05 + 1.5521E−05 + 5.9757E−05 = 6.00063E−03.
Similarly, the energy release rate ERR of “Model 2” is 1.0080E-03 + 1.0452E-03 + 1.5956E-02 = 1.810E-02. The energy release rate ERR of “Model 3” is 3.8936E-03 + 3.9597E-03 + 2.2893E-02 = 3.0747E-02.

Next, the entire process of the semiconductor design apparatus 100 will be described.
<Overall processing>
FIG. 16 is a flowchart showing the overall processing of the semiconductor design apparatus.

[Step S <b> 1] The finite element overall analysis unit 120 executes finite element analysis based on the overall structural analysis model stored in the finite element analysis model DB 110.
When the process transitions from step S4 or step S13, the finite element overall analysis unit 120 executes finite element analysis based on the provisionally created overall structure analysis model.

  [Step S <b> 2] The determination unit 150 calculates a predicted peeling occurrence value Y on the center coordinates of each solder joint. Then, the quality of the entire structural analysis model is determined based on the calculated predicted value.

  [Step S3] As a result of the determination, if it is determined “No” for the wiring layer on the center coordinates of at least one solder joint (No in Step S3), the process proceeds to Step S4. When it is determined that the wiring layer on the center coordinates of all the solder joints is “good” (Yes in step S3), the process proceeds to step S5.

  [Step S4] The determination unit 150 extracts candidate point coordinates. Then, an overall structural analysis model in which solder bumps are arranged and moved to the extracted candidate point coordinates is created. Thereafter, the process proceeds to step S1.

  [Step S5] The LSI detailed model placement unit 170 moves the center coordinates input by the user of the detailed analysis model to the center coordinates of the solder joint determined by the determination unit 150 that the maximum stress is generated. Then, the process proceeds to step S6.

  [Step S6] The finite element detailed analysis unit 180 creates a cracked analysis mesh model by separating the center one node between wiring layers where separation is predicted in the vertical direction. Then, the process proceeds to step S7.

[Step S7] The finite element detailed analysis unit 180 calculates the crack area S of the cracked analysis mesh model. Thereafter, the process proceeds to operation S8.
[Step S8] The displacement extraction unit 190 extracts a displacement difference (displacement difference ΔU) between the nodes 132 and 133 of the mesh model. Thereafter, the process proceeds to operation S9.

  [Step S9] When the displacement difference ΔU is extracted by the displacement extraction unit 190, the finite element detailed analysis unit 200 cancels the displacement difference ΔU and extracts the reaction force F that equalizes the displacements of both nodes from the finite element analysis result. To do. Then, the process proceeds to step S10.

  [Step S <b> 10] The energy release rate calculation unit 210 calculates the crack closing energy E using the displacement difference ΔU obtained from the displacement extraction unit 190 and the reaction force F obtained from the finite element detailed analysis unit 200. Then, the energy release rate calculation unit 210 calculates the energy release rate ERR by dividing the crack closing energy E obtained by the calculation by the crack area S acquired from the finite element detailed analysis unit 200. Then, the process proceeds to step S11.

  [Step S11] The determination unit 220 substitutes the energy release rate ERR obtained by the energy release rate calculation unit 210 into the graph 143, and determines whether the overall structure analysis model is acceptable.

  [Step S12] As a result of the determination, if the entire structural analysis model is determined as “No” (No in Step S12), the process proceeds to Step S13. When it is determined that the overall structural analysis model is “good” (Yes in step S12), the process proceeds to step S14.

[Step S13] The determination unit 220 creates an overall structural analysis model in which the solder bumps are arranged and moved to the candidate point coordinates. Thereafter, the process proceeds to step S1.
[Step S14] The result output unit 230 digitizes and graphs the transferred energy release rate ERR and displays it on the monitor 104a. Thereafter, the entire process is terminated.

This is the end of the description of the entire process.
<Judgment process>
Next, the process of the determination unit 150 (first determination process) will be described in detail.

FIG. 17 is a flowchart showing the first determination process.
[Step S <b> 21] The determination unit 150 acquires the LSI chip maximum principal stress and the LSI chip Z direction stress analyzed by the finite element overall analysis unit 120. Also, constants A, B, and C obtained by regression analysis with the actual peeling occurrence rate are acquired. Thereafter, the process proceeds to operation S22.

[Step S22] The determination unit 150 substitutes the acquired stresses and the constants A, B, and C into the equation (1) to calculate the predicted occurrence rate of peeling Y. Thereafter, the process proceeds to operation S23.
[Step S <b> 23] The determination unit 150 determines whether or not the calculated peeling occurrence rate prediction value Y is equal to or less than a predetermined allowable value P <b> 1. When the peeling occurrence rate prediction value Y is equal to or less than the allowable value P1 (Yes in step S23), the process proceeds to step S24. When the peeling occurrence rate prediction value Y is larger than the allowable value P1 (No in Step S23), the process proceeds to Step S25.

  [Step S24] The determination unit 150 obtains the coordinates of the solder joint that has the highest possibility of peeling from Equation (1), that is, the coordinates of the solder joint where the maximum stress occurs, and obtains the obtained coordinates. Transfer to the LSI detailed model placement unit 170. Thereafter, the first determination process is terminated.

  [Step S25] The determination unit 150 determines whether there is a candidate point coordinate in response to the input of the candidate point coordinate by the user. When the candidate point coordinates exist (Yes in step S25), the process proceeds to step S26. If there is no candidate point coordinate (No in step S25), the process proceeds to step S30.

  [Step S <b> 26] The determination unit 150 calculates the LSI chip maximum principal stress and the LSI chip Z-direction stress at the candidate point coordinates by approximating them from the analysis result of the entire finite element analysis unit 120. When there are a plurality of candidate point coordinates, the LSI chip maximum principal stress and the LSI chip Z direction stress at each candidate point coordinate are calculated. Thereafter, the process proceeds to operation S27.

  [Step S27] The determination unit 150 substitutes the calculated stresses and the constants A, B, and C into the equation (1) to calculate the predicted occurrence rate of peeling Y. When there are a plurality of candidate point coordinates, a peeling occurrence rate prediction value Y at each candidate point coordinate is calculated. Then, the process proceeds to step S28.

  [Step S28] When there is one candidate point coordinate, the determination unit 150 determines the candidate point coordinate as a solder bump arrangement position candidate. If there are a plurality of candidate point coordinates, the candidate point coordinate having the smallest peeling occurrence rate predicted value Y is determined as a solder bump arrangement position candidate. Thereafter, the process proceeds to operation S29.

  [Step S29] The determination unit 150 creates an overall structural analysis model in which the solder bump placement position is placed and moved to the solder bump placement position candidate determined in step S28. Then, the created whole structure analysis model is sent to the finite element whole analysis unit 120. Thereafter, the first determination process is terminated.

[Step S30] The determination unit 150 outputs an error to the monitor 104a. Thereafter, the first determination process is terminated.
This is the end of the description of the first determination process.

Next, the process (second determination process) of the determination unit 220 will be described.
FIG. 18 is a flowchart showing the second determination process.
[Step S31] The determination unit 220 acquires the energy release rate ERR calculated by the energy release rate calculation unit 210. Thereafter, the process proceeds to operation S32.

  [Step S32] The determination unit 220 substitutes the acquired energy release rate ERR into the graph 143 shown in FIG. Thereafter, the process proceeds to operation S33.

  [Step S <b> 33] The determination unit 220 determines whether the acquired peeling occurrence rate is equal to or less than the allowable value P <b> 2. When the peeling occurrence rate is equal to or less than the allowable value P2 (Yes in step S33), the process proceeds to step S34. When the peeling occurrence rate is larger than the allowable value P2 (No in step S33), the process proceeds to step S35.

[Step S <b> 34] The determination unit 220 transfers the determined energy release rate ERR to the result output unit 230. Thereafter, the second determination process is terminated.
[Step S35] The determination unit 220 determines whether there is a candidate point coordinate. If the candidate point coordinates exist (Yes in step S35), the process proceeds to step S36. When there is no candidate point coordinate (No in step S35), the process proceeds to step S38.

[Step S36] The determination unit 220 determines a solder bump placement position candidate. Thereafter, the process proceeds to operation S37.
[Step S37] The determination unit 220 creates an overall structural analysis model in which solder bumps are arranged and moved to the decided arrangement position candidates. Then, the created whole structure analysis model is sent to the finite element whole analysis unit 120. Thereafter, the second determination process is terminated.

[Step S38] The determination unit 220 outputs an error to the monitor 104a. Thereafter, the second determination process is terminated.
This is the end of the description of the second determination process.

<How to obtain the predicted peeling rate Y>
Next, the process (calculation process) for calculating the predicted peeling occurrence rate Y will be described in detail.
FIG. 19 is a flowchart showing a process for calculating a predicted peeling occurrence rate.

  [Step S <b> 2 a] The determination unit 150 extracts candidates that are obtained by finite element analysis with factors that are thought to directly or indirectly affect the separation occurrence rate. If you are not sure whether it affects or not, for the time being, include all of them in the candidate factor.

Specific examples of these influencing factors include (a) to (d) described above.
[Step S2b] A linear multiple regression analysis is performed using each factor extracted in Step S2a as an explanatory variable, and using a peeling occurrence rate obtained from an experiment, actual measurement, or the like as an explanatory variable. In addition, about the procedure after step S2b, it follows the procedure of the general multiple regression analysis (reference example: “Science of data”, Koji Kurihara (Author), Hodai University teaching materials; 89193-1-0111, ISBN4 -595-89193-8 C1341, PP.103-106).

Specifically, regression equation (2) where X1, X2, X3,..., Xk are explanatory variables, and the actually measured peeling occurrence rate is an explained variable Y.
Y = β0 + β1 · X1 + β2 · X2 + β3 · X3 + ··· + βk · Xk (2)
Here, β0, β1, β2, β3,..., Βk are coefficients corresponding to k variables.

And the regression coefficient of β0 to βn is determined by the least square method.
The regression coefficient is determined so that a predicted value (Y (X) −Yi) squared sum (residual sum of squares)) of the regression equation is minimized.

  For example, when the explanatory variable is one variable, the regression equation (2) is Y = β0 + β1 · X1, and the regression coefficients β0 and β1 are calculated by the following equations (3) and (4), respectively.

  Here, n is the number of samples of actual measurement data, yi (= Yi) is the i-th actual measurement data (peeling occurrence rate), and xi (= Xi) is an explanatory variable (simulation of simulation) corresponding to the actual measurement data. Stress, etc.). In the case of a general k variable, Y is displayed as a vector and X is displayed as a matrix, and the following equations (5) to (8)

The estimated value β of each coefficient vector can be calculated from the following equation (9) using the value obtained from:

  [Step S2c] The t value of each explanatory variable is calculated from each coefficient estimated value βi obtained in Step S2b. The t value is calculated from the standard error SE (βi) of each explanatory variable and each coefficient estimated value βi.

  Standard error SE (βi) and t value are calculated by the following equations (10) and (11), respectively.

Here, Cii is an i row i column component of the matrix (XTX) ⁻¹ .
[Step S2d] It is determined whether to exclude or adopt a variable based on the t value. Specifically, when the t value calculated in step S2c is smaller than a certain value, this variable is excluded from the prediction formula. In general, a t distribution function t (α / 2, nk−1) (α is generally 5% (= 0.05)) is used as the reference value. That is,
If | t value i |> t (α / 2, nk−1) (Yes in step S2d), the variable is valid. If | t value i | ≦ (α / 2, n−k−1) (No in step S2d), the variable is excluded.

Further, in the above-described determination formula, when even an originally valid variable is excluded, it is possible to determine simply by empirically setting a certain threshold value. In other words, an empirical threshold is T (for example, T = 0.8),
If | t value i |> T, the variable may be valid, and if | t value i | ≦ T, the variable may be excluded.

  [Step S2e] When there is a variable excluded in step S2d, the process proceeds to step S2b, and the processes in steps S2b to S2d are repeated. This is because when each variable is increased or decreased, the other coefficients and t values also change.

This is the end of the description of the process for calculating the peeling occurrence rate prediction value Y.
As described above, according to the semiconductor design apparatus 100, the energy release rate can be calculated using the finite element analysis program without using a special program by performing the processing of the energy release rate calculation unit 210. . Accordingly, it is possible to facilitate calculation of the wiring layer peeling prediction. In addition, the occurrence of peeling of the wiring layer can be predicted at a low cost.

Further, by performing the processing of the determination unit 150, it is possible to perform highly accurate reliability evaluation.
Specifically, delamination of LSI chips is based on the solder bump layout design, delamination stress generated by the overall thermal stress such as chip dimensions and process temperature conditions, and the strength of adhesion between micro layers (adhesion strength). ) And is determined comprehensively. For this reason, it does not necessarily occur in a place where the entire equivalent stress is large. For this reason, even if the maximum equivalent stress of the chip is obtained by stress analysis using a single stress, it is difficult to determine whether or not delamination has occurred.

  However, according to the semiconductor design apparatus 100, it is possible to evaluate the reliability with higher accuracy than the conventional stress evaluation by evaluating the entire structural analysis model using the above formula (1). .

  For this reason, it is very useful in designing the layout of solder bumps of an LSI chip and determining manufacturing process temperature conditions. In addition, when there is a concern about the occurrence of peeling, it is possible to consider in advance how to avoid it.

Therefore, the product yield is improved, and high-quality products can be mass-produced.
In the present embodiment, the semiconductor design device 100 is configured to include the finite element analysis model DB 110, the evaluation DB 130, the solder bump layout information DB 140, and the detailed analysis model DB 160. Any one or a plurality of DBs may be provided outside the semiconductor design apparatus 100.

  Further, the processing performed by the semiconductor design device 100 may be distributedly processed by a plurality of devices. For example, one device performs processing up to the determination unit 150 to obtain the coordinates of the joint where the maximum stress is generated, and the other device calculates the energy release rate using the coordinates, and the result May be output.

  The semiconductor design program, the semiconductor design method, and the semiconductor design apparatus of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each part has the same function. Can be replaced with any structure having Moreover, other arbitrary structures and processes may be added to the present invention.

In addition, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions of the semiconductor design apparatuses 1 and 100 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic recording device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic recording device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Examples of the optical disc include a DVD, a DVD-RAM, a CD-ROM, and a CD-R / RW. Examples of the magneto-optical recording medium include MO.

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  A computer that executes a semiconductor design program stores, for example, a program recorded on a portable recording medium or a program transferred from a server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

Regarding the above first to second embodiments, the following additional notes are further disclosed.
(Supplementary Note 1) In a semiconductor design program for predicting the occurrence of delamination between wiring layers of a semiconductor integrated circuit,
On the computer,
An energy calculation procedure for calculating energy for closing a crack generated by virtually peeling the wiring layer of the measurement target portion of the circuit model obtained by modeling the semiconductor integrated circuit to be designed;
Conversion procedure for converting the energy calculated by the energy calculation procedure into energy per unit area of the crack,
A semiconductor design program for executing

(Appendix 2) In addition to the computer,
The probability of delamination between the wiring layers according to the relationship between a plurality of stresses acting on the circuit model is calculated for each joint between the solder bump of the circuit model and the wiring layer to determine whether the circuit model is good or bad The semiconductor design program according to appendix 1, wherein a determination procedure for determining the measurement target part is executed based on a determination result.

  (Supplementary note 3) The semiconductor according to supplementary note 2, wherein, in the determination procedure, the probability is calculated based on a relational expression in which each of the plurality of stresses is an independent variable and the probability of occurrence of peeling is a dependent variable. Design program.

(Supplementary note 4) The semiconductor design program according to supplementary note 2, wherein the plurality of stresses include a maximum principal stress of the circuit model and a stress in a stacking direction of the circuit model.
(Additional remark 5) In the said determination procedure, when the said junction part whose probability that peeling will generate | occur | produce between the said wiring layers exists more than predetermined value exists, the said circuit model which changed the arrangement | positioning location of the said solder bump was created, and the said created The semiconductor design program according to appendix 2, wherein the probability is calculated again for the circuit model.

(Appendix 6) In addition to the computer,
Create a mesh model in which a part of the wiring layer of the measurement target part is divided into a grid, and execute a model creation procedure for creating a crack by peeling one node of the mesh,
The semiconductor according to claim 1, wherein in the conversion procedure, the area of a circle whose radius is one side of the mesh is regarded as the total area of the crack, and the energy is converted into energy per unit area of the crack. Design program.

(Appendix 7) In addition to the computer,
A prediction procedure for predicting the peel strength between the wiring layers based on the energy per unit area of the crack converted by the conversion procedure;
The semiconductor design program according to appendix 1, wherein the program is executed.

(Supplementary Note 8) In a semiconductor design method for predicting the occurrence of peeling between wiring layers of a semiconductor integrated circuit,
Computer
In the circuit model obtained by modeling the semiconductor integrated circuit to be designed, the energy for closing the crack generated by virtually peeling the wiring layer of the measurement target part is calculated,
The calculated energy is converted into energy per unit area of the crack.
A semiconductor design method.

(Supplementary Note 9) In a semiconductor design apparatus for predicting occurrence of peeling between wiring layers of a semiconductor integrated circuit,
An energy calculation unit that calculates energy for closing a crack generated by virtually peeling the wiring layer of the measurement target portion of the circuit model obtained by modeling the semiconductor integrated circuit to be designed;
A conversion unit that converts the energy calculated by the energy calculation unit into energy per unit area of the crack;
A semiconductor design apparatus comprising:

(Supplementary Note 10) a substrate;
A semiconductor integrated circuit disposed on the substrate;
An underfill filled in the semiconductor integrated circuit;
Solder bumps regularly arranged between the substrate and the semiconductor integrated circuit so that the density of the portion adjacent to the outermost peripheral portion of the semiconductor integrated circuit is larger than the density of the outermost peripheral portion. When,
A semiconductor device comprising:

(Supplementary Note 11) a substrate;
A semiconductor integrated circuit disposed on the substrate;
Solder bumps regularly arranged between the substrate and the semiconductor integrated circuit so that the density of the arrangement of the central part of the side of the semiconductor integrated circuit is smaller than the density of the arrangement other than the central part;
A semiconductor device comprising:

(Supplementary Note 12) In a semiconductor design program for predicting the occurrence of delamination between wiring layers of a semiconductor integrated circuit,
On the computer,
The probability of delamination between the wiring layers is calculated for each part where the solder bumps of the circuit model are arranged according to the relationship between a plurality of stresses acting on the circuit model that models the semiconductor integrated circuit to be designed. , A determination procedure for determining the quality of the circuit model,
Based on the determination result in the determination procedure, a prediction procedure for determining the wiring layer of the measurement target part and predicting the peel strength between the determined wiring layers,
A semiconductor design program for executing

DESCRIPTION OF SYMBOLS 1,100 Semiconductor design apparatus 2 Stress distribution calculation part 3 Judgment part 4 Detailed analysis model creation part 5 Energy release rate calculation part 5a Energy calculation part 5b Conversion part 6 Judgment part 7 Output part 10 Whole structure analysis model 10a Detailed analysis model 11, 11a Substrate model 12, 12a Solder bump model 12b Central axis 13, 13a LSI chip model 13b, 13c Wiring layer model 131, 132, 133 Node 134 Crack 15 Mesh model 110 Finite element analysis model DB
120 Total Finite Element Analysis Unit 130 Evaluation DB
140 Solder bump layout information DB
150, 220 determination unit 160 Detailed analysis model DB
170 LSI Detailed Model Placement Unit 180, 200 Finite Element Detailed Analysis Unit 190 Displacement Extraction Unit 210 Energy Release Rate Calculation Unit 230 Result Output Unit

Claims (6)

In a semiconductor design program that predicts the occurrence of delamination between wiring layers of a semiconductor integrated circuit,
On the computer,
An energy calculation procedure for calculating energy for closing a crack generated by virtually peeling the wiring layer of the measurement target portion of the circuit model obtained by modeling the semiconductor integrated circuit to be designed;
Conversion procedure for converting the energy calculated by the energy calculation procedure into energy per unit area of the crack,
A semiconductor design program for executing In addition to the computer,
The probability of delamination between the wiring layers according to the relationship between a plurality of stresses acting on the circuit model is calculated for each joint between the solder bump of the circuit model and the wiring layer to determine whether the circuit model is good or bad The semiconductor design program according to claim 1, wherein a determination procedure for determining the measurement target part is executed based on a determination result.   3. The semiconductor design program according to claim 2, wherein in the determination procedure, the probability is calculated based on a relational expression in which the plurality of stresses are independent variables and the probability of occurrence of peeling is a dependent variable.   In the determination procedure, when the joint having a probability of occurrence of delamination between the wiring layers is greater than or equal to a predetermined value, the circuit model in which the placement location of the solder bump is changed is created, and the created circuit model is again created. 3. The semiconductor design program according to claim 2, wherein the probability is calculated. In a semiconductor design method for predicting the occurrence of delamination between wiring layers of a semiconductor integrated circuit,
Computer
In the circuit model obtained by modeling the semiconductor integrated circuit to be designed, the energy for closing the crack generated by virtually peeling the wiring layer of the measurement target part is calculated,
The calculated energy is converted into energy per unit area of the crack.
A semiconductor design method. In a semiconductor design apparatus that predicts the occurrence of delamination between wiring layers of a semiconductor integrated circuit,
An energy calculation unit that calculates energy for closing a crack generated by virtually peeling the wiring layer of the measurement target portion of the circuit model obtained by modeling the semiconductor integrated circuit to be designed;
A conversion unit that converts the energy calculated by the energy calculation unit into energy per unit area of the crack;
A semiconductor design apparatus comprising:

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