JP2011204007A - Apparatus, method and program for designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a semiconductor integrated circuit that meets standards, while reducing the burden on a designer.SOLUTION: A method for designing a semiconductor integrated circuit includes a generation process for generating a bias check definition matching a circuit simulator used, by referring to a format file storing the format of the bias check definition of each circuit simulator, a device rated value information file storing the rated value information of each device, and a model file storing the terminal information of each device model; a verification process for verifying whether or not there is any device violating standards, by inputting the net list including the bias check definition to the circuit simulator; and an extraction process for, when a device violating the standards exists, extracting alternative candidates for the device from among devices included in the device rated value information file.

Description

  The present invention relates to a semiconductor integrated circuit design apparatus, a semiconductor integrated circuit design method, and a program, and more particularly to a semiconductor integrated circuit design method and program for designing a semiconductor integrated circuit that satisfies a rating using a circuit simulator.

  In circuit design, various technology nodes are used, and a single technology node includes many devices. Therefore, it has become difficult to grasp the rated value (for example, rated voltage, rated current, etc.) of each device.

  For example, when creating a circuit diagram, a low-voltage device that is not rated may be used in the circuit diagram of a high-voltage circuit block. Such an error needs to be prevented at the circuit design stage.

  As a method of preventing such an error, there is a method of using a circuit check function (hereinafter referred to as “BiasCheck”) of a commercially available circuit simulator. In order to use BiasCheck, it is necessary to check the rated voltage and current of the device used and to describe a predetermined definition (hereinafter referred to as “BiasCheck definition”) in accordance with the specifications of the circuit simulator to be applied in the netlist.

  A commercially available circuit simulator has a function of outputting a report when the rated voltage / current of each model is exceeded by adding a BiasCheck definition to the netlist. The designer detects the device used in the circuit and uses the BiasCheck by describing the BiasCheck definition according to the format of the circuit simulator to be used.

  FIG. 16 is a flowchart showing a conventional semiconductor integrated circuit design method. Referring to FIG. 16, first, a circuit diagram is generated (step S101) and stored as a SPICE netlist F101.

  Next, the designer manually edits the SPICE netlist F101 while referring to the SPICE netlist F101, the device rated value information file F102, the manual F103 of each simulator, and the terminal information file F104 of each SUBCKT model. (Step S102), a SPICE netlist F105 including a BiasCheck definition is created.

  A circuit simulation is performed using the created BiasCheck-defined SPICE netlist F105 as an input to the circuit simulator (step S103), and a BiasCheck result F106 is obtained.

  According to the conventional semiconductor integrated circuit design method, in order to obtain a BiasCheck result, each designer refers to the SPICE netlist F101, detects a device used in the circuit from the circuit diagram or the netlist, It is necessary to check the rated voltage / current value of each device by referring to the device rated value information file F102, and to understand and describe the syntax of the BiasCheck definition for each circuit simulator by referring to the manual F103 of each simulator. is there. Further, in recent years, a SUBCKT (subcircuit) type model that takes parasitics into account is generally used, and therefore the designer refers to the terminal information file F104 of each SUBCKT model, and SUBCKT has a format different from that of a normal device. It is also necessary to check and specify the terminal name of the sentence.

  FIG. 17 is a diagram illustrating a BiasCheck definition of a conventional circuit simulator. FIG. 17 shows the BiasCheck definition for the circuit simulator A and the circuit simulator B.

  Referring to the BiasCheck definition for the circuit simulator A shown in FIG. 17, the BiasCheck definition includes an identifier “subckt =“ device name ”” for identifying a device in the SUBCKT format, and “diff =“ V ( pin1) −V (pin2) ″ ”and“ max = “xx” min = “xx” ”” representing the rated value between these terminals. Similarly, referring to the BiasCheck definition for the circuit simulator B shown in FIG. 17, the BiasCheck definition includes an identifier “model =“ device name ”” for identifying a device and “term1 =“ pin1 ”representing terminal information. “term2 =“ pin2 ”” and “max =“ xx ”min =“ xx ”” representing the rated value between these terminals are included. As shown in FIG. 17, the format of the BiasCheck definition is generally different for each vendor and for each simulator.

  Patent Document 1 describes an apparatus for determining the presence or absence of a rating violation with reference to a rating value information file including rating information of elements and a simulation result file storing simulation results.

JP 09-093120 A

  The following analysis was made by the present inventors.

  Since the BiasCheck function of a commercially available circuit simulator only detects a device that is used outside the rating, the designer needs to examine a solution for violation of the rated value by himself / herself.

  The apparatus described in Patent Document 1 also only determines the presence / absence of a device that violates the rating, and does not show the designer how to resolve the rating violation. Therefore, it is necessary for the designer to review the circuit diagram together with the BiasCheck result to check whether there is an error in the selection of the device to be used, which requires a lot of labor and time.

  In addition, according to the conventional semiconductor integrated circuit design method, much time and labor are consumed to describe the BiasCheck definition (see FIG. 17), and there is a risk of setting omission or setting error.

  Therefore, it becomes an issue to be able to design a semiconductor integrated circuit that satisfies the rating while reducing the burden on the designer. An object of the present invention is to provide a semiconductor integrated circuit design apparatus, a semiconductor integrated circuit design method, and a program for solving such a problem.

A semiconductor integrated circuit design apparatus according to a first aspect of the present invention includes:
Refer to and use the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. A bias check definition generation unit that generates a bias check definition according to the circuit simulator;
A bias check unit that inputs a netlist including the bias check definition into a circuit simulator and verifies the presence or absence of a device that violates the rating;
An alternative device extraction unit that extracts an alternative candidate for the device from the devices included in the device rating value information file when a device that violates the rating exists;

A semiconductor integrated circuit design method according to a second aspect of the present invention includes:
The computer references the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. A generation process for generating a bias check definition according to the circuit simulator to be used;
A netlist including the bias check definition is input to a circuit simulator, and a verification process for verifying the presence or absence of a device that violates the rating;
An extraction step of extracting an alternative candidate for the device from the devices included in the device rating value information file when there is a device that violates the rating.

The program according to the third aspect of the present invention is:
Refer to and use the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. Generation processing to generate bias check definition according to the circuit simulator,
A verification process for inputting a netlist including the bias check definition into a circuit simulator and verifying the presence or absence of a device that violates the rating;
When there is a device that violates the rating, the computer is caused to execute an extraction process for extracting an alternative candidate for the device from the devices included in the device rating value information file.

  According to the semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method, and program according to the present invention, it is possible to design a semiconductor integrated circuit that satisfies the rating while reducing the burden on the designer.

1 is a block diagram schematically showing a configuration of an apparatus for realizing a semiconductor integrated circuit design method according to a first embodiment of the present invention. 2 is a flowchart showing a semiconductor integrated circuit design method according to the first embodiment of the present invention. It is a figure which shows GUI (Graphic User Interface) for BiasCheck definition file creation as an example. It is a figure which shows a format file as an example. It is a figure which shows the keyword used in a format file as an example. It is a figure which shows a SPICE model file as an example. It is a figure which shows the BiasCheck definition file after reading the terminal information of a SPICE model file as an example. It is a figure which shows a device rating value information file as an example. It is a figure which shows the BiasCheck definition file after reading the rating information of a device rating value information file as an example. It is a figure which shows a BiasCheck definition as an example. It is a figure which shows a BiasCheck result as an example. It is a figure which shows a device rating value information file as an example. It is a figure which shows the BiasCheck definition before and behind as an example. It is a figure which shows the display in the case of rating violation as an example. It is a block diagram which shows the structure of the semiconductor integrated circuit design apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows the conventional semiconductor integrated circuit design method. It is a figure which illustrates the BiasCheck definition of the conventional circuit simulator.

  According to a first development form of the present invention, there is provided a semiconductor integrated circuit design apparatus according to the first aspect.

  According to a second development of the present invention, there is provided the semiconductor integrated circuit design apparatus, wherein the bias check definition includes a device identifier, terminal information of the device, and rated value information of the device.

  According to the third development form of the present invention, the bias check definition generation unit outputs the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file to the terminal for each device included in the model file. Provided is a semiconductor integrated circuit design apparatus that replaces the rated value information included in the format with the rated value information for each device included in the rated value information file, while replacing the rated value information included in the format.

  According to the fourth development mode of the present invention, the alternative device extraction unit converts the rating value information for the first device in the bias check definition into the rating value information for the second device included in the device rating value information file. The netlist including the bias check definition after replacement is input to the circuit simulator, the presence or absence of a device that violates the rating is verified, and if the rating violation is resolved, the second device is There is provided a semiconductor integrated circuit design apparatus that extracts an alternative candidate for one device.

  According to a fifth development of the present invention, there is provided the semiconductor integrated circuit design apparatus, wherein the model is a SPICE model and the model file is a SPICE model file.

  According to a sixth development of the present invention, there is provided the semiconductor integrated circuit design apparatus, wherein the model is a SPICE model in a SUBCKT format, and the model file is a SPICE model file in a SUBCKT format.

  According to a seventh development of the present invention, the device is a MOS device or a CAP device, and the rating information includes a rated value of a voltage applied between two terminals of the MOS device or the CAP device. A semiconductor integrated circuit design apparatus is provided.

  According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit design method according to the second aspect.

  According to a ninth development of the present invention, there is provided the semiconductor integrated circuit design method, wherein the bias check definition includes a device identifier, terminal information of the device, and rated value information of the device.

  According to the tenth development form of the present invention, in the generation step, the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file is replaced with the terminal information for each device included in the model file. In addition, a semiconductor integrated circuit design method is provided in which the rating value information included in the format is replaced with the rating value information for each device included in the rating value information file.

  According to the eleventh development mode of the present invention, in the extraction step, the rating value information for the first device in the bias check definition is replaced with rating value information for the second device included in the device rating value information file. Then, a net list including the bias check definition after replacement is input to the circuit simulator to verify whether there is a device that violates the rating, and when the rating violation is resolved, the second device is set to the first device. A method for designing a semiconductor integrated circuit, which is extracted as an alternative candidate for a device, is provided.

  According to a twelfth development form of the present invention, a program according to the third aspect is provided.

  According to a thirteenth development of the present invention, there is provided a program in which the bias check definition includes a device identifier, terminal information of the device, and rated value information of the device.

  According to the fourteenth development form of the present invention, in the generation process, the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file is replaced with the terminal information for each device included in the model file. In addition, a program is provided that replaces the rating value information included in the format with rating value information for each device included in the rating value information file.

  According to the fifteenth development mode of the present invention, in the extraction process, the rating value information for the first device in the bias check definition is replaced with the rating value information for the second device included in the device rating value information file. Then, a net list including the bias check definition after replacement is input to the circuit simulator to verify whether there is a device that violates the rating, and when the rating violation is resolved, the second device is set to the first device. A program is provided that is extracted as an alternative candidate for a device.

  According to the semiconductor integrated circuit design apparatus, the semiconductor integrated circuit design method, and the program of the present invention, the BiasCheck definition is automatically generated, and it is possible to save the designer from manually creating the BiasCheck definition. Further, according to the semiconductor integrated circuit design method and program of the present invention, when a rating violation is detected by the circuit simulator BiasCheck, a solution is presented to the designer. Therefore, according to the semiconductor integrated circuit design apparatus, semiconductor integrated circuit design method, and program of the present invention, it is possible to design a semiconductor integrated circuit that satisfies the rating while reducing the burden on the designer.

(Embodiment 1)
A semiconductor integrated circuit design method according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram schematically showing the configuration of an apparatus for realizing the semiconductor integrated circuit design method according to the present embodiment.

  Referring to FIG. 1, the apparatus includes an arithmetic processing unit 1, display units 2, 9, 10, an operation unit 3, and recording media 4 to 8.

  The display unit 2 provides a GUI (Graphical User Interface) for creating a BiasCheck definition file. The operation unit 3 specifies a circuit simulator to be used and a recording medium to be input / output.

  The recording medium 4 stores format information of a commercially available circuit simulator. The recording medium 5 stores voltage / current value rating information of each device. The recording medium 6 stores the SUBCKT name of the SPICE model and its terminal information. The recording medium 7 includes device information used in the circuit.

  The display unit 2 and the operation unit 3 input the recording media 4 to 7 to the arithmetic processing unit 1 to generate the BiasCheck definition file 8 corresponding to the circuit simulator designated by the operation unit 3, and the recording medium 5 and the recording medium 7. Are displayed on the display unit 9 to confirm that there is no definition of the device used in the circuit. Further, when a violation is detected in the device rating check result by the commercially available circuit simulator, a device replacement candidate is displayed on the display unit 10.

  FIG. 2 is a flowchart of the semiconductor integrated circuit design method according to the present embodiment.

  Referring to FIG. 2, first, a circuit diagram is created (step S1). Next, the SPICE netlist F5 including the BiasCheck definition is automatically generated based on the input made by the designer via the GUI for creating the BiasCheck definition file (step S2). The designer designates a circuit simulator to be used, a format file F1, a SPICE model file F2, and a device rating value information file F3 via the GUI.

  FIG. 3 is a diagram illustrating a GUI for creating a BiasCheck definition file as an example.

  In FIG. 3, a circuit simulator name to be used (for example, Simulator-A, Simulator-B, Simulator-C) is designated in the “Simulator Name” column. In the “Format File” column, a format file F1 described later is designated. In the “Device Check File” column, a device rating value information file F3 described later is designated. In the “SPICE Model File” column, a SPICE model file F2 to be described later is designated.

  FIG. 4 is a diagram illustrating the format file F1 as an example.

  Referring to FIG. 4, as an example, the format file F1 includes a format of a BiasCheck definition in the circuit simulators Simulator-A, Simulator-B, and Simulator-C. In the format file F1 shown in FIG. 4, it is preferable to be able to support the definition format of each circuit simulator by using a predetermined keyword.

  FIG. 5 shows an example of keywords used in the format file F1 shown in FIG. In FIG. 5, keywords for MOS devices and CAP devices are illustrated as examples of elements used for circuit simulation.

  VDSMAX and VDSMIN in FIG. 5 represent the maximum rated voltage (VdsMax) and the minimum rated voltage (VdsMin), respectively, between the drain and source terminals of the MOS device, and VGDMAX and GDMIN are between the gate and drain terminals of the MOS device, respectively. Represents the maximum rated voltage (VgdMax) and the minimum rated voltage (VgdMin). VMAX and VMIN represent the maximum rated voltage (VMax) and the minimum rated voltage (VMin) at both ends of the CAP device, respectively. Further, TERMD and TERMS represent a drain terminal name and a source terminal name of the MOS device, respectively.

  Note that devices for which rated values are set in circuit simulation are not limited to these devices. That is, the format file F1 is a keyword for a resistance element (Resistor), a diode (Diode), a bipolar transistor (Bipolar Transistor), and an inductor (Inductor) in addition to keywords MOS and CAP for MOS devices and CAP devices (Capacitors). As described above, a RESISTOR, DIODE, BIPOLAR, and INDUCTOR may be included.

  FIG. 6 is a diagram illustrating the SPICE model file F2 as an example.

  FIG. 6 shows a SPICE model file F2 in the SUBCKT format as an example. Referring to FIG. 6, terminal information for the MOS device NMOS1 drain terminal, gate terminal, source terminal, and back gate terminal is represented as “DD GG SS BB”. The terminal information is read from the “.SUBCKT” statement in the SPICE model file F2 and specified in the terminal name designation location (for example, “TERMD”, “TERMS” in FIG. 4) of the BiasCheck definition.

  In the following BiasCheck definition example, the terminal name “DD” and the terminal name “SS” corresponding to the SUBCKT name “NMOS1” in the SPICE model file F2 shown in FIG. 6 are automatically read and defined.

  FIG. 7 is a diagram illustrating, as an example, a BiasCheck definition file after the terminal information of the SPICE model file F2 is read.

  FIG. 8 is a diagram illustrating device rating value information F3 as an example. Referring to FIG. 8, device rating information is described according to the type of device. For example, for MOS devices, VdsMax, VdsMin, VgdMax, VgdMin, VgsMax, VgsMin, VgbMax, VgbMin, VbdMax, VbdMin, VbsMax, and VbsMin may be described in this order. Further, for CAP devices, they may be described in the order of VMax and VMin. Referring to FIG. 8, the maximum rated voltage between any two terminals of the MOS device NMOS1 is 1.0, the minimum rated voltage is −1.0, and the maximum rated voltage between any two terminals of the MOS device NMOS2 is 3. 0.0, the minimum rated voltage is -3.0, the maximum rated voltage between the two terminals of the CAP device CAP1 is 1.0, the minimum rated voltage is -1.0, and the maximum between the two terminals of the CAP device CAP2 The rated voltage is 3.0 and the minimum rated voltage is -3.0. Here, the unit of voltage is, for example, volt.

  In the following BiasCheck definition example, the max value and the min value are defined with reference to VdsMax and VdsMin corresponding to the device name in the device rating information file F3 shown in FIG.

  FIG. 9 is a diagram illustrating, as an example, a BiasCheck definition file after reading the rating value information of the device rating value information file F3.

  FIG. 10 is a diagram illustrating a BiasCheck definition for Simulator-A and Simulator-B as an example.

  According to the format of the format file F1 shown in FIG. 4, a BiasCheck definition statement corresponding to each circuit simulator can be automatically generated.

  When the BiasCheck definition is generated as described above (step S2), a SPICE netlist F5 including BiasCheck definition is generated as shown in FIG.

  According to the semiconductor integrated circuit design method of the present embodiment, since the BiasCheck definition is automatically generated, it is possible to save the designer from manually creating the BiasCheck definition.

  Referring to FIG. 2, a circuit simulation is performed with a circuit simulator using the BiasCheck definition-containing SPICE netlist F5 as an input (step S3), and a BiasCheck result F6 is obtained.

  Below, each process of a device replacement candidate detection (step S6), BiasCheck definition update (step S8), and a result display (step S9) is demonstrated in detail.

  First, the presence or absence of a rating violation device is determined from the BiasCheck result F6 (step S5). If there is a rating violation device (Yes in step S5), information on the rating violation device is acquired.

  FIG. 11 is a diagram illustrating the BiasCheck result F6 as an example. Referring to FIG. 11, in the BiasCheck result F6, NMOS1 and CAP1 exist as rating violation devices (Yes in step S5 in FIG. 2). According to FIG. 11, the voltage between the drain and source of the MOS device NMOS1 exceeds the maximum rated voltage 1.0. Further, the voltage across the CAP device CAP1 exceeds the maximum rated voltage 1.0.

  FIG. 12 is a diagram illustrating a device rating value information file F3 as an example. Referring to FIG. 12, the maximum rated voltage between any two terminals of the MOS device NMOS1 is 1.0, the minimum rated voltage is −1.0, and the maximum rated voltage between any two terminals of the MOS device NMOS2 is 3. 0.0, the minimum rated voltage is -3.0, the maximum rated voltage between any two terminals of the MOS device NMOS3 is 5.0, the minimum rated voltage is -5.0, and between the two terminals of the CAP device CAP1 The maximum rated voltage is 1.0, the minimum rated voltage is -1.0, the maximum rated voltage between the two terminals of the CAP device CAP2 is 3.0, and the minimum rated voltage is -3.0.

  Next, a provisional candidate for device replacement is extracted from the device rated value information file F3 (step S6 in FIG. 2). Specifically, a device having a rating value larger than the rating violation value is detected from the device rating value information file F3.

  In the BiasCheck result F6 of FIG. 11, since the drain-source voltage Vds of the device name “NMOS1” exceeds the maximum rated voltage VdsMax value 1.0, the drain-source voltage maximum rated value VdsMax. The devices “NMOS2” and “NMOS3” having 3.0 and 5.0 are provisional candidates for device replacement (Yes in step S7 in FIG. 2). Similarly, the provisional candidate for device replacement of the device name “CAP1” is “CAP2” (Yes in step S7 in FIG. 2).

  Next, according to the provisional candidate for device replacement, it is confirmed whether or not the rating violation is resolved. Based on the rated value information of the provisional candidate for device replacement, the BiasCheck definition part of the SPICE netlist is updated (step S8).

  FIG. 13 is a diagram illustrating an example of the BiasCheck definition before and after the update. When replacing “NMOS1” and “CAP1” with provisional candidates for device replacement “NMOS2” and “CAP2”, the BiasCheck definition is replaced as shown in FIG. 13 (step S8).

  Using the updated BiasCheck definition file, the BiasCheck of the circuit simulator is executed again (step S3).

  If there is a rating violation in the BiasCheck result (Yes in step S5) and there is a provisional candidate for device replacement (Yes in step S7), the processes in steps S3 and S5 to S8 are repeated.

  If there is no rating violation in the BiasCheck result (No in step S5), or if there is no device replacement provisional candidate (No in step S7), the rating violation result / device replacement candidate is displayed (step S9).

  From the BiasCheck result F6 obtained in step S3, the presence / absence of a rating violation and device replacement candidates are displayed as follows (step S9).

  That is, if there is no rating violation from the beginning, it is displayed that there is no violation. On the other hand, if there is a rating violation but the rating violation can be resolved by the device replacement candidate, the device replacement candidate is displayed. Further, when there is a rating violation and there is no provisional device replacement candidate, it is displayed that there is no device replacement candidate.

  FIG. 14 is a diagram illustrating an example of display in the case where a rating violation exists. Referring to FIG. 14, replacement candidate devices for each violation location Inst1 to Inst4 are displayed. Further, it is displayed that there is no replacement candidate for the violation location Inst5.

  According to the semiconductor integrated circuit design method of the present embodiment, if a violation of the rated value is detected by the bias simulator of the circuit simulator, a solution is presented to the designer. That is, a substitute device for a device that has violated the rating value is automatically extracted from the devices included in the device rating value information file.

  As described above, according to the semiconductor integrated circuit design method of the present embodiment, the BiasCheck definition is automatically generated, and it is possible to save the designer from manually creating the BiasCheck definition, and the rating violation is detected by the BiasCheck of the circuit simulator. If so, the solution is presented to the designer. Therefore, according to the semiconductor integrated circuit design method of the present embodiment, a semiconductor integrated circuit that satisfies the rating can be designed while reducing the burden on the designer.

(Embodiment 2)
A semiconductor integrated circuit design apparatus according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 15 is a block diagram showing a configuration of the semiconductor integrated circuit design apparatus 20 of the present embodiment.

  Referring to FIG. 15, the semiconductor integrated circuit design device 20 includes a bias check definition generation unit 21, a bias check unit 22, an alternative device extraction unit 23, and a storage unit 25.

  The storage unit 25 includes a format file F1 (FIG. 4) storing a bias check definition format of each circuit simulator, a device rating value information file F3 (FIG. 8) storing rating value information of each device, A SPICE model file F2 (FIG. 2) storing model terminal information is stored. The bias check definition includes, for example, a device identifier, device terminal information, and device rating information (see FIG. 10).

  The bias check definition generation unit 21 refers to the format file F1, the device rating value information file F3, and the SPICE model file F2, and generates a bias check definition corresponding to the circuit simulator to be used. The bias check definition generation unit 21 replaces the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file F1 with the terminal information for each device included in the SPICE model file F2, and is included in the format. The rating value information may be replaced with rating value information for each device included in the rating value information file F3.

  The bias check unit 22 inputs a net list including a bias check definition to the circuit simulator, and verifies the presence / absence of a device that violates the rating.

  When there is a device that violates the rating, the replacement device extraction unit 23 extracts a replacement candidate for the device from the devices included in the device rating value information file F3 (FIG. 8). The alternative device extraction unit 23 replaces the rated value information for the first device in the bias check definition with the rated value information for the second device included in the device rated value information file, and includes a net list including the bias check definition after the replacement. Is input to the circuit simulator to verify the existence of a device that violates the rating. When the rating violation is resolved, the alternative device extraction unit 23 may extract the second device as an alternative candidate for the first device.

  According to the semiconductor integrated circuit design device 20 of the present embodiment, the BiasCheck definition is automatically generated, and it is possible to save the designer from manually creating the BiasCheck definition, and when the rating violation is detected by the BiasCheck of the circuit simulator The solution is presented to the designer. Therefore, according to the semiconductor integrated circuit design device 20 of the present embodiment, it is possible to design a semiconductor integrated circuit that satisfies the rating while reducing the burden on the designer.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Arithmetic processing part 2 Display part 3 Operation part 4-8 Recording medium 9, 10 Display part 20 Semiconductor integrated circuit design apparatus 21 Bias check definition production | generation part 22 Bias check part 23 Alternative device extraction part 25 Storage part F1 Format file F2 SPICE model Files F3, F102 Device rating information file F5, F105 BiasCheck definition SPICE netlist F6, F106 BiasCheck result F101 SPICE netlist F103 Simulator manual F104 SUBCKT model terminal information file

Claims (15)

Refer to and use the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. A bias check definition generation unit that generates a bias check definition according to the circuit simulator;
A bias check unit that inputs a netlist including the bias check definition into a circuit simulator and verifies the presence or absence of a device that violates the rating;
A semiconductor device, comprising: a replacement device extracting unit that extracts a replacement candidate for the device from devices included in the device rating value information file when a device that violates the rating exists; Integrated circuit design equipment.   2. The semiconductor integrated circuit design apparatus according to claim 1, wherein the bias check definition includes a device identifier, terminal information of the device, and rated value information of the device.   The bias check definition generation unit replaces the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file with the terminal information for each device included in the model file, and the rating included in the format 3. The semiconductor integrated circuit design apparatus according to claim 2, wherein the value information is replaced with rating value information for each device included in the rating value information file.   The alternative device extraction unit replaces the rated value information for the first device in the bias check definition with the rated value information for the second device included in the device rated value information file, and includes the bias check definition after replacement. The netlist is input to the circuit simulator, the presence / absence of a device that violates the rating is verified, and when the rating violation is resolved, the second device is extracted as an alternative candidate for the first device. The semiconductor integrated circuit design apparatus according to claim 1, wherein the apparatus is a semiconductor integrated circuit design apparatus.   5. The semiconductor integrated circuit design device according to claim 1, wherein the model is a SPICE model, and the model file is a SPICE model file. 6.   6. The semiconductor integrated circuit design apparatus according to claim 5, wherein the model is a SPICE model in a SUBCKT format, and the model file is a SPICE model file in a SUBCKT format.   7. The device according to claim 1, wherein the device is a MOS device or a CAP device, and the rating information includes a rated value of a voltage applied between two terminals of the MOS device or the CAP device. The semiconductor integrated circuit design apparatus according to any one of the above. The computer references the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. A generation process for generating a bias check definition according to the circuit simulator to be used;
A netlist including the bias check definition is input to a circuit simulator, and a verification process for verifying the presence or absence of a device that violates the rating;
A method of designing a semiconductor integrated circuit, comprising: extracting an alternative candidate for the device from the devices included in the device rating value information file when there is a device that violates the rating .   9. The semiconductor integrated circuit design method according to claim 8, wherein the bias check definition includes a device identifier, terminal information of the device, and rating value information of the device.   In the generation step, the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file is replaced with the terminal information for each device included in the model file, and the rating value information included in the format is replaced. 10. The method of designing a semiconductor integrated circuit according to claim 9, wherein replacement is performed by rating value information for each device included in the rating value information file.   In the extraction step, the rated value information for the first device in the bias check definition is replaced with the rated value information for the second device included in the device rated value information file, and a netlist including the replaced bias check definition Is input to a circuit simulator, the presence or absence of a device that violates the rating is verified, and when the rating violation is resolved, the second device is extracted as an alternative candidate for the first device. The method of designing a semiconductor integrated circuit according to claim 8. Refer to and use the format file that stores the bias check definition format for each circuit simulator, the device rating information file that stores the rating information for each device, and the model file that stores the pin information for each device model. Generation processing to generate bias check definition according to the circuit simulator,
A verification process for inputting a netlist including the bias check definition into a circuit simulator and verifying the presence or absence of a device that violates the rating;
A program that causes a computer to execute an extraction process for extracting alternative candidates for a device from the devices included in the device rating value information file when a device that violates the rating exists.   The program according to claim 12, wherein the bias check definition includes a device identifier, terminal information of the device, and rated value information of the device.   In the generation process, the terminal information in the format of the bias check definition for the circuit simulator to be used included in the format file is replaced with the terminal information for each device included in the model file, and the rating value information included in the format is replaced. The program according to claim 13, wherein the program is replaced with rating value information for each device included in the rating value information file.   In the extraction process, the rated value information for the first device in the bias check definition is replaced with the rated value information for the second device included in the device rated value information file, and a netlist including the bias check definition after replacement Is input to a circuit simulator, the presence or absence of a device that violates the rating is verified, and when the rating violation is resolved, the second device is extracted as an alternative candidate for the first device. The program according to any one of claims 12 to 14.

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