JP2011203995A - Analysis device, analysis method and analysis program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To analyze the configuration of a sector cache, with accuracy.SOLUTION: An analysis device 20 collects sampling data D1, including the number of accesses and the number of cache misses obtained by sampling, while switching the sector configuration of a cache memory during execution of an application program 11 from a processor 10. The analysis device 20, having acquired the sampling data D1, calculates cache miss ratio, by dividing the number of cache misses by the number of accesses for each sector configuration.

Description

  The present invention relates to an analysis apparatus, an analysis method, and an analysis program.

  Conventionally, in order to increase the memory access speed of the scalar processor, a configuration in which a cache memory is arranged between the processor and the main memory is used.

  Further, in recent years, sector caches have been developed that logically divide a cache memory into a plurality of sectors and specify which sector is used by each memory access instruction to change the cache usage status. The size of the sector of the cache memory can be changed by a program at the time of execution.

  For example, when a 10-way structure cache is divided into sector 0 and sector 1, by designating the maximum number of ways belonging to sector 0 and the maximum number of ways belonging to sector 1, this 10-way can be divided into two sectors. I can do it. There are 9 × 9 = 81 possible combinations in this case, and there are 82 combinations including the case where the sector cache is not used.

  In the scalar processor, the locality of the memory access by the application program affects the performance. Therefore, by dividing the memory access into two groups, the locality of the memory access can be improved and the performance can be improved.

  The sector in which the cache is configured, that is, the sector configuration of the cache greatly affects the performance when the application program is executed. Therefore, it is required to analyze the cache configuration and feed back to the optimal cache configuration for the application program or the application program itself.

JP 2008-90411 A

  In general, the operation of an application is complex, and it is difficult to predict the effect of sector cache on performance. You cannot know which combination of sector caches is the fastest unless you actually measure it.

  For this reason, the static analysis as in the conventional technique cannot sufficiently evaluate the sector cache configuration. Even if the combination of sector caches is fixed during program execution, there are 82 settings, so in the worst case, the application is executed 82 times, the performance of each is compared, and the optimum sector cache configuration is selected. Become.

  The disclosed technique has been made in view of the above, and an object thereof is to improve the accuracy of analysis of the sector cache configuration.

  An analysis apparatus, an analysis method, and an analysis program disclosed in the present application collect sampled data while switching a sector configuration of a cache memory during execution of an application program. The sampled data includes the number of accesses to the cache memory and the number of cache misses. The disclosed apparatus, method, and program calculate the cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration.

  According to the analysis device, analysis method, and analysis program disclosed in the present application disclosed by the present application, the accuracy of the analysis of the sector cache configuration can be increased.

FIG. 1 is a configuration diagram of an analyzer according to an embodiment. FIG. 2 is an explanatory diagram of the sector cache. FIG. 3 is an explanatory diagram of creating a sector cache compatible object program. FIG. 4 is a flowchart for explaining the processing operation according to the present embodiment. FIG. 5 is a flowchart for further explaining sampling by the sampling thread 12 shown in FIG. FIG. 6 is a flowchart for explaining the processing operation of the analyzer 20. FIG. 7 is an explanatory diagram of a specific example of sampling data and result output. FIG. 8 is an explanatory diagram for explaining evaluation of thrashing. FIG. 9 is a flowchart for explaining the processing operation for calculating the thrashing multiplicity. FIG. 10 is a flowchart for explaining sector selection processing during compilation. FIG. 11 is an explanatory diagram of variable shape and use sector determination results. FIG. 12 is an explanatory diagram of the improvement by correcting the program.

  Hereinafter, an analysis apparatus, an analysis method, and an analysis program disclosed in the present application will be described in detail with reference to the drawings. The present invention is not limited to the following specific examples.

[System configuration]
FIG. 1 is a configuration diagram of an analyzer according to an embodiment. In the example illustrated in FIG. 1, the analysis apparatus 20 is connected to the processor 10 and analyzes the sector configuration of the cache memory used by the processor 10 and the application program executed by the processor 10.

  The processor 10 caches a part of the main memory using the L1 (level 1) cache memory and the L2 (level 2) cache memory. A cache memory used by the processor 10 is logically divided into a plurality of sectors, and a sector cache mechanism that can change a cache usage state by designating which sector each memory access instruction uses. Prepare. A cache divided into sectors is called a sector cache.

  The sector size can be changed by a program at the time of execution. Both the L1 cache and the L2 cache can be sector caches. However, in the following description, an example in which a 10-way L2 cache is divided into sectors 0 and 1 will be described.

  When the 10-way L2 cache is divided into sector 0 and sector 1, there are 9 × 9 = 81 possible combinations by designating the maximum number of ways belonging to sector 0 and the maximum number of ways belonging to sector 1. Therefore, 82 cases including the case where the sector cache is not used are included.

  The processor 10 operates the application program by sequentially executing a plurality of application processes 11 constituting the application program. In addition, the processor 10 executes the sampling thread 12 together with the execution of the application process 11. The sampling thread 12 includes a sector configuration changing unit 13 and a sampling processing unit 14.

  The sector configuration changing unit 13 performs a process of switching the sector configuration of the cache memory during execution of the application program, that is, during execution of the application process 11. The sampling processing unit 14 creates and accumulates sampling data D1 by sampling the number of accesses to the cache memory of the application process 11, the number of cache misses, and the number of instructions executed by the application process 11 in association with the sector configuration. .

  The analysis device 20 is a device that acquires the sampling data D1 from the processor 10 and performs analysis. The analysis apparatus 20 includes a data collection unit 21, a cache miss rate calculation unit 22, a selection unit 23, an effectiveness evaluation unit 24, a cache miss rate differentiation processing unit 25, a thrashing multiplicity calculation unit 26, and an output unit 27.

  The data acquisition unit 21 is a processing unit that collects sampling data D1 from the processor 10. The cache miss rate calculation unit 22 divides the number of cache misses of the sampling data D1 by the number of accesses for each sector configuration, and calculates the cache miss rate for each sector configuration.

  The selection unit 23 compares the cache miss rates of the respective sector configurations, and selects a sector configuration having a smaller cache miss rate as compared with other sector configurations as an appropriate sector configuration. The effectiveness evaluation unit 24 obtains the cache access rate of each configuration by dividing the number of accesses by the number of instructions for each sector configuration, and if the relative standard deviation of the cache access rate is less than a predetermined value, the selection result by the selection unit is Evaluate as effective.

  The cache miss rate differential processing unit 25 obtains a differential value with respect to the sector configuration change of the cache miss rate. The thrashing multiplicity calculation unit 26 is a use state calculation unit that calculates a thrashing multiplicity indicating the use state of the cache memory by the application program from a change in the differential value of the cache miss rate.

  The output unit 27 is a processing unit that outputs an appropriate sector configuration for the application program, its effectiveness, and thrashing multiplicity of the application program.

[Sector cache application]
FIG. 2 is an explanatory diagram of the sector cache. A CPU (Central Processing Unit) 31 that is the processor shown in FIG. 2 is an arithmetic device that uses the main memory 33 as a main storage device.

  The cache memory 32 is a memory that is faster than the main memory 33 and holds a part of the main memory 33. The CPU 31 accesses the cache memory 32 when performing memory access. When the cache memory 32 holds an access target, access to the low-speed memory 33 is unnecessary, and the processing speed is improved.

  For this reason, the higher the probability that the cache memory 32 holds the cache corresponding to the access request of the CPU 31, the higher the performance of the application program. The performance increases as the size of the cache memory increases, and the performance improves as the locality of the memory access of the application program increases.

  The cache memory 32 is a 10-way set associative L2 cache memory having way0 to way9. In addition, the cache memory 32 includes a sector cache mechanism, and can use way0 to way9 logically divided into two sectors, sector 0 and sector 1.

  When such a sector cache is used, the application program designates which sector each memory access instruction uses. Specifically, as shown in FIG. 3, by applying the source program 41 to the sector cache optimizing compiler 42, a sector cache compatible object program 43 can be obtained.

[Processing operation]
FIG. 4 is a flowchart for explaining the processing operation according to the present embodiment. First, in compiling the application program, the sector cache optimizing compiler 42 reads the source program 41 (S101), compiles (S102), and writes the object program 43 (S103).

  When the processor 10 executes the application program obtained as the object program 43, the processor 10 generates the sampling thread 12 at the start of processing (S201). The processor 10 executes calculation processing of the application process 11 (S202) and performs sampling processing by the sampling thread 12 (S300).

  After completing the calculation process (S202), the processor 10 waits for the sampling thread 12 to be erased (S203), outputs the sampling data D1 (S204), and ends the process.

  FIG. 5 is a flowchart for further explaining sampling by the sampling thread 12 shown in FIG. As shown in FIG. 5, the sampling thread 12 first selects the sector configuration of the sector cache, that is, which way is assigned to sector 0 and sector 1 (S301).

  Next, the sampling thread 12 samples from the application process 11, measures the number of executed instructions, the number of cache accesses, and the number of cache misses (S302), and adds them in association with the current sector configuration (S304).

  After completion of S305, the sampling thread 12 determines whether 100 ms has elapsed since the current sector configuration was selected (S305). If 100 ms has not elapsed since the current sector configuration was selected (S305, No), the sampling thread 12 returns to S302 and continues sampling with the same configuration.

  On the other hand, if 100 ms has elapsed since the current sector configuration was selected (S305, Yes), the sampling thread 12 selects the next sector configuration (S301) and continues sampling.

  FIG. 6 is a flowchart for explaining the processing operation of the analyzer 20. As shown in FIG. 6, first, the data acquisition unit 31 collects sampling data D1 (S401). The cache miss rate calculation unit 22 calculates the cache miss rate for each sector configuration by dividing the number of cache misses of the sampling data D1 by the number of accesses (S402). In addition, the effectiveness evaluation unit 24 divides the number of accesses by the number of instructions for each sector configuration to obtain the cache access rate of each configuration.

  The selection unit 23 sets the configuration having the lowest cache miss rate as the optimal configuration (S404), and the validity evaluation unit 24 determines that the selection result by the selection unit 23 is valid when the relative standard deviation of the cache access rate is less than a predetermined value. It is determined that

  Then, the output unit 27 outputs the optimal configuration and validity evaluation result of the sector cache (S406), and ends the process.

[Specific examples of data]
FIG. 7 is an explanatory diagram of a specific example of sampling data and result output. As shown in FIG. 7, the sampling data D1 has information on the sector configuration, the number of executed instructions, the number of cache accesses, and the number of cache misses.

  In the example shown in FIG. 7, the number of instructions executed in sector configuration c1 is 2000, the number of cache accesses is 1000, and the number of cache misses is 500. In addition, the number of instructions executed in sector configuration c2 is 4000, the number of cache accesses is 2000, and the number of cache misses is 1300. In the sector configuration c82, the number of executed instructions is 3000, the number of cache accesses is 1600, and the number of cache misses is 800.

  The output data D2 is the optimum configuration and validity determination result obtained from the sampling data D1. In the example of FIG. 7, the optimum sector configuration is the sector configuration c33, the cache miss rate is 30%, and the relative standard deviation of the cache access rate is 5%, and the result is valid.

  Here, the determination of effectiveness will be described. The cache access rate obtained by dividing the number of cache accesses by the number of executed instructions does not change depending on the sector cache configuration. For this reason, when the measurement in each configuration is executed evenly for various parts of the program, the cache access rate in each configuration is the same, and therefore, it can be used for determining the validity.

  Specifically, the cache access rate in each configuration is 82 in total, and the relative standard deviation of these is obtained, and the fluctuation of the cache access rate is obtained. If it is above a certain value, it is a statistically inappropriate value, so it is judged that the configuration selection has failed, and a conclusion of measurement failure is drawn. The user extends the operation time of the application and re-measures. If it is below a certain value, it is a statistically appropriate value, so the sector cache configuration with the lowest cache miss rate is determined.

  In this way, with regard to 82 sector cache combination settings, the analysis apparatus 20 can obtain an optimum combination by executing the application program only once.

  Application programs often run for several hours, but the sector cache configuration is changed in a round-robin manner in units of 100 msec. Therefore, in 82 ways, measurements are completed once for all combinations in 8.2 seconds. To do. Therefore, if the application program is executed for one hour, it is possible to perform measurement about 440 times.

  Measure and add the number of execution instructions, the number of cache accesses, the number of cache misses obtained by the CPU-PA function for each configuration, and when the application execution is completed, determine the cache miss rate for each configuration, The sector cache configuration with the lowest cache miss rate is selected as the optimal configuration.

  In this way, it is possible to obtain the best result by making many trials in a single execution of the application program, and at the same time statistical judgment using the program characteristics that the cache access rate converges within a predetermined range Thus, the validity of the result can be determined.

  In addition, although the example which calculates | requires the cache miss rate in each structure by sampling by changing a sector structure in a round-robin manner with a fixed time interval was explained, since it is based on a sampling system, execution time is short May be statistically inappropriate.

  Therefore, the cache miss rate in each configuration may be obtained by changing the configuration of the sector cache in a round robin manner at the start and end of the subroutine. By changing the configuration according to the execution of the subroutine, it is possible to perform measurement with higher accuracy than when the configuration is changed at time intervals. Note that it is generally possible to perform some processing at the start and end of a subroutine by the function of the compiler.

[Calculation of thrashing multiplicity]
Thrashing is a phenomenon that significantly reduces cache performance. In general, when the number of ways decreases, thrashing occurs. However, in a highly tuned application, the performance degradation is limited even with a small number of ways. Applications that are tuned to reduce thrashing have superior characteristics that are less likely to cause performance blurring. The analysis device 20 can investigate whether the application supports thrashing by examining the relationship between the decrease in the number of ways and the performance.

  The analysis apparatus 20 takes up the performance of nine combinations of 82 sector cache combinations and divides 10 ways into two without excess and shortage, and analyzes the relationship between the number of ways and the performance.

  FIG. 8 is an explanatory diagram for explaining evaluation of thrashing. As shown in FIG. 8, the analyzing apparatus 20 has the number of ways in (sector 0, sector 1) as (1, 9), (2, 8), (3, 7), (4, 6), (5 , 5), (6, 4), (7, 3), (8, 2), (9, 1).

  In the example of FIG. 8, the cache miss rate D4 of sector 1 is 3.0% at (1,9), 1.7% at (2,8), 1.2% at (3,7), (4 6) 1.0%, (5,5) 1.1%, (6,4) 2.5%, (7,3) 2.6%, (8,2) 2. 8% and (9,1) are 3.0%.

  When thrashing countermeasures are taken, the cache miss rate does not increase even if the number of ways in the sector decreases. When the cache miss rate D3 increases as shown in FIG. 8, it indicates that thrashing countermeasures are insufficient. Specifically, among the data assigned to sector 1, a plurality of data determined to be low in reusability has many memory accesses at addresses close to the cache amount of 1 way. And the cache miss rate is increasing. In this case, since the cache miss rate D4 has not increased up to 5 ways, there is a high possibility that 5 data are competing.

  In this way, it can be determined that thrashing has occurred in a plurality of data assigned to sector 1 from the cache miss rate and determined to have low reusability. In such a case, after selecting a sector configuration in which thrashing occurs, an existing performance tuning tool is used to identify locations where cache misses occur frequently, thereby reducing cache misses. For this procedure, any cache tuning method may be used.

  When the occurrence of thrashing is determined, the differential (change) of the cache miss rate according to the number of ways is obtained, and the portion where this change is large is determined as the number of ways of occurrence of thrashing. This number of ways is called thrashing multiplicity.

  In the example of FIG. 8, the cache miss rate differential value D4 is -1.3 at (2,8), -0.5 at (3,7), -0.2 at (4,6), (5, 5) 0.1, (6, 4) 1.4, (7, 3) 0.1, (8, 2) 0.2, (9, 1) 0.2.

  In this example, the change is large at (6, 4), and since the focus is on the sector 1 side, the thrashing multiplicity is 5. An example of the result of tuning the application program based on this thrashing multiplicity is shown in the cache miss rate D6.

  Improved cache miss rates are 3.0% for (1,9), 1.7% for (2,8), 1.2% for (3,7), 1.0% for (4,6) , (5,5) 1.0%, (6,4) 0.9%, (7,3) 0.8%, (8,2) 0.9%, (9,1) 0.8%.

  The cache miss rate D3 before improvement is the smallest when the sector configuration is (4, 6) and is 1.0%, but the cache miss rate D6 after improvement is when the sector configuration is (8, 2). The minimum is 0.7%. In this way, a cache miss reduction of 30% is realized from 1.0% before improvement.

  FIG. 9 is a flowchart for explaining the processing operation for calculating the thrashing multiplicity. As shown in FIG. 9, the data acquisition unit 31 of the analyzer 20 acquires the sampling data D1 (S501), and the cache miss rate calculation unit 22 calculates the cache miss rate. The cache miss rate differential processing unit 25 selects a target sector configuration from the 82 sector configurations (S502), and calculates a differential value of the cache miss rate (S503). The thrashing multiplicity calculation unit 22 calculates the thrashing multiplicity based on the differential value of the cache miss rate (S504), the output unit 27 outputs the thrashing multiplicity as an analysis result (S505), and the process is terminated.

[Sector selection]
There are two sectors in the sector cache, and setting of an index for determining which sector each memory access is assigned to obtain high performance will be described. It is difficult to determine the reusability of data by analyzing a program statically. This is because data reusability is a dynamic characteristic of a program. Here, as one of means for selecting a sector, a technique for determining reusability based on the declaration shape (size) of data is shown.

First, the two sectors are divided into uses as follows.
Sector 0: Used for data that seems to be highly reusable Sector 1: Used for data that seems to be low reusable

  By dividing the usage in this way, it is possible to prevent memory accesses with low reusability from polluting the entire cache by separating those with high reusability and those with low reusability. In addition, by leaving a way for data that is considered to be low in reusability, it is possible to maintain cache efficiency of memory access with high address space locality such as prefetch.

In general, when the data declaration shape is large, it is expected that the data reference also covers a large range. Therefore, it can be assumed that the locality of access is low and the reusability is low. As an example, the size of one way of the cache is 512 KB. When the data size is known, the following judgment is made.
-It is determined that data of 512 Kbytes or less is highly reusable, and sector 0 is used.
-Data larger than 512 KBytes is judged to have low reusability, and sector 1 is used.

If you don't know the size of the data, you can guess from the number of dimensions of the array.
The data whose dimension number is a predetermined number, for example, 2 or less is judged to be highly reusable and sector 0 is used.
Data having a dimension number greater than 2 is judged to have low reusability, and sector 1 is used.

  According to the above determination, a sector cache compatible object program is generated by the sector cache optimization compiler. FIG. 10 is a flowchart for explaining sector selection processing during compilation.

  As shown in FIG. 10, the sector cache optimizing compiler first selects a variable (S601), and determines whether the data size is obtained (S602). When the data size is required (S602, Yes), sector 0 is used for data of a predetermined size or less, and sector 1 is used for other data (S603). On the other hand, when the size of the data cannot be obtained (S602, No), for example, data having a dimension number of 2 or less uses sector 0, and other data uses sector 1 (S604).

  After S603 and S604, the sector cache optimizing compiler determines whether all variables have been selected (S605). If there are unselected variables remaining (S605, No), variable selection (S601). Return to. If all variables have been selected (S605, Yes), the sector cache optimizing compiler ends the process.

  FIG. 11 is an explanatory diagram of variable shape and use sector determination results. The use sector determination result D7 shown in FIG. 11 indicates that the sector Va is used because the shape of the variable Va1 is (100, 100), that is, the size is 512 KB or less.

  Similarly, the use sector determination result D7 indicates that the shape of the variable Va2 is (100, 100, 100), that is, the size is known and the sector 1 is used because it is not 512 KB or less. The use sector determination result D7 indicates that sector 0 is used because the shape of variable Va3 is (NN, MM), that is, the size is unknown and the number of dimensions is 2 or less. The use sector determination result D7 indicates that the shape of the variable Va4 is (AA, BB, CC), that is, the size is not known, and the number of dimensions is not less than 2, so that the sector 1 is used.

  FIG. 12 is an explanatory diagram of the improvement by correcting the program. In the source program 41 shown in FIG. 12, real * 8 a (256,256), real * 8 d (256,256), a (i, j) = b (i, j) + c (i, j) * d (i , j) + e (i, j) * f (i, j), it is highly possible that the same cache index is subtracted to cause cache contention. As a result, in the hardware monitor information D8 of the source program 41, the L2 data cache miss rate is 9.1415%, and the execution time is long.

  In this way, due to the characteristics of the cache mechanism, cache contention tends to occur between large data having a data size that is a power of two.

  On the other hand, in the modified source program 41a, the data size does not become a power of 2 as real * 8 a (257,256) and b (257,256). For this reason, in the hardware monitor information D8a of the source program 41a, the miss rate of the L2 data cache is reduced to 7.7722%, and the execution time is improved.

  As described above, the analysis apparatus 20 according to the present embodiment collects the sampled access count and cache miss count while switching the sector configuration of the cache memory during execution of the application program. The analysis apparatus 20 that has acquired the sampling data calculates the cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration. This cache miss rate can be used when a sector configuration having a small value is selected as an appropriate sector configuration.

  Further, the analysis device 20 obtains a differential value of the cache miss rate with respect to the sector configuration change, and obtains a use state of the cache memory by the application program from the change of the differential value of the cache miss rate.

  For this reason, the analysis device 20 can analyze the configuration of the sector cache with high accuracy, thereby contributing to the performance improvement of the application program. In addition, since the sector cache configuration can be evaluated during one execution of the application program, the sector cache configuration can be analyzed at high speed.

  In addition, a present Example is an example to the last, A structure and operation | movement can be changed suitably and can be implemented. For example, if each processing unit of the analysis device 20 is realized by software, an analysis program for operating a computer as the analysis device can be obtained. The analysis program may be executed by the processor 10 itself that executes the target application program or may be another computer. The disclosed technology can also be applied to the sector cache of the L1 cache. It can also be applied to multiprocessors.

  The following supplementary notes are further disclosed with respect to the embodiments including the above examples.

(Appendix 1) A collection unit that collects data obtained by sampling at least the number of accesses to the cache memory and the number of cache misses in association with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
A cache miss rate calculator for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration;
An analysis apparatus comprising: a selection unit that selects a sector configuration having a smaller cache miss rate than other sector configurations as an appropriate sector configuration.

(Supplementary note 2) The analyzer according to supplementary note 1, further comprising a selection unit that selects a sector configuration having a smaller cache miss rate as compared to other sector configurations as an appropriate sector configuration.

(Supplementary Note 3) The acquisition unit further acquires the number of instructions executed by the application program in association with the sector configuration,
A cache access rate is obtained by dividing the number of accesses by the number of instructions for each sector configuration, and when the relative standard deviation of the cache access rate is less than a predetermined value, it is evaluated that the selection result by the selection unit is valid The analyzer according to appendix 2, further comprising an effectiveness evaluation unit for

(Appendix 4) A collection unit that collects sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
A cache miss rate calculator for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration;
A cache miss rate differential processing unit for obtaining a differential value with respect to a sector configuration change of the cache miss rate;
An analysis apparatus comprising: a usage state calculation unit that obtains a usage state of the cache memory by the application program from a change in a differential value of the cache miss rate.

(Additional remark 5) The said application program determines the sector to be used based on the magnitude | size and dimension number of the data which a variable uses, The analyzer as described in any one of additional marks 1-4 characterized by the above-mentioned.

(Additional remark 6) The said collection part collects the sampled data, switching a sector structure after the start of the subroutine process by the said application program, and before completion | finish, The additional description 1-5 characterized by the above-mentioned. Analysis equipment.

(Appendix 7) Collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
And a step of calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration.

(Supplementary note 8) The analysis method according to supplementary note 7, further comprising a step of selecting a sector configuration having a smaller cache miss rate as compared to other sector configurations as an appropriate sector configuration.

(Supplementary Note 9) Collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
Dividing the number of cache misses by the number of accesses for each sector configuration to calculate a cache miss rate;
Obtaining a differential value for a sector configuration change of the cache miss rate;
And a step of obtaining a use state of the cache memory by the application program from a change in the differential value of the cache miss rate.

(Supplementary Note 10) A procedure for collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
A procedure for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration;
An analysis program characterized in that a computer is executed.

(Additional remark 11) The analysis program of Additional remark 10 characterized by making a computer further perform the procedure which selects the sector structure with a small cache miss rate compared with another sector structure as an appropriate sector structure.

(Supplementary Note 12) A procedure for collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
A procedure for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration;
A procedure for obtaining a differential value with respect to a sector configuration change of the cache miss rate;
An analysis program causing a computer to execute a procedure for obtaining a use state of the cache memory by the application program from a change in a differential value of the cache miss rate.

DESCRIPTION OF SYMBOLS 10 Processor 11 Application process 12 Sampling thread 13 Sector structure change part 14 Sampling process part 20 Analyzing device 21 Data collection part 22 Cache miss rate calculation part 23 Selection part 24 Effectiveness evaluation part 25 Cache miss rate differentiation process part 26 Thrashing multiplicity calculation Unit 27 Output unit 31 CPU
41 Source program 42 Sector cache optimization compiler 43 Sector cache object program

Claims (8)

A collecting unit that collects sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
An analysis apparatus comprising: a cache miss rate calculation unit that calculates a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration.   The analysis apparatus according to claim 1, further comprising a selection unit that selects a sector configuration having a smaller cache miss rate as compared to other sector configurations as an appropriate sector configuration. The acquisition unit further acquires the number of instructions executed by the application program in association with the sector configuration,
A cache access rate is obtained by dividing the number of accesses by the number of instructions for each sector configuration, and when the relative standard deviation of the cache access rate is less than a predetermined value, it is evaluated that the selection result by the selection unit is valid The analyzer according to claim 2, further comprising an effectiveness evaluation unit that performs the evaluation. A collecting unit that collects sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
A cache miss rate calculator for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration;
A cache miss rate differential processing unit for obtaining a differential value with respect to a sector configuration change of the cache miss rate;
An analysis apparatus comprising: a usage state calculation unit that obtains a usage state of the cache memory by the application program from a change in a differential value of the cache miss rate.   The analysis apparatus according to claim 1, wherein the application program determines a sector to be used based on a size and a number of dimensions of data used by a variable.   6. The analysis apparatus according to claim 1, wherein the collection unit collects sampled data while switching the sector configuration after the start and end of the subroutine processing by the application program. Collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
And a step of calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration. A procedure for collecting sampled data by associating at least the number of accesses to the cache memory and the number of cache misses with the sector configuration while switching the sector configuration of the cache memory during execution of the application program;
An analysis program causing a computer to execute a procedure for calculating a cache miss rate by dividing the number of cache misses by the number of accesses for each sector configuration.

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