JP2011203946A - Integrated circuit and information processing system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit which is easily shared in an information processing system wherein a master circuit and the integrated circuit are combined, and a small-scale information processing system not including the master circuit, while satisfying both speed-up of execution speed of a boot code by a CPU (Central Processing Unit) and securing flexibility of the system, and to provide the information processing system using the integrated circuit.SOLUTION: The integrated circuit includes: the CPU; a RAM (Random Access Memory); an SPI (Serial Peripheral Interface) master 23 capable of being connected with a nonvolatile memory outside it; an SPI slave 24 receiving access to the RAM; an address mapping part 25 mapping the nonvolatile memory in a state of including a start address when a first boot mode is set, and mapping an address of the RAM in a state of including the start address when a second boot mode is set; and a reset control part 26 releasing a reset of the CPU according to a reset signal in the first boot mode, and releasing the reset of the CPU according to access through a second interface part in the second boot mode.

Description

  The present invention relates to an integrated circuit incorporating a CPU and an information processing system using the integrated circuit.

  Conventionally, a boot code (power-on code) to be executed after the reset of the CPU (Central Processing Unit) is released is stored in a non-volatile memory such as a flash memory, and this non-volatile memory is used as a start of the CPU. An information processing system is known in which boot code execution is started by mapping to include an address (see, for example, Patent Document 1).

JP 2001-312411 A

  In recent years, with the miniaturization of semiconductor processes, ASIC (Application Specific Integrated Circuit) in which a CPU and a memory are integrated on a single chip is widely used. In such an ASIC, the CPU can access the memory built in the chip faster than the memory connected to the outside of the ASIC. Further, from the viewpoint of ensuring the flexibility of the system, the ASIC built-in memory is desirably a RAM (Random Access Memory) that can be freely read and written.

  Therefore, a system as shown in FIG. 5 can be considered. FIG. 5 is a block diagram showing an information processing system using such an ASIC.

  The information processing system illustrated in FIG. 5 includes an ASIC 101 and a main system 102. The main system 102 is configured using, for example, a microcomputer, and is a master circuit that operates as a master that can request access to the ASIC 101.

  The ASIC 101 includes a CPU 111, a RAM 112, an interface circuit 113, and an address decoder 114. The CPU 111, RAM 112, interface circuit 113, and address decoder 114 are connected to each other via an internal bus 115.

  The interface circuit 113 is connected to the main system 102 and accepts access from the main system 102. The address decoder 114 decodes an address output from the CPU 111 and generates a selection signal for accessing the RAM 112. The address decoder 114 maps the RAM 112 so as to include the start address of the CPU.

  When the CPU 111 is activated, first, the main system 102 writes a boot code in the RAM 112 and stores it. When the reset of the CPU 111 is released, a start address is output from the CPU 111, the start address is decoded by the address decoder 114, and the RAM 112 is selected, so that the CPU 111 stores the boot code stored in the RAM 112. Read and execute.

  With such a configuration, it is considered that the RAM 112 is built into the ASIC 101, and it is possible to achieve both the increase in the boot code execution speed by the CPU 111 and the securing of the flexibility of the system.

  By the way, the ASIC 101 shown in FIG. 5 cannot operate without a master circuit capable of writing the boot code in the RAM 112. However, the master circuit that can write the boot code in the RAM 112 needs to be configured as a microcomputer system including a CPU, a memory, and the like, so that the circuit scale is large and expensive.

  Therefore, for example, when it is desired to test the ASIC 101, there is a need to operate the ASIC 101 with a small circuit without using the master circuit. There is also a need to share the ASIC 101 for an information processing system combined with a master circuit as shown in FIG. 5 and a small information processing system that does not include a master circuit.

  An object of the present invention is to provide an information processing system that combines a master circuit and an integrated circuit in an integrated circuit with a built-in CPU, while achieving both a high boot code execution speed by the CPU and ensuring the flexibility of the system. Another object of the present invention is to provide an integrated circuit that can be easily shared with a small-scale information processing system that does not include a master circuit, and an information processing system using the integrated circuit.

  An integrated circuit according to the present invention, after reset is released, fetches an instruction word from a preset start address and starts execution, a RAM accessible from the CPU, and a nonvolatile provided outside A first interface unit that can be connected to the memory in a readable manner from the CPU, a second interface unit that accepts write access to the RAM, and the CPU that is executed from the first interface unit after the reset is released. A mode setting receiving unit that selectively receives a setting instruction for one of the first boot mode for acquiring a boot code to be obtained and the second boot mode for acquiring the boot code from the second interface unit; A setting instruction indicating that the first boot mode should be set is received by the mode setting receiving unit. If it is determined, the address of the nonvolatile memory connected to the first interface unit is mapped so as to include the start address, and a setting instruction for setting the second boot mode is provided by the mode setting receiving unit. An address mapping unit that maps the RAM address so as to include the start address, a reset signal indicating the reset, and a configuration that is accessible from the outside through the second interface unit when received. When a setting instruction indicating that the first boot mode should be set is received by the mode setting receiving unit, the CPU reset is canceled in response to the reset signal, and the second boot mode is set by the mode setting receiving unit. If a setting instruction indicating that the And a reset controller for releasing the reset of the CPU in response to access through the second interface unit.

  According to this configuration, when this integrated circuit is used in a small-scale information processing system that does not include a master circuit capable of writing a boot code in the RAM, the boot code and the boot code are transferred to the RAM by the CPU. After that, a non-volatile memory storing an initial processing code that is an instruction code for jumping the execution of the CPU to the boot code transferred to the RAM is connected to the first interface unit, and the first boot is set in the mode setting receiving unit. By inputting a mode setting instruction, this integrated circuit can execute a boot code.

  On the other hand, when this integrated circuit is used in combination with a master circuit, a setting instruction for the second boot mode is input to the mode setting receiving unit, and the master circuit is connected to the second interface unit. Then, the master circuit writes the boot code in the RAM via the second interface unit so that the start address is at the head, and then the master circuit accesses the reset control unit via the second interface unit. Thus, it is possible to cause the integrated circuit to execute the boot code by releasing the reset of the CPU.

  As described above, according to the above-described configuration, the information processing system combining the master circuit and the integrated circuit and the small-scale information processing system not including the master circuit share the integrated circuit having the same configuration. Can be used. In any information processing system, since the CPU can execute the boot code stored in the RAM built in the integrated circuit, it is easy to increase the execution speed of the boot code. Furthermore, when changing the boot code, there is no need to change the integrated circuit, and it is only necessary to change the boot code stored in the nonvolatile memory or the boot code written to the RAM by an external master circuit. It is easy to ensure flexibility.

  An information processing system according to the present invention includes the integrated circuit described above and a nonvolatile memory connected to the first interface unit, and the mode setting accepting unit should set the first boot mode. A setting instruction is accepted, and after the boot code and the boot code stored in the nonvolatile memory are transferred to the RAM by the CPU, the CPU executes the execution of the CPU in the RAM. An initial processing code that is an instruction code for jumping to the transferred boot code is stored, and the start address of the initial processing code is the start address.

  According to this configuration, when the reset is released, the CPU starts fetching the instruction word from the start address of the nonvolatile memory, and the initial processing code is executed. When the initial processing code is executed, the boot code stored in the nonvolatile memory is transferred to the RAM by the CPU and stored. Further, when the transfer of the boot code to the RAM is completed, the execution of the CPU jumps to the boot code transferred to the RAM, and the boot code is executed.

  As a result, the CPU can execute the boot code in a small-scale information processing system that does not include a master circuit. Since the CPU can execute the boot code stored in the RAM built in the integrated circuit, it is easy to increase the boot code execution speed. Furthermore, when changing the boot code, it is not necessary to change the integrated circuit, and it is only necessary to change the boot code stored in the non-volatile memory. Therefore, it is easy to ensure the flexibility of the system. This integrated circuit can also be used in combination with a master circuit as described above.

  In addition, an information processing system according to the present invention includes the integrated circuit described above and a master circuit connected to the second interface unit, and the setting that the second boot mode should be set by the mode setting receiving unit An instruction is accepted, and the master circuit writes the boot code in the RAM via the second interface unit so that the start address is at the head, and then the master circuit transmits the boot code via the second interface unit. The reset of the CPU is released by accessing the reset control unit.

  According to this configuration, the boot code is written in the RAM by the master circuit so that the start address is at the head. Thereafter, the reset circuit is accessed by the master circuit to release the CPU reset. Then, the CPU starts fetching the instruction word from the start address of the RAM and executes the boot code.

  Thereby, in the information processing system in which the master circuit and the integrated circuit are combined, the CPU can execute the boot code. Since the CPU can execute the boot code stored in the RAM built in the integrated circuit, it is easy to increase the boot code execution speed. Further, when changing the boot code, it is not necessary to change the integrated circuit, and it is only necessary to change the boot code written in the RAM by an external master circuit, so that it is easy to ensure the flexibility of the system. This integrated circuit can also be used in a small-scale system that does not include a master circuit as described above.

  An integrated circuit having such a configuration and an information processing system using the same have the same configuration in an information processing system in which a master circuit and an integrated circuit are combined and a small-scale information processing system that does not include a master circuit. The integrated circuit which has can be shared and used. In any information processing system, since the CPU can execute the boot code stored in the RAM built in the integrated circuit, it is easy to increase the execution speed of the boot code. Furthermore, when changing the boot code, there is no need to change the integrated circuit, and it is only necessary to change the boot code stored in the nonvolatile memory or the boot code written to the RAM by an external master circuit. It is easy to ensure flexibility.

It is a block diagram showing an example of an information processing system using an integrated circuit concerning one embodiment of the present invention. It is a block diagram which shows another example of the information processing system using the integrated circuit which concerns on one Embodiment of this invention. FIG. 3 is a block diagram illustrating an example of a configuration of a reset control unit illustrated in FIGS. 1 and 2. FIG. 3 is an explanatory diagram showing a memory map of the nonvolatile memory shown in FIG. 2. It is a block diagram which shows an example of the information processing system which combined the master circuit and the integrated circuit.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. 1 and 2 are block diagrams showing an example of an information processing system using an integrated circuit according to an embodiment of the present invention.

  The information processing system 1 shown in FIG. 1 is configured, for example, by connecting an ASIC 2 (integrated circuit) and a main system 3 (master circuit) via an SPI (Serial Peripheral Interface) 4.

  The information processing system 1a shown in FIG. 2 is configured, for example, by connecting an ASIC 2 and a nonvolatile memory 5 via an SPI 6. As the nonvolatile memory 5, various nonvolatile memory elements such as FlashROM and EEPROM can be used. The information processing system 1a illustrated in FIG. 2 includes the ASIC 2 having the same configuration as the information processing system 1 illustrated in FIG. 1, and does not include the main system 3 serving as a master circuit.

  Further, the main system 3 and the nonvolatile memory 5 are not limited to the example connected to the ASIC 2 by the SPIs 4 and 6, and may be connected by, for example, a parallel bus or may be connected by another serial bus.

  The ASIC 2 includes a CPU 21, an SRAM (Static Random Access Memory) 22 (RAM), an SPI master 23 (first interface unit), an SPI slave 24 (second interface unit), an address mapping unit 25, and a reset control unit. 26, an internal bus 27, a connection terminal 28 (mode setting reception unit), and a connection terminal 29. The CPU 21, SRAM 22, SPI master 23, SPI slave 24, and reset control unit 26 are connected to each other via an internal bus 27.

  After the reset is released, the CPU 21 fetches an instruction word from a preset start address (for example, address 0) and starts instruction execution.

  The SRAM 22 is an example of a RAM, and may be another type of RAM such as a DRAM (Dynamic Random Access Memory).

  The SPI master 23 is an SPI interface circuit that can connect the non-volatile memory 5 connected to the outside in a readable manner from the CPU 21 as shown in FIG.

  The SPI slave 24 is an SPI interface circuit connected to the main system 3. Then, the SPI slave 24 receives write access to the SRAM 22 from the main system 3.

  The ASIC 2 has a first boot mode for acquiring a boot code to be executed after reset release from the SPI master 23 and a second boot mode for acquiring a boot code from the SPI slave 24.

  The connection terminal 28 is a setting terminal for selectively setting one of the first and second boot modes. Then, the signal applied to the connection terminal 28 is output to the address mapping unit 25 and the reset control unit 26 as a mode signal MODE indicating the mode.

  For example, when the connection terminal 28 is set to a low level and the mode signal MODE is set to a low level, the ASIC 2 sets the first boot mode, and when the connection terminal 28 is set to a high level and the mode signal MODE is set to a high level, the second boot mode is set. Is set.

  The address mapping unit 25 is configured by using, for example, an address decoding circuit or a logic circuit. Then, the address mapping unit 25 decodes the address signal of the internal bus 27 and generates selection signals for the SRAM 22, the SPI slave 24, and the reset control unit 26, thereby assigning these to addresses and mapping them. Similarly, the address mapping unit 25 assigns and maps the SPI master 23, that is, the nonvolatile memory 5 connected to the SPI master 23, to the address.

  Specifically, when the connection terminal 28 is set to the low level and the first boot mode is set, the address mapping unit 25 is connected to the SPI master 23 so as to include the start address (for example, address 0). The address of the memory 5 is mapped. Further, when the connection terminal 28 is set to the high level and the second boot mode is set, the address mapping unit 25 maps the address of the SRAM 22 so as to include the start address.

  A power-on reset signal RESET (reset signal) is input to the connection terminal 29 from the outside. This power-on reset signal RESET is input to the reset control unit 26 via the connection terminal 29.

  The reset control unit 26 is configured to be accessible from the main system 3 via the SPI 4 and the SPI slave 24. Then, when the connection terminal 28 is set to the low level and the first boot mode is set, the reset control unit 26 supplies the power-on reset signal RESET to the CPU 21 as the CPU reset signal RES, so that the power-on reset signal RESET When is released, the reset of the CPU 21 is released.

  Further, when the connection terminal 28 is set to the high level and the second boot mode is set, the reset control unit 26 generates the CPU reset signal RES in response to an instruction from the main system 3. Thereby, the reset control unit 26 releases the reset of the CPU 21 when a request instruction for requesting the reset release of the CPU 21 is output from the main system 3.

  FIG. 3 is a block diagram illustrating an example of the configuration of the reset control unit 26 illustrated in FIGS. 1 and 2. The reset control unit 26 illustrated in FIG. 3 includes a reset control register 261 and a multiplexer 262. The reset control register 261 is connected to the internal bus 27.

  When the main system 3 accesses the reset control unit 26, a latch signal is generated by the address mapping unit 25 and input to the clock terminal of the reset control register 261. Thereby, the reset signal RESm indicating the reset request and release from the main system 3 is latched by the reset control register 261.

  The reset signal RESm latched by the reset control register 261 is output to the multiplexer 262. The multiplexer 262 supplies the power-on reset signal RESET to the CPU 21 as the CPU reset signal RES when the mode signal MODE is set to the low level and the first boot mode is set. Further, the multiplexer 262 supplies the reset signal RESm to the CPU 21 as the CPU reset signal RES when the mode signal MODE is set to the high level and the second boot mode is set.

  First, the information processing system 1 shown in FIG. 1 will be described.

  The main system 3 includes, for example, a CPU 31 that executes arithmetic processing for realizing a predetermined application, a non-volatile ROM 32 that stores a predetermined control program, a RAM 33 that temporarily stores data, and an HDD (Hard Disk Drive) 34, an I / F (interface) circuit 35, and peripheral circuits thereof.

  For example, the HDD 34 and the ROM 32 store a boot code to be executed by the CPU 21 after canceling the reset.

  The I / F circuit 35 is an SPI interface circuit, and allows the CPU 31 to access the SRAM 22 via the SPI 4 and the SPI slave 24.

  In the information processing system 1 shown in FIG. 1, the connection terminal 28 is connected to the power source, the mode signal MODE is set to the high level, and the second boot mode is set. As a result, the address mapping unit 25 maps the address of the SRAM 22 so as to include the start address (for example, address 0).

  Then, when the CPU 21 of the ASIC 2 is reset by the reset control unit 26, the CPU 31 of the main system 3 executes a control program stored in, for example, the ROM 32, thereby reading the boot code stored in the HDD 35. Then, the data is stored in the SRAM 22 via the I / F circuit 35, SPI 4, and SPI slave 24.

  At this time, the CPU 31 writes the boot code so that the start address (for example, address 0) of the SRAM 22 is at the head of the boot code.

  When the boot code has been written to the SRAM 22, the CPU 31 accesses the reset control unit 26 via the I / F circuit 35, SPI 4, and SPI slave 24, and sends a reset release request to the reset control register 261. The reset of the CPU 21 is released by latching.

  Then, a CPU reset signal RES indicating reset release is output from the reset control unit 26 to the CPU 21 to release the reset, and the CPU 21 fetches the head of the boot code stored at the start address (for example, address 0) of the SRAM 22. The execution of the boot code is started.

  Next, the information processing system 1a shown in FIG. 2 will be described.

  In the information processing system 1a shown in FIG. 2, the connection terminal 28 is connected to the ground, the mode signal MODE is set to the low level, and the first boot mode is set.

  Thereby, the address mapping unit 25 performs mapping so that the address of the nonvolatile memory 5 includes the start address (for example, address 0x00000000). Further, the address of the SRAM 22 is mapped by, for example, the address 0x10000000 or later by the address mapping unit 25 so as not to overlap with the nonvolatile memory 5. Further, the power-on reset signal RESET is selected by the multiplexer 262 and is output to the CPU 21 as the CPU reset signal RES.

  FIG. 4 is an explanatory diagram showing a memory map of the nonvolatile memory 5 shown in FIG. As shown in FIG. 4, the initial processing code is stored in the area from 0x00000000 as the start address to 0x00000FFF, and the boot code is stored after the address 0x00001000.

  The initial processing code is an instruction code (program) that causes the boot code stored after address 0x00001000 to be transferred to the SRAM 22 by the CPU 21 and then jumps to the boot code transferred to the SRAM 22.

  Thus, when the reset by the power-on reset signal RESET is released, the reset control unit 26 outputs the CPU reset signal RES indicating the release of the RES reset, the reset of the CPU 21 is released, and the CPU 21 starts the nonvolatile memory 5. The beginning of the initial processing code stored at the address (address 0x00000000) is fetched, and execution of the initial processing code is started.

  When the initial processing code is executed, the boot code stored after address 0x00001000 of the nonvolatile memory 5 is transferred and stored by the CPU 21 after address 0x10000000 of the SRAM 22.

  When the transfer of the boot code is completed, the CPU 21 executes a JUMP instruction to, for example, address 0x10000000 in the SRAM 22, and the CPU 21 starts executing the boot code.

  As described above, according to the information processing systems 1 and 1a shown in FIG. 1 and FIG. 2, the same information processing system 1 that combines a master circuit and an integrated circuit and a small information processing system 1a that does not include a master circuit. The ASIC 2 having the configuration can be used in common. In any of the information processing systems 1 and 1a, since the ASIC 2 can execute the boot code stored in the built-in SRAM 22, it is easy to increase the execution speed of the boot code. Further, when the boot code is changed, it is not necessary to change the ASIC 2, and it is only necessary to change the boot code stored in the main system 3 or the nonvolatile memory 5, so that the flexibility of the system can be ensured. Easy.

1,1a Information processing system 2 ASIC
3 Main system 4 SPI
5 Nonvolatile memory 21, 31 CPU
22 SRAM
23 SPI master 24 SPI slave 25 Address mapping unit 26 Reset control unit 27 Internal bus 28, 29 Connection terminal 32 ROM
33 RAM
34 HDD
35 I / F circuit 261 Reset control register 262 Multiplexer MODE mode signal RES CPU reset signal RESET Power-on reset signal RESm Reset signal

Claims (3)

A CPU that fetches an instruction word from a preset start address and starts execution after the reset is released;
RAM accessible from the CPU;
A first interface unit capable of connecting an external nonvolatile memory so as to be readable from the CPU;
A second interface unit for accepting write access to the RAM;
Either a first boot mode in which the CPU obtains a boot code to be executed after reset release from the first interface unit, or a second boot mode in which the boot code is obtained from the second interface unit. A mode setting reception unit that selectively receives setting instructions;
When a setting instruction indicating that the first boot mode should be set is received by the mode setting receiving unit, the address of the nonvolatile memory connected to the first interface unit is mapped so as to include the start address, An address mapping unit that maps the address of the RAM so as to include the start address when a setting instruction to set the second boot mode is received by the mode setting receiving unit;
When a reset signal indicating the reset is received and configured to be accessible from the outside via the second interface unit, and a setting instruction for setting the first boot mode is received by the mode setting receiving unit In response to the reset signal, the reset of the CPU is released, and when the setting instruction indicating that the second boot mode should be set is received by the mode setting receiving unit, the access is made via the second interface unit. And a reset control unit for canceling the reset of the CPU in response. An integrated circuit according to claim 1;
A non-volatile memory connected to the first interface unit,
A setting instruction to set the first boot mode is received by the mode setting receiving unit,
The nonvolatile memory includes
The boot code;
After the boot code stored in the non-volatile memory is transferred to the RAM by the CPU, an initial processing code which is an instruction code for jumping the execution of the CPU to the boot code transferred to the RAM is stored. And
An information processing system, wherein a start address of the initial processing code is the start address. An integrated circuit according to claim 1;
A master circuit connected to the second interface unit,
A setting instruction indicating that the second boot mode should be set is received by the mode setting receiving unit,
The master circuit is
After the boot code is written in the RAM via the second interface unit so that the start address is at the head, the reset control unit is accessed via the second interface unit, so that the CPU An information processing system characterized by releasing a reset.

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