JP2011198417A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory which can suppress increase of a data reading period and increase of a power consumption when the data reading operation are separately executed for one bit line and another bit line of adjacent bit lines.SOLUTION: The device includes: a memory cell array consisting of memory cells which are arrayed at gate intervals of ≤30 nm; a sense amplifier for detecting data stored in the memory cells by detecting a current which flows through the bit lines into the memory cells connected to selection word lines; and a word line driver for applying a voltage to the word line when the data are written into the memory cells. The sense amplifier detects the data of respective memory cells connected to the adjacent first bit line and second bit line respectively in different periods. The word line driver maintains a potential of at least one word line in a period between the data detecting operation of the memory cell connected to the first bit line and the data detecting operation of the memory cell connected to the second bit line.

Description

  The present invention relates to a semiconductor memory device.

  A NAND flash memory is known as one of nonvolatile semiconductor memory devices. Conventionally, in a NAND flash memory, a read method using an ABL (All Bit Line) method is often used. The ABL method is a method in which a read operation is performed on all the bit lines after the bit lines are precharged. In recent years, NAND flash memories have been multi-valued so that each memory cell can store data of 2 bits or more.

  In the multi-level memory, in the data read sequence, the bit line is driven and the sensing is repeated while changing the voltage (gate voltage) of the selected word line. The bit line connected to the memory cell that has been read is fixed to a subsequent reference potential (for example, ground potential). Bit lines connected to memory cells that have not been read are subsequently driven for sensing and verifying. In one read sequence, a plurality of sense operations are repeatedly executed until data of memory cells in all columns is read.

  The ABL method uses a current sensing method that detects data based on the amount of current flowing from a bit line. Therefore, the voltages applied to all the bit lines at the time of precharging are equal and there is no adjacent effect. In the generation with a gate length of around 40 nm, the interval between adjacent bit lines is relatively wide. For this reason, even if a certain bit line is fixed at the reference potential after the sensing operation, the influence (proximity effect) on the potentials of other bit lines adjacent thereto is small during the next sensing operation. Therefore, in the generation where the gate length is around 40 nm, the memory can simultaneously execute the read sequence for all the bit lines.

  However, in the generation with a gate length of 30 nm or less, the interval between adjacent bit lines becomes narrow, and the proximity effect cannot be ignored. Therefore, when a certain bit line is fixed to the reference potential by the sensing operation, there is a possibility that the potential of other bit lines adjacent to the bit line fixed to the reference potential is affected in the subsequent sensing operation. is there. In order to cope with such a proximity effect, the memory needs to execute a read sequence by dividing the read sequence into bit lines of even address columns (even addresses) and bit lines of odd address columns (odd addresses). Such a divided read method increases the read time and power consumption by the amount of increase in the number of reads, compared with the conventional ABL method of reading data from the bit lines of all columns at once.

JP 2009-116993 A

  Provided is a semiconductor memory device capable of suppressing an increase in data read time and an increase in power consumption when data reading is separately performed on one bit line and the other bit line of adjacent bit lines.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array composed of a plurality of memory cells arranged with a gate interval of 30 nm or less, a plurality of word lines connected to the plurality of memory cells, and the plurality of memory cells. A plurality of bit lines crossing the plurality of word lines and the memory cells connected to a selected word line among the plurality of word lines via the bit lines. A sense amplifier that detects the amount of current flowing and detects data stored in the memory cell; and a word line driver that applies a voltage to the plurality of word lines when writing data to the memory cell;
The sense amplifier detects data of the memory cells connected to the first bit line and the second bit line adjacent to each other at different times,
The word line driver has at least 1 in a period between a data detection operation of the memory cell connected to the first bit line and a data detection operation of the memory cell connected to the second bit line. The potential of the word line of the book is maintained.

  The semiconductor memory device according to the present invention can suppress an increase in data read time and an increase in power consumption when data reading is separately performed on one bit line and the other bit line of adjacent bit lines. .

1 is a block diagram showing a configuration of a NAND flash memory according to a first embodiment of the present invention. The figure which shows the mode of the sense amplifier at the time of bit line precharge. The figure which shows the mode of the sense amplifier at the time of a sense. 4 is a timing chart showing a read sequence of the NAND flash memory according to the first embodiment. FIG. The timing diagram which shows the read-out sequence of the NAND type flash memory according to 2nd Embodiment based on this invention. The timing diagram which shows the write-in sequence of the NAND type flash memory according to 3rd Embodiment based on this invention.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to the first embodiment of the present invention. In the memory cell array 11, a plurality of memory cells are two-dimensionally arranged in a matrix. The gate of the memory cell is connected to the word line, and the source or drain of the memory cell is connected to the bit line. The gate length of the memory cell is 30 nm or less. An interval between adjacent memory cells is also 30 nm or less. The gate interval between adjacent memory cells is the interval between the gates of two adjacent memory cells. The plurality of word lines are wired so as to cross each other in the row direction and the bit lines cross each other in the column direction. A sense amplifier 12 is disposed at one end of the memory cell array 11 in the bit line direction. A sense amplifier 12 is also arranged at the other end of the memory cell array 11 opposite to one end in the bit line direction. The sense amplifier 12 is connected to the bit line, and detects data stored in the memory cell by detecting a cell current flowing through the bit line in the memory cell connected to the selected word line. At both ends of the memory cell array 11 in the word line direction, a row decoder 13 and a word line driver 21 are arranged. The word line driver 21 is connected to the word line and is configured to apply a voltage to the word line when data is written to the memory cell.

  In a NAND flash memory, a plurality of memory cells are connected in series to form a NAND string. One end of the NAND string is connected to the bit line BL, and the other end is connected to the source S. Therefore, the memory cell is connected to the bit line BL via another memory cell interposed between the memory cell and the bit line BL.

  Data exchange between the sense amplifier 12 and the external input / output terminal I / O is performed via the data bus 14 and the I / O buffer 15.

  Various external control signals such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE are input to the controller 16. Based on these control signals, the controller 16 identifies the address Add and the command Com supplied from the input / output terminal I / O. Then, the controller 16 transfers the address Add to the row decoder 13 and the column decoder 18 via the address register 17. Further, the controller 16 decodes the command Com. The sense amplifier 12 is configured to apply a voltage to the bit line according to the column address decoded by the column decoder 18. The word line driver 21 is configured to apply a voltage to the word line according to the row address decoded by the row decoder 13.

  The controller 16 performs sequence control of data reading, data writing, and erasing in accordance with an external control signal and a command. The internal voltage generation circuit 19 is provided to generate an internal voltage (for example, a voltage boosted from the power supply voltage) necessary for each operation. The internal voltage generation circuit 19 is also controlled by the controller 16 and performs a boosting operation to generate a necessary voltage.

  Next, an operation at the time of bit line precharging and an operation at the time of sensing in the ABL method of the NAND flash memory will be described. 2 and 3 are circuit diagrams of sense amplifiers in the ABL system. FIG. 2 shows a state of the sense amplifier at the time of bit line precharging, and FIG. 3 shows a state of the sense amplifier at the time of sensing. One read sequence is a series of read operations for reading data from selected memory cells in all columns connected to a selected word line WL.

  In the read sequence, first, the bit line BL and the sense node SEN are precharged. For example, as shown in FIG. 2, the bit line BL is set to 0.5 V, the sense node SEN is set to 2.5 V, and the cell current Icell is set to 1 μA, for example. The P-type transistor Tp1 limits the upper limit of the cell current Icell to a certain current amount (for example, 1 μA). At this time, the bit line is charged while discharging to the ground potential (common source line) via the NAND string (while a current flows). Thereafter, the sensing is started while being charged. Note that Icell is a cell current that flows through the NAND string.

  In the sensing shown in FIG. 3, when the selected memory cell is data “0”, the selected memory cell passes a current of 1 μA (current supply capability) or more. Therefore, the charge precharged in the bit line BL is discharged, the bit line potential is lowered from 0.5V, and the potential of the sense node SEN is lowered from 2.5V. Accordingly, the voltage Vdd is held in the latch circuit LA. On the other hand, when the selected memory cell is “1” data, almost no current flows through the selected memory cell, and the current flowing through the selected memory cell is less than 1 μA (current supply capability). Therefore, the potential of the bit line and the potential of the sense node SEN do not decrease and do not change. Therefore, the ground potential Vss is held in the latch circuit LA.

  Thus, the transistor Tp1 supplies current to the memory cell via the bit line BL. However, since the conduction state of the memory cell changes depending on the logic of the data stored in the memory cell, the potential of the bit line BL changes depending on the logic of the data. The sense amplifier 12 detects the logic of the data stored in the memory cell based on the potential of the bit line BL.

  FIG. 4 is a timing chart showing a read sequence of the NAND flash memory according to the first embodiment. In this comparative example, after data is read from the memory cells connected to the bit lines of the even address columns, the data is read from the memory cells connected to the bit lines of the odd address columns. In addition, this memory drives the sense signal STBn twice for each of the bit line BL of the even address column and the bit line BL of the odd address column, and executes the read operation twice. For each of the bit line BL of the even address column and the bit line BL of the odd address column, in the first read operation (Se1, So1), the sense amplifier 12 supplies data while supplying current to the selected memory cells of all the columns. To detect. In the second read operation (Se2, So2), in order to suppress an increase in the source potential, the sense amplifier 12 detects data while supplying current only to selected memory cells in some columns. A more detailed description will be given later.

  Even address columns and odd address columns can be distinguished by column addresses. For example, a bit line (first bit line) of an even address column is a bit line specified by a column address having “0” as the lowest address A0, and a bit line (second bit line) of an odd address column ) May be a bit line specified by a column address having “1” as the lowest address A0. The bit lines of the even address columns and the bit lines of the odd address columns are alternately provided in the word line direction. That is, two bit lines adjacent to both sides of a bit line of an even address column (or a bit line of an odd address column) become a bit line of an odd address column (or a bit line of an even address column).

  The selected word line SEL_WL is a selected word line in the NAND string, and the unselected word line UNSEL_WL is a word line other than the selected word line SEL_WL in the NAND string.

  First, in the first read sequence, the sense amplifier 12 reads data from the memory cells connected to the bit lines of the even address column. At this time, the potential of the bit line BL of the odd address column is fixed to the ground potential in order to suppress the proximity effect. As described with reference to FIG. 2, the bit line BL of the even address column is precharged.

  At t1, the voltage Vsel is applied to a certain selected word line SEL_WL. The voltage Vread is applied to unselected word lines UNSEL_WL other than the selected word line SEL_WL. Vread is a voltage higher than Vsel. Accordingly, since the non-selected memory cell connected to the non-selected word line UNSEL_WL becomes conductive, the selected memory cell connected to the selected word line SEL_WL is connected between the bit line BL and the source S. Become.

  The selected memory cell connected to the selected word line SEL_WL has its conduction state determined by the charge amount (for example, electron amount) of the floating gate. Therefore, the charged state of the bit line BL changes depending on the conduction state of the selected memory cell. For example, as described above, when the selected memory cell stores data “0” (when the selected memory cell is conductive), the current Icell is discharged from the bit line BL to the source S via the selected memory cell. . On the other hand, when the selected memory cell stores data “1” (when the selected memory cell is non-conductive), the selected memory cell does not flow the current Icell from the bit line BL to the source S. From t1 to t2, the memory operates with the read clock R_CLK.

  While the memory is operating with the read clock R_CLK, the sense signal STBn is driven low once. Sense signal STBn is the same signal as signal STBn (strobe signal) shown in FIGS. 2 and 3, and is driven low to store data (potential) transmitted to sense node SEN in latch circuit LA. .

  When the selected memory cell stores data “0” (when the selected memory cell is in a conductive state), the voltage of the sense node SEN in the sense amplifier 12 decreases. On the other hand, when the selected memory cell stores data “1” (when the selected memory cell is in a non-conducting state), the voltage of the sense node SEN does not drop from the precharged state and maintains a high voltage. By driving the sense signal, the latch circuit LA shown in FIG. 3 in the sense amplifier 12 latches the voltage state of the sense node SEN. Thereafter, the data is sent from the sense amplifier 12 to the I / O buffer 15 via the data bus 14 shown in FIG.

  When there are many selected memory cells (hereinafter referred to as “0” cells) that store data “0” in each column, the potential of the source S may rise due to the cell current Icell. When the potential of the source S rises, the sense amplifier 12 may not be able to detect data of a selected memory cell storing data “1” (hereinafter referred to as “1” cell). Therefore, during the operation period of the read clock R_CLK, the sense amplifier 12 reliably detects data “0” having a large cell current Icell, and thereafter fixes the bit line BL connected to the “0” cell to the ground potential. As a result, an increase in the source potential can be suppressed in the operation period (t2 to t3) by the next sense clock S_CLK.

  In the operation period based on the sense clock S_CLK, the sense signal STBn is driven low again. At this time, the number of “0” cells through which a large cell current Icell flows is smaller than the number of “0” cells in the operation period of the read clock R_CLK. Accordingly, since the increase in the source potential is suppressed in the sense signal STBn, the sense amplifier 12 can detect the “1” cell. The sense amplifier 12 can also detect “0” cells that could not be detected during the operation period of the read clock R_CLK.

  Next, from t3 to t4, the memory operates based on the recovery clock RR1_CLK. During this period, the word line driver 21 maintains the potential of the unselected word line at Vread, and resets the potential of the selected word line. The reset is an operation of once returning the potential of the selected word line from Vsel to the word line potential before the operation.

  From t4 to t6, the memory performs a read operation on the selected memory cell connected to the bit line BL of the odd address column. A more detailed read operation is the same as the read operation described above from t1 to t3, and thus the description thereof is omitted. At this time, the potential of the bit line BL of the even address column is fixed to the ground potential in order to suppress the proximity effect.

  From t6 to t7, the memory resets all the word lines WL in order to end one read sequence based on the recovery clock RR2_CLK. That is, the potentials of all the word lines WL are reset to the word line potentials before the read sequence operation.

  As described above, the generation of NAND flash memories having a gate length of 40 nm or more does not consider proximity effects such as channel coupling effects even when the read sequence includes a plurality of read operations (sense operations). Data detection by the ABL method could be performed.

  However, in the generation with a gate length of 30 nm or less, the proximity effect cannot be ignored as described above when the read sequence includes a plurality of read operations (sense operations). For this reason, in the generation whose gate length is 30 nm or less, it is necessary to read the data by dividing the bit line BL into even address columns and odd address columns. In this case, normally, after reading data from the selected memory cell connected to the bit line of the even address column (or odd address column), the memory executes the reset operation of the word line WL, and then the odd address column ( Alternatively, data is read from the selected memory cell connected to the bit line of the even address column. Thereafter, the memory performs the reset operation of the word line WL again. That is, the memory performs a reset operation at each of the end of reading data in the odd address column and the end of reading data in the even address column. This is because executing the reset operation after each read operation is the most natural and easy to implement from the viewpoint of simplifying the configuration of the word line driver 21 and simplifying the operation.

  However, if a reset operation is performed between the read operation in the even address column and the read operation in the odd address column, the word line WL is reset and then connected to the bit line of the odd address column (or even address column). When data is read from the selected memory cell, it is necessary to recharge the word line WL. In recent years, in order to increase the memory capacity, the number of memory cells included in one NAND string is increasing. As a result, the number of unselected word lines that are charged / discharged during a write or read operation is also increasing. Therefore, the power consumed during the reset operation is increasing.

  On the other hand, the NAND flash memory according to the present embodiment does not execute the reset operation of the unselected word lines in this reset operation. Thereby, although the configuration and operation of the word line driver 21 are somewhat complicated, an increase in power consumption can be suppressed.

  The reason for executing the reset operation of the selected word line without executing the reset operation of the non-selected word line is as follows. There is only one selected word line, and the non-selected word lines are a plurality of word lines other than the selected word line. Therefore, the number of unselected word lines is very large. Further, the voltage Vread applied to the unselected word line is higher than the voltage Vsel applied to the selected word line. Therefore, maintaining the potential of the unselected word line at Vread without resetting eliminates the need to recharge the unselected word line, thus saving power consumption. This also contributes to saving of discharge time and charge time of unselected word lines. Since the voltage Vread is higher than the voltage Vsel, the discharge time and the charge time of the unselected word line are longer than the discharge time and the charge time of the selected word line SEL_WL. Therefore, when the discharge time and the charge time of the unselected word lines are shortened, the length of the entire data read sequence can be shortened. As a result, in order to suppress the proximity effect by reducing the gate length, it is necessary to divide and read the bit line BL into even address columns and odd address columns. The lengthening of the period can be mitigated to some extent.

  In this embodiment, the plurality of bit lines BL are divided into two even-numbered address columns and odd-numbered address columns and the read sequence is executed. However, the plurality of bit lines BL may be divided into three.

  In the first embodiment, only the selected word line is reset without resetting the non-selected word line between the reading in the several address column and the reading in the odd address column. However, on the contrary, the selected word line may be reset without resetting the selected word line between the reading in the several address column and the reading in the odd address column. In this case, since the number of unselected word lines (for example, 63) is larger than the number of selected word lines (for example, one), the effect of this embodiment is reduced. However, since it is not necessary to recharge the selected word line, the power consumption can be reduced to some extent.

(Second Embodiment)
FIG. 5 is a timing chart showing a read sequence of the NAND flash memory according to the second embodiment of the present invention. In the second embodiment, during the operation by the recovery clock RR1_CLK from t3 to t4, the word line driver 21 maintains not only the potential of the unselected word line UNSEL_WL but also the potential of the selected word line SEL_WL without resetting. That is, the word line driver 21 maintains the potentials of all the word lines WL without resetting from t3 to t4. The word line driver 21 maintains the potential of the selected word line SEL_WL at Vsel from t3 to t4. Other operations in the second embodiment are the same as the corresponding operations in the first embodiment. The configuration of the second embodiment may be the same as the configuration of the first embodiment. Therefore, the second embodiment can obtain the same effects as those of the first embodiment. In the second embodiment, since the potential of the selected word line SEL_WL is not reset, the power consumption is further reduced as compared with the first embodiment. Furthermore, in the second embodiment, since the discharge time and the charge time of all the word lines WL can be omitted, it is possible to further suppress the reading sequence from becoming longer.

  The second embodiment is effective when the potential level Vsel of the selected word line SWL_WL is equal in the read operation in the even address column and the odd address column.

  The first and second embodiments can also be applied to multilevel memory reading. In a multi-level memory, the sense amplifier 12 cannot detect data of all bit lines (all columns) by one sensing operation. Therefore, after executing the precharge and sense operations once, the memory fixes the bit line connected to the memory cell whose data is known to the ground potential. The bit line connected to the memory cell with unknown data is then driven again for precharge and sense operations. The memory changes the voltage of the selected word line, and performs precharge and sense operations again on the memory cells with unknown data. As described above, the multi-value data is read from the memory cell by repeatedly performing the precharge and sense operations while changing the voltage of the selected word line. In this case, a person skilled in the art will normally configure the word line driver 21 to reset the word line WL each time a sensing operation is performed.

  However, by applying the first or second embodiment to this precharge and sense operation, the effects of the first or second embodiment can be obtained even if the NAND flash memory is a multi-level memory. Can do. That is, by omitting charging / discharging of unselected word lines (or all word lines) that have been executed after each sensing operation, power consumption can be suppressed and the read operation time can be shortened.

  As described above, in the generation in which the gate length is 30 nm or less, the memory executes the read operation by dividing the read operation into bit lines of even address columns (even addresses) and odd address columns (odd addresses). This is to prevent the potential of other bit lines adjacent to the bit line from being affected by the proximity effect when the bit line of the column for which data has been found is fixed at the reference potential. Therefore, the memory according to the present embodiment first reads multi-value data from the memory cells in the even-numbered address column (or odd-numbered address column), and then reads multi-value data from the memory cells in the odd-numbered address column (or even-numbered address column). read out. That is, in order to read data from the memory cells of all columns connected to a certain word line, it is necessary to execute the above-described series of read operations twice. In this case, a person skilled in the art will normally configure the word line driver 21 to reset the word line WL each time a sensing operation is performed.

  However, by applying the first or second embodiment to each read sequence, even if the NAND flash memory is a multi-value memory and the gate length is a generation of 30 nm or less, The effect of the second embodiment can be obtained. That is, by omitting charging / discharging of unselected word lines (or all word lines) that were performed between the sensing operation of the odd address column and the sensing operation of the even address column, the power consumption is suppressed, and The read operation time can be shortened. In addition, by omitting charging / discharging of unselected word lines (or all word lines) that have been executed after each sensing operation in the odd-numbered address column and even-numbered address column, power consumption is reduced and the read operation time is reduced. It can be shortened.

(Third embodiment)
FIG. 6 is a timing chart showing a write sequence of the NAND flash memory according to the third embodiment of the present invention. The NAND flash memory normally repeatedly performs a write operation (program operation) and a verify read operation while stepping up the voltage of the selected word line SEL_WL in a write sequence. The verify read operation is a read operation for checking (verifying) whether or not data of a desired potential level is written in a selected memory cell after a program operation.

  In the generation with a gate length of 30 nm or less, the proximity effect cannot be ignored in a verify read operation when a single read sequence includes a plurality of read operations (sense operations). For this reason, in the generation whose gate length is 30 nm or less, it is necessary to read the data by dividing the bit line BL into even address columns and odd address columns.

  Since the program operation executed before t1 in FIG. 6 is the same as the known program operation, detailed description thereof is omitted.

  The verify read operation from t1 to t7 shown in FIG. 6 may be the same as the read operation from t1 to t7 shown in FIG. 4 or FIG. Therefore, the effects of the first or second embodiment can be obtained also in the verify read operation in the write sequence in the third embodiment.

DESCRIPTION OF SYMBOLS 12 ... Sense amplifier, 13 ... Row decoder, 14 ... Data bus, 15 ... I / O buffer, 16 ... Controller, 17 ... Address register, 18 ... Column decoder, 19 ... Internal voltage generation circuit, I / O ... External input / output Terminal, /CE...chip enable signal, ALE ... address, latch enable signal, CLE ... command latch enable signal, /WE...write enable signal, /RE...read enable signal, R_CLK ... read clock, S_CLK ... sense clock, RR1_CLK, RR2_CLK: recovery clock, STBn: sense signal (strobe signal)

Claims (5)

A memory cell array composed of a plurality of memory cells arranged with a gate interval of 30 nm or less;
A plurality of word lines connected to the plurality of memory cells;
A plurality of bit lines connected to the plurality of memory cells and intersecting the plurality of word lines;
A sense amplifier for detecting data stored in the memory cell by detecting an amount of cell current flowing through the bit line in the memory cell connected to the selected word line among the plurality of word lines; ,
A word line driver that applies a voltage to the plurality of word lines when writing data to the memory cell;
The sense amplifier detects data of the memory cells connected to the first bit line and the second bit line adjacent to each other at different times,
The word line driver has at least 1 in a period between a data detection operation of the memory cell connected to the first bit line and a data detection operation of the memory cell connected to the second bit line. A semiconductor memory device characterized in that the potential of the word line of the book is maintained.   The sense amplifier fixes the potential of the second bit line when detecting data in the memory cell connected to the first bit line, and the memory connected to the second bit line. 2. The semiconductor memory device according to claim 1, wherein the potential of the first bit line is fixed when detecting cell data.   The word line driver reads data in a period between a data detection operation of the memory cell connected to the first bit line and a data detection operation of the memory cell connected to the second bit line. 3. The semiconductor memory device according to claim 1, wherein the potential of the non-selected word line that is not the target of the data is maintained and the potential of the selected word line that is the target of the data read is reset.   The word line driver includes all the data detection operations of the memory cells connected to the first bit line and the data detection operations of the memory cells connected to the second bit line. 3. The semiconductor memory device according to claim 1, wherein the potential of the word line is maintained. The sense amplifier and the word line driver perform a data write operation to the memory cell and a verify read operation for confirming that the data has been written to the memory cell. Run every time you step up,
The sense amplifier detects data of the memory cells connected to the first bit line and the second bit line at different times in the verify read operation,
In the verify read operation, the word line driver may perform a data detection operation between the memory cell connected to the first bit line and a data detection operation of the memory cell connected to the second bit line. 5. The semiconductor memory device according to claim 1, wherein a potential of at least one of the word lines is maintained in the period of 5.

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