JP2011197118A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine necessity of positional correction between an optical system and a photoreceptor based on the opening of a cover and a temperature change generated in a power saving mode.SOLUTION: When the opening of the cover is detected by a cover opening/closing detection switch 105 in the power saving mode in which power supply to a CPU 106 is shut off, a power source generated by a power-saving mode power source generation part 110 is supplied to a nonvolatile storage device 109 to store the effect that the cover is opened. Meanwhile, the power-saving mode power source generation part 110 generates the power source in association with an alarm signal by a real time clock IC 111, and the temperature change in the image forming apparatus, detected by a temperature/humidity sensor 115, is stored in the nonvolatile storage device, and when recovered to the normal state from the power saving mode, by accessing the nonvolatile storage device 109 by the CPU 106 to which the power source is supplied, information on the opening/closing of the cover and information on the temperature change are obtained, and it is determined whether it is necessary to perform the positional correction between the optical system and the photoreceptor.

Description

  The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus capable of saving power and reducing costs.

  In recent years, image forming apparatuses such as copying machines, printers, and facsimiles are rapidly becoming colorized, and in addition to this, there are increasing demands for low power consumption, apparatus cost reduction, and running cost reduction. In order to reduce the cost, the machine structure has been simplified and reduced in size and the cost of parts has been reduced.

  For low power consumption, the TEC value (Typical Electricity Consumption), which is the standard value for conforming to the International Energy Star Program of the Energy Conservation Center, is calculated based on the printing or copying speed of the product. You can be certified as a compliant product of the “International Energy Star Program” if it is the following, which is a big selling point for selling.

  In addition to satisfying this standard value, in order to further reduce power consumption, it is important to reduce power consumption during the power consumption mode. For example, the shorter the transition time to the power saving mode, the smaller the power consumption, so the transition time tends to be shorter. Note that the transition to the power saving mode is usually performed when an operation such as printing is not performed for a certain period of time on the basis of a clock called a known real-time clock (RTC) IC mounted on the apparatus. The real time clock IC is generally driven by a battery during the power saving mode.

  In order to reduce the cost of the apparatus, there is a problem that the positional relationship between the optical unit and the photosensitive member is shifted by opening and closing the cover of the apparatus, while the structure is simplified and miniaturized. Also, in order to reduce the cost of the lens used in the optical unit by reducing the cost of parts, for example, a plastic lens is used. However, since this plastic lens changes in temperature, the lens is distorted. Deviation of the path of the laser beam from the unit occurs. In order to correct these deviations, when the cover is opened and closed and when a temperature change is detected to such an extent that the lens is distorted, it is necessary to perform position deviation correction control for correcting this deviation.

However, if power supply to the CPU (central processing unit) is stopped during the power saving mode, even if there is a cover open / close or temperature change that occurs during the power saving mode, it is not known. For this reason, it is necessary to always perform misalignment correction control when returning from the power saving mode to correct misalignment even if there is actually no cover opening or closing or temperature change during the power saving mode.
Also, if power supply to the CPU is stopped during the power saving mode, it is necessary to form a toner image on the intermediate transfer belt in order to perform misregistration correction control when returning from the power saving mode. Therefore, there is a problem that toner consumption occurs and the running cost increases.

To solve this problem, as a method of detecting the opening / closing of the cover of the image forming apparatus during the power saving mode, a switching power supply that supplies at least two power supply voltages of a drive system power supply voltage and a control system power supply voltage is prepared. A method has been proposed in which the drive system power supply voltage is cut off during the power saving mode, the control system power supply voltage is switched to supply power to the CPU (see Patent Document 1).
However, the image forming apparatus described in Patent Document 1 requires the CPU to operate even during power saving, and there is a problem that power consumption occurs during the power saving mode.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to open and close a cover that occurs during a power saving mode without supplying power to the CPU during the power saving mode in the image forming apparatus. In addition, the fact that there has been a temperature change is stored, and when returning from the power saving mode to the normal mode, it is determined whether or not to perform misregistration correction control based on the stored contents, so that the power saving mode is in progress. Power consumption and unnecessary toner consumption are reduced, and running costs are reduced.

  The present invention relates to an image forming apparatus that shifts from a normal mode to a power saving mode when not in use for a predetermined time, and a cover opening detection unit that detects that the cover of the image forming apparatus is opened in the power saving mode. A power supply means for supplying power to the storage control means when the cover open detection means in the power saving mode detects cover opening, a storage device for recording the cover open by the storage control means, and the power saving An image forming apparatus comprising: a determination unit configured to access the storage device and determine whether the cover is open during the power saving mode when the mode is returned to the normal mode.

  Even when power is not supplied to the CPU during the power saving mode, the opening / closing of the cover and the temperature change that occurred during the power saving mode are stored in the nonvolatile storage device, and when returning to the power saving mode, the nonvolatile storage device is stored. From the contents stored in the above, it is determined whether or not to perform misalignment correction control when returning to the power saving mode, and if there is no cover open / close or temperature change, the misalignment correction control is not performed. Since the power consumption during the power saving mode can be reduced and unnecessary toner consumption can be suppressed, the running cost can be reduced.

1 is a block diagram illustrating a system configuration of an image forming apparatus according to an exemplary embodiment. 1 is a configuration diagram of a power supply system of an image forming apparatus according to an exemplary embodiment. It is a block diagram which shows the structure inside a non-volatile memory device. It is a figure which shows the structure of the control circuit of the non-volatile memory device at the time of a cover opening. It is an operation | movement flowchart of the control circuit of the non-volatile memory device at the time of a cover opening. It is a figure which shows the structure of the control circuit of NVRAM which is a non-volatile storage device at the time of real-time clock IC alarm signal detection. It is a control circuit operation | movement flowchart of NVRAM which is a non-volatile storage device at the time of real-time clock IC alarm signal detection. It is a figure following FIG. 7a of the control circuit operation | movement flow of NVRAM which is a non-volatile storage device at the time of real-time clock IC alarm signal detection. It is a figure following FIG. 7b of the control circuit operation | movement flow of NVRAM which is a non-volatile storage device at the time of real-time clock IC alarm signal detection.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram illustrating a system configuration of the image forming apparatus according to the present exemplary embodiment.
In FIG. 1, the system 100 does not first block the power saving mode transition determination unit 101, the power saving mode signal generation unit 102, the power supply ON / OFF control unit 103, and the cover open / close detection switch 105 even in the power saving mode. The steady voltage + 5Ve is supplied. Before shifting to the power saving mode, the cover open / close detection signal generation unit 104 indicates the state of the cover open / close detection switch 105, and the CPU 106 determines the cover open / close state.

When the image forming apparatus is not used for a certain period of time, the power saving mode shift determination unit 101 shifts from the normal mode to the power saving mode. When the mode is shifted to the power saving mode, the transition signal generated by the power saving mode signal generation unit 102 is input to the power supply ON / OFF control unit 103, and the power supply ON / OFF control unit 103 stops power supply to the CPU 106. The CPU 106 whose power supply has been stopped cannot detect the opening / closing of the cover.
Here, the cover open / close detection switch 105 is supplied with the steady voltage + 5Ve which cannot be cut even in the power saving mode as described above. When the steady voltage + 5Ve is used and the cover is opened during the power saving mode, the power generation unit 110 in the power saving mode generates the supply voltage Vco to the nonvolatile memory device controller 108 and the nonvolatile memory device 109. At this time, the cover open / close detection signal generation unit 104 outputs a signal indicating that the cover is open (a cover open signal COVER_OPEN_N described later) to the nonvolatile memory device control unit 108, and the nonvolatile memory device control unit that has received this signal 108 writes in the nonvolatile memory device 109 that the cover has been opened. When the normal mode is changed from the power saving mode, the CPU determines whether or not to perform misalignment correction based on the writing information in the nonvolatile storage device 109.

Next, temperature capture during the power saving mode will be described. The real time clock IC 111 and the real time clock IC alarm output detection unit 112 are operated by the battery 113 during the power saving mode. Here, the general real-time clock IC 111 has an alarm function, that is, a function of outputting this alarm signal at regular intervals. The alarm output timing is set in advance before the CPU 106 shifts to the power saving mode.
When the real-time clock IC 111 outputs an alarm signal, the alarm signal is output to the real-time clock IC alarm output detection unit 112 and held. The held alarm signal is output to the power generation unit 110 in the power saving mode, and the power generation unit 110 in the power saving mode receives the signal to generate the supply voltage Vco. Power is supplied to the control unit 108, the nonvolatile storage device 109, the AD converter 114, and the temperature / humidity sensor 115. Further, when the nonvolatile storage device control unit 108 receives the held alarm signal, the nonvolatile storage device control unit 108 receives the digitized temperature data from the AD converter 114.

FIG. 2 is a configuration diagram of a power supply system including the power generation mode power generation unit 110 and the cover open / close detection signal generation unit 104.
In FIG. 2, when the power saving mode signal SLP_N output from the power saving mode signal generation unit 102 becomes the logic level “L”, the image forming apparatus shifts to the power saving mode. The CPU_ACS_P signal is a signal output from the CPU 106. It indicates that the CPU 106 accesses the storage device when the logic level of the CPU_ACS_P signal becomes “H”. The RTC_ALM_P signal is a signal generated by the real time clock IC alarm output detection unit 112. The RTC_ALM_P signal is a signal indicating that an alarm is output from the real-time clock IC 111, and is a signal holding an alarm signal output as a one-shot pulse. This signal indicates that an alarm signal is output from the real-time clock when it becomes “H” level.

Here, the power saving mode signal SLP_N becomes the logic level “H”, the access signal CPU_ACS_P to the CPU 106 and the real-time clock IC alarm signal RTC_ALM_P are at the logic level “L”, that is, no alarm is output from the real-time clock IC 111. Then, the PNP transistors 2 and 3 are turned off.
When the CPU access signal CPU_ACS_P and the real-time clock IC alarm signal RTC_ALM_P signal are “L”, the NPN transistors 6 and 7 are turned off and the collectors are opened, so that the base current of the PNP transistor 4 is not drawn. Therefore, the PNP transistor 4 is turned off.
Therefore, the base of the PNP transistor 1 is in an open state, the PNP transistor 1 is in an OFF state, and no supply voltage is generated in the supply voltage Vco.

Next, an operation when the cover is opened during the power saving mode will be described.
In the cover open / close detection signal generation unit 104 (FIG. 1), the COVER_OPEN_N signal generated by dividing the steady voltage + 5Ve by the resistors 14 and 15 through the switch 5 is opened when the logic level is “L”. It shows that. When the cover is opened, since the switch 5 is opened and is grounded by the resistor 15, the cover open signal COVER_OPEN_N becomes the logic level “L”.
That is, when the cover is closed, the switch 5 is also closed, and the cover open signal COVER_OPEN_N signal becomes a voltage divided by the resistors 14 and 15, which indicates that the logic level is “H”. .

  Here, when the power saving mode signal SLP_N is “L”, the CPU access signal CPU_ACS_P and the real-time clock IC alarm signal RTC_ALM_P are “L”, and the switch 5 is closed, the PNP transistors 2 and 3 are turned on. Therefore, the steady voltage + 5Ve is supplied to the base of the PNP transistor 1 through the switch 5 and the resistor 11 to the collector of the PNP transistor 2, the PNP transistor 1 is turned off, and a supply voltage is generated in the supply voltage Vco. do not do. Since the PNP transistor 4 continues to be in the OFF state, the base voltage of the PNP transistor 1 is not affected.

  When the power saving mode signal SLP_N is “L”, the CPU access signal CPU_ACS_P and the real time clock IC alarm signal RTC_ALM_P are at the logic level “L”, and the switch 5 is open, the PNP transistor 2 is in the ON state. Since the emitter of the PNP transistor 2 is open, power is not supplied to the base of the PNP transistor 1. However, since the PNP transistor 3 is in the ON state, the base of the PNP transistor 1 is grounded via the PNP transistor 3 and the resistor 8, so that the PNP transistor 1 is in the ON state and the supply voltage Vco Supply voltage is generated.

  When the real-time clock IC alarm signal RTC_ALM_P is “H” or the CPU access signal CPU_ACS_P is “H”, the NPN transistor 6 or the power saving mode signal SLP_N “L” and “H”, regardless of whether the switch 5 is opened or closed Since the NPN transistor 7 is turned on and the base current of the PNP transistor 4 is drawn, the PNP transistor 4 is turned on, the base current of the PNP transistor 1 is drawn, the PNP transistor 1 is turned on, and the supply voltage Vco Generates a supply voltage.

  Here, when the cover is opened in the power saving mode, the power generation unit 110 in the power saving mode generates the supply voltage Vco to the nonvolatile memory device controller 108 and the nonvolatile memory device 109 as described above. At this time, the cover open / close detection signal generation unit 104 outputs a cover open signal (COVER_OPEN_N of logic level “L”) indicating that the cover is open to the nonvolatile memory control unit 108, and the nonvolatile memory device that has received this signal The control unit 108 writes in the nonvolatile storage device 109 that the cover has been opened.

Next, the internal configuration of the nonvolatile memory device will be described with reference to FIG. As shown in FIG. 3, the storage device generally has a data storage area for storing, and an address (address) is assigned to the storage area in a one-to-one relationship. Then, which data is written to each address is assigned in advance.
In FIG. 3, an area for storing data indicating that the cover has been opened / closed is assigned to address M, and address n is shifted to the power saving mode, and real-time clock IC 111 (FIG. 1) starts the first time. The temperature data stored at the timing when the alarm signal is output is allocated as an area for storing the temperature data, and the address n + 1 is allocated as an area for storing the humidity data stored at the timing when the first alarm signal is output. Indicates that
The address n + 2 stores temperature data stored at the timing when the real-time clock IC 111 outputs the second alarm signal. The address n + 2 (a−1) has the real-time clock IC 111 receiving the a-th alarm signal. Is assigned to the area for storing the temperature data stored at the timing when the signal is output, and the humidity data stored at the timing when the real-time clock IC 111 outputs the a-th alarm signal is stored at address n + 2a−1. Assigned to the area.

  Next, at the address N, the address recording area where data was last written, for example, the address n + 2a-1 where the humidity data was written when the real-time clock IC 111 outputs the a-th alarm signal is stored. Yes.

Next, processing when the cover is opened during the power saving mode and when an alarm is output from the real time clock IC 111 will be described.
As the nonvolatile storage device 109, a known NVRAM (Non Volatile Random Access Memory) that is generally used is used. This NVRAM has an address signal and write data composed of a plurality of signal lines indicating an area for storing data, a data signal from a plurality of signal lines for exchanging read data, a write signal for writing data to the NVRAM, and data from the NVRAM. Is controlled by a read signal for reading out.
The NVRAMs 200 and 624 described in FIGS. 4 and 6 to be described later are the same, and the selector 201 at the front stage of the NVRAM is used to detect the NVRAM connection signal when the cover open (open) is detected, and the alarm detection of the real-time clock IC 111. It is a selector for selecting the NVRAM connection signal at the time and the NVRAM connection signal of the CPU 106. Similarly to the NVRAM, the selectors 201 and 622 shown in FIGS. 4 and 6 are the same.

First, the case where the cover is opened during the power saving mode will be described. 4 is a diagram showing a configuration of a control circuit of the nonvolatile memory device 109 when the cover is opened, and FIG. 5 is an operation flow diagram of the control circuit of the nonvolatile memory device 109 when the cover is opened.
The NVRAM access control signal generation unit 400 at the time of detection of a cover open in FIG. 4 includes a power-on reset signal generation unit 401, an oscillator 402, a cover open detection unit 403, an NVRAM access sequence control unit 404, an NVRAM read data holding unit 408, and a cover open flag. The presence / absence determination unit 409 controls the NVRAM 200 via the selector 201.

  In FIG. 5, when the supply voltage Vco is supplied to the NVRAM access control signal generation unit 400 when the cover open is detected (S501), the power-on reset signal generation unit 401 outputs a power-on reset signal (S502). Is stabilized, the power-on reset is canceled (S503). Then, a reference clock signal for generating a control signal is output from the oscillator 402 (S504). At this time, when the cover open detection unit 403 in FIG. 4 detects that the cover open signal COVER_OPEN_N is at the logic level “L” (S505: YES), it is determined that the cover has been opened, and the NVRAM access sequence The read sequence of the NVRAM 200 is started by the read access control unit 406 of the control unit 404 (S506).

At this time, the address of the data to be read is the data of the address M shown in FIG. Then, the read data is held by the NVRAM read data holding unit 408 (S507).
The cover open flag presence / absence determination unit 409 determines whether or not the cover has been opened in the past during the continued power saving mode (S508). Here, if there is a cover open flag indicating that the cover has been opened in the past (S508: YES), the processing is terminated as it is.
In step S508, if there is no cover open flag in the past (S508: NO), it is necessary to record the cover open detected this time. Therefore, the write access control unit 407 of the NVRAM access sequence control unit 404 uses the write sequence. The cover open flag is written in the address M (FIG. 3) of the NVRAM (S509), and after this write sequence is completed (S510: YES), this process is terminated.
In this way, whenever a cover open is detected during the power saving mode, it is always stored in the NVRAM.

Next, NVRAM access control when an alarm signal is output from the real-time clock IC 111 during the power saving mode will be described.
FIG. 6 and FIG. 7 are diagrams showing the configuration of the control circuit of the NVRAM, which is a non-volatile storage device when the real-time clock IC alarm signal is detected, and its operation flowchart.
In FIG. 6, the NVRAM access control signal generation unit 600 upon detection of a real-time clock IC alarm includes a power-on reset signal generation unit 601, an oscillator 602, an alarm signal detection unit 603, an NVRAM access sequence control unit 604, a write data selection control unit 608, The RTC_ALM_P hold release signal generation unit 609 and the like are connected to the AD converter access sequence control unit 612 via the selector A623 and the NVRAM 624 via the selector 622. The AD converter access sequence control unit 612 controls each data and signal of the temperature and humidity acquired from the temperature / humidity sensor 115 via the AD converter 114.
Here, the power-on reset signal generation unit 601 and the oscillator 602 in the NVRAM access control signal generation unit 600 when the real-time clock IC alarm is detected are the power-on reset signal generation unit of the NVRAM access control signal generation unit 400 when the cover open is detected. 401 and the oscillator 402 may be shared.

  6 and 7a to 7c, first, when Vco power supply is started (S701), a power-on reset signal is output from the power-on reset signal generation unit 601 (S702), and the power-on reset is canceled (S703). . Then, a reference clock signal for generating a control signal is output from the oscillator 602 (S704). Here, a one-shot pulse is output from the real-time clock IC 111 (FIG. 1), and the RTC_ALM_P signal held by the alarm holding circuit 610 is output. When the logic level of the RTC_ALM_P signal is detected as “H” by the alarm signal detection unit 603 (S705: YES), the NVRAM access control signal generation unit 600 and the AD converter access sequence control unit 612 are activated when the real-time clock IC alarm is detected. The analog temperature data acquisition start signal generation unit 613 of the AD converter access sequence control unit 612 is activated to output an analog temperature data acquisition start signal (S706), and analog temperature data is acquired. At this time, in order to secure the time required for taking in analog data and converting the analog data into digital data, the data take-in specified time securing timer 615 is started (S707). Then, it waits for the time-out output of the data acquisition specified time ensuring timer 615, and when the time-out is output (S708: YES), the digital temperature data acquisition control unit 616 starts to acquire the digital temperature data (S709). Then, the read digital data is held by the digital temperature data holding unit 617 (S710), and after the holding of the digital temperature data is completed, a temperature data capturing completion flag is set by the digital temperature data holding completion flag setting unit 618. (S711).

  When the temperature data capture completion flag is set (S712: YES), the analog humidity data capture start signal generation unit 614 is activated and outputs an analog humidity data capture start signal (S713). At this time, in order to secure the time required for taking in analog data and converting the analog data into digital data, the data take-in specified time securing timer 615 is started (S714). Then, it waits for the time-out output of the data capture prescribed time securing timer 615. After the time-out is output (S715: YES), the digital humidity data capturing control unit 619 starts capturing the digital humidity data (S716). Then, the read digital data is held in the digital humidity data holding unit 620 (S717), and after the holding of the digital humidity data is completed, the humidity data capturing completion flag is set in the digital humidity data holding completion flag setting unit 621. (S718).

  When the humidity data capture completion flag is set (S719: YES), the read access control unit 606 of the NVRAM access sequence control unit 604 starts reading the data at the address N shown in FIG. 3 (S720). The read value is held in the NVRAM read data holding unit 611 (S721). If the read data at address N is n, the read data n is incremented by +1 by the address generation calculation unit 605 (S722), n + 1 is the temperature data write address of the NVRAM 624, and the NVRAM 624 is the address signal. The temperature data is output and generated by the write access control unit 607, and writing of temperature data is started (S723). The written temperature data is output from the digital temperature data holding unit 617, selected by the selector A 623, and output to the NVRAM 624.

After the writing of the temperature data is completed (S724: YES), the humidity data output from the digital humidity data holding unit 620 at the address n + 2 is selected by the selector A623, output to the NVRAM 624, and writing is started (S727).
When the writing of the humidity data into the NVRAM 624 is completed (S728), the completion flag is set in the digital humidity data retention completion flag setting unit 621, and the RTC_ALM_P retention release signal generation unit 609 sets the alarm retention circuit 610 at the logic level “H”. The held RTC_ALM_P signal is canceled (S729). As a result, the supply of the supply voltage Vco is stopped, and the circuit returns to the non-power supply state.

  As described above, the opening / closing of the cover and the temperature change during the power saving mode are stored in the nonvolatile storage device, and the cover opening / closing or temperature is changed based on the stored contents of the nonvolatile storage device when returning from the power saving mode. When it is determined that there has been a change, misalignment correction control can be performed. In other words, even if power is not supplied to the CPU during the power saving mode, misalignment correction control can be performed when returning to the power saving mode, thereby reducing power consumption during power saving and when there is no cover open / close and temperature change. By not performing misregistration correction control, unnecessary toner consumption can be reduced, and running costs can be reduced.

  1, 2, 3, 4 ... PNP transistor, 6, 7 ... NPN transistor, 5, 105 ... Cover open / close detection switch, 8, 9, 10, 11 ... Resistance, 100 ... System DESCRIPTION OF SYMBOLS 101 ... Power-saving mode transition determination part 102 ... Power-saving mode signal generation part 103 ... Power supply ON / OFF control part 104 ... Cover opening / closing detection signal generation part 106 ... CPU , 108... Nonvolatile memory device control unit, 109... Nonvolatile memory device, 110... Power saving mode power generation unit, 111... Real time clock IC, 112. , 113... Battery, 114... AD converter, 115.

JP 2006-159740 A

Claims (7)

In the image forming apparatus that shifts from the normal mode to the power saving mode when not in use for a predetermined time,
Cover opening detection means for detecting that the cover of the image forming apparatus is opened in the power saving mode, and power supply for supplying power to the storage control means when the cover opening detection means in the power saving mode detects the cover opening And a storage device that records the opening of the cover by the storage control means, and a determination to access the storage device and determine whether the cover is open during the power saving mode when returning from the power saving mode to the normal mode. And an image forming apparatus. The image forming apparatus according to claim 1,
Temperature detecting means for detecting the temperature inside the image forming apparatus in the power saving mode;
Means for outputting an alarm signal,
The power supply means supplies power to the storage control means when receiving the alarm signal, and the storage control means stores the temperature detected by the temperature detection means when an alarm signal is generated. Image forming apparatus. The image forming apparatus according to claim 1,
An optical unit; a photoreceptor positioned with respect to the optical unit;
An image forming apparatus, comprising: a correcting unit that executes a positional deviation correction between the optical unit and the photosensitive member when the determining unit determines that the cover is opened during the power saving mode. The image forming apparatus according to claim 2,
An optical unit; a photoreceptor positioned with respect to the optical unit;
When the determination unit determines that the cover is opened during the power saving mode or when it is determined that the temperature change during the power saving exceeds a predetermined value, the correction for performing the positional deviation correction between the optical unit and the photosensitive member And an image forming apparatus. The image forming apparatus according to claim 1, wherein:
The image forming apparatus according to claim 1, wherein the temperature detection unit is supplied with power from the power supply unit in a power saving mode. The image forming apparatus according to claim 3 or 4, wherein:
When returning from the power saving mode to the normal mode, the determining means does not perform correction by the correcting means when it is determined that there is no cover open or predetermined temperature change during the power saving mode. Image forming apparatus. The image forming apparatus according to any one of claims 1 to 6,
The image forming apparatus, wherein the storage device is a nonvolatile storage device.

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