JP2011192135A - Data reception system and interruption execution method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data reception system and an interruption execution method for transmitting data to a data receiver with optional timing efficiently and reliably without missing the data by using asynchronous interruption request signals from a plurality of data output devices. <P>SOLUTION: The data reception system includes: a data buffer circuit part for temporarily holding a plurality of data from a plurality of data output devices; an interruption routine means for determining whether data are held with all the data output devices when interruption signals are received, and sequentially receiving input data; a priority data determination circuit part for obtaining data from the data buffer circuit part in response to the interruption request signals, determining order of priority of the data, and rearranging them; a rearranged data buffer circuit part for temporarily holding a plurality of rearranged data; and a CPU for obtaining data from the rearranged data buffer circuit part in response to the interruption request signals. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data receiving system and an interrupt execution method for receiving data output asynchronously from a plurality of data output devices that output prioritized data without missing at an arbitrary timing.

  Increasing numbers of computers are incorporated into systems as data computing devices. As the system becomes larger and faster, information transmission between subsystems constituting the system has become more complicated. In a complicated system, data output asynchronously from a plurality of subsystems often occurs at an arbitrary timing. For this reason, it is desired that data transmission / reception between subsystems be performed efficiently and reliably and more simply.

  Generally, interrupt processing is known as means for efficiently receiving data from a data output device. The interrupt process is to interrupt a process being executed and perform another process with a higher priority. Specifically, when data output from the data output device is performed, a data transfer request signal is sent to the CPU in the data receiving device such as a computer, and when the CPU receives the data transfer request signal This is a series of processing in which a program being executed is interrupted, processing corresponding to the data output device called an interrupt routine is performed, and when the processing is completed, the CPU resumes processing of the interrupted portion of the program. .

  Interrupt processing is superior to polling processing, which is a method for periodically checking whether or not data is received, because efficient and accurate data acquisition can be realized relatively easily.

  However, in a system having a plurality of data output devices, there is a possibility that some interrupt processing may be lost when interrupts are generated almost simultaneously from the respective data output devices.

  For example, a plurality of reception processing devices that receive data from a plurality of communication lines, and a plurality of reception processing devices that are provided corresponding to each of the plurality of reception processing devices and store received data from these reception processing devices in response to control signals A storage device, an interrupt generation device that periodically outputs an interrupt signal simultaneously to the plurality of reception processing devices, and a notification signal that is output when a preset one of the plurality of reception processing devices is received, A reception data acquisition system is known that includes a reception data acquisition unit that collects and synthesizes the reception data accumulated in a plurality of storage devices (see Patent Document 1).

  As described above, there is a method for acquiring data from a plurality of data output devices, but there are the following problems. Since there are a plurality of data reception processing devices and a reception data acquisition unit for synthesizing the data acquired by the reception processing devices is required, the system is complicated.

  In addition, when prioritized data is output from a plurality of data output devices, there is a problem that data cannot be acquired according to the priority.

  If the same operation can be performed on the entire system in a simpler manner, it will lead to a reduction in system development time, a reduction in the frequency of system errors, and easier development of a larger system.

JP-A-9-83607

  An object of the present invention is to provide a data reception system and an interrupt execution method for transmitting data to a data reception device at an arbitrary timing efficiently and reliably without omission using asynchronous interrupt request signals from a plurality of data output devices. The purpose is to provide.

  It is another object of the present invention to provide a data receiving system and an interrupt execution method for receiving data having a high priority from a plurality of data output devices that output prioritized data to a data receiving device.

In order to solve the above problems, the invention according to claim 1 is a data receiving system that asynchronously receives interrupt request signals and data from a plurality of data output devices,
A data buffer circuit unit that acquires interrupt request signals and received data from the plurality of data output devices, and temporarily holds the plurality of data;
When receiving an interrupt signal from the data output device, it is determined whether data is input to all the data output devices, interrupt routine means for sequentially receiving the input data,
A priority data determination circuit unit that acquires data from the data buffer circuit unit according to the interrupt request signal, determines a data priority order, and rearranges the data.
A plurality of data for which the priority data determination circuit unit has determined the priority order, a rearranged data buffer circuit unit that temporarily holds data, and
A data receiving system comprising: a CPU that acquires data from the rearranged data buffer circuit unit in response to the interrupt request signal.

The invention according to claim 2 is an interrupt execution method in a data receiving system for temporarily holding a plurality of data acquired from a data output device in a data buffer circuit unit,
When the data buffer circuit unit receives an interrupt request signal from the data output device, it interrupts the priority data determination circuit unit, whether or not data is input to all data output devices, and data priority After determining the order and rearranging the data from the high priority data, the data is transmitted to the rearranged data buffer circuit unit, and the CPU responds to the interrupt request signal and all the data from the data buffer circuit unit The interrupt execution method is characterized in that the processing is performed until the data reception is completed.

  According to the present invention, in a system that receives an interrupt request or data asynchronously from a plurality of data output devices, an interrupt request signal from the plurality of data output devices is used to efficiently and reliably transmit data without interruption. Data can be transmitted to the receiving device at an arbitrary timing.

  In addition, it is possible to transmit data from a plurality of data output devices to the data receiving device at an arbitrary timing efficiently and surely in order from the data with the higher priority.

In addition, since the configuration is simple, the development time can be reduced, the frequency of error occurrence can be suppressed, and the development of a larger system can be facilitated.

It is a block diagram which shows an example of the system which concerns on embodiment of this invention. In the system which concerns on embodiment of this invention, it is a block diagram which shows the structure for a data buffer circuit part to transmit data reliably to a priority data judgment circuit part. It is a figure which shows the flowchart of a process from generation | occurrence | production of an interruption request signal to acquisition of reception data by software in CPU in the system concerning embodiment of this invention. It is a figure which shows the time chart in the process in case data is hold | maintained at three data buffer circuit parts in the system which concerns on embodiment of this invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an example of a system according to an embodiment of the present invention. The following embodiments are not intended to limit the application of the present invention or its uses.

  As shown in FIG. 1, the data output circuit 11 is connected to the input terminal of the data buffer circuit unit 21 through the interrupt request signal transmission path 51 and the data transmission path 52. The priority data determination circuit unit 31 is connected to the output terminal of the data buffer circuit unit 21 through the interrupt request signal transmission line 53 and the data transmission line 54. The priority data determination circuit unit 31 is interrupted through the interrupt request signal transmission path 53. .., 2N are connected to the input terminal of the priority data determination circuit unit 31 through the interrupt request signal transmission line 53 and the data transmission line 54. The rearranged data buffer circuit section 32 is connected to the output terminal of the priority data determination circuit section 31 through the interrupt request signal transmission path 55 and the data transmission path 56. The priority data determination circuit unit 31 is connected to the input terminal of the rearranged data buffer circuit unit 32 through the interrupt request signal transmission line 55 and the data transmission line 56. The CPU 41 is connected to the output terminal of the rearranged data buffer circuit unit 32 through the interrupt request signal transmission path 57 and the data transmission path 58. The CPU 41 is interrupted via the interrupt request signal transmission path 57.

  The priority data determination circuit unit 31 receives an interrupt request signal for data output from the plurality of data output devices 11, 12,..., 1N, and asynchronously receives priority from the data buffer circuit units 21, 22,. The order of descending order is determined, and data is transmitted to the rearranged data buffer circuit unit in descending order of priority. The data buffer circuit units 21, 22,..., 2N receive interrupt request signals from the plurality of data output devices 11, 12,..., 1N, and cause the priority data determination circuit unit 31 to generate an interrupt. The data output devices 11, 12,..., 1N are temporarily held.

  The rearranged data buffer circuit unit 32 temporarily holds data in the order of higher priority, receives an interrupt request signal from the priority data determination circuit unit 31, and causes the CPU 41 to generate an interrupt. Is. The CPU 41 receives the interrupt request signal from the rearranged data buffer circuit unit 32 and acquires data.

The number of data output devices 11, 12,..., 1N is N. As long as there are no restrictions on the shape, size, etc. of the terminals of the transmission lines 51, 52 from the data output device 11, 12,. Note that the priority order of data is 1N,. In the processing of the priority data determination circuit unit 31 on the reading side and the software in the CPU 41, these are set in advance in order of priority from the target data output device to 1N,.
12, 11 and an identification number may be assigned. The allocation of the numbers does not limit the present invention and is merely an example. Any method can be used as long as the priority order can be grasped.

  FIG. 2 is a block diagram showing a configuration for the data buffer circuit unit 2N to reliably transmit data to the priority data determination circuit unit 31 in the system according to the embodiment of the present invention. The arrangement for the rearranged data buffer circuit unit to reliably transmit data to the CPU 41 is the same.

  As shown in FIG. 2, the data output device 1N writes the data to the data buffer circuit unit 2N. However, if the data buffer circuit unit is full, the data is overwritten at the next writing, and the old data is deleted. Disappear. Therefore, data loss is prevented by returning a FULL signal indicating whether or not the data is full to the data output device. Further, the priority data judgment circuit unit 31 is made to judge whether it is necessary to read by returning an EMPTY signal indicating whether or not it is empty.

  FIG. 3 is a diagram showing a flowchart of processing from generation of an interrupt request signal to saving received data in a data buffer circuit section in the system according to the embodiment of the present invention.

  As shown in FIG. 3, when an interrupt request signal is generated from an arbitrary data output device (S1), first, the data buffer circuit unit acquires the interrupt request signal (S2). Next, upon receiving an interrupt request signal, the priority data determination circuit unit 31 checks whether data is contained in the interrupt routine, that is, the data buffer circuit unit 2N corresponding to the interrupt request signal which is an interrupt routine means (S3). ). Subsequently, the priority data determination circuit unit 31 confirms whether data is stored in the data buffer circuit unit 2N holding the data with the highest priority (S5).

  In all the data buffer circuit units, it is determined whether the processing is completed from the highest priority, that is, whether a = N (S4) to 1 has been processed (S6). (S7). When the confirmation of all the data buffer circuit units is completed, the priority data determination circuit unit 31 grasps the priority order of the data stored in the data buffer circuit unit (S8). The priority data determination circuit unit 31 moves the data from the data buffer circuit unit containing the data with high data priority to the rearranged data buffer circuit unit 32 (S9). The priority data determination circuit unit 31 transmits an interrupt request signal to the CPU 41 (S10). When the interrupt request signal is received, the software in the CPU 41 acquires data from the rearranged data buffer circuit unit 32 (S11). Then, the CPU 41 performs other processing until an interrupt request signal is input again.

  FIG. 4 is a diagram showing a time chart in processing when data is held in three data buffer circuit units in the system according to the embodiment of the present invention.

  As shown in FIG. 4, reference numeral 81 denotes an interrupt request signal waveform. When the signal is rising (arrow 101), the data buffer circuit unit 21 receives the interrupt request signal. At this time, it is confirmed whether there is data in another data buffer circuit unit, and another interrupt request signal is also received. In the figure, 107 indicates the transition of time T.

Reference numerals 82, 83 and 84 denote data held in the data buffer circuit sections 21, 22 and 23. The priority data determination circuit 31 receives the interrupt request signal and confirms the presence / absence of data in the corresponding data buffer circuit unit 21 and all other data buffer circuit units. The confirmation order of the data buffer circuit unit is set as the priority order, and confirmation is performed from the data buffer circuit units 2N to 21 (arrows 102, 103, and 104 indicate the timing of retrieving data).

  When the confirmation of the presence / absence of data in all the data buffer circuit units is completed, the priority data determination circuit 31 writes the data from the data with the highest priority to the rearranged data buffer circuit unit 32 (arrow 105). Indicates the timing to acquire data). As described above, the data priorities are the data input to the data buffer circuit units 2N,. The priority data determination circuit unit 31 transmits an interrupt request signal to the CPU 41.

  Next, when the software in the CPU 41 receives an interrupt request signal, the software in the CPU 41 acquires data from the rearranged data buffer circuit unit 32 (arrow 106 indicates the timing for acquiring data). Even if the interrupt request signals are inputted almost simultaneously, when the priority data determination circuit unit 31 receives the first one, all the data buffer circuit units are checked so that data can be dropped. Will never happen.

  As described above, according to the data receiving system and the interrupt execution method of the present invention, an asynchronous interrupt request signal from a plurality of data output devices can be used to ensure that the data buffer circuit unit is arbitrarily and efficiently free from loss. Data can be transmitted at the timing. In addition, it is possible to prioritize data with higher priority from a plurality of prioritized data output devices, and efficiently and reliably transmit data to the CPU at an arbitrary timing. In addition, since the configuration is simple, development time can be reduced, the frequency of error occurrence can be reduced, and further large-scale systems can be easily developed.

11 to 1N, data output devices 21 to 2N, data buffer circuit section
31 ... Priority data determination circuit unit 32 ... Rearranged data buffer circuit unit 41 ... CPU
51, 53, 55, 57... Interrupt request signal transmission paths 52, 54, 56, 58... Data transmission path 101... Arrows 102 and 103 indicating the rising timing of interrupt request signals from the data output device , 104... Arrows 105 indicating the timing for obtaining data, 106... Arrows indicating the timing for acquiring data 107.

Claims (2)

A data receiving system that asynchronously receives interrupt request signals and data from a plurality of data output devices,
A data buffer circuit unit that acquires interrupt request signals and received data from the plurality of data output devices, and temporarily holds the plurality of data;
When receiving an interrupt signal from the data output device, it is determined whether data is input to all the data output devices, interrupt routine means for sequentially receiving the input data,
A priority data determination circuit unit that acquires data from the data buffer circuit unit according to the interrupt request signal, determines a data priority order, and rearranges the data.
A plurality of data for which the priority data determination circuit unit has determined the priority order, a rearranged data buffer circuit unit that temporarily holds data, and
A data receiving system comprising: a CPU that acquires data from the rearranged data buffer circuit unit in response to the interrupt request signal. An interrupt execution method in a data receiving system for temporarily holding a plurality of data acquired from a data output device in a data buffer circuit unit,
When the data buffer circuit unit receives an interrupt request signal from the data output device, it interrupts the priority data determination circuit unit, whether or not data is input to all data output devices, and data priority After determining the order and rearranging the data from the high priority data, the data is transmitted to the rearranged data buffer circuit unit, and the CPU responds to the interrupt request signal and all the data from the data buffer circuit unit An interrupt execution method characterized in that the processing is performed until the data reception ends.

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