JP2011187759A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which an insulating film is surely left in a trench, and a method of manufacturing the same. <P>SOLUTION: After a gate electrode is formed in the trench, an insulating film partially including an insulating film with reflow properties is formed and its surface is flattened. The flattened surface is polished thereafter by a CMP method and the trench is thereby filled with the insulating film. At this time, the surface of a field oxide film is also polished. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a MOSFET type semiconductor device having a trench gate structure and a method for manufacturing the same, and more particularly to a low power consumption and high reliability semiconductor device and a method for manufacturing the same.

  FIG. 16 shows an example of a MOSFET type semiconductor device having a conventional trench gate structure. 17 and 18 show a method for manufacturing the MOSFET type semiconductor device of FIG. As shown in FIG. 16, a conventional MOSFET type semiconductor device includes an n-type semiconductor substrate 31 to be a drain region, an n-type semiconductor layer 32 formed thereon by epitaxial growth, and a channel region provided in the n-type semiconductor layer 32. A p-type semiconductor region 33 serving as a base region containing n, an n-type semiconductor region 34 serving as a source region provided in the p-type semiconductor region 33, and penetrating the n-type semiconductor region 34 and the p-type semiconductor region 33 from the surface. A gate oxide film 36 made of a thermal oxide film formed in the trench 35 formed to reach the n-type semiconductor layer 32, a gate electrode 37 formed in the trench 35 via the gate oxide film 36, and a trench 35, an insulating film 38 formed on the gate electrode 37, a contact region formed on the semiconductor region and the insulating film 38, and a part of the insulating film 38 is removed. And a source electrode 40 connected to the n-type semiconductor region 34 serving as the source region through le 39. A drain electrode (not shown) is formed on the back surface of the n-type semiconductor substrate.

  The semiconductor device having such a structure is formed as follows. First, the n-type semiconductor layer 32 is epitaxially grown on the n-type semiconductor substrate 31 to be the drain region. Thereafter, a p-type semiconductor region 33 to be a base region including a channel region is formed on the surface of the n-type semiconductor layer 32 by, for example, an ion implantation method or a thermal diffusion method. Further, an n-type semiconductor region 34 to be a source region is selectively formed on a part of the surface of the p-type semiconductor region 33 (FIG. 17a).

  Next, a trench 35 that penetrates the n-type semiconductor region 34 and the p-type semiconductor region 33 and reaches the n-type semiconductor layer 32 is formed by a normal photolithography method. The surface shape of the trench 35 is formed in a stripe shape (FIG. 17b).

  Next, the exposed surface is thermally oxidized to form a thermal oxide film 36 (FIG. 17c). This thermal oxide film 36 becomes a gate oxide film.

  A thick n-type polysilicon layer 37 doped with an impurity such as phosphorus (P) is formed on the entire surface, filling the trench 35 and flattening (FIG. 17d). The polysilicon layer 37 becomes a gate electrode.

  Then, the polysilicon layer 37 is buried in the trench 35 by anisotropic dry etching of the polysilicon layer 37 to form a gate electrode. At this time, over-etching is performed so as not to leave a polysilicon layer on the thermal oxide film on the surface. As a result, the surface of the gate electrode is formed to be substantially the same as or lower than the surface of the p-type semiconductor region 33 (FIG. 18a).

  After an extraction electrode (not shown) connected to the gate electrode is formed, an interlayer insulating film 38 is formed on the entire surface (FIG. 18b).

  After forming the contact hole 39 (FIG. 18c), the source electrode 40 is formed. A drain electrode (not shown) is formed on the back surface of the n-type semiconductor substrate 31 to complete the semiconductor device. In FIG. 18c, reference numeral 41 denotes a base contact diffusion layer.

  In this type of semiconductor device, in order to reduce the on-resistance, it is necessary to increase the effective gate width by narrowing the cell pitch interval. However, in the semiconductor device having the structure shown in FIG. 16, since the contact hole 39 is formed by a normal photolithography method, it is necessary to consider a margin for mask alignment. The limit of the trench cell pitch by a normal photolithography method is about 2.5 to 3.0 μm, and the on-resistance cannot be reduced.

  Therefore, the applicant of the present application has proposed a semiconductor device having a trench structure shown in FIG. 19 (Patent Document 1). In this semiconductor device, since a trench is filled with a TEOS film 42 which is an insulating film and a reflowable BPSG film 43, a desired structure is formed by an etch back method by dry etching.

JP 2009-224458 A

  The conventional semiconductor device has a problem that it is difficult to reduce the cell pitch in order to reduce the on-resistance. On the other hand, since the manufacturing method of forming an insulating film in the trench in the manufacturing method of the semiconductor device previously proposed by the applicant of the present application is performed by the etch-back method by dry etching, the trench width variation in the wafer surface, Due to variations in the depth of the trench, variations in the thickness of the insulating film, and non-uniformity in the etching rate, there is a problem in that variations in the wafer surface of the insulating film remaining in the trench occur. Further, there is a problem that the insulating film remaining in the trench also varies due to variations in the end point of dry etching. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems and can reliably leave an insulating film in a trench.

  In order to achieve the above object, according to a first aspect of the present invention, in a semiconductor device having a trench gate structure, a first conductivity type semiconductor substrate and a first conductivity type epitaxial layer stacked on a main surface of the semiconductor substrate are provided. A first conductivity type first semiconductor region formed on the surface of the epitaxial layer, a first conductivity type second semiconductor region formed on a part of the surface of the first semiconductor region, and the surface of the epitaxial layer From at least the first semiconductor region to reach the epitaxial layer, a gate oxide film formed on the surface of the semiconductor region in the trench, and the surface in the trench via the gate oxide film A gate electrode filled so as to be located on a surface side of a bottom surface portion where the first semiconductor region and the second semiconductor region are joined, and the gate in the trench. An insulating film including a reflowable insulating film at least partially filled on the first electrode, a source electrode connected to the second semiconductor region, a drain electrode connected to the semiconductor substrate, and an outer periphery of the semiconductor device. Surrounding first and second semiconductor region surfaces exposed at the surface, the surface of the second semiconductor region, the surface of the insulating film filled in the trench, and the surface of the field oxide film are equal in height. It is characterized by that.

  According to a second aspect of the present invention, in a method of manufacturing a semiconductor device having a trench gate structure, a step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate and a field partitioning the semiconductor device formation region A step of forming an oxide film, a step of forming a first semiconductor region of the second conductivity type on the surface of the first conductivity type epitaxial layer, and a portion of the surface of the first semiconductor region of the second conductivity type; Forming a second semiconductor region of the first conductivity type, forming a trench penetrating at least the first semiconductor region from the surface of the epitaxial layer and reaching the epitaxial layer, and a semiconductor region exposed in the trench A step of forming a gate oxide film on the surface, and after the conductive film to be a gate electrode is filled in the trench, the conductive film is etched back A step of forming the gate electrode so that the surface of the gate electrode is located in the trench and above the bottom surface where the first semiconductor region and the second semiconductor region are joined; and Forming a first insulating film; forming a reflowable second insulating film on the first insulating film; and performing a heat treatment to planarize the surface; and Polishing and removing at least part of the second insulating film, the first insulating film, and the field oxide film, the second insulating film and the first insulating film are embedded in the trench, and exposed to the surface Exposing the surface of the first semiconductor region and the surface of the second semiconductor region, and forming a source electrode connected to the second semiconductor region and a drain electrode connected to the semiconductor substrate. It is characterized by.

  According to a third aspect of the present invention, in a method of manufacturing a semiconductor device having a trench gate structure, a step of forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate and a semiconductor device formation region are partitioned. Forming a field oxide film; forming a second conductive type first semiconductor region on the surface of the first conductive type epitaxial layer; and penetrating the first semiconductor region from the surface of the first semiconductor region. A step of forming a trench reaching the epitaxial layer, a step of forming a gate oxide film on the surface of the semiconductor region exposed in the trench, and a conductive film serving as a gate electrode in the trench, A step of forming a gate electrode by etching back the conductive film, a step of forming a first insulating film on the entire surface, and a reflow property on the first insulating film. After the second insulating film is formed, heat treatment is performed to planarize the surface, and the planarized surface is polished to at least one of the second insulating film, the first insulating film, and the field oxide film. Removing the portion, the second insulating film and the first insulating film are embedded in the trench, exposing the surface of the first semiconductor region, and a part of the exposed surface of the first semiconductor region, A step of forming a second semiconductor region of the first conductivity type so that a bottom surface portion joined to the first semiconductor region is deeper than the surface of the gate electrode; and a source electrode connected to the second semiconductor region; And a step of forming a drain electrode connected to the semiconductor substrate.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a semiconductor device having a sufficiently large gate-source breakdown voltage that can reliably leave an insulating film in a trench even when the cell pitch is narrowed. It becomes possible.

  Further, since the field oxide film protruding from the surface is usually removed, there is an advantage that a semiconductor device with good flatness can be formed.

It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining the manufacturing method of the semiconductor device of this invention. It is a figure explaining another semiconductor device of the present invention. It is a figure explaining the cross section according to semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a figure explaining this kind of conventional semiconductor device. It is a figure explaining the manufacturing method of a semiconductor device to this kind of conventional. It is a figure explaining the manufacturing method of this kind of conventional semiconductor device. It is a figure explaining another conventional semiconductor device.

  Hereinafter, the present invention will be described in detail according to the manufacturing process of a MOSFET type semiconductor device. In the following description, a MOSFET in which n-type regions and p-type regions are alternately formed in a stripe shape and a trench is formed so as to intersect with the n-type region and p-type region as in the MOSFET type semiconductor device shown in the plan view of FIG. A type semiconductor device will be described with reference to a cross-sectional view taken along line AA.

  First, the first embodiment will be described. An n-type semiconductor layer 2 is epitaxially grown on the n-type semiconductor substrate 1 serving as a drain region. In order to form a mask for forming a field oxide film that partitions the semiconductor device formation region, an oxide film 3 and a nitride film 4 are formed on the surface of the n-type semiconductor layer 2 (FIG. 1).

  A photoresist 5 is formed on the nitride film 4 and a field oxide film formation planned region is opened, and then the photoresist 5 is used as an etching mask to expose the exposed nitride film 4, oxide film 3 and n-type semiconductor layer 2. The surface is anisotropically etched (FIG. 2). Here, the etching depth of the surface of the n-type semiconductor layer 2 is adjusted so that the formation position of the lower surface of the field oxide film formed thereafter reaches a desired depth described later.

  The photoresist 5 is removed, and a field oxide film 6 is formed by thermal oxidation (FIG. 3). For example, when the etching depth of the surface of the n-type semiconductor layer 2 is 0.2 μm and a field oxide film having a thickness of 0.75 μm is formed, the lower surface of the field oxide film 6 is about 0.55 μm deeper than the surface of the n-type semiconductor layer 2. The upper surface of the field oxide film 6 is about 0.2 μm higher than the surface of the n-type semiconductor layer 2.

  Note that the field oxide film 6 may be formed of a thick first field oxide film 6a and a thin second field oxide film 6b, like the field oxide film of the semiconductor device shown in FIG. In this way, the field oxide films having different thicknesses are formed by forming the first field oxide film 6a, forming another mask for forming the field oxide film, and performing heat treatment thereafter. Field oxide film 6b is formed. Alternatively, after the formation of the first field oxide film 6a, phosphorus is ion-implanted selectively in a region where the second field oxide film is to be formed under conditions of relatively high concentration and high acceleration energy, and thermal oxidation is performed. Thus, the second field oxide film 6b can be formed. Thus, the structure including the second field oxide film 6b has an advantage that the strain stress from the edge of the first field oxide film 6a can be reduced.

After the nitride film 4 is removed, p-type impurities are ion-implanted into the surface of the n-type semiconductor layer 2 to form a p-type semiconductor region 7 serving as a base region including a channel region. Then, TEOS (Tetra
Ethyl Ortho Silicate) film 8 is formed (FIG. 4). In this embodiment, the TEOS film 8 is formed without forming the n-type semiconductor region constituting the source region. However, after the p-type semiconductor region 7 is formed, the n-type impurity is subsequently ion-implanted. After forming the source region, the TEOS film 8 may be formed.

  The TEOS film 8 on the trench formation planned region is removed by a normal photolithography method to expose the surface of the p-type semiconductor region 7 in the trench formation planned region (FIG. 5). Note that when the n-type semiconductor region (source region) is formed first, the n-type semiconductor region and the p-type semiconductor region 7 are exposed.

  Using the TEOS film 8 as an etching mask, the exposed p-type semiconductor region 7 and part of the n-type semiconductor layer 2 are removed by etching to form a trench 9 (FIG. 6).

  After removing the TEOS film 8, the exposed surface is thermally oxidized to form a thermal oxide film 10 (FIG. 7). This thermal oxide film 10 becomes a gate oxide film.

  A thick n-type polysilicon layer doped with an impurity such as phosphorus is formed on the entire surface, and the trench 9 is filled and flattened. Thereafter, the polysilicon layer is embedded in the trench 5 by anisotropic dry etching of the polysilicon layer, and the gate electrode 11 can be formed. At this time, over-etching is performed so as not to leave a polysilicon layer on the thermal oxide film 10 on the surface. Further, the surface of the gate electrode 11 in the trench 9 is positioned on the surface side of the junction (bottom portion of the junction) between the n-type semiconductor region to be a source region and the p-type semiconductor region 7 to be a base region formed in a later process. To do. Further, the interlayer insulating film is left in the trench so as to ensure the gate-source breakdown voltage, so that it is lower than the surface of the p-type semiconductor region 7 (FIG. 8). When the n-type semiconductor region to be the source region is formed first, the junction surface between the n-type semiconductor region and the p-type semiconductor region is disposed below the surface of the gate electrode 11 in the trench.

  After the surface of the gate electrode 11 exposed in the trench is oxidized to form an oxide film 12, a TEOS film 13 having a thickness of about 0.2 μm and a BPSG film 14 having a thickness of about 1.0 μm are formed as an interlayer insulating film. The BPSG film 14 is formed by a CVD method and then flows by heat treatment, and the entire surface can be flattened (FIG. 9).

  Thereafter, in the present invention, the surface is polished by CMP (Chemical Mechanical Polishing) to expose the surface of the p-type semiconductor region 7 (FIG. 10). At this time, since the TEOS film 13 and the BPSG film 14 remain on the surface of the trench 9, the insulation between the gate electrode 11 and the source and drain regions can be kept stable. In particular, in the present invention, since the surface is polished by the CMP method instead of the conventional etch back method, the TEOS film 13 and the BPSG film 14 can be surely left in the trench 9. It is possible to prevent the variation in the breakdown voltage between the gate and the source of the MOSFET due to the variation in the. Further, the present invention has an advantage that the surface of the field oxide film 6 can be polished and planarized by polishing the surface. Note that when the n-type semiconductor region is formed first, the surface of the n-type semiconductor region is also polished.

  After phosphorus or arsenic is ion-implanted into the surface of the p-type semiconductor region 7, a heat treatment for activation is performed to form an n-type semiconductor region 15 to be a source region (FIG. 11).

  On the surface, a source electrode 16 made of aluminum and an extraction electrode (not shown) for a gate electrode are formed. Thereafter, a passivation film 17 is formed on the surface, the n-type semiconductor substrate 1 is made to have a desired thickness, and then a drain electrode 18 is formed, whereby a MOSFET type semiconductor device is completed (FIG. 12).

  FIG. 14 is a cross-sectional view taken along line BB in the cross-sectional view shown in FIG. 15, and shows the structure of the extraction electrode 19 of the gate electrode 11 formed in the trench. As shown in FIG. 14, since the present invention is planarized by the CMP method, the surface of the fold oxide film 6 is also polished, and a method for manufacturing a semiconductor device with good planarity can be provided.

  13, the same structure can be formed by the same manufacturing method except that the field oxide films 6a and 6b are formed by the above-described manufacturing method.

1; n-type semiconductor substrate, 2; n-type semiconductor layer, 3; oxide film, 4; nitride film, 5; photoresist, 6, 6a, 6b; field oxide film, 7; p-type semiconductor region, 8; 9; trench 10; thermal oxide film 11; gate electrode 12; oxide film 13; TEOS film 14; BPSG film 15; n-type semiconductor region 16; source electrode 17; passivation film 18; Drain electrode 19; Lead electrode

Claims (3)

In a semiconductor device having a trench gate structure,
A first conductivity type semiconductor substrate;
An epitaxial layer of a first conductivity type stacked on the main surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type formed on the surface of the epitaxial layer;
A second semiconductor region of a first conductivity type formed on a part of the surface of the first semiconductor region;
A trench that penetrates at least the first semiconductor region from the surface of the epitaxial layer and reaches the epitaxial layer;
A gate oxide film formed on the surface of the semiconductor region in the trench;
A gate electrode filled in the trench through the gate oxide film so that the surface is located on the surface side from the bottom surface where the first semiconductor region and the second semiconductor region are joined;
An insulating film including a reflowable insulating film at least partially filled on the gate electrode in the trench;
A source electrode connected to the second semiconductor region, a drain electrode connected to the semiconductor substrate,
A field oxide film surrounding the outer periphery of the semiconductor device,
At least the first semiconductor region surface exposed to the surface, the second semiconductor region surface, the insulating film surface filled in the trench, and the field oxide film surface have the same height. In a method for manufacturing a semiconductor device having a trench gate structure,
Forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate;
Forming a field oxide film partitioning a semiconductor device formation region;
Forming a second conductive type first semiconductor region on a surface of the first conductive type epitaxial layer;
Forming a second semiconductor region of the first conductivity type on a portion of the surface of the first semiconductor region of the second conductivity type;
Forming a trench that penetrates at least the first semiconductor region from the surface of the epitaxial layer and reaches the epitaxial layer;
Forming a gate oxide film on the surface of the semiconductor region exposed in the trench;
After the trench is filled with a conductive film to be a gate electrode, the conductive film is etched back so that the surface of the gate electrode is in the trench, and the first semiconductor region and the second semiconductor region are etched. Forming a gate electrode so as to be located above the bottom surface where the semiconductor region is joined;
Forming a first insulating film on the entire surface;
Forming a reflowable second insulating film on the first insulating film, and then performing a heat treatment to planarize the surface;
The planarized surface is polished, and at least a part of the second insulating film, the first insulating film, and the field oxide film is removed, and the second insulating film and the first insulating film are placed in the trench. Exposing the surface of the first semiconductor region, the surface of the second semiconductor region that is buried and exposed on the surface;
Forming a source electrode connected to the second semiconductor region and a drain electrode connected to the semiconductor substrate. In a method for manufacturing a semiconductor device having a trench gate structure,
Forming a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate;
Forming a field oxide film partitioning a semiconductor device formation region;
Forming a second conductive type first semiconductor region on a surface of the first conductive type epitaxial layer;
Forming a trench that penetrates the first semiconductor region from the surface of the first semiconductor region and reaches the epitaxial layer;
Forming a gate oxide film on the surface of the semiconductor region exposed in the trench;
A step of forming a gate electrode by filling the conductive film to be a gate electrode in the trench and then etching back the conductive film;
Forming a first insulating film on the entire surface;
Forming a reflowable second insulating film on the first insulating film, and then performing a heat treatment to planarize the surface;
The planarized surface is polished, and at least a part of the second insulating film, the first insulating film, and the field oxide film is removed, and the second insulating film and the first insulating film are placed in the trench. Embedding and exposing the surface of the first semiconductor region;
Forming a second semiconductor region of the first conductivity type in a part of the exposed surface of the first semiconductor region such that a bottom surface portion joined to the first semiconductor region is deeper than the surface of the gate electrode; When,
Forming a source electrode connected to the second semiconductor region and a drain electrode connected to the semiconductor substrate.

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