JP2011180259A - Liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device, capable of suppressing the reduction in productivity, and to provide a method of manufacturing the liquid crystal display device. <P>SOLUTION: The liquid crystal display device includes a first substrate, a second substrate arranged facedly to the first substrate, and a closed-loop sealing material for sticking the first substrate to the second substrate. The first substrate includes a first switching element and second switching element, a first color filter layer arranged on the first switching element, a second color filter layer that is arranged on the second switching element and forms a superposed section superposed on part of the first color filter layer, an insulating film that covers the first color filter layer and second color filter layer and has a recess formed immediately above the superposed section, a first pixel electrode that is arranged on the insulating film positioned above the first color filter layer and electrically connected to the first switching element, and a second pixel electrode that is arranged on the insulating film positioned above the second color filter layer and electrically connected to the second switching element. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a manufacturing method thereof.

  Liquid crystal display devices are utilized in various fields as display devices for OA equipment such as personal computers and televisions, taking advantage of features such as light weight, thinness, and low power consumption. In recent years, liquid crystal display devices are also used as mobile terminal devices such as mobile phones, display devices such as car navigation devices and game machines.

  In such a liquid crystal display device, a dropping injection method is known as a method for forming a liquid crystal layer between a pair of substrates. In this dropping injection method, a sealing material is applied to one substrate in a closed loop shape, then a liquid crystal material is dropped into the loop, the other substrate is overlapped, the liquid crystal material is spread to form a liquid crystal layer, and the sealing material is It cures.

  For example, according to Patent Document 1, the process of applying a seal material is a closed loop seal pattern for the problem that the seal material is difficult to come out at the beginning of drawing with a dispenser and is likely to become a stringed state at the end of drawing. A method for manufacturing a liquid crystal display element is disclosed which includes a step of starting drawing from an external location and finishing drawing at an external location of the closed loop seal pattern.

JP 2003-222883 A

  An object of the present invention is to provide a liquid crystal display device capable of suppressing a decrease in productivity and a manufacturing method thereof.

According to one aspect of the invention,
First and second switching elements, a first color filter layer disposed on the first switching element, and disposed on the second switching element and overlapping a part of the first color filter layer A second color filter layer forming the overlapping portion, an insulating film covering the first color filter layer and the second color filter layer and having a recess formed immediately above the overlapping portion, and the first color filter layer A first pixel electrode disposed on the insulating film located above and electrically connected to the first switching element; and disposed on the insulating film located above the second color filter layer. A second substrate electrically connected to the two switching elements; a second substrate disposed opposite to the first substrate; and the first substrate A closed loop sealing material for bonding the second substrate; and a liquid crystal layer held between the first substrate and the second substrate and surrounded by the sealing material. A liquid crystal display device is provided.

According to another aspect of the invention,
A first switching element and a second switching element are formed on the insulating substrate, a first color filter layer having a first contact hole is formed on the first switching element, and a first color filter layer is formed on the second switching element. Forming a second color filter layer that forms an overlapping portion that overlaps with a part of the first color filter layer, and that is formed on the first color filter layer and the second color filter layer; A resist is applied, and the resist located immediately above the first contact hole and the second contact hole is exposed with a first exposure amount, and the resist located immediately above the overlapping portion is defined as the first exposure amount. A through which is exposed with a different second exposure amount and communicated with the first contact hole and the second contact hole by the resist. The first pixel electrode electrically connected to the first switching element is formed on the insulating film located above the first color filter layer, and the second color filter layer is formed. A first substrate manufacturing step of forming a second pixel electrode electrically connected to the second switching element on the insulating film located above the color filter layer; and the first pixel electrode of the first substrate. And a step of applying a closed loop sealing material on the surface on which the second pixel electrode is formed, a step of dropping a liquid crystal material inside the first substrate surrounded by the sealing material, and the first substrate There is provided a method for manufacturing a liquid crystal display device comprising a step of bonding a second substrate.

  According to the present invention, it is possible to provide a liquid crystal display device capable of suppressing a decrease in productivity and a manufacturing method thereof.

FIG. 1 schematically shows a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a plan view schematically showing the structure of the array substrate of the liquid crystal display panel shown in FIG. FIG. 3 is a cross-sectional view schematically showing the structure of the liquid crystal display panel shown in FIG. FIG. 4 is a view for explaining the manufacturing method of the liquid crystal display device of the present embodiment, and is a schematic cross-sectional view for explaining a process of forming a switching element or the like on the first insulating substrate. FIG. 5 is a diagram for explaining the manufacturing method of the liquid crystal display device of this embodiment, and is a schematic cross-sectional view for explaining the steps of forming the first to third color filter layers on the first insulating substrate. is there. FIG. 6 is a diagram for explaining the manufacturing method of the liquid crystal display device of the present embodiment, and is a schematic cross-sectional view for explaining a step of applying a resist on the first to third color filter layers. FIG. 7 is a view for explaining the manufacturing method of the liquid crystal display device of this embodiment, and is a schematic cross-sectional view for explaining the step of exposing the applied resist. FIG. 8 is a diagram for explaining the manufacturing method of the liquid crystal display device of the present embodiment, and is a schematic cross-sectional view for explaining a step of forming an overcoat layer having a recess on the upper surface with an exposed resist. . FIG. 9 is a diagram for explaining the manufacturing method of the liquid crystal display device of this embodiment, and is a schematic cross-sectional view for explaining a process of forming an overcoat layer whose upper surface is flattened by an exposed resist. is there. FIG. 10 is a diagram for explaining the manufacturing method of the liquid crystal display device of this embodiment, and is a schematic cross-sectional view for explaining the step of applying a sealing material to the array substrate and the step of dropping the liquid crystal material thereafter. It is. FIG. 11 is a diagram for explaining the manufacturing method of the liquid crystal display device of this embodiment, and is a schematic cross-sectional view for explaining the step of bonding the array substrate and the counter substrate. FIG. 12 is a schematic plan view of each pixel in which the first to third color filter layers in the modification of the present embodiment are arranged. FIG. 13 is a schematic cross-sectional view of the first to third color filter layers and the overcoat layer at position A in the modification of the present embodiment shown in FIG.

  Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In each figure, the same reference numerals are given to components that exhibit the same or similar functions, and duplicate descriptions are omitted.

  FIG. 1 is a diagram schematically illustrating a configuration of a liquid crystal display device according to the present embodiment.

  That is, the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 and a flexible wiring board 3 connected to the liquid crystal display panel LPN, a backlight 4 that illuminates the liquid crystal display panel LPN, and the like. .

  The liquid crystal display panel LPN is held between an array substrate AR as a first substrate, a counter substrate CT as a second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown). The array substrate AR and the counter substrate CT are bonded together by a seal material 5. The sealing material 5 is formed in a substantially rectangular frame shape between the array substrate AR and the counter substrate CT.

  Such a liquid crystal display panel LPN is provided with a substantially rectangular active area ACT for displaying an image on the inner side surrounded by the seal material 5. This active area ACT is composed of a plurality of pixels PX arranged in an m × n matrix (where m and n are positive integers).

  In the illustrated example, the backlight 4 is disposed on the back side of the array substrate AR. As such a backlight 4, various forms are applicable, and any of those using a light emitting diode (LED) as a light source or a cold cathode tube (CCFL) is applicable. Description of the detailed structure is omitted.

  FIG. 2 is a schematic top view of the array substrate AR shown in FIG. 1 viewed from the counter substrate CT side. In FIG. 2, only the main parts necessary for the description are shown.

  First, the configuration of one pixel PX in the active area ACT will be described. The array substrate AR includes gate lines G and auxiliary capacitance lines C that extend along the first direction X, source lines S and gate lines G that extend along the second direction Y that intersects the first direction X, and A switching element SW and the like disposed near the intersection with the source line S are provided.

  In the active area ACT, the plurality of gate lines G and storage capacitor lines C are alternately arranged in parallel along the second direction Y. The plurality of source lines S are arranged in parallel along the first direction. Since the gate line G, the auxiliary capacitance line C, and the source line S are substantially orthogonal to each other, they are formed in a lattice shape and form a black matrix in the active area ACT. For example, the grid formed by the storage capacitor line C and the source line S corresponds to the opening of the pixel PX.

  Each switching element SW is configured by, for example, an n-channel thin film transistor (TFT). The switching element SW includes a semiconductor layer SC. The semiconductor layer SC can be formed of, for example, polysilicon or amorphous silicon, and is formed of polysilicon here.

  The gate electrode WG of the switching element SW is electrically connected to the gate line G. In the illustrated example, the gate electrode WG is formed integrally with the gate line G. The source electrode WS of the switching element SW is electrically connected to the source line S. In the illustrated example, the source electrode WS is formed integrally with the source line S. The drain electrode WD of the switching element SW is electrically connected to the pixel electrode PE.

  Such a gate electrode WG can be formed in the same process using the same conductive material as the gate line G and the auxiliary capacitance line C. The source electrode WS and the drain electrode WD can be formed in the same process using the same conductive material as the source line S and the like. These gate lines G and source lines S are formed of a low-resistance conductive material such as aluminum, molybdenum, tungsten, titanium, or the like. The conductive materials shown here are light-shielding materials that have extremely low light transmittance (or almost zero transmittance).

  The color filter layer CF is disposed on the switching element SW. Such a color filter layer CF includes a plurality of types of color filter layers colored in different colors. In the example shown here, as the color filter layer CF, for example, a first color filter layer CF1 made of a resin material colored in red, a second color filter layer CF2 made of a resin material colored in blue, and colored in green. A third color filter layer CF3 made of a resin material is disposed.

  These first to third color filter layers CF1 to CF3 extend along the second direction Y of the active area ACT. The first to third color filter layers CF1 to CF3 are alternately arranged in the first direction X. In the illustrated example, the first color filter layer CF1 is sequentially arranged from the left side to the right side of the active area ACT. The second color filter layer CF2, the third color filter layer CF3, the first color filter layer CF1,..., The third color filter layer CF3 are alternately arranged.

  Further, the first to third color filter layers CF1 to CF3 are disposed so as to overlap each other without being separated from each other. That is, the peripheral portion of the first color filter layer CF1 overlaps with the peripheral portion of the second color filter layer CF2 adjacent in the first direction X to form an overlapping portion. Similarly, the peripheral edge of the second color filter layer CF2 overlaps with the peripheral edge of the third color filter layer CF3 adjacent to the first direction X, and the peripheral edge of the third color filter layer CF3 is adjacent to the first direction X. The first color filter layer CF1 overlaps with the peripheral edge of the first color filter layer CF1 to form overlapping portions. These overlapping portions are located substantially immediately above the source line S in the illustrated example. For this reason, the conductive layers under the first to third color filter layers CF1 to CF3, for example, the source line S, the gate line G, and the auxiliary capacitance line C are not exposed, and the first to third color filter layers CF1 to CF3 are not exposed. It is possible to prevent occurrence of a short circuit when the pixel electrode PE is formed on the substrate.

  Each of the first to third color filter layers CF1 to CF3 is disposed so as to cover the switching elements SW of the pixels PX arranged in the second direction Y. A plurality of pixel electrodes PE arranged in the second direction Y are arranged on the first to third color filter layers CF1 to CF3. Each pixel electrode PE is electrically connected to the drain electrode WD of the switching element SW. Such a pixel electrode PE is arranged corresponding to the opening of each pixel PX.

  In the array substrate AR described above, the sealing material 5 is disposed outside the active area ACT. In the illustrated example, the sealing material 5 is formed in a rectangular frame shape along the outer periphery of the substantially rectangular active area ACT. In particular, the sealing material 5 is formed in a closed loop shape, and is different from a shape interrupted in the middle so as to secure a so-called injection port. In the illustrated example, the sealing material 5 is disposed on the surface of the array substrate AR where the pixel electrodes PE and the like are formed. However, the sealing material may be disposed on the surface of the counter substrate CT (not illustrated) facing the array substrate AR. .

  In the array substrate AR described above, the light shielding layer 6 is disposed outside the active area ACT and inside the sealing material 5. In the illustrated example, the light shielding layer 6 is formed in a rectangular frame shape along the outer periphery of the substantially rectangular active area ACT. Such a light shielding layer 6 is formed of a resin material colored in black, for example.

  The structure of the liquid crystal display panel LPN will be described in detail below.

  FIG. 3 is a schematic cross-sectional view of the liquid crystal display panel LPN when the array substrate AR shown in FIG. 2 is cut along the line AB in the drawing.

  The array substrate AR is formed using a first insulating substrate 10 having optical transparency such as a glass plate. The switching element SW includes a semiconductor layer SC formed on the first insulating substrate 10. The semiconductor layer SC has a source region SCS and a drain region SCD on both sides of the channel region SCC. An undercoat layer that is an insulating film may be interposed between the first insulating substrate 10 and the semiconductor layer SC. The semiconductor layer SC is covered with the gate insulating film 11. The gate insulating film 11 is also disposed on the first insulating substrate 10.

  The gate electrode WG is formed on the gate insulating film 11 and is located immediately above the channel region SCC of the semiconductor layer SC. The gate electrode WG is covered with the interlayer insulating film 12. The interlayer insulating film 12 is also disposed on the gate insulating film 11. The gate insulating film 11 and the interlayer insulating film 12 are formed of an inorganic material such as silicon oxide and silicon nitride, for example.

  The source electrode WS and the drain electrode WD of the switching element SW are formed on the interlayer insulating film 12. The source electrode WS is in contact with the source region SCS of the semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the interlayer insulating film 12. Similarly, the drain electrode WD is in contact with the drain region SCD of the semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the interlayer insulating film 12.

  A color filter layer is disposed on the switching element SW having such a configuration. That is, in the pixel PX1, the first color filter layer CF1 covers the source electrode WS and the drain electrode WD, and is also disposed on the interlayer insulating film 12, and further, two source lines adjacent to each other in the first direction X. Each also extends over S. The first color filter layer CF1 has a substantially tapered cross section. In the vicinity immediately above one of the two source lines S from which the first color filter layer CF1 extends, the third color filter layer CF3 overlaps the first color filter layer CF1, and the overlapping portion OL. Is forming. In such a first color filter layer CF1, a contact hole CH1 reaching the drain electrode WD of the switching element SW arranged in the pixel PX1 is formed.

  Similarly, in the pixel PX2, the second color filter layer CF2 is disposed. The second color filter layer CF2 overlaps the first color filter layer CF1 in the vicinity immediately above the source line S between the pixels PX1 and PX2 to form an overlapping portion OL. In the second color filter layer CF2, a contact hole CH2 reaching the drain electrode WD of the switching element SW disposed in the pixel PX2 is formed.

  Similarly, the third color filter layer CF3 is arranged in the pixel PX3. The third color filter layer CF3 overlaps the second color filter layer CF2 in the vicinity immediately above the source line S between the pixels PX2 and PX3 to form an overlapping portion OL. In the third color filter layer CF3, a contact hole CH3 reaching the drain electrode WD of the switching element SW disposed in the pixel PX3 is formed.

  In the illustrated overlapping portion OL, the first color filter layer CF1, the second color filter layer CF2, the second color filter layer CF2, the third color filter layer CF3, and the third color filter layer are located in the vicinity immediately above the source line S. Although it has a two-layer structure in which two kinds of color filter layers such as CF3 and first color filter layer CF1 are stacked, a three-layer structure in which first to third color filter layers CF1 to CF3 are stacked may be used. Further, the overlapping portion OL is not limited to the vicinity immediately above the source line S, but may be formed in the vicinity immediately above the gate line G or in the vicinity immediately above the storage capacitor line C.

  These first to third color filter layers CF1 to CF3 are covered with an overcoat layer 13 that is an insulating film, substantially including the overlapping portion OL. That is, the overcoat layer 13 is a portion of the first to third color filter layers CF1 to CF3 in which only the first color filter layer CF1 is disposed, that is, the first color filter layer CF1 and the second color filter layer CF2. An overlapping portion OL, a portion where only the second color filter layer CF2 is disposed, an overlapping portion OL between the second color filter layer CF2 and the third color filter layer CF3, a portion where only the third color filter layer CF3 is disposed; Are arranged on the respective upper surfaces of the overlapping portions OL of the third color filter layer CF3 and the first color filter layer CF1.

  A through hole TH is formed in the overcoat layer 13. The through holes TH communicate with contact holes CH1 to CH3 formed in the first to third color filter layers CF1 to CF3, respectively. Such an overcoat layer 13 is formed of, for example, a light-transmitting photoresist such as a positive resist.

  Such an overcoat layer 13 is formed substantially flat without protruding upward (that is, on the side of the counter substrate CT), or a recess is formed in part. In the illustrated example, in the overcoat layer 13, a recess 13C is formed immediately above the overlapping portion OL. In other words, the upper surface T1 of the overcoat layer 13 located immediately above the overlapping portion OL is recessed from the upper surface T2 of the overcoat layer 13 serving as a base on which the pixel electrode PE is disposed. Such a recess 13 </ b> C is located in the vicinity of directly above the source line S. When the first to third color filter layers CF1 to CF3 are formed in a pattern as shown in FIG. 2, the recess 13C extends in the second direction Y in the active area ACT and is formed in a stripe shape. . An example in which the upper surface of the overcoat layer 13 is substantially flat will be described later.

  The pixel electrode PE is disposed in each pixel PX in the active area ACT. That is, the pixel electrode PE is disposed on the overcoat layer 13. Such a pixel electrode PE is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  The pixel electrode PE disposed in the pixel PX1 is electrically connected to the drain electrode WD through the through hole TH formed in the overcoat layer 13 and the contact hole CH1 formed in the first color filter layer CF1. Similarly, the pixel electrode arranged in the pixel PX2 is electrically connected to the drain electrode through the through hole TH and the contact hole CH2. Similarly, the pixel electrode disposed in the pixel PX3 is electrically connected to the drain electrode through the through hole TH and the contact hole CH3.

  The surfaces of these pixel electrodes PE are covered with the first alignment film 14. That is, the first alignment film 14 is disposed on the surface of the array substrate AR facing the counter substrate CT, that is, the surface in contact with the liquid crystal layer LQ.

  A light shielding layer 6 is arranged outside the active area ACT of the array substrate AR, and a seal material 5 is arranged outside the light shielding layer 6.

  On the other hand, the counter substrate CT of the liquid crystal display panel LPN is formed using a second insulating substrate 30 having a light transmission property such as a glass plate. The counter substrate CT includes a counter electrode CE and the like on the second insulating substrate 30.

  The counter electrode CE is a continuous film and faces each pixel electrode PE via the liquid crystal layer LQ in the active area ACT. The counter electrode CE also extends outside the active area ACT, and a predetermined voltage is applied from the array substrate AR side via a conductive member (not shown) outside the seal material 5. Such a counter electrode CE is formed of a light-transmitting conductive material such as ITO or IZO.

  The surface of the counter electrode CE is covered with the second alignment film 31. That is, the second alignment film 31 is disposed on the surface of the counter substrate CT facing the array substrate AR, that is, the surface in contact with the liquid crystal layer LQ.

  The array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film 14 and the second alignment film 31 face each other. At this time, between the first alignment film 14 of the array substrate AR and the second alignment film 31 of the counter substrate CT, for example, a columnar spacer integrally formed on one substrate by a resin material is disposed. As a result, a predetermined gap, for example, a gap of 3 to 7 μm is formed. The array substrate AR and the counter substrate CT are bonded together with the seal material 5 in a state where a predetermined gap is formed.

  The liquid crystal layer LQ is enclosed in the cell gap described above. That is, the liquid crystal layer LQ is made of a liquid crystal material held between the pixel electrode PE of the array substrate AR and the counter electrode CE of the counter substrate CT. A first alignment film 14 is interposed between the liquid crystal layer LQ and the pixel electrode PE. A second alignment film 31 is interposed between the liquid crystal layer LQ and the counter electrode CE.

  A first polarizing plate PL1 is attached to one outer surface of the liquid crystal display panel LPN, that is, the outer surface of the first insulating substrate 10 constituting the array substrate AR with an adhesive or the like. A second polarizing plate PL2 is attached to the other outer surface of the liquid crystal display panel LPN, that is, the outer surface of the second insulating substrate 30 constituting the counter substrate CT with an adhesive or the like.

  Next, a method for manufacturing the above-described liquid crystal display panel LPN will be described.

  First, as shown in FIG. 4, a source line S, a gate line (not shown), and an auxiliary capacitance line are formed above the first insulating substrate 10 and a switching element SW is formed. Here, only the configuration necessary for the description is illustrated, the switching element SW is illustrated in a simplified manner, and the gate insulating film and the interlayer insulating film are omitted. The switching element SW is formed in each of the pixels PX1 to PX3.

  Subsequently, as shown in FIG. 5, a first color filter layer CF1 is formed on the pixel PX1. The first color filter layer CF1 is formed, for example, by forming a colored resin material on the entire upper surface of the first insulating substrate 10 and then patterning it into a desired shape through a photolithography process. When patterning such a resin material, a contact hole CH1 reaching the switching element SW arranged in the pixel PX1 is also formed at the same time. Thereafter, similarly, the second color filter layer CF2 in which the contact hole CH2 is formed in the pixel PX2 is formed. Thereafter, similarly, a third color filter layer CF3 in which a contact hole CH3 is formed in the pixel PX3 is formed.

  These first to third color filter layers CF1 to CF3 are disposed so as to overlap each other at their peripheral edge portions. For this reason, as illustrated, in the overlapping portion OL in which the second color filter layer CF2 overlaps the first color filter layer CF1, the second color filter layer CF2 swells upward. Similarly, in the overlapping portion OL where the third color filter layer CF3 overlaps the second color filter layer CF2, the third color filter layer CF3 rises upward. Although not shown, the third color filter layer CF3 is also raised upward in the overlapping portion OL in which the third color filter layer CF3 overlaps the first color filter layer CF1.

  The height of the swell in the overlapping portion OL varies depending on conditions such as the material characteristics and thickness of the color filter layer, the amount of overlap between the color filters, and the processing process. As an example, the thickness of the applied resist R is about 2 μm. In some cases, the resist R may swell by about 0.2 to 1.0 μm in the vicinity immediately above the overlapping portion OL.

  Subsequently, as shown in FIG. 6, a resist R is applied on the first to third color filter layers CF1 to CF3. Here, as the resist R, a positive resist that is decomposed by light irradiation and dissolved in a developer is applied. The resist R tends to absorb the unevenness of the base when it is applied, but the upper surface of the resist R still rises upward in the vicinity of just above the overlapping portion OL.

  Subsequently, as shown in FIG. 7, among the resists R, the resist R located immediately above the contact holes CH1 to CH3 is exposed with the first exposure amount, and the resist R located immediately above the overlapping portion OL is first exposed. The exposure is performed with a second exposure amount different from the exposure amount. The exposure process with different exposure amounts depending on the position may be performed by, for example, dividing the exposure process with the first exposure dose and the exposure process with the second exposure dose, but in the contact holes CH1 to CH3. The exposure may be performed in a lump using an exposure mask in which the facing region has the first transmittance (high transmittance) and the region facing the overlapping portion OL has the second transmittance lower than the first transmittance. In addition, a halftone mask in which gradation is formed in a region facing the overlapping portion OL may be used as the exposure mask.

  Here, since the positive resist is applied, the decomposition of the resist R is promoted as the exposure amount increases. For this reason, since it is necessary to completely remove the resist R and form the through holes TH communicating with the contact holes CH1 to CH3 immediately above the contact holes CH1 to CH3, the first exposure amount is set to a high exposure amount. Is done. On the other hand, since the purpose is to remove the swell of the resist R immediately above the overlapping portion OL and the resist R is not completely removed, the second exposure amount is lower than the first exposure amount. Set to

  Subsequently, as shown in FIG. 8, by performing development processing or the like on the resist R described above, the overcoat layer 13 in which the through holes TH communicating with the contact holes CH1 to CH3 are formed is formed. Further, in this overcoat layer 13, the bulge just above the overlapping portion OL is removed. In the example shown in FIG. 8, a recess 13 </ b> C is formed in the overcoat layer 13 immediately above the overlapping portion OL. Such a recess 13C does not penetrate to the overlapping portion OL.

  As shown in FIG. 9, in the overcoat layer 13, the portion directly above the overlapping portion OL may be formed substantially flat. In this case, the upper surface T1 of the overcoat layer 13 located immediately above the overlapping portion OL forms the same plane as the upper surface T2 of the overcoat layer serving as a base on which the pixel electrode PE is disposed. 8 and FIG. 9, the overlapping portion OL is covered with the overcoat layer 13.

  Thereafter, although not shown, in each of the pixels PX1 to PX3, the pixel electrode PE is formed on the overcoat layer 13, and then the first alignment film 14 is formed on the pixel electrode PE. The array substrate AR is manufactured through the above processes.

  Subsequently, as shown in FIG. 10, a seal material 5 is applied to the surface of the array substrate AR on which the pixel electrodes PE are formed. At this time, the sealing material 5 is formed in a closed loop shape as shown in FIG. Thereafter, the liquid crystal material L is dropped inside the array substrate AR surrounded by the sealing material 5. At this time, the liquid crystal material L is dropped on the surface of the array substrate AR where the sealing material 5 is formed, and is positioned on the alignment film 14.

  Subsequently, as shown in FIG. 11, the array substrate AR and the counter substrate CT are bonded together. The counter substrate CT prepared here is obtained by forming the counter electrode CE on the second insulating substrate 30 and then forming the second alignment film 31 on the counter electrode CE. In this bonding step, for example, the array substrate AR on which the liquid crystal material L is dropped and the counter substrate CT prepared separately are inserted into a vacuum assembly chamber, and the liquid crystal material L and the counter substrate on the array substrate AR are inserted. It arrange | positions so that the 2nd alignment film 31 of CT may face. As the distance between the array substrate AR and the counter substrate CT becomes smaller, the dropped liquid crystal material L moves toward the periphery between the first alignment film 14 of the array substrate AR and the second alignment film 31 of the counter substrate CT. Liquid crystal injection is performed by spreading and filling between these substrates. Then, the sealing material 5 is cured, and a liquid crystal display panel in which the liquid crystal layer LQ is held between the bonded array substrate AR and the counter substrate CT is manufactured.

  According to the embodiment described above, the step of the color filter layer CF formed on the array substrate AR, that is, the bulge (convex portion) protruding toward the counter substrate CT is reduced. Therefore, when the liquid crystal material L dropped onto the array substrate AR spreads between the array substrate AR and the counter substrate CT toward the periphery, the surface of the array substrate AR (that is, the upper surface of the first alignment film 14) and the counter substrate The liquid crystal layer LQ can be formed in a short time by proceeding smoothly along the surface of the CT (that is, the upper surface of the second alignment film 31). Therefore, liquid crystal can be injected efficiently and the yield can be improved.

  In addition, according to the present embodiment, since an undesired rise immediately above the overlapping portion OL is reduced, it is possible to suppress alignment defects of the liquid crystal molecules or cell gap changes. For this reason, there is no deterioration in image quality in the vicinity immediately above the overlapping portion OL, for example, there is no change in transmittance, contrast, or viewing angle, which can contribute to improvement in display quality.

  On the other hand, when the color filter layer CF remains swelled, for example, when the first to third color filter layers CF1 to CF3 having a pattern as shown in FIG. 2 are formed, the color filter layer CF extends along the second direction Y. Since the swell is formed, it becomes a resistance to the spread of the liquid crystal material L in the first direction X, and the time required to form a uniform liquid crystal layer is longer than that of this embodiment, and in some cases, the periphery of the active area ACT, In particular, a slight amount of bubbles may remain in the corner portion.

  In the above-described embodiment, the example in which any of the first to third color filter layers CF1 to CF3 extends linearly along the second direction Y has been described. However, the present invention is not limited to this example.

  For example, in the example shown in FIG. 12, the second color filter layer CF2 and the third color filter layer CF3 are disposed in the opening of the pixel PX, compared to the example shown in FIG. The color filter layer CF1 is different in that it extends not only on the opening of the pixel PX but also on the auxiliary capacitance line C in which the contact holes CH1 to CH3 are formed.

  Also in such an example, the first to third color filter layers CF1 to CF3 are arranged so that their peripheral portions overlap each other, and the overlapping portion OL is formed. In such an overlapping portion OL, in particular, at the position indicated by A in the figure, three layers of first to third color filter layers CF1 to CF3 are stacked. For this reason, the overlapping portion OL formed at the position A rises higher than the overlapping portion OL at other positions formed by stacking the two color filter layers.

  When the overcoat layer 13 is disposed on the first to third color filter layers CF1 to CF3, the overcoat layer 13 swells in the vicinity immediately above the overlapping portion OL, and in particular, swells at the position A. For this reason, the resistance to the spread of the liquid crystal material increases in the vicinity of the position A.

  Therefore, similarly to the above-described example, when the overcoat layer 13 is formed, the exposure amount is adjusted so that the overcoat layer 13 is positioned immediately above the overlapping portion OL including the position A as shown in the schematic cross-sectional view of FIG. The rise of the overcoat layer 13 can be reduced. Thereby, the liquid crystal material can be spread more smoothly, and the uniform liquid crystal layer LQ can be formed in a short time.

  In addition, this invention is not limited to the said embodiment itself, In the stage of implementation, it can change and implement a component within the range which does not deviate from the summary. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

  For example, in the above-described embodiment, an example in which a positive resist is applied as a resist for forming the overcoat layer has been described. However, a negative resist can also be applied.

  In the present embodiment, the so-called color filter-on-array (COA) structure in which the first to third color filter layers CF1 to CF3 are formed on the array substrate AR has been described, but these first to third color filters are also described. The layers CF1 to CF3 may be formed on the counter substrate CT. In this case, the first to third color filter layers CF1 to CF3 are disposed between the second insulating substrate 30 and the counter electrode CE, and further, the first to third color filter layers CF1 to CF3 and the counter electrode are disposed. The overcoat layer 13 is disposed between the CE. Even in such a configuration, the same effect as that of the present embodiment can be obtained by reducing the rise of the overcoat layer 13 located immediately above the overlapping portion OL.

  Furthermore, in the present embodiment, the case where the electric field applied to the liquid crystal layer LQ is formed between the pixel electrode PE formed on the array substrate AR and the counter electrode CE formed on the counter substrate CT has been described. A so-called lateral electric field mode in which the pixel electrode PE and the counter electrode CE are formed may be applied.

  Further, in the present embodiment, liquid crystal injection has been described by the dropping injection method, but the same effect can be obtained by a conventional injection method in which an injection port is provided by a seal and liquid crystal is attached to the injection port after evacuation and then returned to atmospheric pressure. I can expect.

LPN ... Liquid crystal display panel AR ... Array substrate CT ... Counter substrate LQ ... Liquid crystal layer ACT ... Active area PX ... Pixel G ... Gate line C ... Auxiliary capacitance line S ... Source line SW ... Switching element PE ... Pixel electrode CE ... Counter electrode CF ... color filter layer OL ... overlapping part CH ... contact hole 13 ... overcoat layer 13C ... recessed part TH ... through hole

Claims (5)

First and second switching elements, a first color filter layer disposed on the first switching element, and disposed on the second switching element and overlapping a part of the first color filter layer A second color filter layer forming the overlapping portion, an insulating film covering the first color filter layer and the second color filter layer and having a recess formed immediately above the overlapping portion, and the first color filter layer A first pixel electrode disposed on the insulating film located above and electrically connected to the first switching element; and disposed on the insulating film located above the second color filter layer. A first substrate comprising: a second pixel electrode electrically connected to the two switching elements;
A second substrate disposed opposite the first substrate;
A closed loop sealing material for bonding the first substrate and the second substrate;
A liquid crystal layer held between the first substrate and the second substrate and surrounded by the sealing material;
A liquid crystal display device comprising:   The liquid crystal display device according to claim 1, wherein the insulating film is formed of a positive resist. Forming a first switching element and a second switching element above the insulating substrate;
Forming a first color filter layer having a first contact hole on the first switching element;
A second contact hole is formed on the second switching element and a second color filter layer is formed to form an overlapping portion overlapping a part of the first color filter layer;
Applying a resist on the first color filter layer and the second color filter layer;
Exposing the resist located immediately above the first contact hole and directly above the second contact hole with a first exposure amount, and exposing the resist located immediately above the overlapping portion to a second exposure amount different from the first exposure amount Exposure with
Forming an insulating film in which a through hole communicating with the first contact hole and the second contact hole is formed by the resist;
A first pixel electrode electrically connected to the first switching element is formed on the insulating film located above the first color filter layer, and the insulation located above the second color filter layer. Forming a first substrate on the film to form a second pixel electrode electrically connected to the second switching element;
Applying a closed loop sealing material to a surface of the first substrate on which the first pixel electrode and the second pixel electrode are formed;
Dropping a liquid crystal material inside the first substrate surrounded by the sealing material;
Bonding a second substrate to the first substrate;
A method for manufacturing a liquid crystal display device, comprising:   The method of manufacturing a liquid crystal display device according to claim 3, wherein the resist is a positive resist, and the second exposure amount is lower than the first exposure amount.   The upper surface of the insulating film located immediately above the overlapping portion is recessed from the upper surface of the insulating film on which the first pixel electrode and the second pixel electrode are formed. Liquid crystal display device manufacturing method.

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