JP2011172389A - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small switching regulator with low noise. <P>SOLUTION: The switching regulator includes an output stage of the switching regulator consisting of a plurality of transistors where two states of conduction and interruption are alternately switched, and a drive circuit for individually driving the output stage transistors. In the drive circuit, driving performance when rising and falling is set as unbalance so that transition time from the interruption to conduction state in each output stage transistor becomes longer than that from the conduction to interruption state. Transition time is changed by determining that potential of an output signal reaches that which is previously set. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a switching regulator that efficiently generates a desired power supply voltage, and more particularly to a low-noise switching regulator that can reduce noise by reducing instantaneous current generated during transition time of an output stage.

  Wireless interfaces such as the global positioning system (GPS) and Bluetooth (registered trademark) are required to be reduced as much as possible in order to be built in battery-powered portable terminals. In recent years, low power consumption has been realized by using high-performance fine CMOS (Complementary Metal Oxide Semiconductor) devices. However, as the miniaturization progresses, the breakdown voltage of the element decreases, and it has become necessary to prepare a power supply having a voltage lower than that of the power supplies of other blocks in the system. A linear regulator, which is one of representative circuits having a voltage conversion function, has low noise and has been used in an analog circuit in the past, but its efficiency is a problem. For example, when trying to generate 1.2 V from 3.3 V using a linear regulator, the conversion efficiency is reduced to about 30% by itself, and wasteful power is consumed.

  Switching regulators, which are another representative of voltage conversion, use active elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) as switches, and convert input DC voltage to AC voltage once by turning on / off those switches. It is. The converted voltage is converted into a stable DC voltage through an rectifier circuit and a smoothing circuit using an inductor or the like, and then output. In this circuit, the ratio of the output voltage to the input voltage (voltage conversion rate) is substantially determined by the on / off time ratio of the switch, and the power loss (switching loss) due to switching of the switch is generally small. Can supply power with high efficiency.

  However, this switching regulator has a problem that noise generated during switching is large. Therefore, for the digital unit, a switching regulator can be incorporated in order to efficiently create a desired potential from the battery. However, since the RF analog section sensitive to noise cannot incorporate a switching regulator, it is necessary to prepare a separate switching regulator outside.

  Here, the reason why noise occurs in the conventional switching regulator will be described below. FIG. 1 is a diagram showing a circuit configuration of a final output stage of a conventional step-down switching regulator. A source terminal of the switching transistor 202 configured by a P-type MOS transistor is connected to the DC power supply 201, and a drain terminal thereof is connected to a drain terminal of the switching transistor 203. The switching transistor 203 is composed of an N-type MOS transistor, the drain terminal of which is connected to the drain terminal of the switching transistor 202, and the source terminal of which is connected to the ground voltage (GND).

  The gate terminals of the two switching transistors 202 and 203 are both connected to the input terminal 207. Outputs from the drain terminals of the switching transistors 202 and 203 are input to a low-pass filter including an inductor 204 and a capacitor 205. The drain terminals of the switching transistors 202 and 203 are connected to one terminal of the inductor 204, the other terminal of the inductor 204 is connected to one terminal of the capacitor 205, and the other terminal of the capacitor 205 is connected to the ground voltage (GND). Is done. A smoothed output is obtained from the output terminal 206 to which the other terminal of the inductor 204 and one terminal of the capacitor 205 are connected.

  In order to maintain high conversion efficiency with this switching regulator, the transistor size is designed to be increased in order to reduce the on-resistance of the switching transistors 202 and 203 as much as possible. Or the method of reducing an alternating current loss by raising a switching frequency and performing high-speed switching is taken. However, the input signal changes abruptly at the start of a transition where the source-drain voltage of the switching transistors 202 and 203 is large, or the switching transistors are turned on simultaneously. In such a case, inductive noise is generated in the parasitic inductor of the power supply due to a rapid current change caused by the switching operation. This noise fluctuates the voltage level of the power supply terminal each time switching is performed, and as a result, similar noise appears in the output voltage.

  In order to reduce such switching noise, there is a method of controlling the timing of an input signal with high accuracy. However, such a regulator has a very complicated control circuit configuration, and timing control is not easy.

  On the other hand, an example of a step-down regulator disclosed in Patent Document 1 is shown in FIG. In this example, a plurality of switching transistors having different on-resistances are provided, and when the output switching transistor is on, the transistors are turned on in descending order of the on-resistance. Is configured to operate.

  In the switching regulator shown in FIG. 2, the source terminals of the plurality of switching transistor stars 21, 22, 23 formed by P-type MOS transistors are connected to the DC power source 1, respectively, and the switching transistors 31, configured by N-type MOS transistors, The source terminals 32 and 33 are each connected to a ground voltage (GND). The drain terminals of the switching transistors 21, 22, 23 and the switching transistors 31, 32, 33 are connected to the smoothing circuit 10 having the diode 11, the inductance element 12, and the capacitor 13.

  The control unit 15 controls the on / off operations of the switching transistors 21 to 23 and 31 to 33 according to the output voltage Vout of the switching regulator output from the smoothing circuit 10. In the control unit 15, the voltage comparator 4 compares the output voltage Vout and the reference voltage Vref, and outputs a signal SG indicating the comparison result. The pulse generation circuit 16 receives this signal SG and outputs signals SA1 to SA3 and SB1 to SB3 for controlling the on / off operations of the switching transistors 21 to 23 and 31 to 33.

  A drive circuit 40 is provided for each of the switching transistors 21 to 23 and 31 to 33. Each drive circuit 40 receives the output signals SA1 to SA3 and SB1 to SB3 from the control unit 15 as drive signals, and operates the corresponding switching transistors 21 to 23, 31 to 33. The voltages at the drain terminals of the switching transistors 21 to 23 and 31 to 33 are smoothed by the smoothing circuit 10 and output to the load 5 as the output voltage Vout. The inductor 102 is a power source parasitic inductor.

  Here, the switching transistors 21 to 23 have different transistor widths, and the transistor widths increase in the order of 21 <22 <23. As a result, the on-resistances of the switching transistors 21 to 23 increase in the order of 23 <22 <21. Similarly, the switching transistors 31 to 33 have different transistor widths, and the transistor widths increase in the order of 31 <32 <33. As a result, the on-resistances of the switching transistors 31 to 33 are increased in the order of 33 <32 <31.

  In this example, the plurality of switching transistors 21 to 23 and the plurality of switching transistors 31 to 33 are operated in a predetermined order in their on operation and off operation. This suppresses a rapid current change during the switching operation and reduces switching noise. However, since the output stage occupies a very large area, this method has a drawback of increasing the chip size.

  Furthermore, in Patent Document 2, by selecting a means for driving the output buffer signal level relatively slowly or steeply, either the transmission speed or the noise reduction is prioritized depending on the operation condition. A circuit is disclosed. Patent Document 3 discloses a technique for controlling a change in output level based on a result of comparing an output level with a reference voltage.

Republished patent WO2000 / 13318 JP 2002-111476 A JP 2007-236194 A

  As described above, in order to reduce switching noise due to a sudden current change of the output transistor, there is a technique for controlling an input signal at an accurate timing or operating a plurality of output transistors having different on-resistances in stages. It has been adopted. By using these techniques, it is possible to realize a low noise switching regulator, but there arises a problem that complicated control is required or a large chip area is required.

  The present invention solves the problems of the prior art as described above, and an object thereof is to provide a small and low noise switching regulator that can be integrated on-chip with an RF analog circuit sensitive to noise. It is in.

  According to one aspect of the present invention, when an output signal transitions in an output stage of a switching regulator composed of a plurality of output stage transistors that are alternately switched between two states of conduction and cutoff, the conduction state is changed from the cutoff state. The transition time of the input signal of the output stage transistor that changes to be longer than the transition time of the output signal, and the transition time of the input signal of the output stage transistor that changes from the conduction state to the cutoff state is set to be shorter than the transition time of the output signal. A switching regulator characterized by the above can be obtained.

  According to another aspect of the present invention, an output stage of a switching regulator composed of a plurality of output stage transistors in which two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors When the high level signal is input to the driving circuit, the first driving circuit is changed to the low level output, thereby changing the first output stage transistor from the conduction state to the cutoff state, and the second driving circuit. Changes the second output stage transistor from the cutoff state to the conductive state by slowly changing to a low level in a transition time longer than the transition time in which the first drive circuit changes to a low level output. When the low level signal is input, the second drive circuit becomes a high level output, thereby changing the second output stage transistor from the conduction state to the cutoff state. And the first output stage transistor is changed from the cutoff state to the conductive state by slowly changing to the high level in a transition time longer than the transition time in which the second drive circuit changes to the high level output. It is possible to obtain a method of controlling the operation of the switching regulator, which is characterized by being changed.

  According to the present invention, when the output of the final stage of the switching regulator transitions from the low level to the high level or from the high level to the low level, the transition time of the input signal to the output stage transistor becomes longer than the transition time of the output stage. Set as follows. Therefore, a rapid current change in the output stage is suppressed, and a low-noise switching regulator is obtained.

It is a circuit diagram which shows one example of the last stage of the conventional switching regulator. It is a circuit diagram which shows the other example of the last stage of the conventional switching regulator. It is a circuit diagram of the last stage of the switching regulator of the 1st Embodiment of this invention. It is a circuit diagram of the last stage of the switching regulator of the 2nd Embodiment of this invention. It is a circuit diagram of the last stage of the switching regulator of the 3rd Embodiment of this invention.

Embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 3 is a circuit diagram of the final stage of the switching regulator for explaining the first embodiment of the present invention. In the following embodiments, the same components are denoted by the same reference numerals, and redundant description will be omitted as appropriate.

  The final stage includes a CMOS inverter composed of output stage transistors, a drive circuit for individually driving the output stage transistors, and a low-pass filter for obtaining a smoothed output. The CMOS inverter at the output stage includes a P-type MOS transistor 202 as an output stage transistor and an N-type MOS transistor 203. A node where the drain terminals of the two output stage transistors 202 and 203 are connected is an output node N. . The source terminal of the P-type MOS transistor 202 is connected to the DC power supply 201, the drain terminal is connected to the output node N, and the gate terminal is connected to the output of the previous drive circuit. The source terminal of the N-type MOS transistor 203 is connected to the ground voltage GND, the drain terminal is connected to the output node N, and the gate terminal is connected to the output of the previous drive circuit.

  The output node N is connected to a low pass filter composed of an inductor 204 and a capacitor 205. The output node N is connected to one terminal of the inductor 204, the other terminal of the inductor 204 is connected to one terminal of the capacitor 205, and the other terminal of the capacitor 205 is connected to the ground voltage (GND). A smoothed output is obtained from the output terminal 206 to which the other terminal of the inductor 204 and one terminal of the capacitor 205 are connected. Although the final output is output from the output terminal 207, in the following description, the output node N may be expressed as the final stage output.

  A drive circuit for individually driving the output stage transistors is composed of a CMOS inverter. The drive circuit connected to the gate terminal of the P-type MOS transistor 202 is a CMOS inverter composed of a P-type MOS transistor 208 and an N-type MOS transistor 209. On the other hand, the drive circuit connected to the gate terminal of the N-type MOS transistor 203 is a CMOS inverter composed of a P-type MOS transistor 210 and an N-type MOS transistor 211. The gate terminals of these drive CMOS inverters are both connected to the input terminal 207. A pulse waveform whose duty ratio is controlled is input to the input terminal 207 so that a target power supply voltage is generated at the output terminal.

  The N-type MOS transistor 209 of the front-stage drive inverter that drives the final output stage P-type MOS transistor 202 is designed to have a drive capability smaller than usual, and the P-type MOS transistor 208 of the front-stage drive inverter has a sufficient drive capacity. Designed to. On the other hand, the P-type MOS transistor 210 of the front-stage drive inverter that drives the final output stage N-type MOS transistor 203 is designed to have a smaller drive capacity than usual, and the N-type MOS transistor 211 of the front-stage drive inverter has a sufficient drive capacity. Designed to have.

  The operation of this circuit will be described below using the operation waveforms of the respective contacts shown in the circuit diagram. A pulse signal having a certain duty ratio is applied to the input terminal 207 so as to obtain a predetermined output level. The drive inverter in the previous stage composed of the MOS transistors 208 and 209 is set so that the falling (tf) driving capability is low while the rising (tr) driving capability is high. Therefore, when the final stage output transitions from the low level to the high level, the transition time of the input signal for driving the P-type MOS transistor 202 is set to be longer than the transition time of the output stage, and the P-type MOS transistor 202 is set. Is set to change gradually.

  On the other hand, the previous drive inverter composed of the MOS transistors 210 and 211 has a low rising (tr) driving capability and a high falling (tf) driving capability. Therefore, when the final stage output transitions from the high level to the low level, the transition time of the input signal for driving the N-type MOS transistor 203 is set to be longer than the transition time of the output stage, and the N-type MOS transistor 203 is set. The current is set to change slowly.

  In this way, the rising (tr) driving capability of the driving inverter of the output stage transistor 202 is increased, the falling (tf) driving capability is decreased, and the rising (tr) driving capability of the driving inverter of the output stage transistor 203 is decreased and falling. (Tf) A high driving capability is set. By setting in this way, when the potential of the output node N transitions, the transition time for the output stage transistor to change from the cutoff state to the conducting state can be made longer than the transition time of the input signal to the output stage transistor. On the other hand, the transition time for the output stage transistor to change from the conductive state to the cutoff state is set shorter than the transition time of the input signal to the output stage transistor.

  The switching regulator according to the present embodiment includes an output stage composed of a plurality of output stage transistors in which two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors. Yes. When the output signal transitions, the input signal transition time of the output stage transistor that changes from the cutoff state to the conductive state is longer than the transition time of the output signal, and the input signal of the output stage transistor that changes from the conductive state to the cutoff state The transition time is set shorter than the transition time of the output time. Therefore, the drive circuit is set so that the transition time from the cutoff state to the conductive state in each output stage transistor is longer than the transition time from the conductive state to the cutoff state, and the drive capability at the fall is set to be unbalanced. Yes.

  Since the transition time of the input signal to the output stage transistor that is cut off in each operating state is short and the output stage transistor is cut off immediately, no through current flows. In addition, since the transition time of the input signal to the output stage transistor that is in the conductive state is long, the switching current is reduced by gently changing the flowing current. Even if the device size of the final stage is increased, a large inrush current does not flow instantaneously, and a large drive device other than the final stage is not required, so that a small and low-noise switching regulator can be obtained. As a result, on-chip integration with an RF analog circuit sensitive to noise becomes possible.

(Second Embodiment)
FIG. 4 is a circuit diagram of the final stage of the switching regulator for explaining the second embodiment of the present invention. In this circuit, in the former stage drive inverter that drives the output stage transistor described in FIG. 3, the long transition time is set so that the potential of the output stage (the potential of the output node N) has reached a preset potential. It is embodiment which showed having determined and changing. In this embodiment, compared with the first embodiment, logic elements 214 and 215 for detecting the level of the final stage output, and MOS transistors 212 and 213 for changing the drive capability of the drive inverter in the previous stage are added. .

  The logic element 214 is an AND circuit 214 having the output node N and the input terminal 207 as inputs, and its output is connected to the gate electrode of the N-type MOS transistor 212. The drain electrode of the N-type MOS transistor 212 is connected to the drain electrode of the N-type MOS transistor 209, and the source electrode is connected to the ground voltage (GND). The logic element 215 is an OR circuit 215 having the output node N and the input terminal 207 as inputs, and its output is connected to the gate electrode of the P-type MOS transistor 213. The drain electrode of the P-type MOS transistor 213 is connected to the drain electrode of the P-type MOS transistor 210, and the source electrode is connected to the DC power supply 201.

  Consider first the operation of the circuit of FIG. 4 where the final stage output transitions from low level to high level. First, the potential of the input terminal 207 transitions from the low level to the high level, but at this time, the potential of the final stage output contact N has not changed, so the output of the logic circuit 214 that is an AND circuit maintains the low level. Yes. Next, as the output level of the previous stage drive inverter is inverted, the final stage output node N starts to change from the low level to the high level. Thereafter, when the logic threshold value of the logic circuit is exceeded and the output of the logic circuit 214 changes to a high level, the N-type MOS transistor 212 becomes conductive, and the falling drive capability of the pre-stage drive inverter increases. On the other hand, the output of the logic circuit 215, which is an OR circuit, changes to a high level when the input signal 207 transitions to a high level regardless of the final stage output. Therefore, the P-type MOS transistor 213 is cut off when the input signal 207 transitions to a high level, and therefore does not affect the switching operation of the final-stage N-type MOS transistor 203.

  Next, consider the case where the final stage output transitions from a high level to a low level. First, the potential of the input terminal 207 transitions from a high level to a low level, but at this point, the final-stage output contact N has not changed, so the output of the logic circuit 215 is maintained at a high level. Next, as the output level of the previous stage drive inverter is inverted, the final stage output contact N starts to change from the high level to the low level. Thereafter, the final stage output node N exceeds the logic threshold value of the logic circuit, and the output of the logic circuit 215 changes to the low level, so that the P-type MOS transistor 213 becomes conductive, and the rising drive capability of the preceding stage drive inverter is increased. growing. On the other hand, the output of the logic circuit 214, which is an AND circuit, changes to a low level when the input signal 207 transitions to a low level regardless of the final stage output. Accordingly, since the N-type MOS transistor 212 is cut off, the operation of the final-stage P-type MOS transistor 202 is not affected.

  In the present embodiment, when a logic circuit having an input signal and an output signal (output node N) as inputs is used and the output signal level exceeds the threshold voltage of the logic circuit, which is a preset potential, This is an embodiment in which the drive capability of the drive inverter is changed. When the output signal level transitions to a high level, an AND circuit is used. When the output signal level exceeds a threshold voltage, the AND circuit is changed to a high level and the added transistor is turned on, thereby driving the drive inverter. Increase driving ability. When the output signal level transitions to the low level, an OR circuit is used. When the output signal level exceeds the threshold voltage, the OR circuit is changed to the low level and the added transistor is turned on to drive the drive inverter. Increase ability. Thus, in the drive inverter, a small and low-noise switching regulator can be obtained in which each of the long transition times can be changed by determining that the potential of the output stage has reached the preset potential. .

(Third embodiment)
FIG. 5 is a circuit diagram of the final stage of the switching regulator for explaining the third embodiment of the present invention. The third embodiment includes a level conversion mechanism that adjusts the potential of the output signal (output node) input to the logic circuit described in FIG. In this embodiment, MOS transistors 216 and 219 and resistors 217, 218, 220, and 221 are added as compared to the second embodiment.

  The N-type MOS transistor 216 has a gate electrode connected to the output node N, a drain electrode connected to the DC power supply 201, and a source electrode connected to one end of the resistor 217. The other end of the resistor 217 is connected to the input terminal of the logic circuit 214 and one end of the resistor 218, and the other end of the resistor 218 is connected to the ground voltage. The level conversion circuit composed of the N-type MOS transistor 216 and the resistors 217 and 218 makes the N-type MOS transistor 216 conductive when the output node N is at a high level, and converts the potential of the source electrode into the potential converted by the resistors 217 and 218. , Output to the logic circuit 214.

  In the P-type MOS transistor 219, the gate electrode is connected to the output node N, the source electrode is connected to the DC power supply 201, and the drain electrode is connected to one end of the resistor 220. The other end of the resistor 220 is connected to the inverting input terminal of the logic circuit 215 and one end of the resistor 221, and the other end of the resistor 221 is connected to the ground voltage. In the level conversion circuit composed of the P-type MOS transistor 219 and the resistors 220 and 221, when the output node N is at the low level, the P-type MOS transistor 216 conducts, and the potential obtained by converting the potential of the source electrode by the resistors 220 and 221 is Output to the logic circuit 215.

  In this embodiment, the apparent logic threshold value of the logic circuit 214 is changed by performing level conversion on the output level of the final stage output node N using the N-type MOS transistor 216 and the resistors 217 and 218. . Similarly, level conversion is performed by a circuit composed of a P-type MOS transistor 219 and resistors 220 and 221 to change the apparent logic threshold value of the logic circuit 215.

  In the present embodiment, the potential of the output node N is level-converted, and the level-converted voltage exceeds the threshold voltage of the logic circuit using a logic circuit that receives the level-converted potential and the input signal. In this case, the drive capacity of the drive inverter is changed. In this way, the level of the potential of the output node N is converted and used as an input to the logic circuit, so that the output signal level for changing the drive capability of the drive inverter can be freely set. As a result, it is possible to adjust the potential at which the final stage output transition is completed. Thus, a switching regulator that can freely set the transition time of the output level can be obtained by freely setting the output signal level that changes the drive capability of the drive inverter.

  According to the present invention, an output stage of a switching regulator composed of a plurality of transistors that alternately switch between two states of conduction and cutoff is an output stage transistor that changes from a cutoff state to a conduction state when its output potential transitions. The transition time of the input signal is set longer than the transition time of the output signal, and the transition time of the input signal of the output stage transistor that changes from the conduction state to the cutoff state is set shorter than the transition time of the output time. Since the transition time of the input signal to the output stage transistor that is interrupted in each operation state is short, no through current flows. In addition, since the transition time of the input signal to the output stage transistor that is in the conductive state is long, the switching current is reduced by gently changing the flowing current. According to the present invention, a low-noise switching regulator can be obtained. As a result, it is possible to provide a small and low-noise switching regulator that can be integrated on-chip with an RF analog circuit that is sensitive to noise.

  According to the present invention, an output stage of a switching regulator composed of a plurality of transistors in which two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, the drive The circuit is set so that the transition time from the cutoff state to the conductive state in each output stage transistor is longer than the transition time from the conductive state to the cutoff state, and the drive capability at the fall is set to be unbalanced. A switching regulator characterized by the above can be obtained.

  Further, the switching regulator includes an output stage of a switching regulator composed of a plurality of transistors that are alternately switched between two states of conduction and cutoff, and a drive circuit for individually driving the output stage transistors. Each output stage transistor is set so that the transition from the cutoff to the conduction state is longer than the transition time from the conduction to the cutoff, and the drive capability at the fall is set to be unbalanced, and each transition time is set to the output stage. Thus, a switching regulator can be obtained which is changed in accordance with the potential of.

  The output stage of the switching regulator is composed of a plurality of transistors that are alternately switched between two states of conduction and cutoff, and a circuit for individually driving the output stage transistors. The drive time at the rise and fall is set to be unbalanced so that the transition time from the cutoff to the conduction state in the stage transistor is longer than the transition time from the conduction to the cutoff state. A switching regulator is obtained in which the potential of the stage is changed by determining that the potential has reached a preset potential.

  Although preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate modifications can be made without departing from the scope of the present invention. For example, in the embodiment, the logic circuit is realized by a simple two-input AND circuit or OR circuit, but the present invention is not limited to this, and a logic circuit that receives a plurality of input signals may be used. good.

1, 201 DC power supply 10 Smoothing circuit 102 Parasitic inductor 11 Diode 12, 204 Inductor 13, 205 Capacitance 15 Control unit 16 Pulse generation circuit 21, 22, 23, 202, 208, 210, 213, 219 P-type MOS transistors 31, 32 33, 203, 209, 211, 212, 216 N-type MOS transistors 217, 218, 220, 221 Resistor 214 Logic (AND) circuit 215 Logic (OR) circuit 206 Output terminal 207 Input terminal 4 Voltage comparator 40 Driving circuit 5 load

Claims (7)

  In the output stage of a switching regulator composed of a plurality of output stage transistors in which the two states of conduction and cutoff are alternately switched, when the output signal transitions, the input signal of the output stage transistor that changes from the cutoff state to the conduction state A switching regulator characterized in that the transition time is longer than the transition time of the output signal, and the transition time of the input signal of the output stage transistor that changes from the conduction state to the cutoff state is set shorter than the transition time of the output signal.   An output stage of a switching regulator composed of a plurality of output stage transistors whose two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, The drive capability at the time of rising and falling is set to be unbalanced so that the transition time from the cutoff to the conduction state in the output stage transistor is longer than the transition time from the conduction to the cutoff state. The switching regulator according to claim 1.   An output stage of a switching regulator composed of a plurality of output stage transistors whose two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, The drive time at the rise and fall is set to be unbalanced so that the transition time from cutoff to conduction in the output stage transistor is longer than the transition time from conduction to cutoff, and each transition time is output 3. The switching regulator according to claim 2, wherein the switching regulator is changed according to the potential of the signal.   An output stage of a switching regulator composed of a plurality of output stage transistors whose two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, The drive time at the rise and fall is set to be unbalanced so that the transition time from the cutoff to the conduction state in the output stage transistor is longer than the transition time from the conduction to the cutoff state. 4. The switching regulator according to claim 3, wherein the switching regulator determines and changes that the potential of the output signal has reached a preset potential.   An output stage of a switching regulator composed of a plurality of output stage transistors whose two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, In the output stage transistor, the transition time from cutoff to conduction state is set to be longer than the transition time from conduction to cutoff state, and the drive capability at the time of fall is set to unbalanced, to the output signal and drive circuit The logic circuit according to whether the potential of the output signal is higher or lower than the threshold value of the logic circuit when the output stage transistor transitions from the cutoff state to the conductive state using the logic circuit having the input signal of 5. The switching regulator according to claim 4, wherein the transition time of each driving circuit is changed according to the output level of the switching regulator. .   An output stage of a switching regulator composed of a plurality of output stage transistors whose two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors, The output stage transistor is set so that the transition time from cutoff to conduction state is longer than the transition time from conduction to cutoff state, and the driving capability at the fall is set to unbalance, and the potential of the output signal is leveled When the output stage transistor transitions from cutoff to conduction using the converted potential and the logic circuit that receives the input signal to the drive circuit, the potential obtained by level-converting the potential of the output signal is greater than the threshold value of the logic circuit. The transition time of each drive circuit is changed according to the output level of the logic circuit depending on whether it is higher or lower The switching regulator as claimed in Motomeko 4. An output stage of a switching regulator composed of a plurality of output stage transistors in which two states of conduction and cutoff are alternately switched, and a drive circuit for individually driving the output stage transistors are provided. Is input, the first drive circuit becomes a low level output, thereby changing the first output stage transistor from the conduction state to the cutoff state, and the second drive circuit changes the first drive circuit to the low level output. The second output stage transistor is changed from the cutoff state to the conductive state by slowly changing to a low level with a long transition time compared to the changing transition time,
Further, when a low level signal is input to the driving circuit, the second driving circuit is changed to a high level output, so that the second output stage transistor is changed from the conduction state to the cutoff state. Switching characterized in that the first output stage transistor is changed from a cutoff state to a conductive state by slowly changing to a high level in a transition time longer than a transition time in which the second driving circuit changes to a high level output. Regulator control method.

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