JP2011164838A - Endpoint sharing system and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an endpoint sharing system and a data transfer method, for connecting a server and a storage device by PCIe to increase the speed of data transfer between a specific server among a plurality of servers and integrated endpoints. <P>SOLUTION: When a PCIe packet is transmitted from a predetermined endpoint of the integrated endpoints to the main server of an active system, a server for processing the packet is determined and the name of the server is inserted into the PCIe packet. A secondary shared memory transfer means 16 transfers data to a corresponding one of secondary shared memories used in individually transferring data to the servers. Data are transferred from the server to the integrated endpoints, as well. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an endpoint sharing system and a data transfer method in which a plurality of CPUs (Central Processing Units) or servers perform data transfer for sharing an endpoint as an input / output device. The present invention particularly relates to an endpoint sharing system and a data transfer method suitable for sharing an endpoint using PCI Express, which is a type of expansion bus.

  PCI Express is a serial transfer interface formulated in place of a PCI (Peripheral Component Interconnect) bus. “PCI Express” is abbreviated as “PCIe”. PCI Express uses point-to-point serial transmission.

  A communication system using PCI Express includes a server-side CPU and a plurality of endpoints. An endpoint is a general term for data input / output devices such as a LAN (Local Area Network) controller and a storage device.

  By the way, in the communication system using PCI Express, conventionally, the number of CPUs that can be connected to the end point is limited to one. Therefore, when CPUs are duplicated or multiplexed in order to construct a system that requires reliability, some device is required for each CPU to share an endpoint.

  Therefore, a technique for accessing a target endpoint via another endpoint in order for a plurality of CPUs (processors) to share the endpoint has been proposed as a first related technique of the present invention (for example, Patent Documents). 1).

  FIG. 20 shows an outline of the configuration of the endpoint sharing system in the first related technology. In this endpoint sharing system 1000, the first processor unit 1001 is connected to the first endpoint 1004 via the first host bridge 1002 and the first external bus 1003. Similarly, the second processor unit 1011 is connected to the second endpoint 1014 via the second host bridge 1012 and the second external bus 1013.

  The first endpoint 1004 and the second endpoint 1014 are connected to different external buses 1003 and 1013. For this reason, for example, the first processor unit 1001 cannot use the second endpoint 1014 as it is. Therefore, in the endpoint sharing system 1000, between the first endpoint 1004 and the second endpoint 1014, a converter 1021 that converts a signal transmitted between them, and a converter 1021 that uses the conversion A memory 1022 for storing data to be stored.

  For example, a packet is transmitted from the first processor unit 1001 to the second endpoint 1014 of the second processor unit 1011. In this case, the packet is first transmitted to the first endpoint 1004. A packet that reaches the first endpoint 1004 includes a request source ID (identifier) that includes a request source bus number and a device number. The bus number and device number of the first host bridge 1002 are the request source ID. The request source ID is converted by the conversion unit 1021 to obtain the bus number and device number of the second endpoint 1014. As a result, a valid packet is generated in the device tree under the second processor unit 1011 and the packet can reach a desired unit or device in the tree. The same applies to packet transmission from the device tree of the second processor unit 1011 toward the device tree of the first processor unit 1001.

  The memory 1022 stores the bus numbers and device numbers of the first and second host bridges 1002 and 1012 in association with the tags given to the packets as a request source ID table. The tag is an identification number uniquely determined for a request and response for establishing a certain access.

  In the endpoint sharing system 1000 according to the first related technology, the first processor unit 1001 passes through another endpoint 1004 to which the conversion unit 1021 and the memory 1022 are connected in order to share the endpoint 1014 of the second processor unit 1011. There is a need. For this purpose, it is necessary to prepare one endpoint 1004 and 1014 for each of the first processor unit 1001 and the second processor unit 1011 for one shared endpoint. Further, the conversion unit 1021 and the memory 1022 storing the request source ID table necessary for the conversion by the conversion unit 1021 are required, and the management and operation of the system become complicated.

  Therefore, the present inventor has proposed a second related technology in which a plurality of servers can share one end point without requiring the intervention of another end point.

  FIG. 21 shows the configuration of the endpoint sharing system in the second related technology. The end point sharing system 1100 of the second related technology has a configuration in which the 0th and first servers 1110 and 1111 are connected to an integrated end point (EP) 1112. Here, the 0th and 1st servers 1110 and 1111 and the integrated endpoint 1112 are physically separated from each other.

The integrated endpoint 1112 includes a PCI proxy function unit 1121 and _{0th to} Nth endpoints (EP) 1122 _{0 to} 1122 _N (where N is a positive integer). Here, the PCI proxy function unit 1121 is a function unit acting as a proxy (PCI) function as a computer expansion bus architecture. The PCI proxy function unit 1121 includes a CPU (not shown) and a recording medium such as a ROM (Read Only Memory) storing a control program executed by the CPU, and includes the following units.

(A) 0th port 1131 ₀
It is connected via a server 1110 and PCIe (PCIExpress) cable 1132 ₀ of the 0.
(B) First port 1131 ₁
The first server 1111 is connected via the PCIe cable 1132 ₁ .
(C) ACT (active) / SBY (standby) selection function unit 1133
One of the 0th and 11th servers 1110 and 1111 is selected as an ACT (active) system, and the other is selected as an SBY (standby system) system.
(D) 0th virtual PCIe configuration register 1134 ₀
The PCIe configuration register information of each endpoint 1122 is stored.
(E) First virtual PCIe configuration register 1134 ₁
The PCIe configuration register information of each endpoint 1122 is stored.
(F) Configuration control unit 1135
The 0th virtual PCIe configuration register 1134 ₀ and the first virtual PCIe configuration register 1134 ₁ are managed.
(G) Address conversion table 1136
Address space difference information as difference information of the memory space between the 0th server 1110 and the first server 1111 is held.
(H) Address conversion unit 1137
The addresses are converted so that the access to the memory space of the 0th server 1110 and the first server 1111 is the same address.
(I) Address conversion / distribution function unit 1138
The PCIe packet is distributed between a port connected to the ACT server of the 0th and first servers 1110 and 1111.
(J) _{0th to} Nth PCIe ports (Ports) 1139 _{0 to} 1139 _N
The _{0th to} Nth end points (EP) 1122 _{0 to} 1122 _N are connected correspondingly.

In the endpoint sharing system 1100 of the second related technology, the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N can be commonly used from the 0th and first servers 1110 and 1111 as general-purpose servers. ing. Here, the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N are generic names of data input / output devices as described above. The zeroth and first servers 1110 and 1111 are each mounted with a CPU (Central Processing Unit) (not shown).

In a normal PCIe (PCI Express) system, an endpoint as a data input / output device is usually mounted in a server. In the endpoint sharing system 1100 of the second related technology, the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N are physically independent from the 0th and first servers 1110 and 1111. Thus, during the first 0 server 1110 and between the 0th endpoint 1122 ₀ ～1122 _N of the N or the first server 1111 Like endpoint 1122 ₀ ～1122 _N of 0th N, is, PCIe Connected with a dedicated cable. Here, a technique for connecting a general-purpose server and each end point with a dedicated cable for PCIe has already been technically established.

In the second related technology, one of the 0th and 11th servers 1110 and 1111 is initially set as an ACT (active) system, that is, an active system, and only this ACT system is in the 0th to Nth. The end points 1122 _{0 to} 1122 _N can be accessed. By preparing an SBY (standby) system, the CPU mounted on the server is duplicated.

  In the second related technology, the configuration is executed when the power is turned on, and the configuration is not required when the server is switched between the ACT system and the SBY system. As a result, when the CPU needs to be switched, such as when a failure occurs in one of the CPUs installed in the ACT and SBY servers, the CPU system can be switched without temporarily stopping the endpoint. It can be realized at high speed.

Each of the 0th and 11th servers 1110 and 1111 of the second related technology has PCIe expansion slots 1141 and 1142, respectively. 0th server 1110, a PCIe NIC (Network Interface Card) 1143 for connecting the PCIe cable 1132 _0, are mounted to the PCIe expansion slot 1141 (attached). Similarly, the first server 1111 has a PCIe NIC 1144 for connecting the PCIe cable 1132 ₁ mounted in the PCIe expansion slot 1142.

0th Between the first N Endpoint 1122 ₀ ~1122 _N and PCI Puroshiki functional unit PCIe port 1139 0th N at 1121 ₀ ~1139 _N of being respectively connected to the PCIe bus 1151 ₀ ~1151 _N Yes.

The PCI proxy function unit 1121 has a 0th port 1131 ₀ for connecting to the 0th server 1110 and a first port 1131 ₁ for connecting to the first server 1111. The PCI proxy function unit 1121 includes a configuration control unit 1135 for managing the 0th and first virtual PCIe configuration registers 1134 ₀ and 1134 ₁ , respectively. Configuration control section 1135, the endpoint 1122 ₀ ~1122 _N of 0th N holds connected to PCI proxy function unit 1121 has a function of controlling the PCIe configuration register (not shown). The configuration control unit 1135 also has a function of reflecting the contents of the PCIe configuration register information of each endpoint 1122 to the 0th and first virtual PCIe configuration registers 1134 ₀ and 1134 ₁ .

0th server 1110, to the virtual PCIe configuration (Configuration) register 1134 ₀ of the 0th, performs PCIe configuration information read-write (Read / Write). The first server 1111 also reads / writes PCIe configuration information to / from the _first virtual PCIe configuration register 11341. Therefore, the PCIe configuration registers of the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N are not directly controlled from these servers 1110, 1111. These PCIe configuration registers are accessed via the configuration control unit 1135.

The 0th port 1131 ₀ and the first port 1131 ₁ identify the ACT control signal transferred in the PCIe packet. When an ACT switching instruction is sent from the 0th server 1110 or the first server 1111, an ACT / SBY switching instruction is issued to the ACT / SBY selection function unit 1133. The ACT / SBY selection function unit 1133 sends a signal indicating to the address conversion / distribution function unit 1138 whether the active ACT server is the 0th server or the first server 1110, 1111. Upon receiving this signal, the address translation / distribution function unit 1138 maintains the connection between the 0th port 1131 ₀ and the port connected to the ACT server of the first port 1131 ₁ . The address translation / distribution function unit 1138 does not exchange data between the _0th port 1131 ₀ and the SBY system port of the first port 1131 ₁ .

The configuration control unit 1135 obtains PCIe memory space map information held by the 0th and first servers 1110 and 1111 from the PCIe configuration register information set in the 0th and 1st virtual PCIe configuration registers 1134 ₀ and 1134 _1. get. Then, the servers 1110 and 1111 recognize how the end points 1122 are arranged in the memory space. At this time, if there is a difference between the setting values of the servers 1110 and 1111, the difference of the memory space of the first server 1111 is calculated with respect to the memory space of the 0th server 1110, and the difference information is address-converted. Transfer to table 1136.

The address conversion unit 1137 acquires the address space difference information of the 0th and first servers 1110 and 1111 transmitted from the address conversion table 1136. Then, an address conversion process is performed so that the access to the memory space of the first server 1111 has the same address as the access to the memory space of the 0th server 1110. Thereafter, the PCIe packet is exchanged when an access is performed between the first server 1111 and the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N.

The address conversion / distribution function unit 1138 performs the distribution of the PCIe packet to the _{0th to} Nth endpoints 1122 _{0 to} 1122 _N based on the address information stored in the PCIe packet header.

The packets flowing from the 0th to _Nth endpoints 1122 _{0 to} 1122 _N toward the 0th or first server 1110 or 1111 are based on the ACT information transmitted from the ACT / SBY selection function unit 1133. Thus, the packet is transmitted only in the port direction connected to the ACT server.

  As seen in this endpoint sharing system 1100, in the network device, the CPUs are arranged in both the ACT system and the SBY system, and the two systems are synchronized, while the CPU of one system is under control. It is desirable to operate the data by accessing the endpoint. For this reason, in the case of a network device composed of a total of two ACT and SBY CPUs and an endpoint, it is sufficient that only the ACT CPU is accessible to the endpoint. However, when a failure occurs, a mechanism is required for a new ACT CPU to be able to quickly access the endpoint after switching the CPU.

  When the existing PC eye (PCI) mechanism is used, the CPU to which the endpoint is mapped when the ACT CPU manages the endpoint and switches to the SBY CPU due to the occurrence of a failure. Memory space is not the same. In general, therefore, it is necessary to physically reset the endpoint and reset the setting data, and it is difficult to perform rapid system switching. In addition, during the reset or reset process, the endpoint cannot perform data communication. As a result, the reliability of the network device is lowered. For this reason, in a communication device that requires reliability, it is desired that CPU switching processing can be realized without performing reset or configuration processing for an endpoint.

  In the second related technology described above, a CPU mounted on a general-purpose server is used for system switching. The CPU on the server normally searches for endpoints under PCIe according to BIOS (Basic Input / Output System) instructions immediately after the power is turned on, and automatically maps the endpoints in the memory space. Perform the process. For this reason, it is impossible to control in which address space the user places the endpoint unless the bios is changed, for example. For this reason, it is difficult for two CPUs mounted on physically different servers to map the same end point on the same memory space.

  In PCIe (PCI Express), when an end point is mapped on the memory space of the CPU, a base address (Base Address) is set in the PCIe configuration register of the end point 1122 to determine the position in the memory space. The endpoint recognizes only the PCIe packet in which the address value based on the set base address information is set as the PCIe packet to be processed by itself. For this reason, the address value of the endpoint 1122 at the time of exchange between two CPUs needs to be a value set in the PCIe configuration register. As a result, when CPU switching is performed without resetting the PCIe configuration information of the endpoint 1122, the address for accessing the endpoint 1122 is converted so that it is in the same space before the endpoint 1122. Function is required.

  Therefore, in the second related technology, the endpoint 1122 is mapped to the memory space of the 0th server 1110 as the ACT server immediately after the power is turned on. For the access from the 0th server 1110 to each endpoint 1122, the address information is used as it is. When the ACT system and the SBY system are switched due to the occurrence of a failure, address conversion is performed for the access of each endpoint 1122 from the first server 1111 as the SBY server immediately after the power is turned on. As a result, a function for two CPUs to access the same endpoint is realized.

JP 2007-188446 A (paragraphs 0018 to 0024, FIG. 2)

  When such a second related technology is used, it is possible to realize a mechanism for sharing the endpoint 1122 among the plurality of servers 1110 and 1111. In addition, when the processing on the end point 1122 side increases, an expandable system configuration can be realized by adding the end points 1122.

  However, when the load on the server 1110, 1111 side increases, when the second related technology is used, it is not possible to adopt a method of increasing the number of servers 1110, 1111 according to this. If the method of increasing the number of servers 1110 and 1111 is adopted, the number of ACT servers 1110 increases. In this case, it is impossible for a plurality of ACT servers to access the endpoint 1122. . Therefore, in the method using the second related technology, when the load on the servers 1110 and 1111 increases, a coping method is adopted in which the capacity of the server itself is improved without increasing the number of these servers. However, there is a limit to improving the capabilities of the servers 1110 and 1111 themselves.

  In the second related technique, it has also been proposed to construct a system in which a plurality of servers can share memory by using a storage device using FC (Fibre Channel). This makes it possible to configure a plurality of endpoints and a plurality of servers as one system using PCIe.

  However, storage devices and network devices that use FC are expensive, and the improvement in throughput is inferior to other interface specifications such as Ethernet (registered trademark) and infiniband. In addition, since the PCIe data packet is encapsulated by the FC protocol and transferred between the server and the storage device, overhead is generated in the protocol processing unit, the load on the CPU side is increased, and high-speed data transfer is affected. It is done.

  In a system using FC, a hard disk (HD) is generally used as a storage medium. A hard disk requires a mechanical structure for data storage, and both read and write (Read / Wirte) speeds are slower than a general memory that can store data using only electrical signals. This is a drawback. Therefore, when a hard disk is used, it is common to operate a plurality of disks in parallel in order to increase the reading and writing speed. Although this makes it possible to increase the speed of reading and writing data, a large number of hard disks are required, which is disadvantageous in terms of cost in systems that do not require disk capacity.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an endpoint sharing system and a data transfer method for connecting a server and a storage device by PCIe and accelerating data transfer between a specific server of a plurality of servers and an integrated endpoint. It is to provide.

  In the present invention, (a) an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints (B) processing the data stored in the PCIe packet transmitted by the integrated endpoint side transmission means, which transmits the PCIe packet from the predetermined endpoint to the main server as the active server; Extended server determining means for determining an extended server; (c) extended server name inserting means for inserting the server name of the extended server determined by the extended server determining means into the PCIe packet; and (d) inserting the extended server name. Main server with PCIe packet with server name inserted by means Main server side transmitting means for transmitting to a predetermined storage device, and (e) a primary shared memory book for receiving the PCIe packet transmitted by the main server side transmitting means and writing it to the primary shared memory in the storage device. And (1) the PCIe packet written in the primary shared memory by the primary shared memory writing means is provided corresponding to each of the active and standby servers individually. The endpoint sharing system includes secondary shared memory transfer means for transferring to the secondary shared memory determined by the extended server determination means among the secondary shared memories used for individual transfer of data to and from.

  In the present invention, (b) an integrated end composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of end points. An expansion server side insertion means for inserting identification information representing the specific endpoint described above into the PCIe packet when an arbitrary main server and expansion server transmit data to the specific endpoint at the point; A plurality of PCIe packets into which the above-described identification information is inserted by the extension server side inserting means are individually provided for each main server and extension server and used for individual transfer of data to and from these servers. For any of the primary servers and expansion servers of the transmission source in the next shared memory Secondary shared memory storage means for storing in the secondary shared memory; and (c) when the secondary shared memory storage means stores the PCIe packet in any of the secondary shared memories, and reads out the identification information. The endpoint sharing system includes PCIe packet transmitting means for transmitting a PCIe packet to the endpoint determined from the identification information.

  Furthermore, in the present invention, (a) an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints (B) The main server that has received the PCIe packet transmitted in the integrated endpoint side transmission step transmits the PCIe packet from the predetermined endpoint to the main server as the active server. An expansion server determination step for determining an expansion server for processing data stored in the PCIe packet; and (c) an expansion server name insertion step for inserting the server name of the expansion server determined in the expansion server determination step into the PCIe packet. And (d) this expansion server A main server side transmission step of transmitting the PCIe packet with the server name inserted in the insertion step from the main server to the predetermined storage device; and (e) receiving the PCIe packet transmitted in the main server side transmission step A primary shared memory write step for writing to the primary shared memory in the storage device; and (f) the PCIe packet written to the primary shared memory in the primary shared memory write step for the active and standby systems. Transfer to the secondary shared memory determined in the above-described extended server determination step among the secondary shared memories provided individually corresponding to each server and used for individual transfer of data to and from these servers 2 And a next shared memory transfer step.

  Furthermore, in the present invention, (a) an integrated end composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for a computer and a plurality of end points. An expansion server-side insertion step in which an arbitrary primary server and an expansion server that transmit data to a specific endpoint at a point insert identification information representing the specific endpoint described above into a PCIe packet; A plurality of secondary shares used for individually transferring data to and from each of the main servers and expansion servers provided with the PCIe packet in which the identification information is inserted in the server-side insertion step. The secondary shared memory stored in the secondary shared memory corresponding to its own server A memory storing step; and (c) when the PCIe packet is stored in any of the secondary shared memories described in the secondary shared memory storing step, the identification information is read out and addressed to the endpoint determined from the identification information The data transfer method includes a PCIe packet transmission step of transmitting a PCIe packet to the network.

  As described above, according to the present invention, the PCIe packet sent from the integrated endpoint side is sent to the storage device, where the process of incorporating the transfer destination server selection result from the main server side and the data to the transfer destination server To store data in the secondary shared memory for passing the data. Thereby, the load on the CPU mounted on the main server can be reduced.

  Further, according to the present invention, when data is transferred from the server to the endpoint side, the identification information of the transfer destination endpoint is incorporated into the PCIe packet, and 2 corresponding to the transmission source server among the plurality of secondary shared memories. Next decided to store in shared memory. Thereby, it is possible to reduce the load on the CPU mounted on the server and transfer the PCIe packet to the destination endpoint.

It is a claim correspondence diagram of the endpoint sharing system of the present invention. It is a claim corresponding | compatible figure of the other end point sharing system of this invention. It is a claim corresponding figure of the data transfer method of this invention. It is a claim corresponding | compatible figure of the other data transfer method of this invention. 1 is a system configuration diagram illustrating an endpoint sharing system according to an embodiment of the present invention. It is explanatory drawing which showed the mode of the configuration process until the address conversion table preparation after power-on of the server in this Embodiment. It is explanatory drawing which showed the concept of the base address in this Embodiment. It is explanatory drawing which contrasted and showed the memory space of the ACT type | system | group server group in this Embodiment, and a SBY type | system | group server group. It is explanatory drawing showing the read-and-write process of the data by the 0-0 server which comprises the ACT type | system | group server group in this Embodiment. It is explanatory drawing showing the data read-and-write process by the 1-0th server which comprises the SBY type | system | group server group in this Embodiment. It is explanatory drawing which showed switching operation of the ACT type | system | group and SBY type | system | group in this Embodiment. It is explanatory drawing showing the mode of the software process by the side of the server in this Embodiment. It is explanatory drawing showing a mode that a server accesses with respect to an endpoint via the memory | storage device in this Embodiment. It is explanatory drawing which showed the mode of the data acquisition to the server from the 1st integrated endpoint in this Embodiment. 1 is a system configuration diagram specifically illustrating a configuration of an endpoint sharing system according to the present embodiment, centering on a storage device. FIG. 2 is a system configuration diagram showing a general connection state between each server and a storage device in the present embodiment. It is explanatory drawing showing the mode of the transfer process of the data in the endpoint sharing system of this Embodiment. It is a system configuration figure showing composition of an end point sharing system in the 1st modification of the present invention. FIG. 10 is a system configuration diagram showing an endpoint sharing system in which N integrated endpoints and N expansion servers are used as a second modification of the present invention. It is a system configuration figure showing an outline of composition of an end point sharing system in the 1st related art. It is a system configuration figure showing an outline of composition of an end point sharing system in the 2nd related art.

  FIG. 1 is a diagram corresponding to claims of the endpoint sharing system of the present invention. The endpoint sharing system 10 of the present invention includes an integrated endpoint side transmission unit 11, an extended server determination unit 12, an extended server name insertion unit 13, a main server side transmission unit 14, and a primary shared memory writing unit 15. And secondary shared memory transfer means 16. Here, the integrated endpoint transmission means 11 transmits a PCIe packet from a predetermined endpoint in the integrated endpoint to the main server as the active server. The integrated endpoint is composed of a PCI proxy function unit as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers, and a plurality of endpoints. The expansion server determination unit 12 determines an expansion server that processes data stored in the PCIe packet transmitted by the integrated endpoint side transmission unit 11. The extension server name insertion unit 13 inserts the server name of the extension server determined by the extension server determination unit 12 into the PCIe packet. The main server side transmission means 14 transmits the PCIe packet having the server name inserted by the extended server name insertion means 13 from the main server to a predetermined storage device. The primary shared memory writing unit 15 receives the PCIe packet transmitted by the main server side transmission unit 14 and writes it in the primary shared memory in the storage device. The secondary shared memory transfer means 16 is provided for each of the active system and standby system servers, and the secondary shared memory transfer means 16 is a secondary shared memory used for individual transfer of data to and from these servers. The data is transferred to the secondary shared memory determined by the extension server determining means 12. This PCIe packet is a packet written in the primary shared memory by the primary shared memory writing means 15.

  FIG. 2 is a diagram corresponding to claims of another endpoint sharing system of the present invention. Another endpoint sharing system 20 according to the present invention includes an extended server side insertion unit 21, a secondary shared memory storage unit 22, and a PCIe packet transmission unit 23. Here, the extended server side inserting means 21 is identification information representing the specific end point described above in the PCIe packet when any main server and the extended server transmit data to the specific end point in the integrated end point. Insert. The integrated endpoint is composed of a PCI proxy function unit as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers, and a plurality of endpoints. The secondary shared memory storage means 22 is a plurality of secondary shared memories which are provided for individually corresponding to the main server and the expansion server and used for individual transfer of data to and from these servers. Are stored in the secondary shared memory corresponding to the above-mentioned arbitrary main server and expansion server. This PCIe packet is a packet in which the above-described identification information is inserted by the extended server side inserting means 21. The PCIe packet transmitting unit 23 reads the identification information when the secondary shared memory storage unit 22 stores the PCIe packet in any of the secondary shared memories, and reads the identification information to the endpoint addressed from the identification information. Send the packet.

  FIG. 3 is a diagram corresponding to claims of the data transfer method of the present invention. The data transfer method 30 of the present invention comprises an integrated endpoint side transmission step 31, an expansion server determination step 32, an expansion server name insertion step 33, a main server side transmission step 34, and a primary shared memory writing step 35. A secondary shared memory transfer step 36 is provided. Here, in the integrated endpoint transmission step 31, a PCIe packet is transmitted from a predetermined endpoint in the integrated endpoint to the main server as the active server. The integrated endpoint is composed of a PCI proxy function unit as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers, and a plurality of endpoints. In the expansion server determination step 32, the main server that has received the PCIe packet transmitted in the integrated endpoint side transmission step 31 determines an expansion server that processes the data stored in the PCIe packet. In the extension server name insertion step 33, the server name of the extension server determined in the extension server determination step 32 is inserted into the PCIe packet. In the main server side transmission step 34, the PCIe packet into which the server name is inserted in the extended server name insertion step 33 is transmitted from the main server to a predetermined storage device. In the primary shared memory writing step 35, the PCIe packet transmitted in the main server side transmission step 34 is received and written in the primary shared memory in the storage device. In the secondary shared memory transfer step 36, the PCIe packet is provided for each of the active and standby servers individually corresponding to each of the secondary shared memory used for individual transfer of data to and from these servers. The data is transferred to the secondary shared memory determined in the extended server determination step 32. This PCIe packet has been written in the primary shared memory described above in the primary shared memory write step 35.

  FIG. 4 shows a claim correspondence diagram of the data transfer method of the present invention. The data transfer method 40 of the present invention includes an extended server side insertion step 41, a secondary shared memory storage step 42, and a PCIe packet transmission step 43. Here, in the extended server side insertion step 41, any main server and extended server that transmit data to a specific endpoint in the integrated endpoint inserts identification information representing the specific endpoint described above into the PCIe packet. To do. The integrated endpoint is composed of a PCI proxy function unit as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers, and a plurality of endpoints. In the secondary shared memory storing step 42, the PCIe packet into which the identification information described above in the extended server side inserting step 41 is inserted is provided corresponding to each of the main server and the extended server, and data between these servers is provided. Are stored in the secondary shared memory corresponding to the own server among the plurality of secondary shared memories used for the individual transfer. In the PCIe packet transmission step 43, when the PCIe packet is stored in one of the secondary shared memories described in the secondary shared memory storage step 42, the identification information is read out and addressed to the endpoint determined from the identification information. A PCIe packet is transmitted.

  <Embodiment of the Invention>

  Next, an embodiment of the present invention will be described.

FIG. 5 shows an endpoint sharing system according to an embodiment of the present invention. The endpoint sharing system 100 includes first and second integrated endpoints 101 ₁ and 101 ₂ . In addition, the endpoint sharing system 100 includes a 0-0 server (Server # 0-0) 103, a 0-1 server (Server # 0-1) 104 ₁ , and an SBY as an ACT (active) server group. It includes a first 1-0 server (server # 1-0) 105 as (standby) system server group, a 1-1 server (server # 1-1) 106 _1. The endpoint sharing system 100 further includes a storage device 107. A storage device 107, a 0-0, a 0-1, each server 103 to 106 ₁ of the 1-0 and 1-1, in addition to being directly connected via a LAN (Local Area Network) 108 connected Has been. A first integrated endpoint 101 _1, first 0-0 server 103 and the 1-0 server 105 is directly connected. A second integrated endpoint 101 _2, first 0-0 server 103 and the 1-0 server 105 are also similarly connected directly.

The 0-0 server 103 and the 1-0 server 105 are defined as main servers in this specification. The 0th to Nth endpoints (EP # 0) of the first integrated endpoint 101 ₁ ~EP # N) have the ability to access 111 ₀ ~111 _N. On the other hand, the 0-1st server 104 ₁ and the 1-1st server 106 ₁ are defined as extended servers in this specification, and the 0th to Nth endpoints (EP # 0 to EP #). N) Does not have an access function to 111 _{0 to} 111 _N.

In the present embodiment, one 0-1 server 104 ₁ is arranged as an expansion server in the ACT server group, and one 1-1 server 106 is used as an expansion server in the SBY server group. ₁ is arranged. A plurality of expansion servers may be arranged in the ACT server group or the SBY server group.

The 0-0, the 0-1, the 1-0 and 1-1 each server 103-106 ₁ and the first and second integrated endpoint 101 _1, 101 _2, are physically separated from each Yes. The first and second integrations between the 0-0 server 103 as the primary server and the first and second integration endpoints 101 ₁ , 101 ₂ , and also the 1-0 server 105 as the primary server The end points 101 ₁ and 101 ₂ are connected using a PCIe cable. Here, “PCIe” is an abbreviation of “PCI (Peripheral Component Interconnect) Express”.

The 0th to 0th servers 103 as the main servers are mounted with a PCIe NIC card (Network Interface Card) (PCIe NIC # 001) 121 for connection to the first integrated endpoint 101 ₁ using a PCIe cable. Yes. Further, the 0-0 server 103 implements a PCIe NIC card (PCIe NIC # 002) 122 for connecting with the second integrated endpoint 101 ₂ and PCIe cable. Further, the 0-0 server 103 includes a PCIe NIC card (PCIe NIC # 00E) 123 as an interface for exchanging data with the first and second integrated endpoints 101 ₁ and 101 _2, and between the extended servers. PCIe NIC card (PCIe NIC # 00S) 124 used for data exchange.

Similarly, the 1-0 server 105 as the main server implements a PCIe NIC card (PCIe NIC # 101) 125 for connecting with the first integrated endpoint 101 ₁ and PCIe cable. The server 105 of the 1-0 implements a PCIe NIC card (PCIe NIC # 102) 126 for connecting with the second integrated endpoint 101 ₂ and PCIe cable. Further, the 1-0 server 105 includes a PCIe NIC card (PCIe NIC # 10E) 127 as an interface for exchanging data with the first and second integrated endpoints 101 ₁ and 101 _2, and between the extended servers. PCIe NIC card (PCIe NIC # 10S) 128 used for data exchange.

On the other hand, the 0-1st and 1-1st servers 104 ₁ , 106 ₁ as expansion servers have a single system NIC NIC card for connection to the storage device 107. That is, the 0-1st server 104 ₁ has a PCIe NIC card (PCIe NIC # 01S) 131 used for data exchange between servers. The _first-first server 106 ₁ includes a PCIe NIC card (PCIe NIC # 11S) 132 used for data exchange between servers.

Next, the first and second integrated endpoints 101 ₁ and 101 ₂ will be described. However, since the second integrated endpoint 101 ₂ has the same configuration as the _first integrated endpoint 101 ₁ , the illustration and description of the specific configuration are omitted.

The first integrated endpoint 101 ₁ includes the above-described _{0th to} Nth endpoints (EP # _{0 to} EP # N) 111 _{0 to} 111 _N and a PCI proxy function unit 141. The PCI proxy function unit 141 and the _{0th to Nth} end points 111 _{0 to} 111 _N are connected using a PCIe bus.

  The PCI proxy function unit 141 is a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers. The PCI proxy function unit 141 includes a CPU (not shown) and a recording medium such as a ROM (Read Only Memory) (not shown) that stores a control program executed by the CPU, and includes the following units.

(A) 0th port 151 ₀
It is connected to the 0th-0th server 103 via the PC Express cable 161.
(B) First port 151 ₁
The first 1-0 server 105 is connected to the PC Express cable 162.
(C) ACT (active) / SBY (standby) selection function unit 152
And ACT-based server group consisting server 104 ₁ of the first 0-0 server 103 and the 0-1, the server 105 of the 1-0, one of the SBY system server group consisting of 1-1 server 106 ₁ The ACT (active) system is selected and the other is selected as the SBY (standby) system.
(D) 0th virtual PCIe configuration register 154 ₀
PC i Express Config register information of each end point 111 is stored.
(E) First virtual PCIe configuration register 154 ₁
PC i Express Config register information of each end point 111 is stored.
(F) Configuration control unit 155
Zeroth managing virtual PCIe configuration registers 154 ₀ and the first virtual PCIe configuration register 154 _1.
(G) Address conversion table 156
Address space difference information is held as difference information of the memory space between the ACT server group and the SBY server group.
(H) Address conversion unit 157
The address is converted so that the access to the memory space of the ACT server group and the SBY server group is the same address.
(I) Address conversion / distribution function unit 158
PC iExpress packets are distributed between the ACT server group and the port connected to the ACT server in the SBY server group.
(J) _{0th to} Nth PCIe ports (Port) 159 _{0 to} 159 _N
The _{0th to} Nth end points 111 _{0 to} 111 _N are connected correspondingly.

The PCI proxy function unit 141 will be described more specifically. The 0th port 151 ₀ and the first port 151 ₁ identify the ACT control signal transferred in the PC Express packet. When an ACT switching instruction is sent from an ACT server group or an SBY server group, an ACT / SBY switching instruction is issued to the ACT / SBY selection function unit 152. In the ACT / SBY selection function unit 152, the ACT server sends a signal indicating the ACT server group or the SBY server group to the address conversion / distribution function unit 158. The address translation / distribution function unit 158 maintains the connection with the port connected to the ACT system server and does not exchange data with the SBY system port.

The configuration control unit 155 has a function of controlling a PC eye express configuration register (not shown) held by the _{0th to} Nth end points 111 _{0 to} 111 _N. Further, with respect to the virtual PCIe configuration (Configuration) register 154 ₁ virtual PCIe configuration (Configuration) register 154 ₀ and the first of the 0 has a function to reflect the contents of the CPC's eye Express configuration registers information for each endpoint 111 . ACT-based servers and the SBY system server group, the 0th virtual respect PCIe configuration registers 154 ₀ and the first virtual PCIe configuration register 154 _1, CPC eye Express configuration information read (Read) and write (Write) I do. Therefore, the PC Express configuration register register of each endpoint 111 is directly set from the 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 _1. There is no control. The PC Express configuration register register of each end point 111 is accessed via the configuration control unit 155.

Further, configuration controller 155, from the 0 virtual PCIe configuration registers 154 ₀ and the first virtual PCIe configuration register 154 ₁ CPC eye Express configuration register information set to the, ACT-based servers and the SBY system server group The PC Eye Express memory space map information held is acquired. Then, how the 0-th server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 ₁ arrange each endpoint 111 in the memory space. Recognize. If there is a difference, the difference of the memory space of the SBY server group is calculated for the memory space of the ACT server group, and the obtained difference information is transferred to the address conversion table 156.

  The address conversion unit 157 acquires address space difference information for the ACT server group and the SBY server group transmitted from the address conversion table 156. Then, an address conversion process is performed so that the access to the memory space of the SBY server group has the same address as the access to the memory space of the ACT server group. Further, when accessing between the SBY server group and each of the end points 111, PC iExpress packets are exchanged.

  The address conversion / distribution function unit 158 distributes the PC-Express packet to each endpoint 111 based on the address information stored in the PC-Express packet header. A packet that flows from each end point 111 in the server direction transmits the packet only in the port direction connected to the ACT server group based on the ACT information transmitted from the ACT / SBY selection function unit 152.

Next, the storage device 107 will be described. The storage device 107 is connected to the 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 ₁ via the LAN. As a result, the data stored in the storage device 107 can be shared by the 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 _1. Become.

The storage device 107 according to the present embodiment uses a general-purpose semiconductor memory such as a DRAM (Dynamic Random Access Memory) and an FRAM (FeRAM). PCIe is used for data transfer between the 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, the 1-1 server 106 _1, and the storage device 107. These parts and data transfer standards are general-purpose products and standardized ones that are available on the market at a low cost.

Only the 0-0 server 103 and the 1-0 server 105 are accessible to the _{0th to} Nth endpoints 111 _{0 to} 111 _N. When the 0-1st server 104 ₁ and the 1-1st server 106 ₁ access the endpoint 111, the target data is once transferred to the storage device 107. Then, the endpoint 111 is accessed via the corresponding one of the 0-0 server 103 or the 1-0 server 105.

<Description of operation>
Next, the operation of the endpoint sharing system 100 configured as described above will be described.

The 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 ₁ are each equipped with a CPU (not shown). PC Eye Express access from the CPU mounted on these servers to the _{0th to} Nth endpoints 111 _{0 to} 111 _N is roughly divided into access to the PC Eye Express configuration register (configuration register) and actual data. There are two types of access. In the endpoint sharing system 100 according to the present embodiment, the configuration control unit 155 performs processing for access to the PC express configuration register. Further, the actual data access is executed by the address conversion unit 157 and the address conversion / distribution function unit 158 as the center. In the endpoint sharing system 100, access to the PC Express configuration register is executed when the power is turned on. After the PC Express configuration register is once set, switching to the 0-0 server 103, the 0-1 server 104 ₁ , the 1-0 server 105, and the 1-1 server 106 ₁ is performed. Even if it occurs, the setting is not changed.

  <Configuration processing>

  FIG. 6 shows how the configuration process is performed until the address conversion table is created after the server is turned on. This will be described with reference to FIG.

It is the 0-0 server 103 and the 1-0 server 105 that configure the endpoint 111. In the general-purpose server, immediately after the power is turned on, the endpoint under the PC Express bus is searched and the endpoint is mapped on the PCI memory space. In the endpoint sharing system 100 of the present embodiment, the first integrated endpoint 101 ₁ is the 0-0 server 103 (“Server # 0-0”) and the 1-0 server 105 (Server # 1-0). The proxy server responds to the access to the PC express configuration register by proxy, so that the 0-0 server 103 or the 1-0 server 105 has the 0th to Nth endpoints. It is possible to map 111 _{0 to} 111 _N on the memory space.

This will be specifically described. As shown in FIG. 6, it is assumed that the powers of the 0-0 server 103 and the 1-0 server 105 are turned on at time t ₁ . The configuration control unit 155 transmits the PC Express configuration space of the _{0th to Nth} endpoints 111 _{0 to} 111 _N connected to the first integrated endpoint 101 ₁ to the 0-0 server 103 or the first Read in place of the server 105 of −0 (step S201). In FIG. 6, the Xth end point 111 _X is simply expressed as “EP # X” (where X is an arbitrary integer between 0 and N). The same applies to the following figures.

In the example shown in FIG. 6, first, the 0th endpoint 111 ₀ (“EP # 0”) is read at time t ₂ , and then the first endpoint 111 ₁ (“EP # 1”) is read. The Similarly, the reading is executed up to the N-th endpoint 111 _N (“EP # N”).

The configuration control unit 155 reflects the result read in step S201 in the 0th and 1st virtual PCIe configuration registers 154 ₀ and 154 ₁ . Thus, the 0-0 server 103 and the 1-0 server 105 send the contents of the PC express configuration registers of the _{0th to Nth} endpoints 111 _{0 to} 111 _N via the configuration control unit 155. It becomes possible to lead.

By the way, it is assumed that the ACT (active) server group is set to the active system when the power is turned on at time t ₁ . Further, this basis the N endpoint 111 _N ( "EP # N") to the time t ₃ after the previous read is finished in the state of the port 151 ₀ of the 0 ACT, the first port 151 Assume that ₁ is in the SBY state. FIG. 6 collectively shows a state of processing of configuration data between the 0-0 server 103 and the first integrated endpoint 101 ₁ after time t ₃ as step S202. Further, in FIG. 6, the state of processing of the configuration data between the server 105 of the 1-0 in the case of the first integrated endpoint 101 ₁ shows collectively as step S203.

First, the process of step S202 performed between the ACT 0-0 server 103 and the first integrated endpoint 101 ₁ will be described. The 0-0 server 103 first reads the contents of the 0th endpoint 111 ₀ (“EP # 0”) stored in the _0th virtual PCIe configuration register 154 ₀ , and the 0th endpoint 111 _0. to write the configuration data to the virtual PCIe configuration register 154 ₀ of the 0 to be written to. Configuration control unit 155, the data from the first 0-0 server 103 to the virtual PCIe configuration register 154 ₀ of the 0 is written, the configuration data via the PCIe ports 159 ₀ of the zeroth, first 0 implementing the writing to the endpoint 111 _0. Writing to the 0th endpoint 111 ₀ CPC eye Express configuration registers of it is made at time t ₄ in FIG.

Similarly, the 0th-0th server 103 reads the content of the first endpoint 111 ₁ (“EP # 1”) stored in the _0th virtual PCIe configuration register 1540, and the first endpoint The configuration data to be written to 111 ₁ is written to the 0th virtual PCIe configuration register 154 ₀ . Configuration control unit 155, the data from the first 0-0 server 103 to the virtual PCIe configuration register 154 ₀ of the 0 is written, the configuration data via the first PCIe ports 159 _1, the first The end point 111 _{1 is written} .

In the same manner, the 0-0 server 103 performs the processing after the second endpoint 111 ₂ (“EP # 2” (not shown)) stored in the _0th virtual PCIe configuration register 1540. Do in order. When reading the contents of the 0th virtual PCIe configuration register 154 ₀ stored in the first N endpoint 111 _N ( "EP # N"), the virtual configuration data to be written to the endpoint of the first N of the 0 writing to the PCIe configuration register 154 _0. Configuration control unit 155, the data from the first 0-0 server 103 to the virtual PCIe configuration register 154 ₀ of the 0 is written, the configuration data via the PCIe ports 159 _N of the N, N-th Write to the end point 111 _N of this.

Next, a description is given of processing of step S203 which is performed between the first 1-0 server 105 of the SBY side of the first integrated endpoint 101 _1. The 1-0 server 105 first reads the content of the 0th endpoint 111 ₀ (“EP # 0”) stored in the _first virtual PCIe configuration register 1541 and writes it to the 0th endpoint. to write the configuration data to the first virtual PCIe configuration register 154 _1. However, in this case, configuration control unit 155 is not performing a write to the end point 111 ₀ of the 0th behalf.

In the same manner, the server 105 of the 1-0 performs the first endpoint 111 ₁ ( "EP # 1") and the subsequent processing stored in the first virtual PCIe configuration register 154 ₀ in order. When reading the contents of the first virtual PCIe configuration register 154 endpoint of the N stored in ₁ 111 _N ( "EP # N"), the configuration data to be written to the endpoint of the N first virtual to write to the PCIe configuration register 154 _1. However, in this case as well, the configuration control unit 155 does not write to the _Nth endpoint 111 _{N on} behalf of the proxy.

As described above, after power-on, the 0-0 server 103 is fixed as the active server. In this state, the first integrated endpoint 101 ₁ reflects only the read and write processing for the PC Express configuration from the 0-0 server 103 to the _{0th to Nth} endpoints 111 _{0 to} 111 _N. (Step S202). As for access from the 1st- _0th server 105 which is the standby server, the data is held inside the first integrated endpoint 101 ₁ and reflected to the _{0th to Nth} endpoints 111 _{0 to} 111 _N Not implemented (step S203).

  By the way, the setting contents of the PC Express configuration register by the 1-0 server 105 may be set to a value different from the setting contents of the configuration register by the 0-0 server 103. For this reason, the configuration control unit 155 holds the setting values of the PC express configuration registers of both the 0-0 server 103 and the 1-0 server 105.

On the other hand, the configuration control unit 155 creates the address conversion table 156 based on the value of the base address (Base Address) included in the PC express configuration register information of each server obtained after power-on ( Step S204). This is to prevent the base address from differing when the 0-0th server 103 or the 1-0 server 105 accesses the _{0th to} Nth end points 111 _{0 to} 111 _N.

FIG. 7 is for explaining the concept of the base address. As described above, the 0-0th server 103 and the 1-0th server 105 recognize the _{0th to Nth} endpoints 111 _{0 to} 111 _N when the power is turned on. Then, the PC Express configuration register is set for the _{0th to} Nth end points 111 _{0 to} 111 _N. When the configuration process is completed, the 0-0 server 103 and the 1-0 server 105 independently create PCIe memory spaces 170 and 171 (steps S221 and S222).

The 0-0th server 103 and the 1-0th server 105 cannot directly access the _{0th to Nth} endpoints 111 _{0 to} 111 _N as described above. Therefore, by passing through the first integration zeroth and first endpoint 101 ₁ virtual PCIe configuration register 154 _0, 154 ₁ configuration controller 155 using endpoint 111 ₀ of 0th N Access to 111 _N. Therefore, in the virtual PCIe configuration registers 154 ₀ and 154 ₁ , registers having the same configuration as the configuration register of each endpoint 111 (“EP # 0_config”, “EP # 1_config”,..., “EP #” N_config ") 180, 181 exist. The 0-0th server 103 and the 1-0th server 105 access the virtual PCIe configuration registers 154 ₀ , 154 ₁ .

After acquiring the PC Express configuration space information of the 0-0 server 103 and the 1-0 server 105, the configuration control unit 155 determines the 0th mapping information for each of the end points 111 _{1 to} 111 _N. The difference between the set values of the −0 server 103 and the 1-0 server 105 is calculated. This will be described as step S223 in FIG.

  FIG. 8 compares the memory space of the ACT server group and the SBY server group. This will be described with reference to FIGS. 5 and 7.

  The PCIe memory space 170 of the ACT server group is compared with the PCIe memory space 171 of the SBY server group. Then, from the calculation result of the difference between the setting values of the ACT server group and the SBY server group, the PCIe memory space 171 of the SBY server group is incremented by “0x0001_0000” with respect to the base address of each endpoint 111. It turns out that it is a value. Therefore, the configuration control unit 155 subtracts the base address by “0x0001 — 0000” for each endpoint 111 in the address conversion table 156 when the 1st-0th server 105 enters the state of accessing each endpoint 111. A value should be set.

Returning to FIG. 7 again, the description will be continued. In the address conversion unit 157, the address information stored in the header portion of the PC-Express packet when communication is performed between the 1-0 server 105 and the _{0th to Nth} endpoints 111 _{0 to} 111 _N Is changed to a value obtained by subtracting “0x0001 — 0000”. By accessing with the address information after this change, the access that does not contradict the address space based on the base address set in the _{0th to Nth} endpoints 111 _{0 to} 111 _N is performed. The server 105 can be provided.

Note that the PCIe configuration registers 163 _{1 to} 163 _N (“EP # 0_config” to “EP # N_config”) illustrated in FIG. 7 are originally mounted for each of the _{0th to Nth} endpoints 111 _{0 to} 111 _N. Register. Therefore, these PCIe configuration registers 163 _{1 to} 163 _N should be directly controlled by CPUs originally mounted on the ACT server group and the SBY server group, respectively. However, in the endpoint sharing system 100 of the present embodiment using the _first integrated endpoint 1011, the configuration control unit 155 has a function of performing control by proxy. Therefore, by concealing the PC Express memory space difference between the ACT server group and the SBY server group from the endpoint 111, both the 0-0 server 103 and the 1-0 server 105 can conceal. Access is made possible.

  <Data transfer processing>

At the time of access for data transfer between the ACT server group and the _{0th to} Nth endpoints 111 _{0 to} 111 _N , the address conversion process in the PCI proxy function unit 141 does not occur. Data read and write processing in this case will be described next.

  FIG. 9 shows data read and write processing by the 0-0 servers constituting the ACT server group. This will be described with reference to FIG.

For access from the ACT server group to the _{0th to} Nth endpoints 111 _{0 to} 111 _N , the corresponding endpoint is based on the base address information set in the _0th virtual PCIe configuration register 154 _0. Sort to connected ports. Specifically, based on the address information included in the header information of the PC-I express packet, the address translation / distribution function unit 158 determines the access destination end point 111. Then, the distribution is performed on the ports ( _{0th to} Nth PCIe ports 159 _{0 to} 159 _N ) to which the corresponding endpoint 111 is connected.

In addition, for data transfer from the _{0th to} Nth endpoints 111 _{0 to} 111 _N to the ACT server group or the SBY server group, the address conversion / distribution function unit 158 also sends the data to the active server. Perform data transfer. If the SBY server group is the active system, the address information in the PC Express packet header is not changed, and the data is transferred to the SBY server group.

A specific example is given. First, using the 0th port (“Port # 0”) 151 ₀ from the 0-0 server 103 to the PCI proxy function unit (“PCIProxy”) 141 of the first integrated endpoint 101 ₁ , based on the base address information, the 0 endpoint ( "EP # 0") 111 to write the data to ₀ (step S241). PCI Puroshiki function unit 141 writes the data to the endpoint 111 ₀ of the 0 (step S242). Thereafter, data is read from the endpoint 111 ₀ of the 0 to PCI Puroshiki function unit 141 (step S243). Next, the read data is sent (read) from the PCI proxy function unit 141 to the 0th-0th server 103 (step S244).

Thereafter, from the 0-0 server 103 using ports 151 ₀ of the zeroth, the first integrated endpoint 101 ₁ of PCI Puroshiki function unit 141, based on the base address information, first Data for the end point ("EP # 1") 111 _{1 is written} (step S245). The PCI proxy function unit 141 writes this data to the first end point 111 ₁ (step S246). Thereafter, data is read from the first end point 111 ₁ to the PCI proxy function unit 141 (step S247). Next, this data is read from the PCI proxy function unit 141 to the 0th-0th server 103 (step S248). In the same manner, the data read and write processing by the 0-0 server 103 continues.

At the time of access for data transfer between the 1-0th server 105 and the _{0th to} Nth endpoints 111 _{0 to} 111 _N , an address conversion process in the PCI proxy function unit 141 occurs. Data read and write processing in this case will be described next.

  FIG. 10 shows data read and write processing by the 1-0th servers constituting the SBY server group. This will be described with reference to FIG.

Regarding the access from the 1-0th server 105 to the _{0th to} Nth endpoints 111 _{0 to} 111 _N , data write from the 1st-0 server 105 will be described first. For data writing, the address conversion unit 157 changes the address information in the PC express packet header, and transfers the data to the address conversion / distribution function unit 158. The address translation / distribution function unit 158 determines which of the _{0th to Nth} endpoints 111 _{0 to} 111 _N is to be allocated based on the information managed by the configuration control unit 155 and transfers the data. To implement.

In addition, for data transfer from the _{0th to} Nth endpoints 111 _{0 to} 111 _N to the 0-0 server 103 or the 1-0 server 105, the address translation / distribution function unit 158 also sends it to the active server. Data is transferred only to that. When the first 1-0 server 105 is an active system, the address information in the PC Express packet header is changed, and the data is transferred to the first 1-0 server 105.

A specific example is given. First, the PC Express packet (step S261) sent from the 1-0th server 105 via the first port ("Port # 1") 151 ₁ in the ACT state is sent to the address conversion unit 157. In step S262, the address information in the PC express packet header is changed. Address conversion and sorting function unit 158 receives the transfer of the data, based on the information managed by the configuration control unit 155, the zeroth endpoint ( "EP # 0") which is transferred to 111 ₀ (step S263).

Data sent from the endpoint 111 ₀ of the 0 is allocated to deliver to a 1-0 server 105 as active server by the address converting and sorting function unit 158, transferred to the address conversion unit 157 (Step S264). Then, the address information in the PC express packet header is changed (step S265) and transferred to the 1-0 server 105 (step S266). Data transferred from the 1-0th server 105 to the 1st to Nth endpoints ("EP # 1" to "EP # N") 111 _{1 to} 111 _N and the 1st to Nth endpoints 111 ₁ The same applies to data transferred from ˜111 _N to the 1-0 server 105. Therefore, description of the processing in steps S267 to S278 is omitted.

  <ACT switching operation>

  FIG. 11 shows the switching operation between the ACT system and the SBY system. Here, a case where the 0-0 server 103 is the active system and the 1-0 server 105 is the standby system is shown as an example. The operation is the same when the 0-0th server 103 is the standby system and the 1-0th server 105 is the active system. This will be described with reference to FIG.

  The 0-0 server 103 and the 1-0 server 105 have a function of periodically monitoring each other's state using some signal transmission means such as a LAN (Local Area Network) 108. Such a function is achieved, for example, by a CPU mounted on each of the 0-0 server 103 and the 1-0 server 105 and a recording medium in the 0-0 server 103 and the 1-0 server 105 (see FIG. This is realized by executing a control program stored in (not shown).

  Assume that the active 0th-0 server 103 does not return a response to a response request from the standby 1-0 server 105. In this case, the 1-0 server 105 detects that some abnormality has occurred in the 0-0 server 103 (step S291). Based on this, the system switching operation is started (step S292).

With this system switching operation, the 1-0 server 105 is the first port (“Port # 1”) 151 ₁ that is the standby system of the first integrated endpoint 101 ₁ to which it is directly connected. In response to this, a system switching request is sent out as a PC express packet (step S293). When receiving the system switching request, the first port 151 ₁ transmits an ACT / SBY switching request signal to the ACT / SBY selection function unit 152. ACT · SBY selecting function unit 152 receives the system switching request (step S294), the zeroth port ( "Port # 0") 131 transmits the ACT · SBY switching request signal to _0.

When receiving the ACT / SBY switching signal (step S295), the 0th port 151 _{0 serving as} the active system sends a system switching request to the 0-0th server 103 as a PC Express packet (step S296). As a result, the 0-0th server 103 recognizes the system switching (step S297). The 0-0 server 103, based on which to implement the switching of the active system and the standby system (step S298), thereafter, the zeroth port 151 using CPC eye express packet that was carried out system switching ₀ (Step S299).

This system switching completion notification is received and confirmed by the ACT / SBY selection function unit 152 (step S300). Based on this, the ACT / SBY selection function unit 152 sets the 0th port 151 ₀ of the first integrated endpoint 101 ₁ to the standby system (step S301), and sets the first port 151 ₁ to the active system. Setting is made (step S302). Thereafter, a signal indicating that the system has been switched is notified from the _first port 151 ₁ to the 1-0 server 105 using the PC Express packet (step S303). Upon receiving this notification, the 1-0 server 105 determines that the 1-0 server 105 has been switched from the standby system to the active system (step S304).

Next, a description will be given of a case where an abnormality occurs in the 0-0 server 103 that is the active system and there is no response to the transmission of the system switching request from the 1-0 server 105 (step S293). In this case, ACT · SBY selecting function unit 152 inside the first integrated endpoint 101 ₁ activates a timer (not shown). Then, if the 0-0 server 103 is normal, it is determined whether there is a response from the 0-0 server 103 within a predetermined time to respond sufficiently. If there is a response from the 0-0 server 103 within the specified time, the same processing as described above may be performed.

In contrast, it is assumed that there is no response from the 0-0th server 103 within the specified time. In this case, the 1-0 server 105 performs a system switching completion notification without waiting for a response from the 0-0 server 103 any more. Then, the first port 151 ₁ that has been the SBY system until now is switched to the ACT system.

In the endpoint sharing system 100 according to the present embodiment, apart from the above, it is also possible to start system switching for the purpose of periodic system switching and maintenance work. The first port 151 ₁ of the 1-0th server 105 switched from the standby system to the active system can communicate actual data to the _{0th to Nth} endpoints 111 _{0 to} 111 _N.

Note that the PC Express configuration register on the 1-0th server 105 side is already set after the 1-0th server 105 is powered on. For this reason, the PC Express configuration operation for corresponding to the memory space of the 1-0th server 105 for the _{0th to} Nth end points 111 _{0 to} 111 _N is unnecessary. Therefore, processing such as resetting the _{0th to} Nth endpoints 111 _{0 to} 111 _N before changing the setting of the configuration register and resetting processing of each PC express configuration register becomes unnecessary.

Therefore, communication between the _{0th to Nth} endpoints 111 _{0 to} 111 _N and the 0-0 server 103 and the 1-0 server 105 cannot be executed during system switching. However, in the communication processing between the end points 111 in the _first integrated end point 101 ₁ (for example, communication from the 0th end point 110 ₀ to the first end point 111 ₁ via the PCI proxy function unit 141), Communication processing can be continued during the system switching operation.

  <Data transfer between servers>

  FIG. 12 shows the state of software processing on the server side. In the endpoint sharing system 100 according to the present embodiment, as described with reference to FIG. 5, two types of servers, that is, an ACT server group and an SBY server group are used. The ACT server group and the SBY server group have the same configuration. Accordingly, application software that operates on these server groups will be described with a focus on the ACT server groups.

  Table 1 below shows application software that operates in the ACT server group and the SBY server group according to the present embodiment. Each application software described in Table 1 has an interface capable of mutual notification of events, and detects the occurrence of an event.

FIG. 12 shows a state where the ACT server group and the SBY server group are connected in such a manner that one storage device 107 is divided and used. Here, for the sake of convenience, the storage device portion to which the ACT server group is connected is represented as a storage device 107 ₀ , and the storage device portion to which the SBY server group is connected is represented as the storage device 107 ₁ .

Each of the storage devices 107 ₀ and 107 ₁ is used for endpoint communication as a server temporary region as an area accessible by application software and an area used for data exchange with the _first integrated endpoint 101 ₁ . It is divided into areas. Here, as described with reference to FIG. 5, the storage device 107 is connected to the servers 103 and 105 via the LAN 108.

Inside the storage device 107 ₀ and a storage device 107 _1, the primary shared memory 191 _0, 191 ₁ region, secondary shared memory 192 _0, 192 ₁ region is present. The areas of the primary shared memories 191 ₀ and 191 ₁ correspond to the corresponding ones of the output memory (OutputMem) areas 193 ₀ and 193 ₁ accessed during transmission, and the input memory (InputMem) accessed during reception. A corresponding _one of the areas 194 ₀ and 194 ₁ exists.

The secondary shared memories 192 ₀ and 192 ₁ are divided into a transmission side area and a reception side area, and are configured as follows. First, in the transmission side area, application software (APL) (PS # 0-5) operating on the 0-0 server 103 (main server) transmits data to the _first integrated endpoint 101 ₁ . Output memory server (OutputMemServer # 0-0) area 195 _0-0 and application software (PS # 1-5) operating on the 0-1st server 104 ₁ (extended server) Is configured from an output memory server (OutputMemServer # 0-1) area 195 _0-1 that is accessed when data is transmitted to the first integrated endpoint 101 ₁ .

The reception side area is accessed when application software (PS # 0-5) operating on the 0-0 server 103 (main server) receives data from the first integrated endpoint 101 _1. , An input memory server (InputMemServer # 0-0) area 196 _0-0 and application software (PS # 1-5) operating on the 0-1st server 104 ₁ (extended server) are connected to the first integrated end. It is configured from an input memory server (InputMemServer # 0-1) area 196 _0-1 that is accessed when data is received from the point 101 ₁ .

The configuration of the storage device 107 ₁ that is accessed by the 1-0 server 105 (main server) and the 1-1 server 106 ₁ (extended server) that constitute the SBY server group is the 0-0 server 103. When the server 104 ₁ of the 0-1 is the same as that of the storage device 107 ₀ for accessing.

By the way, in the endpoint sharing system 100 according to the present embodiment, it is the 0-0 servers that are the primary servers that are physically connected to the first integrated endpoint 101 ₁ or the second integrated endpoint 101 _2. 103 and the 1-0 server 105. Therefore, when the 0-1st server 104 ₁ and the 1-1st server 106 _1, which are expansion servers, access the first integrated endpoint 101 ₁ or the second integrated endpoint 101 ₂ , It is necessary to pass data through the server.

When transferring data to and from the main server, a protocol such as IP (Internet Protocol) can be used. However, in that case, it is necessary to define a protocol for data transmission / reception with respect to the extension server and the main server, and there is a problem in that overhead increases and obstructs high-speed transmission / reception. In the present embodiment, high-speed data transfer is realized by using the storage device 107 as a data transfer buffer. Thus, even extension server integrated endpoint 101 _1, 101 ₂ are not connected, thereby realizing a fast access to these integrated endpoint 101 _1, 101 ₂ via the main server in a high speed.

Data exchanged between the server group and the first integrated endpoint 101 ₁ is transferred between the primary shared memory 191 and the secondary shared memory 192 in the storage device 107 with the following relationship.

<ACT server group>
Transfer from output memory server (OutputMemServer # 0-0) area 195 _0-0 to output memory (OutputMem # 0) area 193 ₀ Output memory server (OutputMemServer # 0-1) area 195 _0-1 to output memory ( Transfer in the direction of OutputMem # 0) area 193 ₀ Transfer from input memory (InputMem # 0) area 194 ₀ to input memory server (InputMemServer # 0-0) area 196 _0-0 Input memory (InputMem # 0) Transfer from area 194 ₀ to input memory server (InputMemServer # 0-1) area 196 _0-1

<SBY server group>
Transfer from the output memory server (OutputMemServer # 1-0) area 195 _1-0 to the output memory (OutputMem # 1) area 193 ₁ Direction from the output memory server (OutputMemServer # 1-1) area 195 _1-1 to the output memory ( Output in the direction of OutputMem # 1) area 193 ₁ Transfer from input memory (InputMem # 1) area 194 ₁ to the direction of input memory server (InputMemServer # 1-0) area 196 _1-0 Input memory (InputMem # 1) transfer from region 194 ₁ to the input memory server (InputMemServer # 1-1) regions 196 _1-1 direction

In FIG. 12, the CPU # 0-0 as the CPU mounted on the 0-0th server 103 is associated with each application software PS # 0-0, PS # 0-1, PS # 0-3, PS #. 0-4, PS # 0-5 are shown to be executed. Similarly, the 0-1 CPU # 0-1 each application software PS # 1-3 as CPU mounted in the server 104 _1, PS # 1-4, be performed PS # 1-5 It is shown.

  FIG. 13 shows a state in which the server accesses the endpoint via the storage device. This will be described with reference to FIGS.

  <Sending data from the server>

Application software PS # 0-5 operating on the 0-0 server 103 will be described incorporation of data from the PS # 1-5 to the first integrated endpoint 101 _1.

(A) will be described first access from the 0-0 server 103 (main server) to the first integrated endpoint 101 _1.

When the application software PS # 0-5 operating on the 0th-0th server 103 transmits data to the endpoint 111, the application software PS # 0-5 is an output memory secured on the storage device 107. write data to the server area 195 _0-0 (step S401). When the storage device 107 detects that data has been written to the output memory server area 195 _0-0 , it copies the data to the output memory area 193 ₀ .

The application software PS # 0-5 notifies the application software PS # 0-1 that data has been written in the output memory server area 195 _0-0 (step S402). The application software PS # 0-1 confirms that there is no data transmission request from another server to the endpoint 111, and then the application software PS # 0-2 sends the endpoint software 111 from the 0-0 server 103 to the endpoint 111. An instruction is issued to transmit data to (step S403).

When the application software PS # 0-2 receives an instruction to transmit data to the endpoint 111, the application software PS # 0-2 transmits data from the output memory area 193 ₀ to the endpoint 111 (step S404). In this way, data is transmitted via the storage device 107 from the 0-0 server 103 to the first integrated endpoint 101 _1.

(B) Next, access from the 0-1st server 104 ₁ (extended server) to the first integrated endpoint 101 ₁ will be described.

If the application software PS # 1-5 operating on the 0-1 of the server 104 ₁ transmits the data to the first integrated endpoint 101 _1, application software PS # 1-5 are on the storage device 107 Data is written to the secured output memory server area 195 _0-1 (step S410). When the storage device 107 detects that data has been written to the output memory server area 195 _0-1 , it copies the data to the output memory area 193 ₀ .

The application software PS # 1-5 needs to notify the application software PS # 0-1 that data has been written in the output memory server area 195 _0-1 . Therefore, a data transmission request instruction is issued to the application software PS # 1-4 (step S411).

Application software PS # 1-4 applications the software PS # 0-4, server 104 ₁ of the 0-1 as an extension server notifies the requesting data transfer to the end point 111 ( Step S412). Based on this, the application software PS # 0-4 is that the server 104 ₁ of the first 0-1 is performing a data transfer request to the endpoint 111, and notifies the application software PS # 0-1 ( Step S413).

The application software PS # 0-1 confirms whether there is a request for data transmission from the other server to the endpoint 111. The application for the software PS # 0-2, to transmit the data from the application software PS # 0-1 on the first integrated endpoint 101 ₁ issues a command (step S414).

When the application software PS # 0-2 receives the instruction data transmitted to the first integrated endpoint 101 _1, to implement the transmission of data from the output memory area 193 ₀ to the end point 111 (step S415). In this way, data is transmitted from the 0-1st server 104 ₁ to the first integrated endpoint 101 ₁ via the storage device 107.

  <Importing data to the server>

Then the first integrated data capture from the endpoint 101 ₁ to the server will be described.

  FIG. 14 shows how data is captured from the first integrated endpoint to the server. This will be described with reference to FIGS.

(A) First, data fetching from the first integrated endpoint 101 ₁ to the 0-0 server 103 as the main server will be described.

Assume that data to be transferred from the _first integrated endpoint 101 ₁ to the 0-0 server 103 has occurred. In this case, the data is transferred from the first integrated endpoint 101 ₁ via the 0-0 server 103 as the main server to the input memory (InputMem # 0) by the DMA (Direct Memory Access) without going through the CPU. ) Transferred to area 194 ₀ (step S431). Data transfer from the first integrated endpoint 101 ₁ to the storage device 107 is executed by the application software PS # 0-2.

Application software PS # 0-2 after the transfer of data to the storage device 107, the application software PS # 0-1, the data transfer to the first integrated endpoint 101 ₁ from the storage device 107 The occurrence is notified (step S432).

The application software PS # 0-1 investigates the load status of each server in order to execute processing on a server having a light load among the servers constituting the server group. The investigation of the load situation is executed by the application software PS # 0-3. Therefore, the application software PS # 0-1 instructs the load investigation to the application software PS # 0-3 (step S433). The application software PS # 0-3 has a load status such as CPU load and memory usage with respect to the application software PS # 1-3 operating on the 0-1st server 104 ₁ (extended server) constituting the server group. Is issued (step S434). The 0-1st server 104 ₁ receives the load status investigation instruction by the application software PS # 1-3, and then reports the load status from the application software PS # 1-3 to the application software PS # 0-3 (step S435). ). At this time, communication between the application software PS # 0-3 and the application software PS # 1-3 is performed using the LAN 115.

The application software PS # 0-3 notifies the application software PS # 0-1 of the report result of the application software PS # 1-3 and the load status of the 0-0 server 103 (step S436). The application software PS # 1-3 determines the server with the lower load as the server for processing based on the load status of the 0-0 server 103 (main server) and the 0-1 server 104 ₁ (extended server). To do.

When it is determined that the 0th-0th server 103 is lightly loaded, a processing instruction is issued from the application software PS # 0-1 to the application software PS # 0-5 as application software for executing processing. (Step S347). If it is determined that the load on the _0th-0th server 103 is small, the application software PS # 0-1 records in the input memory area 194 ₀ from the application software PS # 0-1 to the storage device 107 at the same time as issuing the processing instruction in step S347. An instruction to transfer the received data to the input memory server area 196 _0-0 is issued (step S438). At this time, an instruction from the storage device 107 is issued via the LAN 115.

The application software PS # 0-5 reads data from the input memory server area 196 _0-0 (step S439). As a result, the application on the server can obtain data necessary for processing from the first integrated endpoint 101 ₁ .

(B) Next, data loading from the _first integrated endpoint 101 ₁ to the 0-1st server 104 ₁ (extended server) will be described.

Assume that data transferred from the first integrated endpoint 101 ₁ to the server has occurred. In this case, the DMA transfers the data from the first integrated endpoint 101 ₁ to the input memory (InputMem # 0) area 194 ₀ via the 0-0 server 103 as the main server without going through the CPU. Then, the data is transferred (step S441). Data transfer from the first integrated endpoint 101 ₁ to the storage device 107 is executed by the application software PS # 0-2.

Application software PS # 0-2 after the transfer of data to the storage device 107, the application software PS # 0-1, the data transfer to the first integrated endpoint 101 ₁ from the storage device 107 The occurrence is notified (step S442).

The application software PS # 0-1 investigates the load status of each server in order to execute processing on a server having a light load among the servers constituting the server group. The investigation of the load situation is executed with PS # 0-3. Therefore, the application software PS # 0-1 instructs the load investigation to the application software PS # 0-3 (step S443). The application software PS # 0-3 has a load status such as CPU load and memory usage with respect to the application software PS # 1-3 operating on the 0-1st server 104 ₁ (extended server) constituting the server group. Is issued (step S444). The 0-1st server 104 ₁ receives the load status investigation instruction by the application software PS # 1-3, and then reports the load status from the application software PS # 1-3 to the application software PS # 0-3 (step S445). ). At this time, communication between the application software PS # 0-3 and the application software PS # 1-3 is performed using the LAN 115.

The application software PS # 0-3 notifies the report result of the application software PS # 1-3 and the load status of the 0-0 server 103 to the application software PS # 0-1 (step S446). The application software PS # 1-3 determines the server with the lower load as the server for processing based on the load status of the 0-0 server 103 (main server) and the 0-1 server 104 ₁ (extended server). To do.

Sequence up to this, the data transfer for the first 0-0 server 103 is the main server from a first integrated endpoint 101 _1, the same sequence.

Assume that it is determined that the load on the 0-1st server 104 ₁ (extended server) is small. In this case, the data read out from the application for the software PS # 0-1 application software PS # 0-4 from the memory to the server 104 ₁ of the 0-1 unit 107 (S # 0-1_REC_temp (not shown)) An instruction is issued (step S447). At this time, data read from the storage device 107 is stored in a primary area (REC_temp) for application software S # 0-1 (not shown). Simultaneously with the issuance of the data read instruction in step S447, the application software PS # 0-1 transfers the data recorded in the input memory area 194 ₀ to the input memory server area 196 _0-1 to the storage device 107. An instruction is issued (step S448).

In the application software PS # 0-4, and issued a data read instruction from the input memory server area 196 _0-1 by the server 104 ₁ of the 0-1, the application software PS # 1-4, stores A data read instruction is issued from the device 107 (step S449). The application software PS # 1-4 receives a data read instruction from the 0-0 server 103 and issues an instruction to read data from the input memory server area 196 _0-1 to the application software PS # 1-5. (Step S450). The application software PS # 1-5 reads data necessary for processing from the input memory server area 196 _0-1 (step S451).

<Configuration of storage device>
FIG. 15 is a diagram in which the configuration of the endpoint sharing system according to the present embodiment is embodied centering on a storage device. The storage device 107 includes the following units.

(1) Primary shared memory 191 and secondary shared memory 192
The primary shared memory 191 and the secondary shared memory 192 have been described with reference to FIG. The primary shared memory 191 is a memory for temporarily storing data from the main server and data to be transferred to the main server. The secondary shared memory 192 is a memory area for data transfer between the storage device 107 and each server 103, 104 ₁ , 105, 106 ₁ .

(2) CTL between the 0th and first endpoints (CTL between EPs) 501 and 502
The 0th inter-endpoint CTL unit 501 passes through the 0th-0 server (Server # 0-0) 103 as the main server, to the 0th to Nth endpoints (EP # 0 to EP # N). Data from 111 _{0 to} 111 _N (see FIG. 5) is exchanged. The first inter-endpoint CTL unit 502 passes through the 1-0th server (Server # 1-0) 105 as the main server to the 0th to Nth endpoints (EP # 0 to EP # N). Data from 111 _{0 to} 111 _N is exchanged.

(3) 0th and first memory-to-memory CTL (MEM-to-MEM CTL) units 503 and 504
Control between the primary shared memory 191 and the secondary shared memory 192 is performed.

(4) 0th to 0th, 0th to 1st, 1st to 0th, and 1-1st inter-server CTL units 505 to 508
Data transfer between the main server or expansion server and the storage device 107 is performed.

(5) Storage device CTL unit 509
The storage device 107 is controlled.

  The 0th and first end-point CTL units 501 and 502 and the server in the storage device 107 having such a configuration operate as PCIe endpoints and are connected by a PCIe cable. Configuration processing for operating as PCIe is executed from the server side. PCIe configuration processing is equivalent to normal processing.

Therefore, when viewed from the CPU of the main server, it appears that the first integrated endpoint 101 ₁ and the storage device 107 are connected as endpoints. From the CPU of the expansion server, it appears that the storage device 107 is connected as an end point.

  The 0th inter-endpoint CTL unit 501 is connected to the 0-0th server 103 as the main server, and the first interendpoint CTL unit 502 is also connected to the 1-0th server 105 as the main server. Connecting. Here, the 0-0 server 103 constitutes an ACT (active) server group, and the 1-0 server 105 constitutes an SBY (standby) server group. Of these, the active server is a target of data transmission / reception, so it is necessary to acquire ACT (active) / SBY (standby) system information as to which system is the active system.

The storage device CTL section 509 is connected to the 0-0, 0-1, 1-0, and 1-1 servers 103, 104 ₁ , 105, and 106 ₁ via the LAN 108 (see FIG. 5). LAN interface. Therefore, the storage device CTL unit 509 collects ACT / SBY system information with each of the servers 103 to 106 ₁ constituting the server group via the LAN 108. As a result, the storage device CTL unit 509 recognizes the active server group and notifies the 0th and first inter-endpoint CTL unit to prohibit access to the storage device 107 from the standby server group. 501 and 502 are sent out.

When data is transferred between the main server and the storage device 107, data transfer occurs between the 0th or first end-point CTL units 501 and 502 and the primary shared memory 191. The primary shared memory 191 includes an output memory (OutputMem) area 193 ₀ (OutputMem # 0) and 193 ₁ (OutputMem # 1) for transmission, and an input memory (InputMem) area 194 ₀ (InputMem # 0) for reception. , 194 ₁ (InputMem # 1). The primary shared memory 191 performs only the active data transfer based on the ACT / SBY system information from the storage device CTL unit 509.

It is assumed that data is transferred from the first integrated endpoint 101 ₁ to the server. In this case, the PCIe packet stored in the primary shared memory 191 is transferred to any of the 0th, 0th, 0th, 1st, 0th, and 1-1st servers 103, 104 ₁ , 105, 106 _1. It is necessary to decide. In order to determine the destination server, the main server makes a determination based on the load status (CPU usage rate, memory usage, etc.) of each server. The determination result is notified to the storage device CTL unit 509 via the LAN 108 (see FIG. 5). The storage device CTL unit 509 notifies the 0th or first inter-memory CTL units 503 and 504 of the packet transfer destination.

  The 0th or first memory-to-memory CTL units 503 and 504 are based on the completion of data writing to the primary shared memory 191 and the packet transfer destination notification information notified from the storage device CTL unit 509. The packet header information is rewritten. Then, based on the rewritten header information, data is transferred to the secondary shared memory 192 corresponding to the transfer destination server.

The header information added to the PCIe packet will be described later. In the example shown in FIG. 15, when the transfer destination is the 0-0 server 103 or the 1-0 server 105 as the main server, the input memory server (InputMemServer # 0-0) area 196 _0-0 (or input) Data is written in the memory server (InputMemServer # 1-0) area 196 _1-0 ). When the transfer destination is the 0-1st server 103 or 1-1 server 105 as an expansion server, the input memory server (InputMemServer # 0-1) area 196 _0-1 (or the input memory server (InputMemServer #) 1-1) Write data in area 196 _1-1 ).

  The primary server or the expansion server is the 0-0, 0-1, 0-1, 1-0, 1-0 corresponding to the 0-0, 0-1, 0-1 and 1-1 servers. The server-to-server CTL units 505 to 508 are monitored. Then, after confirming that the data has been written, the data is read from the secondary shared memory 192.

Next, a case where data is transferred from the 0-0th, 0-1st, 1-0, and 1-1 servers to the first integrated endpoint 101 ₁ will be described. In this case, data of the secondary shared memory 192 is transmitted via the 0-0, 0-1, 1-0, and 1-1 server CTL units 505 to 508 prepared for each server. Perform the transfer. Zeroth or first-memory CTL unit 503 and 504, data to be transferred first to the integration endpoints 101 ₁ monitors whether written in the secondary shared memory 192.

When it is detected that the data to be transferred is written in the secondary shared memory 192, the data is read from the secondary shared memory 192. Then, data transfer to the primary shared memory 191 is performed. When the main server recognizes that data has been written to the primary shared memory 191 via the 0th or first inter-endpoint CTL units 501 and 502, it reads the data from the primary shared memory 191 and The data is transferred to the integrated endpoint 101 ₁ .

  <Connection between storage device and server>

FIG. 16 shows a generalized state of connection between each server and the storage device. In FIG. 5, there is one 0-1 server (Server # 0-1) 104 ₁ as an expansion server for the 0-0 server (Server # 0-0) 103 as the ACT server group. Showed the case. In FIG. 16, the 0th- ₁ server (Server # 0-1) 104 ₁ to the 0-Nth server (Server # 0-N) 104 _N exist as expansion servers of the ACT server group. Similarly, in FIG. 5, one 1-1-1 server (Server # 1-1) 106 ₁ as an expansion server is compared to the 1-0 server (Server # 1-0) 105 as the SBY server group. The case where exists. In FIG. 16, there are a 1-1 server (Server # 1-1) 106 ₁ to a 1-Nth server (Server # 1-N) 106 _N as expansion servers of the SBY server group. The numerical value N is an arbitrary positive integer.

In the endpoint sharing system 100A, the 0-0, 0-1 to 0-N, 1-0, 1-1 to 1-N inter-server CTL units 505, 506 ₁ are stored in the storage device 107A. ˜ 506 _N , 507, 508 _{1 to} 508 _N , and the 0th and first end point CTL units 501 and 502 are arranged. Here, the 0-0 inter-server CTL unit 505 is connected to the 0-0 server 103 as a main server in a one-to-one relationship using a PCIe cable. Similarly, the 0-th to 0-N server-to-server CTL units 506 _{1 to} 506 _N use PCIe cables as the 0-1 to 0-N servers 104 _{1 to} 104 _N as expansion servers, respectively. Are connected one to one. The 1-0 inter-server CTL unit 507 is connected to the 1-0 server 105 as a main server in a one-to-one manner using a PCIe cable. Similarly server inter CTL unit 508 ₁ ~508 _N of the 1-1 second 1-N includes a server 106 ₁ - 106 _N of the 1-1 second 1-N as an extension server, using a PCIe cable respectively Are connected one to one. Further, the 0-th and first-end-point CTL units 501 and 502 are connected to the 0-0 server 103 and the 1-0 server 105 as the main server on a one-to-one basis using PCIe cables. Has been.

Therefore, the server-to-server CTL units 505, 506 _{1 to} 506 _N , 507, 508 _{1 to} 508 _N and the server-to-endpoint CTL units 501, 502 are respectively connected to the servers 103, 104 _{1 to} 104 _N , as PCIe endpoints. 105, 106 _{1 to} 106 _{N are} recognized. For this reason, each of the servers 103, 104 _{1 to} 104 _N , 105, 106 _{1 to} 106 _N requires driver software for data transmission / reception, but if the installation is completed, the influence of other servers is not considered. The storage device 107A can be controlled. The control of the storage device 107A by each of the servers 103, 104 _{1 to} 104 _N , 105, 106 _{1 to} 106 _N is the same as the normal PCIe endpoint control.

Further, each of the servers 103, 104 _{1 to} 104 _N , 105, 106 _{1 to} 106 _N and the storage device 107A map the storage device to the mutually independent PCIe memory space for the one-to-one connection. It becomes possible. Therefore, it is not necessary to consider the memory space of other servers.

The 0th-0th server 103 and the 1st-0th server 105 serving as the main server provide PCIe to the storage device 107A for access to the primary shared memory 191 and the secondary shared memory 192 (see FIG. 15). Two interfaces are provided. Expansion for server _{104 1 ~104 N, 106 1 ~106} N only access to the secondary shared memory 192 is permitted. For this reason, the expansion servers 104 _{1 to} 104 _N and 106 _{1 to} 106 _N have only one PCIe interface for the storage device 107A.

And the 0-0 server 103 as the primary server first 1-0 server 105 performs the mapping as two endpoints integrated in the memory space endpoint 101 ₁ and memory 107A. However, the work for mapping the 0-0 server 103 and the 1-0 server 105 is the same as the normal operation.

  <Description of operation>

FIG. 17 shows a state of data transfer processing in the endpoint sharing system of the present embodiment. In FIG. 17, data transfer processing is performed by taking the first integrated endpoint 101 ₁ , the 0-0 server 103 as the main server, the storage device 107 and the 0-1 server 104 ₁ as the expansion server as examples. explain. As described above, only the 0th to 0th servers 103 in FIG. 17 can directly access the _first integrated endpoint 101 ₁ . Data exchange between the integrated endpoint 101 ₁ and the 0-1st server 104 ₁ takes the form of data transfer via the storage device 107.

  <Data transfer from integrated endpoint to main server and expansion server>

The first integrated endpoint 101 ₁ transmits the PCIe packet 601 as transfer data (step S701). The PCIe packet 601 is composed of a PCIe header and PCIe data as a data body. The 0th to 0th servers 103 as the main server receive this PCIe packet.

The 0-0 server 103 receives the PCIe packet from the first integrated endpoint 101 _1, and between the data area descriptor (descriptor), the server (Server) names, integrated endpoint (EP) number and end A header field 602 composed of point (EP) numbers is inserted. Then, the PCIe packet 601 is transferred to the storage device 107 (step S702). Here, in “server name”, a server name indicating which application on which the PCIe packet is executed is inserted.

  PS # 0-4 and PS # 1-4 (refer to FIG. 10), which are software operating on the 0th-0th server 103 as the main server, are determined in cooperation with each other to determine the server that processes the PCIe packet. . Here, the software PS # 0-4 determines, for example, a server with a light load based on the load status (CPU usage rate, memory usage rate, etc.) of each server. When determining the transfer destination server name, the 0-0th server 103 notifies the storage device CTL unit 509 (FIG. 15) of the transfer destination server name. The storage device CTL unit 509 inserts the server name in the server name field of the received PCIe packet 601 based on the information determined by the software PS # 0-4.

In the storage device 107, the integrated endpoint number of the transmission source of the PCIe packet 601 and the endpoint number are inserted into the integrated EP number and EP number fields of the received PCIe packet 601. As a result, in the 0-1st server 104 ₁ as an expansion server, the end point of what function the packet received based on the integrated EP number of the header field 602 and the number described in the EP number field has. It is possible to determine whether the packet is transmitted from 111 (FIG. 5). In addition, a packet can be passed to an application by passing it to a predetermined device driver.

  The storage device 107 detects that the data transferred from the 0-0th server 103 as the main server has been written in the primary shared memory 191 (step S703). When the transfer destination of the PCIe packet 601 is notified from the storage device CTL unit 509 (FIG. 15) (step S704), the transfer destination server name is written in the 0th memory-to-memory CTL unit 503. Thereafter, the PCIe packet 601 is transferred to the secondary shared memory 192 corresponding to the server described in the server name field (step S705).

The 0-1st server 104 ₁ as an expansion server periodically monitors whether the data addressed to its own server is written in the secondary shared memory 192 for each server. When the 0-1st server 104 ₁ confirms that the data has been written, it reads out the data from the secondary shared memory 192 (step S706).

  <Transfer data from the main server and expansion server to the endpoint>

Shall first 0-1 application server 104 on _one of the extension server to transmit the data to the endpoint. In this case, PCIe packet 611 for the endpoint transmission is generated by the application on the server 104 ₁ of the first 0-1. A header field 612 composed of a server name, an integrated endpoint number, and an endpoint number is inserted into the PCIe packet 611, and data is written to the secondary shared memory 192 (step S711).

  Here, the name of the server that executed the process is inserted into the server name in the header field 612. For the extended endpoint number and the endpoint number, if the data transmission process is a response to the data received from the endpoint, the same number as that at the time of reception is described. This makes it possible to determine to which integrated endpoint or endpoint the 0-0 server 103 as the main server that ultimately transmits data to the endpoint transmits data.

In this example, the destination of the PCIe packet 611 is only the first integrated endpoint 101 ₁ . Accordingly situation that server 104 ₁ of the 0-1 as an extension server can not determine the destination does not occur. There may be a plurality of integrated endpoints such as the first and second integrated endpoints 101 ₁ and 101 ₂ shown in FIG. In such a case, it is assumed that the 0-1st server 104 ₁ cannot determine which of these is the destination. In this case, the 0-1st server 104 ₁ gives “Don't Care” to the integrated endpoint number.

When the storage device 107 detects that data has been written to the secondary shared memory 192 from the 0-1st server 104 ₁ as the expansion server or the 0-0th server 103 as the main server, the storage device 107 stores this data as 1 The data is transferred to the next shared memory 191 (step S712).

  The 0th to 0th servers 103 as the main servers periodically monitor whether transmission data to the endpoint is written in the primary shared memory 191 of the storage device 107. When it is confirmed that the transmission data is written in the primary shared memory 191, the 0th-0th server 103 executes reading of the transmission data (step S 713).

The 0th-0th server 103 deletes the header field (extension header) 612 inserted in the read PCIe packet 611. Then, by using the number described in the endpoint number in the deleted header field 612, it is determined to which endpoint the PCIe packet 611 is transmitted. The 0th-0th server 103 transmits the PCIe packet 611 to the endpoint (in this case, the first integrated endpoint 101 ₁ ) using the device driver corresponding to the next corresponding endpoint. (Step S714).

  As described above, “Don't Care” may be added to the integrated endpoint number in the header field 612. In this case, the 0th-0th server 103 as the main server determines the destination integrated endpoint. Then, the PCIe packet 611 is transmitted to the determined integrated endpoint.

  As described above, the endpoint sharing system 100 according to the present embodiment has the following effects.

  As a first effect, in this embodiment, a plurality of CPUs can access the same endpoint. For the endpoint, a device conforming to PCIe can be used as it is.

  As a second effect, in the present embodiment, CPU switching can be realized at high speed. This is because when the CPU that can access the endpoint is switched, reset or reset processing for the endpoint is unnecessary.

  As a third effect, in the present embodiment, it is possible to construct a highly scalable system in which servers can be increased or decreased according to the load on the CPU side. This is because the ACT CPU and the SBY CPU can be composed of a plurality of physically separated CPUs.

  As a fourth effect, in the present embodiment, it is possible to construct a highly scalable system that can increase or decrease the number of integrated endpoints according to the load on the endpoint side. This is for incorporating a plurality of physically separated EPs into the system.

  As a fifth effect, according to the present embodiment, scalability that can be individually increased or decreased according to the load situation according to the load on the CPU side (software processing) and the load on the endpoint side (hardware processing). It is possible to build a high system.

  As a sixth effect, in this embodiment, by implementing a data transmission / reception method between servers using a memory, it is possible to input / output data to / from an endpoint from a server not connected to the endpoint. It is possible to build a system.

  As a seventh effect, in the present embodiment, a general-purpose product and a standardized semiconductor memory are used for the storage device. Accordingly, the storage device and the endpoint sharing system 100 using the storage device can be configured at low cost. In this embodiment, each server and the storage device 107 are connected by PCIe. By transferring PCIe packets directly from the server to the storage device, it is possible to save labor on protocols such as SAS (Serial Attached SCSI) and SATA (SerialATA) that occur when data is transferred to the hard disk. Become. As a result, the overhead of the protocol can be reduced, and the processing load of the CPU mounted on the server can be reduced.

  As an eighth effect, in the present embodiment, the storage device is mainly used for data transfer between servers. In such applications, it is necessary to increase the speed of data transfer, but it is not always necessary to increase the capacity. In such a case, if the use of a hard disk is avoided by using a semiconductor memory, the reliability of the system can be improved. This is because a hard disk includes mechanically driven parts, so that there is a high possibility that a failure will occur, and this is a bottleneck in terms of reliability.

  As a ninth effect, in this embodiment, it is possible to transfer data to destination endpoints corresponding to a plurality of integration endpoints by incorporating the integration endpoint number into the PCIe packet. Also, by adding an extension header that describes information such as the data transfer destination, it is possible to easily determine what kind of endpoint the extension server that is not connected to the endpoint has received, and Data can be passed to other applications. Further, when transmitting, it is possible to correctly transmit the data to the destination endpoint by notifying to which endpoint the data should be passed to the server connected to the endpoint.

  <Deformability of invention>

  By implementing multiple integrated endpoints as shown in the previous embodiment, it is possible to increase or decrease the number of integrated endpoints according to the required processing capacity, and to build a highly versatile system It becomes possible. However, in order to increase the number of integrated endpoints, it is necessary to add a PCIe NIC card for connection with the integrated endpoint to the main server as described above. However, since the number of expansion slots of the server is limited, there is a possibility that an integrated endpoint required as a system cannot be added.

  In PCIe, data is transferred as a PCIe packet. For this reason, it is possible to encapsulate PCIe packets with other protocols.

  FIG. 18 shows the configuration of the endpoint sharing system in the first modification of the present invention. In the modified endpoint sharing system 100B, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In the endpoint sharing system 100B of the first modified example, the PCIe NIC card (PCIe NIC # 001) 121B of the 0-0th server 103B is connected to one end of the first Ethernet (registered trademark) switch 801. . At the other end of the first Ethernet switch 801, the 0th port 151 ₀ B of the _first integrated endpoint 101 ₁ and the 0th port (not shown) of the _second integrated endpoint 101 ₂ are shown. Connected). Similarly, a PCIe NIC card (PCIe NIC # 101) 125B of the 1-0 server 105B is connected to one end of the second Ethernet (registered trademark) switch 802. The other end of the second Ethernet switch 802 is connected to the first port 151 ₁ B of the first integrated endpoint 101 ₁ and the 0th port (not shown) of the _second integrated endpoint 101 ₂ . Connected).

That is, in the endpoint sharing system 100B of the first modified example, encapsulation is performed with an Ethernet (registered trademark) frame. This makes it possible to identify a server and a plurality of endpoints based on the Ethernet (registered trademark) MAC address (Media Access Control address), and to specify a destination. For this purpose, PCIe NIC cards 121B and 125B for encapsulating PCIe packets in Ethernet (registered trademark) frames are provided to both the 0-0 server 103B and the 1-0 server 105B as the main servers. Implemented. Also, the Ethernet (registered trademark) encapsulation function of the PCIe packet is provided on the first and second integrated endpoints 101 ₁ and 101 ₂ side like the 0th port 151 ₀ B and the 1st port 151 ₁ B. It has been added.

Each server 103B, 104 ₁ , 105B, 106 ₁ and the first and second integrated endpoints 101 ₁ , 101 ₂ are connected by Ethernet (registered trademark). Accordingly, the first and second Ethernet (registered trademark) switches 801 and 802 are provided between the 0-0 and 0-1 servers 103B and 105B and the first and second integrated endpoints 101 ₁ and 101 _2. By interposing, it becomes possible to control the destination of the packet. As a result, the integrated end of the first and second integrated endpoints 101 ₁ , 101 _2, etc., without depending on the number of PCIe slots mounted on the 0-0 and 0-1 servers 103B, 105B. You can increase or decrease the number of points. For example, the 0th-0th server 103B is configured such that one PCIe NIC card (PCIe NIC # 001) 121B is connected to the 0th port of any number of integrated endpoints via the first Ethernet (registered trademark) switch 801. 151 ₀ B can be connected.

As described above, according to the first modification, a plurality of expansion servers such as the server 1041 can be added to _one main server such as the 0th-0th server 103B constituting the server group. .

  FIG. 19 shows an endpoint sharing system in which there are N integrated endpoints and extended servers of each system as a second modification of the present invention. Here, the numerical value N is an integer of 2 or more. In the endpoint sharing system 100C of the second modified example shown in FIG. 19, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In the endpoint sharing system 100C of the second modified example, the storage device 107C is connected to the LAN 115, and is connected to the ACT server group 901 and the SBY server group 902. Here, the ACT server group 901 includes a first main server 911 as one main server, and 0-1 to 0-N expansion servers 912 _{1 to} 912 _N. Similarly, the SBY server group 902 includes a second main server 921 as one main server and 0-1 to 0-N expansion servers 922 _{1 to} 922 _N.

The first main server 911 is connected to the storage device 107C by an endpoint (EP) communication PCIe cable 931. Further, the first main server 911 extend server 912 ₁ ~912 _N of the 0-1～ second 0-N is connected to the storage device 107C respectively separate server communication for PCIe cable 932 ₀ ~932 _N . Similarly, the second main server 921 is connected to the storage device 107C via an endpoint (EP) communication PCIe cable 941. Further, a second main server 921 extend server 922 ₁ ~922 _N of the 0-1～ second 0-N is connected to the storage device 107C respectively separate server communication for PCIe cable 942 ₀ ~942 _N . Further, the first main server 911 and the second main server 921 are respectively Ethernet connection with (R) first to N integrated endpoint through the switch 801C (EP) 101 ₁ to 101 _N.

The endpoint sharing system 100C according to the second modified example includes N integrated endpoints (EP) 101 _{1 to} 101 _N and N 0-1 to 0-N expansion servers 912 _{1 to} 912 _N. And 0-1 to 0-N expansion servers 922 _{1 to} 922 _N. As described above, in the endpoint sharing system 100C, a plurality of extension servers can be added to one main server 911 (main server 921) constituting the server group. In addition, the software processing for the ACT server group 901 and the SBY server group 902 and the hardware processing for the first to Nth integrated endpoints (EP) 101 _{1 to} 101 _N are separately required. It is possible to increase or decrease the number.

Moreover, in the second modification, the servers 911, 912, 921, and 922 by software processing are connected to the integrated endpoint 101 by hardware processing via Ethernet (registered trademark). As a result, the servers 911, 912, 921 and 922 and the integrated EP 101 connected via Ethernet (registered trademark) can be virtually configured as one system. In the storage device 107C, the main servers 911 and 921 are connected by two systems of PCIe cables, and the expansion servers 912 and 922 are connected by a system of PCIe cables. This makes it possible to realize data transfer between the integrated endpoint 101 and each server (main servers 911 and 921 and expansion servers 912 and 922). As a result, the physically separated server groups 901 and 902, integrated endpoint groups 101 _{1 to} 101 _N and the storage device 107C can be virtually controlled as one system.

  Some or all of the embodiments described above are described as in the following supplementary notes, but are not limited to the following descriptions.

(Appendix 1)
An active system from a predetermined endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints Integrated endpoint side transmission means for transmitting a PCIe packet to a main server as a server of
Extended server determining means for determining an extended server for processing data stored in the PCIe packet transmitted by the integrated endpoint side transmitting means;
Extended server name inserting means for inserting the server name of the extended server determined by the extended server determining means into the PCIe packet;
Main server side transmitting means for transmitting the PCIe packet, in which the server name is inserted by the extended server name inserting means, from the main server to a predetermined storage device;
Primary shared memory writing means for receiving the PCIe packet transmitted by the main server side transmitting means and writing it to the primary shared memory in the storage device;
The PCIe packet written to the primary shared memory by the primary shared memory writing means is individually provided for each of the active and standby servers and is individually transferred to these servers. A secondary shared memory transfer means for transferring to a secondary shared memory determined by the expansion server determination means among the secondary shared memories used for the endpoint shared system.

(Appendix 2)
For a specific endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An extension server side insertion means for inserting identification information representing the specific endpoint into the PCIe packet when an arbitrary main server and extension server transmit data;
A plurality of secondary packets, each of which is provided in correspondence with each main server and each expansion server, and is used for individual transfer of data to and from these servers, with the PCIe packet having the identification information inserted by the expansion server side insertion means. Secondary shared memory storage means for storing in a secondary shared memory corresponding to the arbitrary main server and expansion server of the transmission source in the shared memory;
PCIe packet transmitting means for reading the identification information when the secondary shared memory storing means stores the PCIe packet in any of the secondary shared memories and transmitting the PCIe packet to the endpoint determined from the identification information; An end point sharing system comprising:

(Appendix 3)
The endpoint sharing system according to claim 1 or 2, wherein the main server and the extension server exist in one or more sets.

(Appendix 4)
3. The endpoint sharing system according to claim 1, wherein one or more sets of integrated endpoints exist.

(Appendix 5)
The endpoint sharing system according to claim 1, wherein the extension server determination unit determines an extension server having a light load status of each server.

(Appendix 6)
2. The endpoint sharing system according to claim 1, wherein the storage device is constituted by a semiconductor memory.

(Appendix 7)
3. The endpoint sharing system according to claim 2, wherein the secondary shared memory is constituted by a semiconductor memory.

(Appendix 8)
An active system from a predetermined endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An integrated endpoint side transmission step of transmitting a PCIe packet to a main server as a server of
An extended server determining step in which the main server that has received the PCIe packet transmitted in the integrated endpoint side transmitting step determines an extended server that processes the data stored in the PCIe packet;
An extended server name inserting step of inserting the server name of the extended server determined in the extended server determining step into the PCIe packet;
A main server side transmission step of transmitting the PCIe packet into which the server name is inserted in the extended server name insertion step from the main server to a predetermined storage device;
A primary shared memory writing step of receiving the PCIe packet transmitted in the main server side transmission step and writing it into the primary shared memory in the storage device;
The PCIe packet written to the primary shared memory in the primary shared memory writing step is individually provided for each of the active and standby servers and individually transferred to these servers. And a secondary shared memory transfer step of transferring to the secondary shared memory determined in the extended server determination step among the secondary shared memories used for the data transfer.

(Appendix 9)
For a specific endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An extension server-side insertion step in which any main server and extension server that transmit data inserts identification information representing the specific endpoint in the PCIe packet;
A plurality of secondary packets, which are provided in correspondence with the main server and the expansion server, respectively, and are used for individual transfer of data to and from these servers, with the PCIe packet having the identification information inserted in the insertion step on the expansion server side. A secondary shared memory storing step of storing in a secondary shared memory corresponding to the own server of the shared memory;
A PCIe packet transmitting step of reading the identification information and transmitting the PCIe packet to the endpoint determined from the identification information when the PCIe packet is stored in any of the secondary shared memories in the secondary shared memory storing step A data transfer method comprising:

10, 20, 100, 100A, 100B, 100C Endpoint shared system 11 Integrated endpoint transmission means 12 Extended server determination means 13 Extended server name insertion means 14 Primary server side transmission means 15 Primary shared memory writing means 16 Secondary Shared memory transfer means 21 Expansion server side insertion means 22 Secondary shared memory storage means 23 PCIe packet transmission means 30, 40 Data transfer method 31 Integrated endpoint side transmission step 32 Extension server determination step 33 Extension server name insertion step 34 Main server side transmission step 35 primary shared memory writing step 36 secondary shared memory transfer step 41 extended server-side insertion step 42 secondary shared memory storage step 43 PCIe packet transmission step 101 ₁ first integrated endpoint 101 ₂ second If the end point 103 the first 0-0 of the server (Server # 0-0)
104 ₁ 0-1 server (Server # 0-1)
105 1-0 server (Server # 1-0)
106 ₁ 1-1 server (Server # 1-1)
107 Storage device 111 Endpoint 121-128, 131, 132 PCIe NIC card 141 PCI proxy function unit 151 ₀ 0th port 151 ₁ 1st port 152 ACT / SBY selection function unit 154 ₀ 0th virtual PCIe configuration ) Register 154 ₁ First virtual PCIe configuration register 155 Configuration control unit 158 Address conversion / distribution function unit 161, 162 PC-Express cable 191 Primary shared memory 192 Secondary shared memory 501 CTL between 0th endpoints (EP-to-EP CTL) part 502 First inter-endpoint CTL (EP-to-EP CTL) part 503 0th memory-to-memory CTL (MEM-to-MEM CTL) part 504 First memory-to-memory CTL (to-MEM CTL) part 505 0- 0 CTL section between servers 506 0-1 CTL section between servers 507 CTL section between 1-0 servers 508 1-1 CTL section between servers 509 Storage device CTL section 601 611 PCIe packet 602 612 header field 193 Output memory (OutputMem) area 194 Input memory (InputMem) area 195 Output memory server area 196 Input memory server area

Claims (9)

An active system from a predetermined endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints Integrated endpoint side transmission means for transmitting a PCIe packet to a main server as a server of
Extended server determining means for determining an extended server for processing data stored in the PCIe packet transmitted by the integrated endpoint side transmitting means;
Extended server name inserting means for inserting the server name of the extended server determined by the extended server determining means into the PCIe packet;
Main server side transmitting means for transmitting the PCIe packet, in which the server name is inserted by the extended server name inserting means, from the main server to a predetermined storage device;
Primary shared memory writing means for receiving the PCIe packet transmitted by the main server side transmitting means and writing it to the primary shared memory in the storage device;
The PCIe packet written to the primary shared memory by the primary shared memory writing means is individually provided for each of the active and standby servers and is individually transferred to these servers. A secondary shared memory transfer means for transferring to a secondary shared memory determined by the expansion server determination means among the secondary shared memories used for the endpoint shared system. For a specific endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An extension server side insertion means for inserting identification information representing the specific endpoint into the PCIe packet when an arbitrary main server and extension server transmit data;
A plurality of secondary packets, each of which is provided in correspondence with each main server and each expansion server, and is used for individual transfer of data to and from these servers, with the PCIe packet having the identification information inserted by the expansion server side insertion means. Secondary shared memory storage means for storing in a secondary shared memory corresponding to the arbitrary main server and expansion server of the transmission source in the shared memory;
PCIe packet transmitting means for reading the identification information when the secondary shared memory storing means stores the PCIe packet in any of the secondary shared memories and transmitting the PCIe packet to the endpoint determined from the identification information; An end point sharing system comprising:   The endpoint sharing system according to claim 1 or 2, wherein the main server and the extension server exist in one or more sets.   3. The endpoint sharing system according to claim 1, wherein one or more sets of integrated endpoints exist.   The endpoint sharing system according to claim 1, wherein the extension server determination unit determines an extension server having a light load status of each server.   2. The endpoint sharing system according to claim 1, wherein the storage device is constituted by a semiconductor memory.   3. The endpoint sharing system according to claim 2, wherein the secondary shared memory is constituted by a semiconductor memory. An active system from a predetermined endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An integrated endpoint side transmission step of transmitting a PCIe packet to a main server as a server of
An extended server determining step in which the main server that has received the PCIe packet transmitted in the integrated endpoint side transmitting step determines an extended server that processes the data stored in the PCIe packet;
An extended server name inserting step of inserting the server name of the extended server determined in the extended server determining step into the PCIe packet;
A main server side transmission step of transmitting the PCIe packet into which the server name is inserted in the extended server name insertion step from the main server to a predetermined storage device;
A primary shared memory writing step of receiving the PCIe packet transmitted in the main server side transmission step and writing it into the primary shared memory in the storage device;
The PCIe packet written to the primary shared memory in the primary shared memory writing step is individually provided for each of the active and standby servers and individually transferred to these servers. And a secondary shared memory transfer step of transferring to the secondary shared memory determined in the extended server determination step among the secondary shared memories used for the data transfer. For a specific endpoint in an integrated endpoint composed of a PCI proxy function unit serving as a function unit acting as a PCI (Peripheral Component Interconnect) function as an expansion bus architecture for computers and a plurality of endpoints An extension server-side insertion step in which any main server and extension server that transmit data inserts identification information representing the specific endpoint in the PCIe packet;
A plurality of secondary packets, which are provided in correspondence with the main server and the expansion server, respectively, and are used for individual transfer of data to and from these servers, with the PCIe packet having the identification information inserted in the insertion step on the expansion server side. A secondary shared memory storing step of storing in a secondary shared memory corresponding to the own server of the shared memory;
A PCIe packet transmitting step of reading the identification information and transmitting the PCIe packet to the endpoint determined from the identification information when the PCIe packet is stored in any of the secondary shared memories in the secondary shared memory storing step A data transfer method comprising:

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