JP2007148621A - Computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To share an I/O card among a plurality of servers while preventing deterioration of performance of I/O access. <P>SOLUTION: An I/O card sharing mechanism 400 for relaying an answer signal from the I/O card 501 to servers #1-#n replaces an identifier of a server of a requesting source embedded in an MMIO base address by an I/O processor blade 600 to an address of header information of the answer signal, whereby an I/O card of a general bus can be shared. After starting the I/O card 501, the I/O processor blade 600 does not intervene in transfer of the answer signal, and hardware of the I/O card sharing mechanism 400 performs the address replacement. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a computer system that shares an I / O device, and more particularly to a blade server system capable of server integration.

  In recent years, with the increase in the number of servers, the complexity of operation has increased, and the increase in operation cost has become a problem. As a technique for reducing the operation cost, server consolidation (server integration) that consolidates a plurality of servers is attracting attention.

  As a technology for realizing server integration, a blade server system capable of mounting a plurality of server blades and a plurality of I / O blades on the backplane is known. A server blade is mounted according to the server to be integrated, and one chassis is installed. Multiple servers are integrated in the body. That is, a high-performance server in which a plurality of servers are aggregated in one housing is provided.

  In server integration, servers that have been operating independently in a plurality of cases are consolidated into one high-performance blade server system, and a plurality of OSs and applications are operated. Here, when a plurality of servers are integrated into one blade server system, it is necessary to integrate the I / O cards (or I / O devices) of the servers that have been operating independently. When an I / O card used by each server before integration is used as it is, the backplane (or I / O slot) of the blade server system is insufficient.

  Although it is possible to attach a required number of I / O cards by adding an I / O expansion case to the blade server system case, it is larger because the size of the case increases. Installation space is required and the effect of server integration is reduced.

  For this reason, in server integration using a blade server system, it is necessary to share I / O cards between server blades and reduce the number of I / O cards.

  As a technique for sharing an I / O card among a plurality of servers, a virtual computer that divides one computer into arbitrary logical partitions is known. This is because a plurality of guest OSs are operated on the host OS, each guest OS is provided as a logical partition, and is operated as an application of the guest O host OS, and the host OS centralizes I / O requests from the guest OS. An I / O device is shared by processing an I / O request (for example, Patent Document 1).

Alternatively, a technique for sharing an I / O card from a plurality of servers using an I / O switch represented by AS (Advanced Switching) or the like is also known. This is a switch for performing communication between a PCI-EXPRESS standard I / O card and a server using a dedicated protocol, and a single I / O card can be switched and used by a plurality of servers.
US Pat. No. 6,496,847

  However, in the conventional example as described in Patent Document 1, I / O access between the guest OS and the I / O card is always relayed by the host OS. For this reason, when performing a DMA transfer between the guest OS and the I / O card, a process for transferring from the memory area of the host OS to the memory area of the guest OS is necessary, and this host OS process becomes an overhead. There has been a problem that the performance (transfer speed and response) of I / O access is reduced.

  In the conventional AS, a dedicated I / O card corresponding to a standard (dedicated protocol) that is an extension of PCI-EXPRESS is required, and a conventional interface such as conventional PCI, PCI-x, or PCI-EXPRESS is used. The configured I / O card cannot be used as it is. Therefore, in order to share an I / O card using AS, there is a problem that a large amount of money is required to replace the conventional I / O card. Furthermore, since an AS-compatible I / O card uses a dedicated protocol, a device driver or the like needs to be newly introduced. For this reason, in server integration, work for changing a device driver incorporated in a conventional OS is required, and there is a problem that labor required for server integration increases in addition to the above-described cost problem.

  Accordingly, the present invention has been made in view of the above problems, and aims to realize the sharing of an I / O card between a plurality of servers by preventing a decrease in performance of I / O access. It is an object of the present invention to reduce the cost of server integration by making the / O card configurable with a general-purpose interface.

  The present invention provides a computer system comprising a plurality of servers and a switch for connecting the plurality of servers to the I / O card, wherein the server has a memory space writable from the I / O card. An I / O card sharing unit that is disposed between the switch and the I / O card and operates an access request signal and a response signal between the plurality of servers and the I / O card; and the I / O card; A memory that is accessible to the I / O card sharing unit and is writable from the I / O card sharing unit; and a processor that receives an interrupt from the I / O card sharing unit. An I / O processor that manages the allocation of the I / O card, and the switch is configured to specify a command from the server to the I / O card and the memory space. The access request signal including the address of the access request signal is added to the header information of the access request signal and the path information of the access request signal is transmitted to the I / O card sharing unit. A header processing unit for transferring a response signal including a response from the card to the server and a base address designating the memory space to a destination server included in header information of the response signal, and the I / O card The sharing unit includes a request signal writing unit that writes the access request signal to the memory of the I / O card sharing unit when the command included in the access request signal received from the switch is a preset first command; When the command included in the access request signal received from the switch is a second command set in advance, an interrupt request for interrupting the I / O processor is assigned. When a response signal from the I / O card to the server is received, the request source route information is extracted from the base address included in the response signal, and the extracted request source route information is returned as a response. A header correction unit for setting the destination of the header information of the signal, a base address correction unit for deleting the route information of the request source embedded in the base address of the response signal, and a transmission unit for transmitting the response signal to the switch The I / O processor receives, from the header information of the access request signal, a predetermined upper bit of a base address included in the access request signal written in the memory when the interrupt occurs. An address conversion unit for setting request source route information, and the base address in which the request source header information is set in upper bits based on the interrupt. A response address setting unit for setting the address as a response destination of the I / O card, and an I / O for starting the operation of the I / O card by transmitting the access request signal to the I / O card based on the interrupt A card activation unit, and the I / O card returns a response signal of processing corresponding to the access request signal to the I / O card sharing unit.

  Therefore, according to the present invention, the I / O card sharing unit that relays the response signal from the I / O card to the server replaces the identifier of the requesting server embedded in the base address with the destination of the header information. The bus I / O card can be shared. After the I / O card is activated, the I / O processor does not intervene in the transfer of the response signal, and the hardware of the I / O card sharing unit performs the address change. It is possible to realize sharing of an I / O card among a plurality of servers while preventing overhead and preventing performance degradation of I / O access.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a blade server system showing the first embodiment.

  The blade server system includes a plurality of server blades 10-1 to n, I / O cards 501 and 502 having various I / O interfaces, and a switch 200 that connects the server blades 10-1 to n and the I / O card. And an I / O card sharing mechanism 400 for sharing the I / O cards 501 and 502 among the plurality of server blades 10-1 to 10-n, and an I / O processor blade 600 for managing the sharing of the I / O card. Prepare. Each blade, the switch 200, and the I / O card sharing mechanism 400 are housed in a single housing (not shown).

  In each of the server blades 10-1 to 10-n, the CPU 101 and the memory 102 are connected via a chip set (or I / O bridge) 103, and the chip set 103 is connected to the switch 200 via the general-purpose buses 11-1 to n. Connected. Here, for example, PCI-EXPRESS (PCI-ex in the figure) is applied as the general-purpose buses 11-1 to 11-n.

  The CPU 101 provides the servers # 1 to n by executing the OS and applications loaded in the memory 102. Then, the CPU 101 accesses the I / O cards 501 and 502 from the chipset 103 via the switch 200 and the I / O card sharing mechanism 400.

  The switch 200 includes a header processing unit 210 that adds header information of packets transmitted and received between the server blades 10-1 to 10-n and the I / O cards 501 and 502, and forwards the packets based on the header information. .

  The header processing unit 210 adds header information to packets (access request signals) transmitted from the server blades 10-1 to 10-n to the I / O cards 501 and 502, and the destination node included in the header information Transfer to (I / O card). In this header information, the address information (identifier) of the server blades 10-1 to 10-n is set as the request source, and the address information of the I / O card is set as the destination. Further, the header processing unit 210 of the switch 200 sends a packet (response signal) from the I / O card to the server blades 10-1 to 10-n, and server blades 10-1 to 10-1 of destinations (server identifiers) included in the packet. forward to n. Here, since the packet of this embodiment employs PCI-EXPRESS as a general-purpose bus, it is a PCI transaction (PCI-Tx).

  Between the switch 200 and the I / O cards 501 and 502, an I / O for sharing the I / O cards 501 and 502 among the plurality of server blades 10-1 to 10-n via the general-purpose buses 301, 311, and 312. A card sharing mechanism 400 is connected. The I / O card sharing mechanism 400 is connected to the I / O processor blade 600 via the general-purpose bus 401. The I / O processor blade 600 performs address conversion and I / O card sharing as described later. Perform management such as sharing status. The console 5 is connected to the I / O processor blade 600, and the sharing state of the I / O cards 501 and 502 is set by an input from an administrator or the like.

  The I / O cards 501 and 502 include an interface such as SCSI (or SAS), FC (Fibre Channel), or Ethernet (registered trademark). Each of the I / O cards 501 and 502 includes a DMA (Direct Memory Access) controller 513 that directly accesses the memory 102 of the server blades 10-1 to 10-n. The I / O cards 501 and 502 include a base address register 511 for designating a base address of an MMIO (Memory Mapped I / O) of the memory 102 on the server blades 10-1 to 10 -n that performs DMA by the DMA controller 513, and A command register 512 for designating commands to the I / O cards 501 and 502 is provided. The DMA controller 513 executes an operation corresponding to the command written in the command register 512 with respect to the address of the memory 102 written in the base address register 511. The I / O cards 501 and 502 have registers (configuration register, latency timer register, etc.) (not shown) conforming to the PCI standard.

  Next, in the I / O processor blade 600, the CPU 602 and the memory 603 are connected via a chip set (or I / O bridge) 601, and the chip set 601 is connected to an I / O card sharing mechanism via a general-purpose bus 401. 400 is connected. In the I / O processor blade 600, as described later, a predetermined control program is executed, and processing such as address conversion is executed for the I / O access from the server blades 10-1 to 10-n.

<I / O card sharing mechanism>
Next, details of the I / O card sharing mechanism 400 of the present invention will be described in detail below with reference to the block diagram of FIG.

  The I / O card sharing mechanism 400 is located between the server blades 10-1 to n and the I / O cards 501 and 502, and converts the addresses of I / O access packets from the server blades 10-1 to n. By doing so, it is possible to share one I / O card among the plurality of server blades 10-1 to 10-n. Here, the switch 200, the general-purpose bus, and the I / O cards 501 and 502 conform to PCI-EXPRESS, and hereinafter, the I / O access packet is referred to as a PCI transaction.

The main functions of the I / O card sharing mechanism 400 are:
1) A function of writing PCI transactions from the server blades 10-1 to 10-n to the I / O cards 501 and 502 into the memory 603 of the I / O processor blade 600. 2) To the command register 512 of the I / O cards 501 and 502. Function of requesting interrupt to CPU 602 of I / O processor blade 600 based on write request 3) Function of converting PCI transaction destination by DMA from I / O card 501, 502 to server blade 10-1 to n There are three.

  In FIG. 2, the I / O card sharing mechanism 400 includes an associative memory 410 that stores an address information table 411, which will be described later, and a header information extraction unit 406 that separates header information from PCI transactions from the server blades 10-1 to 10-n. The first transaction decoder 402 (Tx decoder 1 in the figure) that sends a command to the I / O processor blade 600 by analyzing the main body of the PCI transaction excluding header information, and the signal from the I / O processor blade 600 are analyzed. The second transaction decoder 403 (Tx decoder 2 in the figure) that sends a command to the I / O cards 501 and 502 and the PCI transaction from the I / O cards 501 and 502 are analyzed. The third transaction decoder 4 for correcting (converting) 4 (Tx decoder 3 in the figure), an interrupt generation unit 407 for interrupting the CPU 602 of the I / O processor blade 600 by a command from the transaction decoder 402, and a memory of the I / O processor blade 600 by a command from the transaction decoder 402 A memory writing unit 408 for writing to 603, a signal selection unit 412 for selecting a signal to be output to the I / O processor blade 600 based on a command from the first transaction decoder 402, and a command from the third transaction decoder 404 And a signal selection unit 413 that selects a signal to be output to the servers # 1 to #n (switch 200).

  Here, as shown in FIG. 3, the PCI transaction includes a PCI transaction body 461 that stores data such as a command, an order, or a server address (MMIO base address) 462, and header information 451 that stores path information. . The header information 451 stores the request source 453 that issued the PCI transaction with the destination 452 as the head. For example, in a PCI transaction from the server blade 10-1 to the I / O card 501, route information (address, etc.) to the I / O card 501 is set in the destination 452, and the route of the server blade 10-1 is sent to the request source 453. The information is set, and in the PCI transaction main body 461, the address information of the I / O register of the server blade 10-1 is set as the MMIO base address 462 in addition to the command and the order.

  In FIG. 2, 301-1 is a downlink from the switch 200 to the I / O card sharing mechanism 400 on the general-purpose bus 301 that connects the switch 200 (server blades 10-1 to n) to the I / O card sharing mechanism 400. The PCI transaction 301-2 indicates an upward PCI transaction from the I / O card sharing mechanism 400 to the switch 200 (server blades 10-1 to n) on the general-purpose bus 301. Similarly, reference numeral 401-2 designates a down command signal from the I / O card sharing mechanism 400 to the I / O processor blade 600 on the general-purpose bus 401 that connects the I / O card sharing mechanism 400 and the I / O processor blade 600. Reference numeral 401-1 denotes an upstream command signal (or PCI transaction) from the I / O processor blade 600 to the I / O card sharing mechanism 400 on the general-purpose bus 401. Further, reference numerals 311-1 and 312-1 denote the I / O card sharing mechanism 400 from the I / O cards 501 and 502 on the general-purpose buses 311 and 312 that connect the I / O card sharing mechanism 400 and the I / O cards 501 and 502. Upward PCI transactions going to the I / O card sharing mechanism 400 on the general-purpose buses 311 and 312, and 311-2 and 312-2 show down PCI transactions going to the I / O cards 501 and 502.

  When the I / O card sharing mechanism 400 receives the downstream PCI transaction 301-1 from the switch 200 (server side), the header information extraction unit 406 sends the PCI transaction to the header information 451 and the PCI transaction body 461 shown in FIG. To separate. The header information extraction unit 406 extracts an offset from the MMIO base address set in the PCI transaction. Then, the header information extraction unit 406 inputs the header information 451 and the offset to the associative memory 410, and inputs the PCI transaction body 461 to the first transaction decoder 402.

  The associative memory 410 is configured by a CAM (Contents Addressable Memory) or the like, and holds an address information table 411 set by the I / O processor blade 600. The address information table 411 stores access permission information (allocation information) of the servers # 1 to #n for the I / O cards 501 and 502 connected to the I / O card sharing mechanism 400, as will be described later. ing.

  The associative memory 410 inputs an address to be searched (header information 451) as a search key (bit string) and outputs an address corresponding to the input search key from a preset table (address information table 411). is there. As will be described later, the associative memory 410 outputs the base address of the corresponding MMIO and the address of the memory 603 on the I / O processor blade 600 from the input header information 451.

  The first transaction decoder 402 analyzes the command of the PCI transaction main body 461 from the PCI transaction main body 461 received from the header information extracting unit 406 and the MMIO base address received from the associative memory 410 and analyzes the I / O processor blade 600. The down command signal 401-2 to be output to is selected. If the command of the PCI transaction main body 461 is not a predetermined command, the transaction decoder 402 transfers the PCI transaction received by the I / O card sharing mechanism 400 as it is to the I / O card 501 or 502 as a downward PCI transaction. To do.

  Here, a memory space when one I / O card is shared among the plurality of server blades 10-1 to n (servers # 1 to #n) will be described. The following example shows a case where three servers # 1 to # 3 share one I / O card 501.

  The MMIO address space is an I / O area set by each server # 1 to # 3 in its own memory 102 for one I / O card. For example, as shown in FIG. 4, each of the servers # 1 to # 3 (server blades 10-1 to 3) has an I / O card (in this case, an I / O card 501) to be used (or shared). MMI / O areas having MMIO base addresses of 0xA, 0xB, and 0xC and offsets indicating the size of the memory space are set to 0xX, 0xY, and 0xZ. These MMIO base addresses and offsets are determined by the BIOS or OS that is started by each server blade 10-1 to n.

  Corresponding to the MMIO of each of these servers # 1 to # 3, the memory 603 of the processor blade 600 has a memory space 6031 of the I / O card 501 shared by the servers # 1 to # 3 as shown in FIG. ˜6032 are set as described later. In FIG. 5, a memory space 6031 (0xP) is set in the memory 603 of the processor blade 600 corresponding to the MMIO base address 0xA of the server # 1. Note that the I / O processor blade 600 stores only the MMIO of the server that shares the I / O card to be shared on the memory 603 based on the I / O card sharing setting table (see FIG. 7) set in the memory 603. Set memory space to. Similarly, a memory space 6032 (0xQ) is set corresponding to the MMIO base address 0xB of the server # 2 sharing the I / O card 501 and a memory space 6032 (0xR) corresponding to the MMIO base address 0xC of the server # 3. Is set.

  Since the MMIO base addresses of the servers # 1 to # 3 = 0xA, 0xB, and 0xC share the I / O card 501, the address information table 411 of the associative memory 410 is as shown in FIG. Are set by the I / O processor blade 600.

  The address information table 411 in FIG. 6 includes a header 4111 for comparison with the header information 451 of the PCI transaction received by the I / O card sharing mechanism 400 from the servers # 1 to # 3, and the header information 451 and the address information table 411. The MMIO base address 4112 of each server that is output when the header 4111 matches, the address of the memory space of the I / O processor blade 600 that is output when the header information 451 and the header 4111 of the address information table 411 match (in the figure) An offset 4114 for comparing with the offset input to the associative memory 410 when the interrupt to the CPU 602 of the I / O processor blade 600 is performed in advance.

  When the servers # 1 to # 3 share the I / O card 501 as described above, the address information of the I / O card 501 and the servers # 1 to # 3 is stored in the header 4111 of the address information table 411 in FIG. The MMIO base address 4112 is set with the MMIO base addresses of the servers # 1 to # 3 shown in FIG. 4, and the memory space address 4113 is set to the servers # 1 to # 3 as shown in FIG. The address information of the memory spaces 6031 to 6033 corresponding to the MMIO base address is set. The offset 4114 is set with a difference from the MMIO base address in order to obtain the size of the memory space of the servers # 1 to # 3.

  Here, in the header 4111, the destination 452 of the header information 451 is “Io1” indicating the address information of the I / O card 501, and the address information of the servers # 1 to # 3 of the request source 453 that requested the I / O access. “SV1” to “SV3” are set in the header 4111 as a pair of comparison addresses.

  For example, in a PCI transaction from the server # 1 (server blade 10-1) to the I / O card 501, “Io1” is set in the destination 452 of the header information 451, and the address information of the server # 1 is set in the request source 453. A certain “SV1” is set. When the header information 451 extracted by the header information extraction unit 406 is input to the address information table 411 of the associative memory 410, the MMIO base address 0xA of the server # 1 and the server # 1 for sharing the I / O card 501 The address = 0xP of the memory space 6031 of the I / O processor blade 600 is output from the associative memory 410.

  The MMIO base address output from the associative memory 410 is input to the first transaction decoder 402, and the address of the memory space 6031 is input to the signal selection unit 412.

  The operation of each of the transaction decoders 402 to 404 will be described below with the above memory space.

  The first transaction decoder 402 extracts a command for the I / O cards 501 and 502 from the PCI transaction body 461 received from the header information extraction unit 406, and the I / O card sharing mechanism 400 determines that the command is in accordance with the content of the command. A signal to be output to the I / O processor blade 600 or the I / O cards 501 and 502 is determined as follows.

  A) If the command extracted from the PCI transaction body 461 is a write command to the command register 512 of the I / O cards 501 and 502 (command for starting the operation of the I / O card, for example, a DMA transfer start command), The transaction decoder 402 instructs the interrupt generation unit 407 to output an interrupt, selects the output of the interrupt generation unit 407 to the signal selection unit 412, and sends it to the I / O processor blade 600 as a down command signal 401-2 on the general-purpose bus 401. Command to output. This interrupt signal includes the address 4113 of the I / O processor blade 600 output from the associative memory 410. Further, when interrupting, the header information 451 and the offset input to the associative memory 410 need to match the header 4111 and the offset 4114 of the address information table 411.

  B) The command extracted from the PCI transaction main body 461 is changed by a write command (for example, a DMA initialization request) to a register other than the command register 512 (for example, the base address register 511) of the I / O cards 501 and 502. If it is a command that does not start the operation of the / O card), the transaction decoder 402 sends a PCI transaction (header information 451 and PCI transaction body 461) to the memory writing unit 408 to a predetermined memory space of the I / O processor blade 600. ) Is selected, and the output of the memory writing unit 408 is selected to the signal selection unit 412 to be output to the I / O processor blade 600 as the down command signal 401-2 of the general-purpose bus 401. The memory writing unit 408 writes the header information 451 and the PCI transaction body 461 to the address 4113 of the I / O processor blade 600 output from the associative memory 410.

  C) If the command extracted from the PCI transaction main body 461 is a command other than a write request to the registers of the I / O cards 501, 502, the transaction decoder 402 converts the PCI transaction received from the signal line 420 to the I / O card. From the general-purpose buses 311 and 312 that connect the sharing mechanism 400 and the I / O cards 501 and 502, they are output as they are as the downward PCI transactions 311-2 and 312-2. In this case, the transaction decoder 402 selects and outputs the general-purpose bus 311 or 312 to which the corresponding I / O card 501 or 502 is connected based on the destination 452 of the header information 451 of the PCI transaction.

  In the above A) to C), the transaction decoder 402 refers to an I / O card sharing setting 405 described later, and accesses if the request destination I / O card is not allocated to the request source server. Ban. Further, the transaction decoder 402 refers to an I / O card sharing setting 405 described later, and when the allocation state (attribute) is “Dedicate” indicating the occupation, the address is not decoded by the associative memory 410 and the above C ), The PCI transaction is directly transferred to the destination I / O card, and the servers # 1 to #n and the I / O cards 501 and 502 perform normal access for direct I / O processing.

  As described above, the transaction decoder 402 of the I / O card sharing mechanism 400 is interposed between the servers # 1 to #n and the I / O cards 501 and 502 to transfer the I / O cards 501 and 502 to the registers. The writing is converted into an operation to the I / O processor blade 600 (write processing to the memory space, interrupt processing) so that the I / O cards 501 and 503 having no sharing function can be shared. For example, when the servers # 1 to #n make a DMA transfer request (DMA initialization request) to the I / O cards 501 and 502, the I / O card sharing mechanism 400 performs the MMIO that performs the DMA transfer by the function B). The base address is written into the memory space of the I / O processor blade 600. Next, when the servers # 1 to #n command the start of the DMA transfer, the I / O processor blade 600 is interrupted by the function A), and the CPU 602 of the I / O processor blade 600 causes the server to operate as described later. Write to the command register 512 and the base address register 511 of the I / O card 501 or 502 for executing DMA instead of # 1 to #n. Then, the I / O card 501 or 502 performs DMA transfer to the requesting servers # 1 to #n in response to a command from the I / O processor blade 600 that made an I / O access request on behalf of the servers # 1 to #n. I do. The detailed operation of the I / O processor blade 600 will be described later. When the server blade 10-1 to n receives an I / O card configuration register (not shown) reference request for initialization at startup, the transaction decoder 402 displays the CPU 602 of the I / O processor blade 600. And a PCI transaction is written to the memory 603.

  Next, the main function of the second transaction decoder 403 of the I / O card sharing mechanism 400 is to share the upstream command signal 401-1 received from the I / O processor blade 600 via the general-purpose bus 401. Filtering is performed so as to output only to the existing I / O card 501 or 502.

  Therefore, the I / O card sharing mechanism 400 uses the I / O card sharing setting 405 as an area for referring to the I / O card sharing setting table 610 (see FIG. 7) set on the memory 603 of the I / O processor blade 600. Is stored.

  Here, as shown in FIG. 7, the I / O card sharing setting table 610 is an attribute table indicating which server is assigned (available) for each I / O card, such as the console 5. It is set by the administrator. This table includes an identifier 611 composed of I / O card address information (device number and the like), a type 612 indicating the function of the I / O card, and the allocation states 613 to 603 of the servers # 1 to # 3. 615.

  FIG. 7 shows the relationship (attribute) between the servers # 1 to # 3 and the I / O cards 501, 502, the IO card 1 with the identifier 611 shows the I / O card 501, the type 612 is a SCSI card, and the attributes are “Share” indicates that the servers # 1, # 2, and # 3 share the I / O card 1. Note that the number of allocation states 613 to 615 also increases or decreases according to the number of servers that are operating.

  Also, the IO card 2 with the identifier 611 indicates the I / O card 502, the type 612 is a NIC card, and indicates the attribute “Dedicate” that is assigned only to the server # 2 and is occupied (unshared). This indicates that the / O card 2 is not shared by other servers # 1 and # 3. Note that the number of allocation states 613 to 615 also increases or decreases according to the number of servers that are operating. Further, since the I / O card 2 is not assigned to the servers # 1 and # 3 (not usable), access from these servers to the I / O card 2 is prohibited.

  When the transaction decoder 403 receives a PCI transaction from the I / O processor blade 600, the transaction decoder 403 extracts the server address (MMIO base address) from the PCI transaction body 461, compares it with the MMIO base address 4112 of the address information table 411, and matches the MMIO. If there is a base address, the destination and request source are acquired from the header 4111 of the entry. Next, the identifier of the I / O card sharing setting 405 is compared with the acquired destination, and the same server as the request source acquired with the matching entry is searched. If a destination I / O card is assigned to the corresponding server, the PCI transaction received by the transaction decoder 403 is valid and is output to the destination I / O card. On the other hand, if the destination I / O card is not assigned to the corresponding server, the PCI transaction is discarded because of an unequal I / O access request. The I / O card sharing mechanism 400 may notify the requesting server of an error after discarding the PCI transaction.

  Next, the main function of the third transaction decoder 404 of the I / O card sharing mechanism 400 is that the upstream PCI transactions 311-1 and 312 received from the I / O cards 501 and 502 via the general-purpose buses 311 and 312. -1 is to convert the header information 451 and the server address 462 of the PCI transaction main body 461 in order to send a reply to the servers # 1 to #n that request the I / O access.

  Further, the transaction decoder 404 determines whether the PCI transactions 311-1 and 312-1 received from the I / O card side are transactions that require address translation (such as DMA) or transactions that do not require address translation (for example, interrupts). The signal selection unit 413 selects either the output of the transaction decoder 404 or the upstream PCI transactions 311-1 and 312-1.

  If the PCI transactions 311-1 and 312-1 received from the I / O card side are DMA transfers or the like, the transaction decoder 404 determines that address conversion is necessary and selects the output of the transaction decoder 404. Commands the selection unit 413. On the other hand, if it is a PCI transaction that does not require address translation, it instructs the signal selection unit 413 to output the received PCI transactions 311-1 and 312-1 as they are.

  Here, the determination of the presence / absence of the address translation is made as follows. As described later, the servers # 1 to #n are assigned to predetermined high-order bits set in the unused area of the MMIO base address 462 of the PCI transaction body 461 shown in FIG. The transaction decoder 404 determines whether or not an identifier (address information or the like) is included. That is, the transaction decoder 404 is a PCI transaction that requires address conversion if the high-order bits of the MMIO base address 462 of the PCI transaction main body 461 include the identifiers of the servers # 1 to #n (hereinafter referred to as server identifiers). If the server identifier is not included, it is determined that the PCI transaction does not require address translation.

<I / O processor blade>
Next, functions of the I / O processor blade 600 will be described below. FIG. 8 is a functional block diagram mainly composed of the I / O processor blade 600.

  8, the memory 603 of the I / O processor blade 600 includes the I / O card sharing setting table 610 shown in FIG. 7 and memory spaces 6031 to 6032 of I / O cards shared by a plurality of servers (FIG. 8). In addition, an interrupt processing unit 620 activated by an interrupt (INT in the figure) from the I / O card sharing mechanism 400 is loaded from a ROM (not shown) or the like. In addition, when the server blades 10-1 to 10 -n are activated, the initialization processing unit 630 is loaded from the ROM (not shown) or the like into the memory 603 by an interrupt from the I / O card sharing mechanism 400.

  The I / O card sharing setting table 610 is appropriately set by the administrator or the like from the console 5 connected to the I / O processor blade 600 as described above, and the I / O card and servers # 1 to #n are set. Specify the allocation of As described later, the memory space 603x of the memory 603 is set by the CPU 602 when the servers # 1 to #n are activated. Then, when the received PCI transaction from the switch 200 corresponds to the above B), the I / O card sharing mechanism 400, for example, writes a command (DMA initialization request) to the base address register 511 of the I / O card. The PCI transaction main body 461 and header information 451 are written in the memory space 603x corresponding to the I / O card to be accessed and the requesting server.

  After that, the I / O card sharing mechanism 400 interrupts the CPU 602 of the I / O processor blade 600 when the received PCI transaction from the switch 200 corresponds to the above A) (write to the command register 512). Then, the interrupt processing unit 620 is activated.

  The interrupt processing unit 620 reads the header information 451 and the PCI transaction main body 461 previously written in the memory space 603x based on the address of the memory space 603x included in the interrupt command from the I / O card sharing mechanism 400. When the command included in the PCI transaction body 461 is DMA transfer, the header information 451 and the MMIO base address 462 included in the PCI transaction body 461 are temporarily converted as will be described later, and the address register 511 of the I / O card to be activated Write the converted MMIO base address.

  Next, the interrupt processing unit 620 sends a command (for example, DMA transfer start) included in the PCI transaction body 461 that generated the interrupt to the command register 512 of the I / O card that is the destination 452 of the header information 451. Write to start the operation of the I / O card.

  Next, the address conversion performed when the interrupt processing unit 620 performs DMA transfer will be described below.

  As shown in FIG. 3, in PCI-EXPRESS or PCI, 64 bits (0 to 63 bits in the figure) are defined as the MMIO address space of the PCI transaction. Also, CPUs 101- # n (server blades 10-1 to n) that are capable of 64-bit addressing are becoming popular. However, it is not realistic to mount the memory 102 that uses up the 64-bit address space in the server blades 10-1 to 10-n. At present, it is generally the upper limit of the memory space that can be loaded with tens of GB. Is. For this reason, the address bus of the CPU 101 and the like is also set to a predetermined value of less than 64 bits, for example, 52 bits (0 to 51 bits), as in the use area of FIG.

  Therefore, although 64 bits are defined as the MMIO address space, the upper bits of the address space are not used in mounting the server blades 10-1 to 10-n.

  As described above, when the lower 52 bits are used as an accessible address space, 52 to 63 bits in FIG. 3 among the upper bits of the MMIO base address 462 stored in the PCI transaction main body 461 become the unused area 463. In the blade server system, if the number of mountable server blades is about several tens, the unused area in FIG. 3 has 12 bits. Therefore, if at least 6 bits of the 12 unused areas are used, the chassis All servers in the body can be identified.

  On the other hand, an I / O card conforming to PCI-EXPRESS cannot identify a plurality of servers # 1 to #n on the I / O card side, and once DMA transfer is started, the MMIO at initialization Since only the base address 462 can be recognized, DMA transfer cannot be performed to the servers # 1 to #n to the plurality of servers # 1 to #n.

  Therefore, in the present invention, during DMA transfer, the unused upper bits of the MMIO base address 462 of the PCI transaction are used as an area for storing a server identifier (address information), and the interrupt processing of the I / O processor blade 600 is performed. The unit 620 performs address conversion by embedding the request source 453 serving as a server identifier in the upper bits of the MMIO base address 462.

  Then, the interrupt processing unit 620 writes the MMIO base address 462 subjected to address conversion into the base address register 511 of the I / O card, writes the start of DMA transfer into the command register 512, and activates the DMA of the I / O card.

  After the DMA transfer of the I / O card is started, when the transaction decoder 404 of the I / O card sharing mechanism 400 receives the PCI transaction from the I / O card, it is embedded in the unused area 463 of the upper bits of the MMIO base address 462. The extracted server identifier is extracted and written in the destination 452 of the header information 451 of the PCI transaction. Then, the transaction decoder 404 writes “0” in the server identifier area of the MMIO base address 462 to delete the embedded path information of the request source, and then transmits this PCI transaction to the switch 200. The switch 200 transfers the PCI transaction to the server designated as the destination based on the header information of the PCI transaction, that is, the servers # 1 to #n that requested the DMA transfer.

  In other words, the interrupt processing unit 620 of the I / O processor blade 600 writes the address of the request source 453 embedded in the unused area 463 of the MMIO as a server identifier into the address register 511 of the I / O card. The DMA transfer of the card is started, and the DMA transfer output from the I / O card is extracted by the I / O card sharing mechanism 400 by extracting the server identifier from the unused area 463 of the MMIO base address 462 in the PCI transaction, and the header It is set to the destination 452 of the information 451. As a result, the I / O card itself can be shared by the I / O card sharing mechanism 400 and the I / O processor blade 600 even if the I / O card itself does not have a function of identifying a plurality of servers # 1 to #n. It becomes.

<I / O card sharing process>
Next, FIG. 9 shows I / O card sharing processing by the I / O card sharing mechanism 400 and the I / O processor blade 600 mainly using PCI transactions.

  In FIG. 9, in S1, the servers # 1 to #n set and transmit a DMA initialization command or the like in the PCI transaction to the I / O card that performs I / O access. The servers # 1 to #n set their own address information (server identifier) in the request source 453 of the PCI transaction header information 451, and the MMIO base address assigned by the server to this I / O card is set as the MMIO base address 462. Set.

  In S2, when the I / O card sharing mechanism 400 interposed between the I / O card and the server receives this PCI transaction, there is a DMA initialization command including a write instruction to the address register 511 of the I / O card. The PCI transaction is written into the memory space 603x of the I / O processor blade 600. At this time, access to the I / O card is not performed.

  In S3, when the servers # 1 to #n transmit a PCI transaction for starting DMA transfer to the I / O card, the I / O card sharing mechanism 400 includes a command for starting the operation of the I / O card, so The O processor blade 600 is interrupted and the interrupt processing unit 620 is activated.

  The interrupt processing unit 620 reads the MMIO base address 462 from the PCI transaction written in the memory space 603x and writes it in the address register 511 of the I / O card. At this time, the interrupt processing unit 620 embeds the request source 453 of the header information 451 indicating the request source server in the unused area 463 of the MMIO base address 462 in the PCI transaction. Then, the interrupt processing unit 620 writes the DMA transfer start to the command register 512 of the I / O card, and activates the operation of the I / O card.

  In S4, the I / O card performs a DMA transfer (write or read) to the MMIO base address 462 set in the address register 511.

  In the PCI transaction by DMA from the I / O card, the server identifier is embedded in the unused area 463 set in the upper bits of the MMIO base address 462.

  In S5, when the I / O card sharing mechanism 400 interposed between the I / O card and the servers # 1 to #n receives the PCI transaction, the transaction decoder 404 in FIG. Determine.

  Whether or not the PCI transaction from the I / O card performed by the transaction decoder 404 is DMA is determined based on whether or not all bits of the unused area 463 of the MMIO base address 462 are 0, the server identifier is embedded. It can be determined that the transaction is a PCI transaction by DMA.

  In the case of a DMA PCI transaction, the transaction decoder 404 sets the contents of the unused area 463 of the MMIO base address 462 to the destination 452 of the header information 451, and addresses of servers # 1 to #n that can be identified by the switch 200 Convert to information. Thereafter, the transaction decoder 404 transmits this PCI transaction after setting all bits of the unused area 463 to 0 in order to erase the contents of the unused area 463.

  Based on the destination 452, the switch 200 transfers the DMA PCI transaction to the server that requested the DMA set in the destination 452, and the MMIO set in the servers # 1 to #n performs predetermined access. Is called.

  As described above, since the server identifier (request source 453) that requested the DMA is set in a predetermined upper bit of the MMIO base address set in the address register 511 of the I / O card, the DMA is repeatedly performed. In addition, since the I / O card sharing mechanism 400 replaces the address 452 of each PCI transaction with the address information of the server that is the DMA request source, the server blades 10-1 to 10-n can use the general-purpose I / O card. It becomes possible to share.

  The time chart of FIG. 10 shows the above processing in time series. First, in S11, the servers # 1 to #n set and transmit a DMA initialization command or the like in the PCI transaction to the I / O card that performs I / O access.

  In S 12, since the I / O card sharing mechanism 400 is a write request to a register other than the command register 512 of the I / O card, the contents of the PCI transaction are written in the memory space of the I / O processor blade 600.

  Next, in S13, the servers # 1 to #n set and transmit a write command to the command register 512 such as a DMA transfer start command in the PCI transaction to the I / O card that performs I / O access.

  In S14, since the I / O card sharing mechanism 400 is a write command to the command register 512 of the I / O card, it requests an interrupt to the CPU 602 of the I / O processor blade 600.

  In S15, the CPU 602 of the I / O processor blade 600 activates the interrupt processing unit 620 and reads contents other than the command register 512 such as the address register 511.

  In S16, if the content of the PCI transaction read by the interrupt processing unit 620 is DMA, the request source 453 of the header information 451 is set in the unused area 463 of the MMIO base address 462. Then, the address-converted MMIO base address 462 is written into the address register 511 of the I / O card, and a DMA transfer start command is written into the command register 512 to activate the operation of the I / O card.

  In S 17, the DMA controller 513 of the I / O card performs DMA access to the memory space of the address register 511.

  In S18, the PCI transaction from the I / O card is received, and the transaction decoder 404 determines whether it is DMA as described above. In the case of a DMA PCI transaction, the transaction decoder 404 sets the server identifier of the unused area 463 of the MMIO base address 462 of the PCI transaction main body 461 as the destination 452 of the header information 451 and converts (restores) the address information. ). Then, the transaction decoder 404 transmits a PCI transaction to the server that requested the DMA via the switch 200.

  By the above procedure, the identifier of the server that requested the DMA is embedded in the unused area 463 of the MMIO base address 462, and the I / O card DMA controller 513 executes processing, so that one I / O card can be connected to a plurality of I / O cards. The servers # 1 to #n can be shared.

<Address information setting process>
Next, FIG. 11 is a time chart showing an example of setting processing of the address information table 411 executed when the server blades 10-1 to n are activated.

  The address information table 411 stored in the associative memory 410 is updated by the process of FIG. 11 every time the server blades 10-1 to 10-n are activated. Hereinafter, a case where the server blade 10-1 is activated will be described.

  First, in S20, the server blade 10-1 is turned on. In S21, when the power is turned on, the CPU 101 activates a BIOS (not shown) and requests the configuration register of each I / O card to read in order to initialize the I / O card (device).

  In S22, since the transaction decoder 402 of the I / O card sharing mechanism 400 has received a request to read the configuration register of the I / O card, as described above, it interrupts the CPU 602 of the I / O processor blade 600, Further, the PCI transaction for requesting reading of the configuration register is written to the memory 603. At this time, since the MMIO is not set in the server blade 10-1 that issued the configuration register read request, the transaction decoder 402 writes to a preset address.

  In S23, the CPU 602 of the I / O processor blade 600 activates the initialization processing unit 630 shown in FIG. The initialization processing unit 630 reads the I / O card sharing setting table 610 from the configuration register read request written at a predetermined address, and confirms the I / O card assigned to the server blade.

  In S24, if the I / O card is not assigned to the server blade 10-1 (access prohibition), the initialization processing unit 630 notifies that there is no assignment via the I / O card sharing mechanism 400 (master). Abort treatment). On the other hand, if the I / O card is assigned to the server blade, the initialization processing unit 630 reads the contents of the configuration register of the I / O card and responds to the server blade 10-1. Note that the processing in S24 is sequentially executed for all the I / O cards set in the I / O card sharing 610.

  In S25, upon receiving the contents of the I / O card configuration register from the I / O processor blade 600, the server blade 10-1 sets the MMIO space and IO space from the acquired I / O card information, and the MMIO base Set the address. Then, the server blade 10-1 notifies the I / O card of the MMIO base address. This notification is executed for each I / O card.

  In S26, the I / O card sharing mechanism 400 receives a PCI transaction notifying the MMIO base address from the server blade 10-1. Since the I / O card sharing mechanism 400 is an MMIO base address setting notification, the I / O card sharing mechanism 400 interrupts the CPU 602 of the I / O processor blade 600 and writes a PCI transaction for notifying the MMIO base address to the memory 603. This process is performed in the same manner as S22.

  In S <b> 27, the CPU 602 of the I / O processor blade 600 activates the initialization processing unit 630 by the interrupt of the transaction decoder 402. The initialization processing unit 630 allocates a memory space 6031 corresponding to the I / O card of the server blade 10-1 to the memory 603 from the MMIO base address setting notification of the server blade 10-1 written at a predetermined address. The initialization processing unit 630 then sets the MMIO base address and offset of the server blade 10-1, the address of the memory space 6031 of the I / O processor blade 600, the address information of the assigned I / O card, and the server blade 10 -1 address information is notified to the I / O card sharing mechanism 400 and these addresses are reflected in the address information table 411 of the associative memory 410. Note that the process of S27 may be repeatedly executed for each I / O card used by the server blade 10-1.

  With the above processing, the I / O processor blade 600 acts as a proxy without directly accessing the activated server blades 10-1 to 10-n to the I / O cards 501 and 502 shared by the plurality of server blades 10-1 to 10-n. The contents of the configuration register are acquired and the memory space 603x is set. In the blade server system, a new server blade can be installed and activated when another server blade is operating. In such a case, the I / O processor blade 600 responds instead of the I / O card when a new server blade is started, thereby affecting the I / O access of other operating server blades. It becomes possible to start a new server blade without any problems.

  In the above description, the example is shown in which the boot is performed by the BIOS mounted on the server blade. However, although not illustrated, even when the boot is performed by EFI (Extensible Firmware Interface), the same processing as described above can be performed.

<I / O card sharing setting table>
The I / O card sharing setting table 610 shown in FIG. 7 will be described below.

  As described above, the I / O card sharing setting table 610 is a table indicating which server is assigned to each I / O card, and is set appropriately by the administrator from the console 5 or the like. The attributes of sharing, occupying, and prohibiting access to the servers # 1 to #n and the I / O card are displayed on the display of the console 5 with the interface shown in FIG. 7, and set with an interface such as a mouse or a keyboard (not shown). can do.

  The identifier 611 of the I / O card sharing setting table 610 is appropriately set by the administrator every time an I / O card is added or changed. The type 612 indicating the function of the I / O card can be set in this table by reading the class code and subclass code of the configuration register of the I / O card.

  In the allocation states 613 to 615 of the servers # 1 to # 3, the administrator appropriately sets the presence or absence of sharing and the presence or absence of allocation from the characteristics and performance of the servers # 1 to # 3 and the I / O card. In FIG. 7, “Share” is set when allocating to a plurality of servers for sharing, “No Assigned” is set when not allocating, and “Dedicate” is set when occupying one server. The access to this I / O card from other servers is prohibited. Note that a server whose I / O card assignment is set to “No Assigned” is denied access when accessing the I / O card. When the denied access is read, the I / O card sharing mechanism 400 responds with data having all bits set to 1, and when the access is write, it notifies the master abort.

  This I / O card sharing setting table 610 is reflected in the I / O card sharing setting 405 of the I / O card sharing mechanism 400. Then, the second transaction decoder 403 that manages the PCI transaction from the I / O processor blade 600 to the I / O card permits only a legitimate transaction based on the I / O card sharing setting 405 and performs an illegal transaction. That is, access by a server not assigned in the I / O card sharing setting table 610 is prohibited.

  Although all I / O cards can be shared using this I / O card sharing setting table 610, other I / O cards can be occupied by a server with one I / O card in order to ensure throughput. Can be set to share. As a result, sharing and occupation of the I / O card can be mixed, and the configuration of the I / O device of the blade server system can be made flexible. Can be used effectively.

Second Embodiment
FIG. 12 is a block diagram of a blade server system showing the second embodiment. In this blade server system, a command chain control unit 514 is added to the I / O card of the first embodiment, and the data structures set in the memory 02 of the servers # 1 to #n are sequentially read to perform I / O processing. The other configurations are the same as those of the first embodiment.

  The I / O cards 1501 and 1502 sequentially read the data structures set in the memory 102 of the server blades 10-1 to 10-n and perform I / O operations according to the description of each data structure. The processing is performed.

  When using the I / O card, the servers # 1 to #n operating on the server blades 10-1 to 10-n have predetermined addresses in the memory spaces of the servers # 1 to #n as shown in FIG. Data structures 1020 to 1022 are set in advance.

  For example, in the memory space of the server # 1, three data structures 1020 (CCW1 to 3) are set to the address 0xD, and in the memory space of the server # 2, two data structures 1021 (CCW11 and 12) are set. Address 0xE is set, and four data structures 1022 (CCW21 to 24) are set to address 0xF in the memory space of server # 3. These data structures are set appropriately by the OS or application of each of the servers # 1 to # 3.

  A flag indicating that there is a next data structure is set in the first and intermediate data structures. For example, a flag indicating that there is the next data structure is set in CCW1 and CCW2 of the data structure 1020, and this flag is not set in CCW3, indicating that it is the last data structure.

  Each of the servers # 1 to # 3 transmits a command for starting the operation to the I / O card 1501 or 1502 to be used, and notifies the addresses of the data structures 1020 to 1022 set in the memory space.

  When the I / O cards 1501 and 1502 receive the address of the memory space together with the activation instruction from the servers # 1 to #n, the I / O cards 1501 and 1502 read the data structure of the designated memory space and are described in the data structures 1020 to 1022 I / O access is executed.

  An example in which an I / O card sharing mechanism 400 and an I / O processor blade 600 similar to those of the first embodiment are applied to a blade server system including I / O cards 1501 and 1502 for performing such command chain processing. Is shown below.

  A time chart of I / O card sharing processing by the I / O card sharing mechanism 400 and the I / O processor blade 600 is shown in FIG. Hereinafter, a case where the server # 1 (server blade 10-1) uses the I / O card 1501 will be described.

  First, the server # 1 transmits a PCI transaction instructing activation of operation to the I / O card 1501 that performs I / O access (S31). In this PCI transaction, the MMIO base address assigned to the I / O card 1501 by the server # 1 is set in the MMIO base address 462, and the command for instructing the start of operation and the address 0xD of the data structure 1020 are stored in the PCI transaction body 461. Set to.

  When the I / O card sharing mechanism 400 receives the PCI transaction from the server # 1, the I / O card sharing mechanism 400 analyzes the command of the PCI transaction, and the command for starting the operation is a command to write to the command register 512 of the I / O card 1501. An interrupt is issued to the CPU 602 of the I / O processor blade 600 (S32). At the same time, the I / O card sharing mechanism 400 writes the contents of the PCI transaction in a predetermined memory space 6031 (see FIG. 5) of the I / O processor blade 600 (S33).

  The CPU 602 activated by the interruption activates the interrupt processing unit 620 of the first embodiment. Then, the interrupt processing unit 620 reads the address 0xD of the data structure 1020 of the PCI transaction written in the memory space, and acquires the request source 453 of the MMIO base address 462. Next, the interrupt processing unit 620 reads the data structure 1020 from the acquired address with respect to the memory 102 of the server # 1 of the request source 453, and loads the data structure 1020 into a predetermined memory space of the I / O processor blade 600. Copy (S34). As shown in FIG. 15, this memory space is an area for storing a data structure preset for each of the servers # 1 to #n. In this example, the data structure memory of the servers # 1 to # 3 is stored. 0xS, 0xT, and 0xU are set as the space, and the data structure 1020 of the server # 1 is stored from the address 0xS as illustrated.

  Next, the interrupt processing unit 620 performs MMIO processing used in DMA or the like. From the PCI transaction written in the memory space 6031, the request source 453 of the header information 451 set in the unused area 463 of the MMIO base address 462 is written into the address register 511 of the target I / O card 1501 to convert the address. (S35).

  Thereafter, the interrupt processing unit 620 writes the operation start command in the command register of the I / O card 1501 based on the received PCI transaction operation start command, and the command chain control unit 514 receives data. The address 0xS of the structure 1020 is notified (S36).

  The I / O card 1501 is activated based on the activation instruction of the interrupt processing unit 620, and reads one data structure (CCW1) 1020 from the received address 0xS of the memory 603 of the I / O processor blade 600 (S37). Note that the I / O card sharing mechanism 400 transfers the communication from the I / O card 1501 to the I / O processor blade 600 as it is.

  The I / O card 1501 performs an I / O operation according to the description of the data structure 1020. For example, when the read data structure 1020 is DMA, the I / O card 1501 performs DMA transfer with respect to the MMIO base address set in the address register 511 (S38). In the PCI transaction by DMA from the I / O card, the server identifier is embedded in the unused area 463 set in the upper bits of the MMIO base address 462.

  When the I / O card sharing mechanism 400 interposed between the I / O card 1501 and the server # 1 receives the PCI transaction, the transaction decoder 404 in FIG. 2 determines whether or not it is a PCI PCI transaction.

  Whether or not the PCI transaction from the I / O card performed by the transaction decoder 404 is DMA is determined based on whether or not all bits of the unused area 463 of the MMIO base address 462 are 0, the server identifier is embedded. It can be determined that the transaction is a PCI transaction by DMA.

  In the case of a DMA PCI transaction, the transaction decoder 404 sets the contents of the unused area 463 of the MMIO base address 462 to the destination 452 of the header information 451, and addresses of servers # 1 to #n that can be identified by the switch 200 Convert to information. Thereafter, in order to erase the contents of the unused area 463, the transaction decoder 404 sets this bit to 0 in all the unused areas 463 and then transmits this PCI transaction (S39).

  Based on the destination 452, the switch 200 transfers the DMA PCI transaction to the server that requested the DMA set in the destination 452, and the MMIO set in the servers # 1 to #n performs predetermined access. Is called.

  When the I / O operation designated by the data structure (CCW1) 1020 is completed, the I / O card 1501 stores the address 0xS of the memory 603 of the I / O processor blade 600 designated by the next data structure (CCW2). And execute as above.

  As described above, in the case of the I / O cards 1501 and 1502 that perform command chain processing, the data structures 1020 to 1022 of the servers # 1 to # 3 are copied to the memory space of the memory 603 of the I / O processor blade 600. The I / O processor blade 600 responds to a read request from the I / O cards 1501 and 1502 in place of the servers # 1 to # 3.

  Therefore, when the I / O cards 1501 and 1502 are activated, the command chain processing is performed by notifying the I / O card of the address on the memory 603 storing the data structures 1020 to 1022 of the server that requested the I / O access. It is possible to share the I / O card for performing the processing among a plurality of servers # 1 to # 3.

<Third Embodiment>
FIG. 16 is a block diagram of a blade server system showing the third embodiment. In the present embodiment, the switch 200 of the first or second embodiment is integrated with an I / O card sharing mechanism 400.

  The switch 200A includes the I / O card sharing mechanism 400, and operates as described in the first or second embodiment. By including the I / O card sharing mechanism 400 in the switch 200A, the number of slots installed in the blade server system can be reduced, and the housing can be configured compactly.

<Summary>
As described above, according to the present invention, when a plurality of server blades 10-1 to 10-n share one I / O card and perform DMA transfer, the I / O processor blade 600 is set to I The I / O card sharing mechanism 400 that embeds the identifier of the server that requested the DMA in the address register 511 of the / O card in the MMIO base address and relays the PCI transaction from the I / O card to the server. The general-purpose bus I / O card can be shared by replacing the server identifier embedded in the destination address 452 of the header information 451.

  After the DMA transfer is started, the I / O processor blade 600 does not intervene in the PCI transaction transfer and the hardware of the I / O card sharing mechanism 400 performs address conversion. It is possible to realize sharing of an I / O card among a plurality of servers while preventing overhead and preventing performance degradation of I / O access.

  Furthermore, since the I / O card shared by the plurality of server blades 10-1 to 10-n can be configured with a general-purpose bus interface, when performing server integration as described above, the I / O card that has been conventionally used is used. Since the / O card can be used as it is, the cost for server integration can be suppressed.

  In addition, when integrating servers, a plurality of server blades 10-1 to 10-n can share one I / O card, so that the number of I / O cards can be reduced. / O cards can be prevented from increasing, and a compact housing can be used.

  In addition, the I / O card sharing setting table 610 allows a shared I / O card and an I / O card to be occupied only by one server blade to be mixed, thereby enabling a flexible configuration of the blade server system. .

  In each of the above embodiments, an example in which PCI-EXPRESS is applied as a general-purpose bus has been described. However, a general-purpose bus such as PCI or PCI-X may be adopted.

  In the above embodiments, the server blades 10-1 to n and the servers # 1 to #n correspond to each other on a one-to-one basis. However, the servers # 1 to #n are configured by logical partitions of virtual machines. Server identifier may be a logical partition number.

  Further, in each of the above embodiments, an example in which the I / O processor blade 600 is directly connected to the I / O card sharing mechanism 400 has been described, but the I / O processor blade 600 may be connected to the switch 200. Further, instead of the I / O processor blade 600, the server blade may execute the processing of the I / O processor blade 600.

  As described above, the present invention can be applied to a computer system in which a plurality of servers and I / O cards or I / O devices are connected by a general-purpose bus, and in particular, by being applied to a blade server system that performs server integration. Reduce costs and ensure performance.

The block diagram of the blade server system which shows 1st Embodiment. The block diagram of an I / O card sharing mechanism. Explanatory drawing of a PCI transaction. Explanatory drawing which shows the memory space of a server. Explanatory drawing which shows the memory space of an I / O processor blade. Explanatory drawing which shows an example of an address information table. Explanatory drawing which shows an example of an I / O card sharing setting table. The block diagram which shows the relationship between an I / O card sharing mechanism and an I / O processor blade. Explanatory drawing which shows the flow of an I / O card sharing process. The time chart which shows the flow of an I / O card sharing process. It is a time chart which shows an example of the setting process of address information performed when starting a server blade. The block diagram of the blade server system which shows 2nd Embodiment. Explanatory drawing which shows 2nd Embodiment and shows the memory space of a server. The time chart which shows 2nd Embodiment and shows the flow of an I / O card sharing process. Explanatory drawing which shows 2nd Embodiment and shows the memory space of an I / O processor blade. The block diagram of the blade server system which shows 3rd Embodiment.

Explanation of symbols

10-1 to 10-n Server blade 200 Switch 400 I / O card sharing mechanism 501, 502 I / O card 600 I / O processor blade 405 I / O card sharing setting 411 Address information table 610 I / O card sharing setting table

Claims (10)

Multiple servers,
A switch for connecting the plurality of servers and the I / O card,
In the computer system in which the server has a memory space writable from the I / O card,
An I / O card sharing unit that is disposed between the switch and the I / O card and operates an access request signal and a response signal between the plurality of servers and the I / O card;
A memory capable of accessing the I / O card and the I / O card sharing unit and writable from the I / O card sharing unit; and a processor for accepting an interrupt from the I / O card sharing unit. An I / O processor that manages allocation of the I / O card to the plurality of servers;
With
The switch sends an access request signal including a command from the server to the I / O card and a base address designating the memory space, the destination of the access request signal and the path information of the request source in the access request signal. A response signal including a response from the I / O card to the server and a base address designating the memory space is added to the header information and transmitted to the I / O card sharing unit. A header processing unit that transfers to a destination server included in
The I / O card sharing unit
A request signal writing unit that writes the access request signal to the memory of the I / O card sharing unit when the command included in the access request signal received from the switch is a first command set in advance;
An interrupt generator that interrupts the I / O processor when the command included in the access request signal received from the switch is a second command set in advance;
When a response signal from the I / O card to the server is received, the request source route information is extracted from the base address included in the response signal, and the request source route information is extracted from the header information of the response signal. A header correction part to be set in the destination;
A base address correction unit that deletes the route information of the request source embedded in the base address of the response signal;
A transmission unit for transmitting the response signal to the switch,
The I / O processor is
An address converter configured to set the request source path information from the header information of the access request signal in a predetermined upper bit of a base address included in the access request signal written in the memory when the interrupt occurs; ,
A response address setting unit that sets the base address in which the header information of the request source is set to upper bits based on the interrupt as a response destination of the I / O card;
An I / O card activation unit that transmits the access request signal to the I / O card based on the interrupt and activates the operation of the I / O card;
The I / O card returns a response signal of processing corresponding to the access request signal to the I / O card sharing unit. The I / O card is
A command register for setting a command included in the access request signal;
An address register that specifies a memory space of a server that responds to the access request signal,
The request signal writing unit receives the access request signal received from the switch when the command included in the access request signal is a first command including a write process to an I / O card excluding the command register. Write to the memory of the I / O card sharing unit,
The interrupt generation unit interrupts the I / O processor when a command included in the access request signal received from the switch is a second command including a write process to the command register,
The said response address setting part writes the said base address which set the header information of the said request origin to the high-order bit to the address register of the said I / O card based on the said interruption. Computer system. The request signal writing unit receives the access request signal received from the switch when the command included in the access request signal includes a DMA initialization process requesting writing to an address register. Write to the memory of
The interrupt generation unit interrupts the I / O processor when a DMA start command for requesting writing to a command register is included in an access request signal received from the switch. The computer system described. The I / O processor is
There is an I / O card sharing setting management unit that identifies whether each of the servers can use the I / O card and sets an attribute that identifies whether the I / O card is shared or not. And
The I / O card sharing unit
With reference to the I / O card sharing setting management unit, when the attributes of the destination I / O card and the requesting server of the access request signal received from the switch are available and occupied, a request from the server 2. The computer system according to claim 1, wherein the signal is directly transferred to the I / O card, and the response signal from the I / O card to the server is transferred as it is. The I / O processor is
There is an I / O card sharing setting management unit that identifies whether each of the servers can use the I / O card and sets an attribute that identifies whether the I / O card is shared or not. And
The I / O card sharing unit
With reference to the I / O card sharing setting management unit, when the attributes of the I / O card set as the destination of the access request signal received from the switch and the requesting server are unavailable, the server 2. The computer system according to claim 1, wherein either one of master abort and data having all bits of 1 is returned in response to the request signal. The I / O processor is
An I / O card sharing setting management unit that identifies whether each of the servers can use the I / O card and sets an attribute that identifies whether the I / O card is shared;
An attribute setting unit for setting an attribute of the I / O card sharing setting unit via an input unit connected to the I / O processor;
The computer system according to claim 1, comprising: The I / O card sharing unit
An address information determination unit that outputs the address information used in the request signal writing unit or the interrupt generation unit by comparing header information included in the access request signal received from the switch with preset information;
2. The computer system according to claim 1, wherein the address information determination unit sets the information based on a write command to the I / O card that is executed when the server is started. The I / O card is
A command register for setting a command included in the access request signal;
An address register that specifies a memory space of a server that responds to the access request signal;
A command chain processing unit that reads a data structure stored in the memory of the server and performs command chain processing;
Have
The first and second commands are composed of one activation request, and the activation request is written to the command register of the I / O card,
The request signal writing unit writes the request signal to the memory of the I / O processor, and writes the data structure set in the memory of the server to the memory of the I / O processor.
3. The computer system according to claim 2, wherein the I / O card reads and processes a data structure set in a memory of the I / O processor after the I / O card is activated. Multiple servers,
A switch for connecting the plurality of servers and the I / O card,
In the computer system in which the server has a memory space writable from the I / O card,
An I / O card sharing unit that is disposed between the switch and the I / O card and operates an access request signal and a response signal between the plurality of servers and the I / O card;
A memory that is accessible to the I / O card and the I / O card sharing unit and is writable from the I / O card sharing unit; and a processor that receives an interrupt from the I / O card sharing unit. An I / O processor that manages allocation of the I / O card to the plurality of servers;
With
The switch is
An access request signal including a command from the server to the I / O card and a base address designating the memory space is added to the header information of the access request signal with the destination of the access request signal and the request source path information. The response signal including the response from the I / O card to the server and the base address designating the memory space is transmitted to the I / O card sharing unit, and the destination included in the header information of the response signal A header processing unit for transferring to the server, and the I / O card sharing unit,
The I / O card sharing unit
A request signal writing unit that writes the access request signal to the memory of the I / O card sharing unit when the command included in the access request signal received from the header processing unit is a first command set in advance;
An interrupt generation unit that interrupts the I / O processor when the command included in the access request signal received from the header processing unit is a second command set in advance;
When the response signal from the I / O card to the server is received, the request source route information is extracted from the base address included in the response signal, and the request source route information is extracted from the header information of the response signal. A header correction part to be set in the destination;
A base address correction unit that deletes the route information of the request source embedded in the base address of the response signal;
A transmission unit for transmitting the response signal to the switch,
The I / O processor is
An address conversion unit configured to set the request source path information from the header information of the access request signal in a predetermined upper bit of a base address included in the access request signal written in the memory when the interrupt occurs; ,
A response address setting unit that sets, as a response destination of the I / O card, the base address in which the header information of the request source is set to upper bits based on the interrupt;
An I / O card activation unit that transmits the access request signal to the I / O card based on the interrupt and activates the operation of the I / O card;
The I / O card returns a response signal of processing corresponding to the access request signal to the I / O card sharing unit.   2. The server and the switch, and the switch and the I / O card sharing unit and the I / O card sharing unit and the I / O card are connected by PCI or PCI-EXPRESS. Or the computer system of Claim 9.