JP2011161100A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which permits a surefire measure against a fraudulent act to be taken by surely detecting the fraudulent act to a detector to detect the game medium. <P>SOLUTION: The game machine detects game balls winning in a first start winning opening 13a, a second start winning opening 13b, and a big winning opening 23b, respectively by two sensors using different detection systems (proximity switches 14a, 15a, 23 and photosensors 14b, 15b, and 23a) and decides that an excess of a difference between the number of balls detected by the proximity switches 14a, 15a and 23 and the number of balls detected by the photosensors 14b, 15b, and 23a over a prescribed threshold value represents abnormal winning. The threshold value is a value larger than the difference between the number of balls detected by the proximity switches and the number of balls detected by the photosensors at the time when the balls get caught in a first winning passageway 1360a and 1360b corresponding to a winning opening in which the flowing down distance from the proximity switches to the photosensors is longest from among a plurality of winning openings. The game machine prevents a decision from leading to abnormal winning due to the balls getting caught. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a gaming machine having a plurality of winning holes through which game media can be won, and paying out a prize gaming medium as a prize based on the winning of a gaming medium in any one of the plurality of winning holes.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

  Further, in order to prevent illegally paying out game media as prizes due to fraudulent acts, the payout control means includes the number of winning game media actually detected by each of the winning switches provided for each winning area. There is a gaming machine that compares the number of detections by a safe sensor as a collective winning ball detector that detects all winning game media and determines that an abnormality has occurred in winning detection when they do not match (for example, , See Patent Document 1).

JP 2000-237436 A (paragraphs 0074, 0081)

  As a switch for detecting a game ball, a proximity switch for detecting a change in electric field or magnetic field due to the approach of a metal (for example, a game ball) is often used. Since the proximity switch detects a change in an electric field or a magnetic field, it may malfunction if it receives a strong electromagnetic wave (radio wave). In other words, there is room for fraudulent acts by radio waves. That is, by illegally emitting radio waves, a switch for detecting a game ball is caused to output a detection signal (false detection signal) indicating that a game ball has been detected even though the game ball is not actually detected. There is a possibility of cheating. In addition, as a switch for detecting a game ball, a light-emitting element and a light-receiving element are juxtaposed, and light from the light-emitting element reflected by the game ball is detected by the light-receiving element so that the light passes through the vicinity of the light-emitting element and the light-receiving element In the case of using a reflection type photosensor that detects the game ball, the light of the light receiving element in the photosensor is irradiated by some means, so that the game ball is actually detected by the switch that detects the game ball. In spite of this, there is a possibility that a fraudulent act of outputting a detection signal (false detection signal) indicating that a game ball has been detected may be received.

  In the case where both the winning switch and the safe sensor described in Patent Document 1 receive an illegal act that outputs a false detection signal, the number of winning game media actually detected by each winning switch and the safe Since there is no discrepancy with the number detected by the sensor, it is not possible to detect fraud.

  Therefore, an object of the present invention is to provide a gaming machine that can more reliably detect fraudulent acts with respect to the detection means for detecting game media and can take a certain measure against fraudulent acts.

In order to solve the above-mentioned problem, a gaming machine according to claim 1 of the present invention provides:
A plurality of winning holes (first start winning port 13a, second starting winning port 13b, large winning port 23b) through which game media (game balls) can be won are provided, and the game medium is placed in any one of the plurality of winning ports. A game machine (pachinko machine 1) that pays out a prize game medium (prize ball) as a prize based on winning a prize,
Each of the plurality of winning prize openings is
First detection means (first start port switch 14a, second start port switch 15a, count switch 23) for detecting a game medium and outputting a first detection signal;
Second detection means (first winning confirmation switch 14b, second winning confirmation switch 15b, third winning confirmation switch 23a) for detecting a game medium and outputting a second detection signal are provided;
Abnormality determining means (game) for determining a winning abnormality in the winning opening based on the first detection signal output from the first detecting means and the second detection signal output from the second detecting means In the control microcomputer 560, a part for executing step S113 in the switch process),
Transition means (a part for executing step S135 in the switch process in the game control microcomputer 560) that shifts to a predetermined error state based on the determination that the prize is abnormal by the abnormality determination means,
The first detection means and the second detection means are constituted by sensors of different detection methods (for example, the detection method of the game medium of the first detection means is electromagnetic, and the game medium of the second detection means is The detection method is optical),
The abnormality determination means is detected by the first detection means based on the first detection signal output from the first detection means and the second detection signal output from the second detection means. When the difference between the number of played game media and the number of game media detected by the second detection means exceeds a predetermined threshold value (for example, 15), it is determined that an award abnormality has occurred in the prize opening (for example, The game control microcomputer 560 determines Y in step S134 and determines that an abnormal winning has occurred in any of the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b).
The predetermined threshold value is determined based on the first detection at the winning opening (first winning path 1360a, 1360b) having the longest flow distance of the game medium from the first detecting means to the second detecting means among the plurality of winning holes. Difference between the number of game media detected by the first detection means and the number of game media detected by the second detection means when a plurality of game media stays between the means and the second detection means The value (for example, 15) is larger than (for example, 9).
It is characterized by that.
According to this feature, it is possible not only to more reliably detect fraudulent acts against the detection means for detecting game media, and to take measures against illegal acts, but also to prevent erroneous determination due to jamming of game media in a plurality of winning holes. it can.

A gaming machine according to claim 2 of the present invention is the gaming machine according to claim 1,
The game medium (game ball) that is disposed below the second detection means (first winning confirmation switch 14b, second winning confirmation switch 15b, and third winning confirmation switch 23a) and passes through the second detection means is collected. A recovery road surface (bottom surface 1501) to be
A direction change portion (a discharge direction change surface 1453a, which is provided between the second detection means and the recovery road surface so as to be able to change the flow direction of the game medium by contacting the game medium that has passed through the second detection means. 1455a),
It is characterized by that.
According to this feature, the direction of flow of the game medium that has passed through the second detection means is changed by the direction changing unit, so that the game medium that has fallen and jumped up on the collection road surface is detected again by the second detection means. It is prevented.

A gaming machine according to claim 3 of the present invention is the gaming machine according to claim 1 or 2,
Normal winning ports (winning ports 29a to 29d) provided separately from the plurality of winning ports (first starting winning port 13a, second starting winning port 13b, large winning port 23b);
Normal winning detection means (winning port switches 30a, 30b) for detecting the game medium won in the normal winning port;
Payout control execution means (for example, a part for executing step S32 in the game control microcomputer 560) for performing control for paying out the prize game medium as a prize based on detection of the game medium by the normal winning detection means. Comprising
It is characterized by that.
According to this feature, since the detection means for determining an error is not provided in the normal winning opening which is not likely to be fraudulent, the manufacturing cost of the gaming machine can be reduced.

A gaming machine according to claim 4 of the present invention is the gaming machine according to any one of claims 1 to 3,
A large winning device (special variable winning ball device 20) that constitutes a large winning port (23b) among the plurality of winning ports;
The big prize device is
A movable member (opening / closing plate 1406) that is movable between an open state in which a game medium can win a prize winning opening and a closed state in which a prize cannot be won based on the fact that a predetermined condition is satisfied (controlled to a big hit gaming state). )When,
Electromagnetic drive means (solenoid 21) for driving the movable member,
The detection method of the first detection means (count switch 23) for detecting a game medium (game ball) won in the big prize opening is an electromagnetic type (proximity switch),
The first detection means and the electromagnetic drive means are arranged separately on both sides of the movable member (see FIG. 30B).
It is characterized by that.
According to this feature, it is possible to prevent erroneous detection of the electromagnetic detection means due to the electromagnetic waves of the electromagnetic drive means, and it is possible to efficiently arrange both the electromagnetic detection means and the electromagnetic drive means.

A gaming machine according to claim 5 of the present invention is the gaming machine according to any one of claims 1 to 4,
A large winning device (special variable winning ball device 20) that constitutes a large winning port (23b) among the plurality of winning ports;
The big prize device is
A movable member (opening / closing plate 1406) that is movable between an open state in which a game medium can win a prize winning opening and a closed state in which a prize cannot be won based on the fact that a predetermined condition is satisfied (controlled to a big hit gaming state). )When,
Drive means (solenoid 21) for driving the movable member;
A link member (transmission) which is provided so as to be movable up and down around a predetermined rotation axis (1427) and moves up and down in accordance with the drive of the drive means. Member 1422);
The link member is supported so as to be movable up and down, and a support member (large winning passage wall 1402) formed so as to be fitted into an attachment opening formed in the game board,
The link member is formed such that a dimension in the thickness width direction of the game board is shorter than a thickness width dimension of the game board (see FIG. 33C),
The support member is formed with an opening (1428) capable of accommodating at least a part of the link member in the closed position or the open position (see FIG. 33C).
It is characterized by that.
According to this feature, it is possible to avoid an increase in the size of the winning device, and since the opening is closed by fitting the support member to the mounting opening, the improper member or the like can be entered from the opening and moved. It is possible to prevent an illegal act such as illegally opening the member.

It is the front view which looked at the pachinko game machine from the front. It is a rear view which shows a game machine. (A) is a 1st start winning opening, (b) is a 2nd starting winning opening, (c) is explanatory drawing which shows the specific example of the cross-sectional structure in a big winning opening. It is a circuit diagram for demonstrating the system of the detection means which can detect a game ball. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram showing a circuit configuration of the main board and a signal line of an effect control command transmitted from the main board to the effect control board. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which a serial communication circuit transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a circuit diagram which shows the internal structure of a terminal board | substrate. It is a perspective view which shows the state which open | released the pachinko game machine. It is a rear view which shows a game board. (A) is a front view which shows a start winning unit, (b) is a rear view of (a). (A) is a top view which shows a start winning unit, (b) is a side view of (a). It is a disassembled perspective view which shows the structure of a variable winning ball apparatus. (A) is a longitudinal cross-sectional view which shows the open state of a variable winning ball apparatus, (b) is AA sectional drawing of (a). (A) is a longitudinal cross-sectional view which shows the closed state of a variable winning ball apparatus, (b) is A'-A 'sectional drawing of (a). (A) is a front view which shows a special variable winning ball apparatus, (b) is a rear view of (a). (A) is a top view which shows a special variable winning ball apparatus, (b) is a side view of (a). 30A is a sectional view taken along line BB in FIG. 30A, FIG. 30B is a sectional view taken along line CC in FIG. 30A, and FIG. 30C is a sectional view taken along line DD in FIG. FIG. (A) is an exploded perspective view showing the structure of the special variable winning ball apparatus. It is a principal part enlarged view which shows the back surface of a game board. It is EE sectional drawing of FIG. It is FF sectional drawing of FIG. It is GG sectional drawing of FIG. It is a front view which shows a fluctuation | variation display control unit. (A) is a figure which shows the state in which the accessory provided in the fluctuation | variation display control unit performed the raising operation | movement, (b) is a figure which shows the state in which the accessory released operation | movement. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 10 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a winning ball operation cannot be executed immediately. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing for demonstrating a switch normal / abnormality check process. It is explanatory drawing which shows the case where a game ball raise | generates the ball clogged state in the start winning opening. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the main process which CPU for production control performs. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the modification of the physical structure of a terminal board | substrate. It is explanatory drawing which shows the cross-section of the site | part to which the terminal board | substrate of a cover member is attached.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol (effect symbol). The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 variably displays the effect symbol as a decoration (effect) symbol during the variable display period of the special symbol by the first special symbol indicator 8a or the second special symbol indicator 8b. The effect display device 9 that performs variable display of effect symbols is controlled by an effect control microcomputer mounted on the effect control board.

  A first special symbol display (first variable display means) 8a for variably displaying a first special symbol as first identification information is provided at a lower right position on the game board 6. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. A second special symbol display (second variable display means) 8b for variably displaying the second special symbol as the second identification information is provided above the first special symbol display 8a. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. The first special symbol display 8a and the second special symbol display 8b each variably display a number (or a two-digit symbol) from 0 to 99 using, for example, two 7-segment LEDs. It may be configured.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b may be collectively referred to as a special symbol indicator.

  The variable display of the first special symbol is a variable display start condition (for example, after the game ball has won the first start winning opening 13a) after the first start condition, which is the variable display execution condition, is established (for example, When the number of reserved memories is not 0, the variable display of the first special symbol is not executed, and the variable display is started based on the fact that the big hit game is not executed) When time (fluctuation time) elapses, a display result (stop symbol) is derived and displayed. In addition, the variable display of the second special symbol is a variable display start condition (for example, that the game ball has won the second start winning opening 13b) after the second start condition, which is a variable display execution condition, is satisfied (for example, For example, when the number of reserved memories is not 0, the variable display of the second special symbol is not executed, and the big hit game is not executed) is started, When the variable display time (variation time) elapses, the display result (stop symbol) is derived and displayed. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  The effect display device 9 is for decoration (effect) during the variable display time of the first special symbol on the first special symbol display 8a and during the variable display time of the second special symbol on the second special symbol display 8b. Display design (also referred to as a decorative design) as a design. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Synchronous means that the start time and end time of variable display are substantially the same (may be exactly the same) and the variable display period is substantially the same (may be exactly the same). In addition, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 causes the jackpot to be recalled. The combination of is stopped and displayed.

  Below the effect display device 9, a winning device having a first start winning port 13a is provided. The game ball won in the first start winning opening 13a is guided to the back of the game board 6, and is detected by the first start opening switch 14a (for example, proximity switch) and the first winning confirmation switch 14b (for example, photo sensor). The

  A variable winning ball device 15 having a second starting winning port 13b through which a game ball can be won is provided below the winning device having the first starting winning port (first starting port) 13a. The game ball that has won the second start winning opening (second start opening) 13b is guided to the back of the game board 6 and detected by the second start opening switch 15a and the winning confirmation switch 15b. The variable winning ball device 15 is opened by a solenoid 16. When the variable winning ball apparatus 15 is in the open state, the game ball can be won in the second start winning opening 13b (it is easy to start winning), which is advantageous for the player. In a state where the variable winning ball device 15 is in the open state, it is easier for the game ball to win the second starting winning port 13b than the first starting winning port 13a. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 13b. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Further, as will be described later, whether or not an abnormal winning has occurred is determined based on the detection results of the first start opening switch 14a and the first winning confirmation switch 14b and the detection results of the second starting opening switch 15a and the second winning confirmation switch 15b. A security signal is externally output based on the determination and the occurrence of an abnormal winning. The variable winning ball device 15 is opened by a solenoid 16.

  Hereinafter, the first start winning opening 13a and the second start winning opening 13b may be collectively referred to as a start winning opening or a starting opening. Further, in the present embodiment, the game board 6 in a state in which the winning device having the first starting winning port 13a and the variable winning ball device 15 having the second starting winning port 13b are integrated into the starting winning unit 12. However, the game device 6 may be provided with the winning device and the variable winning ball device 15 separately.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 13b. The first start winning opening 13a is provided directly below the effect display device 9, but the interval between the lower end of the effect display device 9 and the first start winning port 13a is further reduced, or the first start winning port is set. The winning rate of the second starting winning port 13b is such that the nails are densely arranged around 13a, or the nail arrangement around the first starting winning port 13a is difficult to guide the game ball to the first starting winning port 13a. You may make it make higher than the winning rate of the 1st start winning opening 13a.

  In the upper part of the second special symbol display 8b, the number of effective winning balls that have entered the first start winning opening 13a, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol reserved memory display section and the first special symbol reserved memory display section are provided separately, and a second special special display for displaying the number of effective winning balls that have entered the second start winning slot 13b, that is, the second reserved memory number. For example, a special symbol storage memory display unit 18 including a 7-segment LED provided with a symbol storage memory display unit is provided. The first special symbol reserved memory display unit displays up to four first reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one. The second special symbol reserved memory display unit displays up to four second reserved memory numbers in the order of winning, and increases the number of indicators that are turned on by 1 each time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one. In this example, the upper limit number (up to 4) is provided for the starting memory number by winning at the first starting winning port 13a and the starting memory number by winning at the second starting winning port 13b. May be four or more.

  On the display screen of the effect display device 9, a first reserved memory display unit (not shown) for displaying the first reserved memory number and a second reserved memory display unit (not shown) for displaying the second reserved memory number. And are provided. In addition, you may make it provide the area | region (sum total pending | holding memory display part) which displays the total number (sum total pending memory count) which is the sum total of the 1st pending memory count and the 2nd pending memory count. As described above, if the summation pending storage display section for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition.

  In this embodiment, as shown in FIG. 1, the variable winning ball device 15 that opens and closes only the second starting winning opening 13b is provided. However, the first starting winning opening 13a and the second starting winning opening 13a are provided. Any of the start winning openings 13b may be provided with a variable winning ball apparatus that performs an opening / closing operation.

  Below the variable winning ball apparatus 15, there is provided a special variable winning ball apparatus 20 using an opening / closing plate 1406 (see FIG. 30A) that is controlled to be opened by the solenoid 21 in a specific gaming state (big hit state). ing. The special variable winning ball apparatus 20 is means for opening and closing the special winning opening 23b (see FIG. 30A). The winning ball that has won the special variable winning ball device 20 and led to the back of the game board 6 is detected by the count switch 23.

  The normal symbol display 10 is provided on the right side of the first special symbol display 8a. The normal symbol display 10 is composed of, for example, two lamps. When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. When the lamp on the lower side of the normal symbol display 10 is turned on and it is a win, the variable winning ball device 15 is opened for a predetermined number of times. That is, the state of the variable winning ball device 15 is a state that is advantageous from a disadvantageous state for the player when the lower lamp is turned on (a state in which a game ball can win a prize at the second start winning opening 14). ). An upper part of the special symbol storage memory display 18 is provided with a normal symbol storage memory display 41 having four display portions (for example, four segments among seven segment LEDs) for displaying the number of winning balls that have passed through the gate 32. It has been. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of display units to be turned on by one. Then, each time the variable display of the normal symbol display 10 is started, the number of display units that are lit is reduced by one.

  In addition, the normal symbol storage memory display 41 composed of 7-segment LEDs has four display units (segments) for displaying the number of winning balls that have passed through the gate 32 and, for example, the number of times the special variable winning ball device 20 is opened at the time of a big hit. There are two display units (segments) that indicate (the number of big hits) and two display units (segments) that indicate the gaming state, but these display units are separate from the normal symbol hold storage display unit. You may comprise. Further, the normal symbol display 10 may be configured by a segment LED or the like that can variably display a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  The game board 6 is provided with a plurality of winning holes 29a to 29d. The winning of the game balls to the winning holes 29a, 29c, 29d is detected by the winning hole switch 30a, and the winning of the game balls to the winning hole 29b is won. Detected by mouth switch 30b. Each of the winning ports 29a to 29d constitutes a winning area provided on the game board 6 as an area for accepting game media and allowing winning. The first start winning opening 13a, the second start winning opening 13b, and the big winning opening 23b also constitute a winning area that accepts game media and allows winning. In addition, it is good also as a structure which detects that the game ball passed the predetermined area | region (for example, gate) with a detection switch instead of the structure which detects the game ball won to each winning opening 29a-29d with a winning switch. Decorative lamps 25a blinking and displayed during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a game ball that has not won a prize is provided at the bottom. In addition, two speakers 27 that emit sound effects are provided on the left, right, top, and bottom of the outside of the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decorative member 25 provided with a decorative lamp 25a is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine. In this embodiment, the case where the light emitter provided in the gaming machine is configured by using a lamp or an LED is shown. However, the present invention is not limited to the mode shown in this embodiment. You may make it comprise all the provided light-emitting bodies using LED.

  Although not shown in FIGS. 1 and 2, a prize ball lamp that is turned on during the prize ball payout is provided in the vicinity of the left frame lamp 28b, and a supply ball is provided in the vicinity of the top frame lamp 28a. There is a ball-out lamp that illuminates when it runs out. Note that the award ball lamp and the out-of-ball lamp are controlled to be turned on by the effect control microcomputer mounted on the effect control board when the award ball is being paid out or when the out-of-ball is detected. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the first start winning port 13a and is detected by the first start port switch 14a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the first special symbol display 8a starts variable display (variation) of the first special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. That is, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13a. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning port 13b and is detected by the second start port switch 15a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol (decoration symbol). Is done. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 13b. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  The variable display of the first special symbol on the first special symbol display 8a and the variable display of the second special symbol on the second special symbol display 8b are stopped when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. The opening of the special variable winning ball apparatus 20 is allowed until the last round of the determined number of rounds (for example, up to 15 rounds).

  When the first special symbol on the first special symbol indicator 8a at the time of stoppage or the second special symbol on the second special symbol indicator 8b at the time of stoppage is a jackpot symbol (probability variable symbol) with probability variation, The probability of a big hit increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as viewed from the back. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, etc. Various boards such as a game control board (main board) 31 on which is mounted, an audio output board 70, a lamp driver board 35, and a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted. ing. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, there are provided a power supply board 910 and a touch sensor board (not shown) on which power supply circuits for creating various power supply voltages such as DC30V, DC21V, DC12V and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out the game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to the upper plate or the lower plate. The number-of-payout counting switch 301 (see FIG. 6) for counting prize balls and rental balls is also configured as a part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 has, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (a start port signal shown in FIG. 74, one signal for determining the number of symbols, one jackpot signal, two jackpot signals, three jackpot signals, hour An information output terminal for externally outputting a short signal, security signal, prize ball signal 1, gaming machine error state signal) is provided. Note that the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1, and a door indicating that the gaming frame is open from the information output terminal instead of the gaming machine error status signal. An open signal or the like may be output.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. When the ball break switch 187 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  3A is a specific example of a cross-sectional structure in the first start winning opening, FIG. 3B is a second starting winning opening, FIG. 3C is a specific example of the cross-sectional structure in the large winning opening, and FIG. It is explanatory drawing which shows the specific example of an internal cross-section. As shown in FIG. 3A, in the first start winning opening 13a, two switches (a first start opening switch 14a and a first winning confirmation switch 14b) capable of detecting a game ball won in the start winning opening. Is provided. In this embodiment, a first start opening switch 14a and a first winning confirmation switch 14b are vertically arranged in the first start winning opening 13a (in this example, the first start opening switch 14a is on the upper side). And the first winning confirmation switch 14b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the first start winning opening 13a is guided to the back of the game board 6, first detected by the first start opening switch 14a, and then by the first winning confirmation switch 14b. Detected.

  Further, as shown in FIG. 3B, in the second start winning opening 13b, there are two switches (a second start opening switch 15a and a second winning confirmation switch) capable of detecting a game ball won in the start winning opening. 15b) is provided. In this embodiment, the second start opening switch 15a and the second winning confirmation switch 15b are vertically arranged in the second start winning opening 14a (in this example, the second start opening switch 15a is on the upper side). And the second winning confirmation switch 15b is arranged on the lower side). Therefore, in this embodiment, the game ball won in the second start winning opening 14a is guided to the back of the game board 6, first detected by the second start opening switch 15a, and then by the second winning confirmation switch 15b. Detected.

  In addition, as shown in FIG. 3C, in the special winning opening 23b, there are two switches (a count switch 23 and a third winning confirmation switch 23a) capable of detecting a game ball won in the special winning opening 23b. Is provided. In this embodiment, the count switch 23 and the third winning confirmation switch 23a are arranged up and down in the big winning opening 23b (in this example, the counting switch 23 is arranged on the upper side, and the third winning confirmation switch 23a is arranged on the lower side). Therefore, in this embodiment, the game ball won in the big winning opening 23b is guided to the back of the game board 6, first detected by the count switch 23, and then detected by the third winning confirmation switch 23a.

  Also, different detection system switches are used as the first start opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, the count switch 23 and the third winning confirmation switch 23a. It is done. In this embodiment, proximity switches are used as the first start opening switch 14a, the second start opening switch 15a, and the count switch 23, and the first winning confirmation switch 14b, the second winning confirmation switch 15b, and the third winning confirmation switch 23a are used. The case where a photo sensor is used is shown.

  Further, in this embodiment, as will be described later, based on the detection of the game ball by the first start port switch 14a, the first special symbol variation display is started and the prize ball payout is executed. Further, based on the fact that the game ball is detected by the second start port switch 15a, the display of the variation of the second special symbol is started, and a prize ball payout is executed. Also, based on the fact that the game ball is detected by the count switch 23, a prize ball payout is executed. Further, as will be described later, it is determined whether or not an abnormal winning has occurred based on the detection result of the first winning confirmation switch 14b in addition to the detection result by the first start opening switch 14a, and the occurrence of the abnormal winning is detected. A security signal is output externally. In addition to the detection result of the second start opening switch 15a, the presence / absence of an abnormal winning is determined based on the detection result of the second winning confirmation switch 15b, and the security signal is generated based on the detection of the abnormal winning. Output externally. In addition to the detection result of the count switch 23, whether or not an abnormal winning has occurred is determined based on the detection result of the third winning confirmation switch 23a, and a security signal is externally output based on the detection of the abnormal winning. The Therefore, in this embodiment, the first winning confirmation switch 14b, the second winning confirmation switch 14b, and the third winning confirmation switch 23a are used only for determination of abnormal winning.

  Thus, in this embodiment, in addition to the first start opening switch 14a, the first start winning opening 13a includes the first winning confirmation switch 14b, and the second start winning opening 13b includes the second start opening switch 15a. In addition to the second winning confirmation switch 15b, the large winning opening 23b is provided with a third winning confirmation switch 23a in addition to the count switch 23. The first start winning opening 13a, the second starting winning opening 13b, and the count switch 23 are configured using proximity switches, and the first winning check switch 14b, the second winning check switch 15b, and the third winning check switch 23a are photosensors. However, the detection method of the first start opening switch 14a and the first winning confirmation switch 14b, the second starting opening switch 15a and the second winning confirmation switch 15b, the count switch 23 and the third winning confirmation switch 23a is as follows. For example, if the detection method is different between the first and second start port switches 14a and 15a and the count switch 23 and the first to third winning check switches 14b, 15b and 23a, not limited to those shown in the embodiment, Conversely, photosensors are used as the first and second start port switches 14a and 15a and the count switch 23, and Winning confirmation switch 14b, 15b, may be used proximity switch as 23a. In this case, based on the detection results of the first and second start port switches 14a and 15a and the count switch 23, which are photosensors, special symbol variation display and prize ball payout processing are executed, and the first to third winning prizes which are proximity switches. The detection results of the confirmation switches 14b, 15b, and 23a are used only for the determination of abnormal winning of the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23. For example, instead of a proximity switch or an optical photosensor that is an electromagnetic switch, the first and second start port switches 14a and 15a and the count switch 23 or the first to third winning confirmation switches 14b, 15b, and 23a are used. Alternatively, a mechanical switch (such as a micro switch) may be used.

  In this embodiment, the first and second start port switches 14a and 15a and the count switch 23, which are used as triggers for the special symbol variation display and the prize ball payout process, are used for the determination of abnormal winning. The three winning confirmation switches 14b, 15b and 23a are provided on the upstream side, but may be provided on the downstream side of the switch used for determining the abnormal winning.

  FIG. 4 is a circuit diagram for explaining a method of detection means capable of detecting a game ball. In FIG. 4, the first start opening switch 14a and the first winning confirmation switch 14b will be described as an example. However, the second starting opening switch 15a and the third winning confirmation switch 14b, the count switch 23, and the third winning confirmation switch 23a are described. Is the same as the first start opening switch 14a and the first winning confirmation switch 14b, and detailed description thereof is omitted here.

  FIG. 4A shows a first start port switch 14a (second start port switch 15a) that is a proximity switch. A + 12V power supply voltage is supplied from the power supply substrate 910 to one terminal of the first start port switch 14a (second start port switch 15a, count switch 23). A detection signal that is the voltage level of the other terminal of the first start port switch 14 a is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer. A resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the first start port switch 14a.

  When a metal game ball passes through a hole provided in the first start port switch 14a that is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Accordingly, the output of the first start port switch 14a becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the first starter switch 14a, the output of the first starter switch 14a is divided by + 12V by the resistance value of the coil L and the resistor R. Exceeding a threshold level that is considered high. That is, the detection signal is at a high level. Therefore, in this embodiment, the game control microcomputer can determine that the first start port switch 14a is in the OFF state if the output from the first start port switch 14a is at a high level. If the output from the start port switch 14a is at a low level, it can be determined that the first start port switch 14a is in an ON state (that is, the output of the first start port switch 14a has a negative logic). The detection signal level may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  FIG. 4B shows a first winning confirmation switch 14b (second winning confirmation switch 15b, third winning confirmation switch 23a) which is a photosensor. The photosensor illustrated in FIG. 4B includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. In this case, since a current flows from the collector terminal of the phototransistor 342 toward the emitter terminal, the detection signal of the photosensor is negative logic as in the proximity switch. The output side of the photosensor is connected to the main board 31, and the detection signal of the photosensor is input from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer. As with the proximity switch, the level of the detection signal may be logically inverted by an input driver circuit and then input to the game control microcomputer 560.

  The game control microcomputer can determine that the game ball has passed through the photosensor when the detection signal from the input driver circuit is at a low level.

  In this embodiment, a reflective photosensor is used as a photosensor. As shown in the upper part of FIG. 4C, a light emitting element (LED 341) and a light receiving element (phototransistor 342) are used as winning balls. The game balls that have been installed so as to face each other and the game ball blocks light from the light emitting element and the light receiving element does not detect the light, thereby detecting the game ball that has passed between the light emitting element and the light receiving element. A transmissive photosensor may be used. When a transmissive photosensor is used, as shown in the lower part of FIG. 4C, the optical axis of the light emitting element (illustrated by a black circle in FIG. 4C) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared to the case where the optical axis corresponds to the central portion of the game ball, a portion where the interval between two game balls passing through is relatively wide (the portion of “void” in FIG. 4C) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 4B, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is shifted from the center of the game ball. It is preferable to do.

  FIG. 5 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 5 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer may include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads the numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 14a or the second start port switch 15a occurs, and starts to change the special symbol and the effect symbol Sometimes it is determined whether or not to make a big hit display result as a specific display result based on the random R, that is, whether or not to make a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  Further, the game control microcomputer 560 inputs / outputs (transmits / receives) signals to / from the payout control board 37 (the payout control microcomputer 370) and the effect control board 80 (the effect control microcomputer) by serial communication. Serial communication circuit 505 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also incorporate a serial communication circuit for inputting / outputting signals to / from the game control microcomputer 560 through serial communication (the payout control microcomputer 370 includes (See FIG. 6 for the built-in serial communication circuit). The game control microcomputer 560 includes a two-channel serial communication circuit 505, and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, for serial communication with the production control microcomputer 100, a signal is output only from the game control microcomputer 560 to the production control microcomputer, and the production control microcomputer 100 No signal is output to the game control microcomputer 560. Note that the communication between the game control microcomputer 560 and the effect control microcomputer is not limited to the serial communication configuration, and may be configured to perform parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the pending storage number counter) and data indicating the number of unpaid prize balls (specifically, prize balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board that is backed up by a backup power supply (for example, the main board 31). Further, a clear signal (see FIG. 5) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Further, the gate switch 32a, the first start opening switch 14a, the first winning confirmation switch 14b, the second starting opening switch 15a, the second winning confirmation switch 15b, the count switch 23, the third winning confirmation switch 23a, and each winning opening switch 30a. , 30b, an input driver circuit 58 for supplying a detection signal to the basic circuit 53 is also mounted on the main board 31, and the basic circuit 53 includes a solenoid 16 for opening and closing the variable winning ball apparatus 15 and a solenoid 21 for opening and closing the special variable winning ball apparatus. An output circuit 59 that is driven in accordance with a command from the system is also mounted on the main board 31, and a system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and jackpot information indicating the occurrence of a jackpot gaming state The information output signal such as Information output circuit 64 for outputting to an external device such as a computer is also mounted on the main substrate 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 6 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 6, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. The predetermined payout condition is that a game ball has won a prize area (ordinary prize openings 29a to 29d, large prize opening 23b, first start prize opening 13a, second start prize opening 13b) provided in the game area. It is established when a rental ball request is made. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Further, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560. It should be noted that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described in detail with reference to FIGS.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. The interface board (relay board) 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are given to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 7 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 7, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control microcomputer 101 including an effect control CPU 101a and a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads the image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 8 is a block diagram showing a circuit configuration of the main board 31 and signal lines of an effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. 8, in this embodiment, the game control microcomputer 560 mounted on the main board 31 uses a single signal line for transmission of an effect control signal to produce an effect control command (effect control signal). Is transmitted to the effect control board 80.

  As shown in FIG. 8, wiring from the first start opening switch 14a, the first winning check switch 14b, the second starting opening switch 15a, and the second winning check switch 15b is connected to the main board 31. In addition, the main board 31 has various counts for detecting a winning of a game ball to the other winning opening, such as the count switch 23 of the special variable winning ball apparatus 20 that is the big winning opening 23b, the third winning confirmation switch 23a, and the like. Wirings from the switches 32a, 30a, 30b are also connected. Further, the main board 31 is connected to a solenoid 16 that opens and closes the variable winning ball device 15 and wirings to the solenoid 21 that opens and closes the special variable winning ball device 20.

  The main board 31 includes a game control microcomputer 560, an input driver circuit 58, and an output circuit 59. The game control microcomputer 560 operates in accordance with a clock circuit 501, a reset controller 502 that functions as a system reset means, a random number circuit 503a, 503b, a ROM 54 that stores a game control program, a RAM 55 that is used as a work memory, and a program. CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal by timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with microcomputers provided in payout control board 37 and effect control board 80, and I / O An O port unit 57 is incorporated.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case where the serial communication circuit 505 is used for communication will be described, the serial communication circuit 505 may perform serial communication with another microcomputer included in the board on which the microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK having a predetermined period generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503a and 503b. When a low level signal is input for a predetermined period, the reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b to reset the game control microcomputer 560.

  In this embodiment, as shown in FIG. 8, the game control microcomputer 560 is equipped with two random number circuits 503a and 503b having different ranges of random value values that can be generated. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo-random number. The 12-bit random number circuit 503a has a function of generating a random number having a value within a range that can be generated by 12 bits (that is, a range from 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo-random number. The 16-bit random number circuit 503b has a function of generating a random number having a value in a range that can be generated in 16 bits (that is, a range from 0 to 65535). In this embodiment, the case where the game control microcomputer 560 includes two random number circuits is described. However, the game control microcomputer 560 may include three or more random number circuits. In this embodiment, when the 12-bit random number circuit 503a and the 16-bit random number circuit 503b are comprehensively expressed, or when indicating either the 12-bit random number circuit 503a or the 16-bit random number circuit 503b, This is called a random number circuit 503.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, Perform serial communication. The serial communication circuit 505 includes a transmission unit that transmits various data (for example, a prize ball number command and an effect control command) to the microcomputer of each control board, and various data (for example, a prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 9 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 505. FIG. 10 is a block diagram illustrating a configuration example of a receiving unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception. Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 9, the transmission unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, and a transmission data register 710. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 10, the receiving unit of the serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 505, the transmission unit and the reception unit are actually configured using a common circuit. As described above, the serial communication circuit 505 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 505.

  First, the data format of data transmitted and received by the serial communication circuit 505 with the microcomputer mounted on each control board will be described. FIG. 11 is an explanatory diagram showing an example of a data format of data transmitted / received by the serial communication circuit 505 to / from a microcomputer mounted on each control board. As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted / received by the serial communication circuit 505 can be set to either 8 bits or 9 bits by performing an initial setting in a serial communication circuit setting process described later. FIG. 11A shows an example of a data format when the data length is set to 8 bits. FIG. 11B shows an example of a data format when the data length is set to 9 bits.

  As shown in FIG. 11, the data format of data transmitted and received by the serial communication circuit 505 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 505 transmits / receives data first from the least significant bit (bit 0) of the transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 using equation (1).
Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 12 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 13A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 13A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 13B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 13B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 13B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of control register A707, setting data for setting a wake-up method for waking up a receiver circuit in the standby state (reception unit of serial communication circuit 505). Is set. As shown in FIG. 13 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 13B, by setting bit 2 to “0”, a detection method for detecting an idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether or not to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 13B, by setting bit 1 to “0”, the parity function is set not to be used. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 13B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 14A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 505. In this embodiment, whether the interrupt request from the serial communication circuit 505 is permitted or prohibited is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B708. As shown in FIG. 14A, the control register B708 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 14B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 14B, in the bit 7 (bit name “TIE”) of the control register B708, setting data indicating whether or not a transmission interrupt request that is an interrupt request to be performed at the time of data transmission is permitted is set. Is done. As shown in FIG. 14B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 14B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request when data is received, is permitted. As shown in FIG. 14B, the reception interrupt request is set to be prohibited by setting bit 5 to “0”. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B708 is set with setting data indicating whether or not an idle line interrupt request that is an interrupt request to be performed when an idle line of received data is detected is permitted. As shown in FIG. 14B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether to use the transmission circuit (the transmission unit of the serial communication circuit 505) is set. As shown in FIG. 14B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 14B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 14B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 505 causes the microcomputer on which the control board (the payout control board 37 and the effect control board 80) is mounted with a break code (for example, a signal including “0” continuously). Send to.

  FIG. 15A is an explanatory diagram illustrating an example of the status register A705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 15A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bit 0 to bit 7 of the status register A705, it is invalidated.

  In this embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 15B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 15B, transmission data indicating that transmission data is not stored in transmission data register 710 (transmission data empty) in bit 7 (bit name “TDRE”) of status register A705. Stores an empty flag. As shown in FIG. 15B, when “0” is stored in the bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S5211, S52305, transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed. As shown in FIG. 15B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 505 is not transmitted. Indicates that transmission has not been completed. Further, when “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and transmission of transmission data from the serial communication circuit 505 has been completed. It shows that. When the command storage area is in the ring buffer format, if “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set as will be described later, the serial communication circuit 505 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 15B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in steps S5221, S52401, and S52501, it is determined that the command is received on condition that “0” is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when reception data is read from reception data register 711 by game control microcomputer 560. If the bit 5 (RDRF) of the status register A 705 is not automatically cleared when the received data is read, the game control microcomputer 560 reads the received data from the received data register 711. Every time reception data is read, it is necessary to perform processing for clearing bit 5 (RDRF) of the status register A705.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 505 sets the bit 5 of the status register A 705 to “1” when reception data full is detected, and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 15B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 505 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 15B, when “0” is stored in bit 3, it indicates that the receiving circuit is not detecting an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 505 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 15B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise generated in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 15B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 505 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 15B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 16A is an explanatory diagram illustrating an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B 706. As shown in FIG. 16B, the status register B706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if a control for writing a value to bits 1 to 7 of the status register A 705 is performed, the value is invalid and all the values read from the bits 1 to 7 are “0 (= 0000b)”.

  FIG. 16B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 16B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 16B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 505 detects the start bit, it assumes that reception of received data has started, and sets bit 0 of the status register B 706 to “1”.

  FIG. 17A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register for setting whether to permit an interrupt request when a communication error occurs in the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 17A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if control is performed to write a value to bits 4 and 5 of the control register C709, it is invalid, and all values read from bits 4 and 5 are “0 (= 0000b)”.

  FIG. 17B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 17B, bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the ninth bit of transmission data when the data length is set to nine bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 17B, by setting bit 3 to “0”, an overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 17B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 17B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 17B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 18 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 505. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 18, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when the bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where the reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the interrupt control circuit 714 interrupts the CPU 56 with the occurrence of the communication error as a cause of interruption when detecting a parity error. Make a request.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display results of the first special symbol display unit 8a and the second special symbol display unit 8b are to be a big hit symbol. . Specifically, as shown in FIG. 19A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Further, as shown in FIG. 19B, the jackpot determination table memory 571 stores a probability change big hit determination table 571b used in the probability change state. When the big hit determination is performed using the determination table shown in FIG. 19, the probability of determining a big hit depends greatly on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 503 and the random number maximum value. Also good. Then, the CPU 56 uses the random number circuit 503 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the big hit determination table memory 571, in accordance with the display result determination program 552, and the first special You may make it determine whether the display result of the symbol display 8a and the 2nd special symbol display 8b is made a big hit symbol. By doing so, even if the type of random number circuit 503 to be used and the maximum random number value are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  In the example shown in FIG. 19, for example, in the case of the normal big hit determination table shown in FIG. 19A, determination values are assigned to four ranges of 1020 to 1059, 13360 to 13399, 34400 to 34439, and 57700 to 577739. In the case of the probability change jackpot determination table shown in FIG. 19B, the determination values are assigned to four ranges of 1020 to 1219, 13360 to 13559, 34400 to 34599, and 57700 to 57899. In each jackpot determination table, a determination value may be assigned to a series of one range.

  FIG. 20 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 20, a payout control signal (a connection signal in this example) transmitted to the payout control board 37 is output from the output port 0. Further, a solenoid (large winning opening door solenoid) 21 for opening and closing the variable winning ball apparatus 20 for opening and closing the large winning opening 23b and a solenoid (normal electric accessory solenoid) 16 for opening and closing the variable winning ball apparatus 15 are provided. The drive signal is also output from the output port 0.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 20 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Then, from the output port 1 to the external device (for example, hall computer) via the terminal board 160, a seed information output signal, that is, information related to the control (for example, start port signal, symbol determination number 1 signal, jackpot 1 signal, 2 jackpots, 3 jackpots, short time signal, security signal) are output. In this embodiment, a prize ball signal 1 (a signal that is output every time one prize ball payout is detected) or a gaming machine error status signal (a gaming machine is in an error status (in this example, a ball is out of ball). An error state or a full tank error state) is also output to the external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout or an error state of the gaming machine is detected, and a prize ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main board 31 are output via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. Is done. The prize ball signal 1 and the gaming machine error state signal input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the gaming control microcomputer 560.

  In addition, since the pachinko gaming machine 1 in this embodiment has two start winning ports, a first start winning port 13a and a second start winning port 13b, a game ball wins the first start winning port 13a. The start port 1 signal for notifying that the game ball has been won and the start port 2 signal for notifying that the game ball has won the second start winning port 13b are individually output to the outside via the terminal board 160. You may do it.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the game frame is in an open state and prize ball information output every time ten prize balls are paid out are also output to an external device via the terminal board 160. May be. In this case, on the payout control board 37 side, it is detected that the game frame is in the open state and the payout of the winning ball is detected, and a door opening signal and winning ball information are input to the main board 31. The door opening signal and prize ball information input to the main board 31 are output to the outside via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. However, it is assumed that the door opening signal and the prize ball information are branched on the main board 31 and input to the game control microcomputer 560. In this case as well, the door opening signal and prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after passing through the game control microcomputer 560 once. .

  In addition, for example, the gaming machine has two start winning ports, a first start winning port 13a and a second start winning port 13b, so that two special symbols, a first special symbol and a second special symbol, can be displayed in a variable manner. If configured, a start port 1 signal for notifying the first start winning port 13a that a game ball has won, and a second start winning port 13b for notifying that a game ball has won. The start port 2 signal is individually output to the outside through the terminal board 160, and the symbol determination number 2 signal is also added to the symbol determination number signal 1 as a symbol determination number signal for notifying the number of fluctuations of the special symbol. Alternatively, an external output may be made via the terminal board 160. In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 21 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 21, gate switches 32a, winning port switches 30a and 30b, magnet sensor signal 1, magnet sensor signal 2, door opening signal, and prize ball information are input to bits 0 to 7 of input port 0, respectively. Is done. In this embodiment, two magnet sensors (not shown) for detecting fraud using a magnet are provided, and detection signals from the respective magnet sensors are also input from the input port 0. . Also, the detection signal of the first start port switch 14a is input to bit 0 of the input port 1, and the detection signal of the first winning confirmation switch 14b is input to bit 1 of the input port 1, The detection signal of the second start port switch 15 a is input to bit 2, the detection signal of the second winning confirmation switch 15 b is input to bit 3 of the input port 1, and the count signal is input to bit 4 of the input port 1 The detection signal of the switch 23 is input, the detection signal of the third winning confirmation switch 23a is input to the bit 5 of the input port 1, and the power-off signal from the power supply board 910 is input to the bits 6 and 7 of the input port 1. And the detection signal of the clear switch is input.

  FIG. 22 is a circuit diagram showing the internal configuration of the terminal board 160. In the terminal board 160 shown in FIG. 22, the upper left connector CN-1 is a connector for connecting a cable for transmitting a signal from the main board 31, and the lower left connector CN1-2 is a payout control board 37. This is a connector for connecting a cable for transmitting a signal from the main board 31 via the main board 31. The right connectors CN1 to CN9 are connectors for connecting cables that transmit signals to external devices such as hall computers. The terminal board 160 is mounted with semiconductor relays (PhotoMOS relays) PC1 to PC9 as driver circuits.

  When the cable from the main board 31 is connected to the connector CN-1, various signals are input from the main board 31 (game control microcomputer 560) to the terminal board 160. Specifically, the start port signal is input to the terminal “2” of the connector CN-1, the symbol determination number 1 signal is input to the terminal “3” of the connector CN-1, and the terminal “5” of the connector CN-1 is input. 1 jackpot signal is input, 2 jackpot signals are input to terminal “6” of connector CN-1, 3 jackpot signals are input to terminal “7” of connector CN-1, and terminal “8” of connector CN-1 is input. The time reduction signal is input to “”, and the security signal is input to the terminal “9” of the connector CN-1.

  In addition, when the cable from the payout control board 37 is connected to the connector CN-2 via the main board 31, various signals from the payout control board 37 (the payout control microcomputer 370) are input to the terminal board 160. Is done. Specifically, the prize ball signal 1 is input to the terminal “2” of the connector CN-2, and the gaming machine error state signal is input to the terminal “3” of the connector CN-2.

  As shown in FIG. 22, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-1 and the connector CN-2, and the signal line branches to each of the semiconductor relays PC1 to PC1. It is connected to the input terminal “1” of the PC 9. Further, the signal lines connected to the terminals “2”, “3”, “5” to “9” of the connector CN-1 and the connectors “2” and “3” of the connector CN-2 are 1 KΩ resistances, respectively. It is connected to the input terminals “2” of the semiconductor relays PC1 to PC9 via R1 to R9. The signal lines connected to the output terminals “4” of the semiconductor relays PC1 to PC9 are connected to the terminals “1” of the connectors CN1 to CN9, respectively. The signal lines connected to the output terminals “3” of the semiconductor relays PC1 to PC9 are connected to the terminals “2” of the connectors CN1 to CN9, respectively.

  In the semiconductor relays PC1 to PC9, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light is exchanged for voltage according to the amount of light, and this voltage passes through the control circuit to charge the MOSFET gate of the output section. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relays PC1 to PC9 as described above, the signals input from the connectors CN-1 and CN-2 on the input side are transmitted to the connectors CN1 to CN9 on the output side to the external device such as a hall computer. Is output. Specifically, the start signal is output from the connector CN1, the symbol determination number 1 signal is output from the connector CN2, the jackpot signal is output from the connector CN3, the jackpot signal is output from the connector CN4, and the connector CN5 is output. Three jackpot signals are output, a time reduction signal is output from the connector CN6, a security signal is output from the connector CN7, a prize ball signal 1 is output from the connector CN8, and a gaming machine error state signal is output from the connector CN9. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN9) provided on the terminal board 160. Further, the gaming machine error status signal does not necessarily have to be output to the outside of the pachinko gaming machine 1. For example, from the connector CN9, a door opening indicating that the gaming frame is in an opened state instead of the gaming machine error status signal is opened. A signal or the like may be output.

  The security signal output from the connector CN7 is a signal indicating the security state of the gaming machine. Specifically, as described later, the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, the detection result of the second start opening switch 15a and the detection result of the second winning confirmation switch 15b, Based on the detection result of the count switch 23 and the detection result of the third winning confirmation switch 23a, it is determined that an abnormal winning has occurred in the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b. In some cases, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). With such a configuration, it is possible to recognize that the number of winnings at the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b is larger than the actual winning number using radio waves or the like. An external device such as a hall computer can recognize that an illegal act has been performed.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, when the abnormal winning is detected and the initialization process (for example, the operation of the clear switch is performed when the power to the gaming machine is turned on) A common security signal is output from the common connector CN7 of the terminal board 160 to the outside when the process (such as clearing the stored contents) is executed. This is because the initialization process is usually performed only when the game machine power is reset when the amusement store is opened, so the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, a signal for external output is configured by outputting a security signal from the common connector CN7 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b, but abnormal winning to the normal winning openings 29a to 29d is detected, and a common connector of the terminal board 160 is detected. You may comprise so that external output is possible as a security signal from CN7. In this case, for example, the normal winning holes 29a to 29d are also used as a switch for detecting the winning of the game ball, like the first starting winning hole 13a, the second starting winning hole 13b, and the big winning hole 23b. Two different types of switches (proximity switch and photo sensor) are provided, and the presence / absence of abnormal winning is determined according to the same determination method as the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b. You can do it.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN7 of the terminal board 160. You may comprise so that external output is possible. In addition, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value has exceeded the threshold value), a common terminal board 160 is used. The connector CN7 may be configured so that it can be output externally as a security signal.

  As described above, if it is configured such that abnormal winnings, abnormal magnetic errors, and abnormal radio wave errors in the special winning opening 23b can be output externally as security signals from the common connector CN7 of the terminal board 160, one signal line Even if it is connected, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In the case of detecting an abnormal winning at the big winning opening 23b, the number detected by the count switch 23 and the number detected by the third winning confirmation switch 23a are equal to or greater than a predetermined value (for example, 15). In addition to the case of determination, when the value of the special symbol process flag is not a value indicating that the jackpot game is being played (for example, when the value of the special symbol process flag is not 4 or more, see FIG. 65). Even when a game ball is detected by the count switch 23, it may be determined that an abnormal winning to the big winning opening 23b has occurred. Also, when it is determined that an abnormal winning to the big winning opening 23b has occurred based on the value of the special symbol process flag, the security signal information timer is set in the same manner as in step S127 in the switch normal / abnormal check process. The security signal may be externally output by setting a predetermined time (for example, 4 minutes).

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, detection of initialization processing, detection of abnormal winning in the first starting winning port 13a, second starting winning port 13b, or big winning port 23b, abnormal magnetic error Separate signal lines are provided for detection, detection of abnormal radio wave errors, and detection of communication errors, and an external output signal corresponding to each error is also sent from the terminal board 160 together with a security signal to an external device such as a hall computer. May be output. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  As described above, by providing the semiconductor relays PC1 to PC9 on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relays PC1 to PC9 are provided on the terminal board 160. However, other relay elements such as mechanical relays may be used instead of the semiconductor relays PC1 to PC9.

  Next, the structure of the pachinko gaming machine 1 will be described. FIG. 23 is a perspective view showing a state in which the pachinko gaming machine is opened.

  As shown in FIG. 23, the pachinko gaming machine 1 is mainly configured by an outer frame 400 formed in a vertically long rectangular frame shape, and a front frame 401 attached to the outer frame 400 so as to be openable and closable. A glass door frame 402 and a lower door frame 403 are provided on the front surface of the front frame 101 so as to be openable and closable around the left side. The outer frame 400 is formed in a rectangular frame shape from an upper plate and a lower plate made of a wooden plate material and left and right side plates made of an iron plate material. Although the left and right side plates are made of iron, they may be made of other metal materials such as aluminum.

  The front frame 401 is formed with a vertically long rectangular opening 415 at the center. Locking recesses 416a and 416b are provided on the upper left and right sides of the opening 415, and the panel retainers 417a and 417b are provided on the upper and lower sides on the right. In the state where the left end portion of the game board 6 is inserted into the locking recesses 416a and 416b as shown by the thick arrows in the figure, the right end portion is locked by the board presser fittings 417a and 417b. Can be attached to the front. Board holding springs 416c and 416d are provided in the locking recesses 416a and 416b, so that back and forth play of the game board 6 locked in the locking recesses 416a and 416b is prevented.

  The game board 6 is composed of a wooden plywood board. On the back side of the game board 6, game parts related to the game such as a variable display control unit including the effect display device 9 and the effect control board 80 are provided. A unit member 460 to be assembled is integrally attached. When the game board unit in which the game board 6 and the unit member 460 are integrally assembled is attached to the front surface of the front frame 401, the unit member 460 provided on the back surface of the game board 6 is inserted through the opening 415. Thus, it can be made to face the back side of the front frame 401.

  Next, each winning device constituting the first starting winning opening 13a, the second starting winning opening 13b, the large winning opening 23b, and the winning openings 29a to 29d, and the game ball that has flowed down (entered) into each winning opening The structure of the passage will be described with reference to FIGS. FIG. 24 is a rear view showing the game board. FIG. 25A is a front view showing a start winning unit, and FIG. 25B is a rear view of FIG. 26A is a plan view showing the start winning unit, and FIG. 26B is a side view of FIG. FIG. 27 is an exploded perspective view showing the structure of the variable winning ball apparatus. 28A is a longitudinal sectional view showing the open state of the variable winning ball apparatus, and FIG. 28B is an AA sectional view of FIG. 29A is a longitudinal sectional view showing a closed state of the variable winning ball apparatus, and FIG. 29B is a sectional view taken along line A′-A ′ of FIG. 30A is a front view showing the special variable winning ball apparatus, and FIG. 30B is a rear view of FIG. FIG. 31A is a plan view showing the special variable winning ball apparatus, and FIG. 31B is a side view of FIG. 32A is a cross-sectional view taken along the line B-B in FIG. 30A, FIG. 32B is a cross-sectional view taken along the line C-C in FIG. 30A, and FIG. It is DD sectional drawing. FIG. 33 (a) is an exploded perspective view showing the structure of the special variable winning ball apparatus. FIG. 34 is an enlarged view of a main part showing the back surface of the game board. 35 is a cross-sectional view taken along line EE in FIG. 36 is a cross-sectional view taken along line FF in FIG. 37 is a cross-sectional view taken along the line GG in FIG.

  As shown in FIG. 24, the game board 6 is attached with a decoration member or an accessory (not shown) disposed on the right side of the effect display device 9 when the effect display device 9 and the game board 6 are viewed from the front. A first opening 451, a second opening 452 to which a start winning unit 12 including a winning device and a variable winning ball device 15 is attached, a third opening 453 to which a special variable winning ball device 20 is attached, and a decoration lamp 25 are provided. A fourth opening 454 to which a decorative member (not shown) is attached and a fifth opening 455 constituting the out port 26 are respectively formed, and the second opening 452 and the third opening 453 are positioned below the first opening 451. Are formed vertically.

  First, the start winning unit 12 will be described with reference to FIGS.

  As shown in FIGS. 25 to 27, the start winning unit 12 is attached from the front side (game area 7) side of the game board 6 to the second opening 452 and attached from the back side of the game board 6. The start winning path member 1301 is mainly configured by being attached to and integrated with the back of the main body 1300 with the game board 6 interposed therebetween.

  The main body 1300 has a generally fan-shaped mounting plate 1302 attached to the front surface of the game board 6 with screws (not shown) and a top surface of the mounting plate 1302 that protrudes from the front surface of the mounting plate 1302 and constitutes the first start winning opening 13a. The first ball receiving portion 1303 formed in the shape of a box having an opening, and the second ball receiving portion 1304 formed below the first ball receiving portion 1303 on the front surface of the mounting plate 1302 and constituting the second start winning opening 13b. And comprising. From the first ball receiving portion 1303, a guide path 1305 for guiding the game ball that has entered the first start winning opening 13a to the back side of the game board 6 is extended toward the back side. The second ball receiving portion 1304 is provided with a pair of left and right opening / closing blades 1306a and 1306b (opening / closing pieces) so as to be rotatable inside, and is opened and closed by driving a solenoid 16 described later. The opening formed in the mounting plate 1302, that is, the game ball that has entered the second start winning opening 13b is formed so as to be guided to the back side.

  On the back surface of the mounting plate 1302 in the main body 1300, a later-described link mechanism 1307 that opens and closes the opening and closing blades 1306a and 1306b by driving the solenoid 16 as driving means, and a game ball that has entered the second start winning opening 13b are guided. A guide path 1308 (see FIG. 28A) and a cylindrical support member 1309 provided inside are attached, and are accommodated in the second opening 452 when the main body 1300 is attached to the game board 6. It has come to be.

  As shown in FIGS. 27 and 28, the left and right opening / closing blades 1306a and 1306b are formed in a substantially triangular prism shape imitating a petal of a tulip. A rotating shaft 1310 (see FIG. 28A) facing in the front-rear direction protrudes rearward from each predetermined position on the lower back surface, and the rotating shaft 1310 is pivotally supported by the mounting plate 1302. Then, the second start winning opening 13b is closed in the vertical direction around the rotation shaft 1310, that is, a closed position where the game ball does not enter (closed state, see FIG. 29B), and the closed position. The second start winning opening 13b is tilted outward from the first position, that is, it is provided so as to be rotatable between an open position where the ball can easily enter (open state, see FIG. 28B).

  Inside these open / close blades 1306a and 1306b, flat ball receiving surfaces 1311 and 1311 are formed, which are inclined slightly downward from the outside toward the center in the open position, and the ball receiving surfaces 1311 and 1311 in the open position. The ball that has fallen upward is guided toward the center, and the ball receiving surfaces 1311 and 1311 face each other in the closed position with a width dimension separation slightly larger than the diameter of the game ball. Are arranged as follows.

  Therefore, the sphere guided toward the center by the ball receiving surfaces 1311 and 1311 in the open position falls into the gap formed between the both opening and closing blades 1306a and 1306b and is guided toward the back side, and is attached to the mounting plate 1302. It passes through the formed opening, that is, the second start winning opening 13b and flows into the support member 1309 on the back side.

  In addition, linkage pins 1312a and 1312b project rearwardly at eccentric positions eccentric from the rotation shaft 1310 on the back surfaces of the opening and closing blades 1306a and 1306b. The tips of the linkage pins 1312a and 1312b extend through the mounting plate 1302 into the support member 1309 and are linked to a transmission member 1320, which will be described later. The opening and closing blades 1306a and 1312b are linked to the rotation of the transmission member 1320. 1306b opens and closes.

  Next, the link mechanism 1307 will be described with reference to FIGS. First, the support member 1309 is formed in a cylindrical shape from a transparent synthetic resin material that can be seen through, and is attached to the back surface of the attachment plate 1302. In addition, the transmission member 1320 is rotatably supported in a state of being accommodated therein, and the plunger 16a of the solenoid 16 is accommodated, and a game ball that has entered the interior through the second start winning opening 13b is accommodated on the bottom surface. A guide passage 1308 that guides toward the back side is formed.

  In the left and right side walls of the support member 1309, a bearing long hole 1313 (see FIG. 26 (FIG. 26)) supports a rotation shaft 1324 of a transmission member 1320, which will be described later, so as to be rotatable and movable in the front-rear direction. b) is formed in the front-rear direction, and a guide groove 1314 (see FIG. 26B) for moving and guiding the guide pin 1326 of the transmission member 1320 is formed thereabove. The guide groove 1314 includes an arc groove portion formed in an arc shape with the bearing long hole 1313 as a center, and a linear straight groove portion continuously provided forward from the front end of the arc groove portion.

  When the rotation shaft 1324 is located at the rear end (rotation position) of the bearing elongated hole 1313, the transmission member 1320 has a closed posture (closed state) in which the open / close blades 1306a and 1306b are in the closed position (closed state) (FIG. a)) and an open posture (see FIG. 28A) in which the open / close blades 1306a and 1306b are in the open position (open state). That is, when the rotation shaft 1324 is located at the rear end (rotation position) of the bearing long hole 1313, the first direction for rotating the opening / closing blades 1306a, 1306b from the open position toward the closed position, and the opening / closing When the blades 1306a and 1306b are rotatably supported in the second direction in which the blades 1306a and 1306b are rotated from the closed position toward the open position, and the rotation shaft 1324 is positioned at the front end of the bearing long hole 1313, The rotation in the first direction and the second direction is restricted by the contact between the guide pin 1326 and the linear groove portion, and is supported so as to be movable only in the front-rear direction (the forward and backward direction of the plunger 16a).

  The transmission member 1320 is made of a synthetic resin material, and is arranged on the left linkage arm 1321a linked to the opening / closing blade 1306a, the right linkage arm 1321b linked to the opening / closing blade 1306b, spaced from the linkage arm 1321a, The connecting arm 1322 is a connecting member that connects the upper portions of the pair of left and right linkage arms 1321a and 1321b.

  The left and right linking arms 1321a and 1321b are respectively provided with rotation shafts 1324 that protrude in the left-right direction on the outer surfaces of the left and right linking arms 1321a and 1321b. A linkage pin locking portion 1325 is formed. Further, on both left and right ends of the connecting arm 1322, guide pins 1326 that are slidably fitted in the above-described guide grooves 1314 and project in the left-right direction are projected outward. The guide pin 1326 is disposed at an eccentric position that is eccentric from the rotation shaft 1324 that is the rotation center of the transmission member 1320, and moves and guides the linkage pin locking portion 1325 in the vertical direction.

  The connecting arm 1322 is locked with a connecting arm locking member 1330 formed in a downward bifurcated shape attached to the tip of the plunger 16 a of the solenoid 16 disposed above the connecting arm 1322. As the connecting arm locking member 1330 is locked to the connecting arm 1322, the connecting arm 1322 that rotates about the rotating shaft 1324 is moved back and forth and up and down according to the back and forth movement of the plunger 16a. The

  The solenoid 16 includes a main body portion, a plunger 16a that is detachably fitted to the main body portion, and a coil spring 16b that biases the plunger 16a to a protruding position when the solenoid 16 is in a non-excited state (off state). In the excited state (on state) of the solenoid 16, the plunger 16a is moved to the retracted position against the urging force of the coil spring 16b.

  Next, based on FIG.28 and FIG.29, the interlocking | linkage state of the solenoid 16, the opening-and-closing blade | wing 1306a, 1306b, and the transmission member 1320 and its effect | action are demonstrated.

  First, as shown in FIG. 29, when the solenoid 16 is in a non-excited state (off state), the plunger 16a is located at the protruding position by the biasing force of the coil spring 16b. At this time, the transmission member 1320 is in a closed posture in which the opening / closing blades 1306a and 1306b are in the closed position (closed state), and the connecting arm 1322 is urged forward by the connecting arm locking member 1330 to rotate. Since the rotating shaft 1324 is positioned at the front end (restricted position) of the bearing long hole 1313, the guide pin 1326 is positioned at the front position that contacts the front end of the linear groove portion of the guide groove 1314 (see FIG. 26 (a)). Since the linkage pins 1312a and 1312b are located at the lower limit position, the opening / closing blades 1306a and 1306b are located at the closed position.

  When the solenoid 16 is in a non-excited state (off state) as described above, for example, when a stress for forcibly opening the opening and closing blades 1306a and 1306b is applied to at least one of the opening and closing blades 1306a and 1306b, The pins 1312a and 1312b are raised from the lower limit position and locked to the linkage pin locking portion 1325. However, since the guide pin 1326 is positioned in the linear groove portion, the upward movement of the guide pin 1326 causes the guide groove 1314 to move upward. The contact is regulated by the linear portion. Therefore, even if a stress is applied to forcibly rotate the open / close blades 1306a and 1306b toward the open position, the ascent of the linkage pins 1312a and 1312b is restricted by the rotation-restricted transmission member 1320. It is kept in the closed position and is prevented from being forcibly opened.

  Next, when the solenoid 16 changes from the non-excitation state (off state) to the excitation state (on state), the plunger 16a moves backward against the urging force of the coil spring 16b. When the rearward movement of the plunger 16a, that is, the excitation operation (second operation) is started, the connecting arm locking member 1330 biases the connecting arm 1322 rearward. At this time, the transmission member 1320 is guided together with the plunger 16a by the guide pin 1326 being guided rearward and the rotation shaft 1324 being guided toward the rear end (rotation position) of the bearing long hole 1313. Slide horizontally toward the rear. In other words, the transmission member 1320 moves rearward without rotating in the closed posture, so that the opening / closing blades 1306a and 1306b are maintained at the closed position.

  Then, at the stage where the plunger 16a is moved backward by a predetermined distance after the backward movement is started, that is, when the initial excitation operation is completed, the rotating shaft 1324 is placed at the rear end of the bearing slot 1313 as shown in FIG. At the same time, the guide pin 1326 is positioned in the arcuate groove and is rotatable upward. Further, when the plunger 16a moves rearward, the guide pin 1326 moves along the guide groove 1314 upward and rearward. Then, the connecting arm 1322 is urged rearward by the connecting arm locking member 1330, whereby the transmission member 1320 rotates upward.

  As shown in FIG. 28A, the rotation of the transmission member 1320 causes the linkage pin locking portion 1325 to be locked and lifted to the linkage pins 1312a and 1312b, so that the opening and closing blades 1306a and 1306b rotate. It rotates about the shaft 1310 and is located at the open position. When the plunger 16a is moved to the retracted position and the solenoid 16 is maintained in the excited state (on state), the transmission member 1320 is in a tilted posture in which the linkage arms 1321a and 1321b have the linkage pin locking portion 1325 upward. Since the linkage pins 1312a and 1312b are maintained in the open posture at the upper limit position, the open / close blades 1306a and 1306b are maintained in the open position.

  In this way, the variable winning device 15 is such that the plunger 16a of the solenoid 16 moves forward and backward (moves back and forth) with respect to the opening and closing blades 1306a and 1306b, so that the linear advance / retreat force of the plunger 16a is a connecting arm as a plunger linking portion. The rotating force of the transmission member 1320 is converted to the rotational force of the transmission member 1320 via the 1322, and the rotational force of the transmission member 1320 is converted to the vertical rotational force of the opening and closing blades 1306a and 1306b via the linkage pin locking portion 1325 as the opening and closing blade linkage portion. Thus, the opening and closing blades 1306a and 1306b rotate between the open position and the closed position.

  Further, the transmission member 1320 is a forward / backward movement of the plunger 16a, that is, a backward movement which is an excitation operation (second operation) based on the excitation of the solenoid 16 and an excitation release operation (first operation) based on the excitation release of the solenoid 16. It rotates in conjunction with a certain forward movement. Specifically, in response to the excitation operation of the plunger 16a, the rotation shaft 1324 moves from the front end (regulation position) to the rear end (rotation position) of the bearing long hole 1313 (see FIG. 28), so that the guide pin The rotation restriction of 1326 in the second direction is released, and the opening / closing blades 1306a and 1306b are opened by rotating upward and backward to change from the closed posture to the open posture.

  Further, according to the excitation release operation of the plunger, after rotating from the open posture to the closed posture around the rotation shaft 1324 located at the rear end (rotation position) of the bearing long hole 1313, When the rotation shaft 1324 moves from the rear end (rotation position) to the front end (regulation position) of the bearing long hole 1313 in the closed posture (see FIG. 29), the guide pin 1326 is positioned in the linear groove and rotates. Since the opening and closing blades 1306a and 1306b cannot be forcibly rotated from the closed position to the open position by being restricted, the opening and closing blades 1306a and 1306b are illegally rotated by an unauthorized member such as a wire, thereby It is possible to prevent illegal acts such as winning a prize as much as possible.

  Next, the structure of the start winning path member 1301 will be described with reference to FIGS. The start winning path member 1301 is formed of a transparent synthetic resin material, and a first winning path through which a mounting plate 1350 attached to the back of the game board 6 and a game ball that has entered the first start winning opening 13a flows down (passes). The first winning path wall 1361 that forms 1360a and the second winning path wall 1371 that forms the second winning path 1370a through which game balls that have entered the second start winning opening 13b flow (pass). ing.

  At the position facing the rear end of the guide path 1305 on the mounting plate 1350, a game ball receiving port 1362 flowing down the guide path 1305 is formed, and facing the rear end of the guide path 1308 on the mounting plate 1350. At a position to be received, a receiving port 1372 for a game ball that has flowed down the guide path 1308 is formed.

  Since the solenoid 16 protrudes directly under the receiving port 1362, the first prize passage wall portion 1361 has a left side along the back surface of the mounting plate 1350 when viewed from the back side in order to avoid this. After extending so as to be detoured, it is hung downward, and further bent and extended to the left, then hung downward. In addition, by bending at the two positions toward the left side in this way, the flow-down distance is made as long as possible without causing the first winning path 1360a to protrude rearward. In addition, an attachment portion 1363 for attaching the first start port switch 14a so as to face the first first prize passage 1360a is formed in the vertical portion of the first prize passage wall 1361, and the first prize passage 1 The game ball flowing down 1360a is detected by the first start port switch 14a in the vertical portion.

  The second prize passage wall portion 1371 is suspended downward from the receiving port 1372 along the back surface of the mounting plate 1350, and is shorter than the first prize passage wall portion 1361. The second prize passage wall 1371 is formed with an attachment portion 1373 for attaching the second start port switch 15a so as to face the internal second prize passage 1370a, and flows down the first prize passage 1360a. The played game ball is detected by the second start port switch 15a in the vertical portion.

  The main body of the first start port switch 14a and the second start port switch 15a is formed in a plate shape having a rectangular shape in plan view, and a passage hole through which a game ball can pass is formed on one end side. The passage hole is attached so as to face the passage. In addition, the width dimension of the short side of the main body is formed to be approximately the same as the front-rear width dimension of the first prize path wall portion 1361 and the second prize path wall portion 1371. Therefore, by attaching the first start port switch 14a and the second start port switch 15a horizontally in the left-right direction, a part of the main body is behind the first prize path wall part 1361 and the second prize path wall part 1371. Since the front and rear width dimension of the variable winning ball apparatus 15 is shortened as much as possible and the entire apparatus is miniaturized, the degree of freedom in arrangement of the apparatus is improved.

  The start winning path member 1301 is formed of a transparent synthetic resin material, and the first winning path wall 1361 that constitutes the first winning path 1360a and the second winning path wall that constitutes the second winning path 1370a. 1371 is juxtaposed in the left-right direction along the mounting plate 1350, so that a ball clogging situation occurring in the first winning path 1360a and the second winning path 1370a, the first start port switch 14a, and the second start Since the installation state of the mouth switch 15a can be seen through from the outside, the maintainability is improved, and it is easily confirmed whether or not the first starting port switch 14a and the second starting port switch 15a are improper. can do.

  Further, the first start port switch 14a and the second start port switch 15a are arranged at different positions not only in the left-right direction but also in the up-down direction, so that when an illegal act due to electromagnetic waves is performed, It is possible to avoid as much as possible that both the first start port switch 14a and the second start port switch 15a are cheated simultaneously.

  Next, the special variable winning device 20 will be described with reference to FIGS.

  As shown in FIGS. 30 to 33, the special variable prize-winning device 20 includes a horizontally long mounting plate 1401 attached to the front surface of the game board 6 with screws (not shown), and a horizontal center position on the back surface of the mounting plate 1401. Formed on the front surface (game area 7) side of the game board 6 and fitted to the third opening 453, and a second to be described later disposed on the back surface of the big prize passage wall portion 1402. It is mainly composed of a second winning passage wall portion 1410 constituting the winning passage 1370b and spacer portions 1404 and 1405 provided on the left and right sides of the big winning passage wall portion 1402.

  A large winning opening 23b having a horizontally long rectangular shape is formed at the center position in the left-right direction of the mounting plate 1401, and the large winning opening 23b can be opened and closed by an opening / closing plate 1406 described later. The prize-winning passage wall 1402 is formed in a box shape whose front surface is opened with a transparent synthetic resin material, and a prize-winning passage 1403 for guiding a game ball entering from the prize-winning opening 23b is a prize-winning. It is formed so as to face the mouth 23b. The big winning passage 1403 is formed in a horizontally long shape along the big winning opening 23b, and its bottom surface is formed in an inclined shape so as to guide the game ball that has entered the big winning opening 23b to the left as viewed from the front. .

  A count switch 23 for detecting a game ball that has entered the big prize opening 23b is attached to the left end side of the big prize passage 1403, and a game that has passed through the count switch 23 is located on the left side of the big prize passage wall 1402. An outlet 1407 from which the sphere flows out is formed. The game ball guided to the left side by the big winning passage 1403 and passing through the count switch 23 is changed in direction toward the back side of the game board 6 and then flows out from the outlet 1407.

  A solenoid 21 for driving the opening / closing plate 1406 and a link mechanism 1408 for transmitting the driving force of the solenoid 21 to the opening / closing plate 1406 are accommodated at the right end portion inside the big winning passage wall 1402, that is, on the right side of the big winning passage 1403. An accommodating portion is provided.

  As shown in FIG. 33, the opening / closing plate 1406 is formed in a horizontally long rectangular shape that is substantially the same shape as the special winning opening 23b. From the lower portions of the left and right side surfaces, a rotating shaft 1420 that faces in the left-right direction protrudes outward, and the rotating shaft 1420 pivots to a position near the lower portion of the big prize opening 23b in the big prize passage wall 1402 respectively. A closed position (closed state, solid line position in FIG. 33 (c)) that is supported and closes the special winning opening 23b in the vertical direction around the rotation shaft 1420, that is, a game ball does not enter; It tilts outward from the closed position to open the special winning opening 23b, that is, it can freely rotate between an open position where the ball can easily enter (open state, position indicated by a two-dot chain line in FIG. 33C). Is provided. In the open position, the opening / closing plate 1406 is held in an inclined posture that is inclined downward from the tip toward the rotating shaft 1420, and the ball guided on the inner surface of the opening / closing plate 1406 passes through the big prize opening 23b. It flows into the big prize passage 1403.

  In addition, a linkage pin 1421 that faces in the left-right direction protrudes outward from an eccentric position that is eccentric from the rotation shaft 1420 on the right side surface of the opening / closing plate 1406. The linkage pin 1421 is linked to a transmission member 1422 described later, and the opening / closing plate 1406 opens and closes in conjunction with the rotation of the transmission member 1422.

  The solenoid 21 includes a main body, a plunger 21a that is detachably fitted to the main body, and a coil spring 21b that urges the plunger 21a to a protruding position when the solenoid 21 is in a non-excited state (off state). In the excited state (on state) of the solenoid 21, the plunger 21a is moved to the retracted position against the urging force of the coil spring 21b.

  The link mechanism 1408 includes a transmission member 1422 and a locking member 1423. The transmission member 1422 is formed with a C-shaped linkage pin locking portion 1424 that can be locked to the linkage pin 1421 at the tip, and an elongated hole 1425 that is formed in the locking member 1423 on the inner side of the rear portion and faces in the vertical direction. A connecting pin 1426 that is slidably fitted to the connecting pin 1426 is formed. The connecting pin 1426 is provided so as to be rotatable about a rotating shaft 1427 that protrudes outward at a position eccentric to the connecting pin 1426. Yes. The rotating shaft 1427 is pivotally supported by a side wall (not shown) provided in the special winning award passage wall portion 1402.

  The locking member 1423 is attached to the distal end of the plunger 21a of the solenoid 21, and a long hole 1425 into which the connecting pin 1426 is slidable in the vertical direction is formed at the distal end. In this way, the locking member 1423 is locked to the transmission member 1422 via the connecting pin 1426 and the elongated hole 1425, so that the transmission member 1422 rotates around the rotation shaft 1427 according to the back and forth movement of the plunger 21a. By moving, the linkage pin locking portion 1424 moves up and down.

  Next, the operating states of the solenoid 21, the opening / closing plate 1406, and the transmission member 1422 will be described with reference to FIG. 33. As shown in FIG. 33A, the solenoid 21 is in a non-excited state (off state). In some cases, the plunger 21a is located at the protruding position by the biasing force of the coil spring 21b. At this time, the transmission member 1422 is in a closed posture in which the linkage pin locking portion 1424 faces downward and pushes the linkage pin 1421 toward the lower limit position, whereby the opening / closing plate 1406 is located at the closed position, so The mouth 23b is closed.

  Next, when the solenoid 21 changes from the non-excitation state (off state) to the excitation state (on state), the plunger 21a moves backward against the urging force of the coil spring 21b, so that it fits into the elongated hole 1425. The connected pin 1426 rotates around the rotation shaft 1427 and moves backward. As a result, the transmission member 1422 rotates around the rotation shaft 1427, so that the linkage pin locking portion 1424 at the tip is lifted from the lower limit position, and is directed to the front to push up the linkage pin 1421 to the upper limit position. As a result, the opening / closing plate 1406 is rotated to the open position to open the special winning opening 23b.

  In the present embodiment, the link mechanism 1408 for connecting the solenoid 21 serving as a driving means for opening and closing the opening / closing plate 1406 and the opening / closing plate 1406 has a thickness width of the game board 6 as shown in FIG. The rear portion of the link mechanism 1408 does not protrude greatly toward the back side of the game board 6 by being formed to have substantially the same dimensions.

  The linkage pin locking portion 1424 that reciprocates up and down by rotating around the rotation shaft 1427 in accordance with the back and forth movement of the plunger 21a is positioned at the lower limit position. Since part of the opening 1428 formed in the wall 1402a is accommodated, the vertical width of the link mechanism 1408 can be shortened as much as possible to reduce the size of the apparatus.

  In addition, since the outer side of the opening 1428 is closed by the peripheral wall surface of the third opening 453 by fitting the prize-winning passage wall part 1402 in the third opening 453, an illegal member such as a wire can be used as a game. An illegal act of inserting the third opening 453 and the bottom wall 1402a from the front side of the board 6 into the big prize passage wall 1402 through the opening 1428 and forcibly opening the transmission member 1422 is prevented. can do.

  In addition, the count switch 23 including a proximity switch that detects a game ball that has won a prize winning opening 23b and the solenoid 21 that drives the opening / closing plate 1406 to open / close are disposed apart from each other in the longitudinal direction of the opening / closing plate 1406. As a result, it is possible to prevent erroneous detection of the count switch 23 composed of an electromagnetic proximity switch due to electromagnetic waves of the solenoid 21 serving as electromagnetic drive means, and to efficiently arrange the solenoid 21 and the count switch 23. it can.

  As shown in FIGS. 31 and 32, on the back surface of the big prize passage wall portion 1402, the second prize passage wall constituting the second prize passage 1370b through which the game ball flowing down the second prize passage 1370a described above flows down. A portion 1410 is provided. The second winning path 1370b is formed in the vertical direction, and the upper end opening of the second winning path 1370b is opposed to the lower end opening of the second winning path 1370a disposed above the second winning path 1370b with respect to the second winning path 1370a. Are disposed slightly rearward.

  An attachment portion 1411 for attaching the second winning confirmation switch 15b is formed in the second winning passage 1370b. The main body of the second winning confirmation switch 15b is formed in a plate shape having a rectangular shape in plan view, and a passage hole through which a game ball can pass is formed on one end side so that the passage hole faces the passage. It is attached. Further, the width dimension of the short side of the main body is formed to be approximately the same as the width dimension in the front-rear direction of the second prize-winning passage wall portion 1410. Therefore, by attaching the second winning confirmation switch 15b horizontally in the left-right direction, a part of the main body does not protrude rearward from the second winning passage wall portion 1410. Since the front-rear width dimension is shortened as much as possible and the entire apparatus is miniaturized, the degree of freedom of arrangement of the apparatus is improved.

  In addition, the second prize passage wall portion 1410 is formed of a transparent synthetic resin material, and is provided on the back surface of the big prize passage wall portion 1402, so that a ball generated inside the second prize passage 1370b. Since the clogging status and the mounting status of the second winning confirmation switch 15b can be seen through from the outside, the maintainability is improved, and it is easy to check whether the second winning confirmation switch 15b is fraudulent. be able to.

  Further, as shown in FIG. 32A, the big winning path 1403 and the second winning path 1370b are partitioned by a partition wall 1429 so that the game ball does not enter the other path. Since the front surface 1429a of the partition wall 1429 is knurled, the second winning confirmation switch 15b is not easily seen through the transparent partition wall 1429 when the big prize opening 23b is opened. It has become. As a result, the arrangement position of the second winning confirmation switch 15b cannot be easily specified from the big winning opening 23b, so that it is difficult to cheat on the second winning confirmation switch 15b. In this embodiment, it is difficult to visually recognize the second winning confirmation switch 15b on the back side by knurling the front surface of the transparent partition wall 1429. However, the partition wall 1429 is made of a non-translucent synthetic resin. You may comprise with a material, and you may stick a non-light-transmissive sheet | seat etc. to it.

  On the other hand, convex guide portions 1430 and 1430 are provided on the left and right sides of the big prize opening 23b on the front surface of the mounting plate 1401 so as to protrude from above the big prize opening 23b near the left and right ends of the big prize opening 23b. The falling direction of the falling game ball is changed to either the big prize opening 23b side or the opposite side of the big prize opening 23b, so that the game ball wins the big prize opening 23b. Can be improved.

  In addition, on the outer sides of the left and right guide portions 1430 and 1430, ball receiving portions 1431a and 1431b formed in a box shape in which upper surfaces constituting the winning holes 29a and 29b are opened are projected. Guide paths 1432a and 1432b for guiding the game balls that have entered the winning holes 29a and 29b to the back side of the game board 6 are formed on the upper sides of the spacer portions 1404 and 1405 on the back side of the ball receiving portions 1431a and 1431b. Yes.

  The spacer portions 1404 and 1405 are formed so as to be able to be fitted into the third opening 453 together with the big prize passage wall portion 1402, and the front-rear width dimension thereof is the front-rear width dimension of the third opening 453, that is, the thickness of the game board 6. Since it is formed to be substantially the same as the width dimension, the back surfaces 1404a and 1405a of the spacer portions 1404 and 1405 are located at the same position in the front-rear direction as the back surface of the game board 6. The back surface 1404a of the spacer part 1404 constitutes a part of the front wall surface of the winning path 1440a, and the back surface 1405a of the spacer part 1405 forms a part of the front wall surface of the first winning path 1360b and the winning path 1440b described later. Configure (see FIGS. 32B and 32C).

  As shown in FIG. 34, the winning path 1440a through which the game balls that have entered the winning openings 29a, 29c, and 29d pass covers the part of the third opening 453 and the part of the fourth opening 454 from the back side. It is formed by a first winning path member 1450 attached to the back surface of the board 6. The winning path 1440b through which the game ball that has entered the winning opening 29b passes is formed by a second winning path member 1451 attached to the back of the game board 6 so as to cover a part of the third opening 453 from the back side. The

  The first winning path member 1450 has a box shape with a front surface opened by a transparent synthetic resin material. The first winning path member 1450 is formed in such a size that each of the winning holes 29a, 29c, 29d can be covered from the back side. It is attached to the back surface of the game board 6 by a not shown). The game balls that have entered the winning holes 29a, 29c, and 29d and are guided to the back side of the game board 6 are dropped onto the bottom wall 1450a and merged, guided toward the center, and then entered the winning path 1440a. After flowing in and detected by a winning opening switch 30a attached to the winning passage 1440a, the air is discharged from a discharge opening 1452 provided in the lower portion.

  The winning path 1440a is bent to the right in the rear view at a position below the winning opening switch 30a, and is discharged toward the lower right. That is, a release direction changing surface 1452a for changing the release direction of the game ball to the right side is provided at a position below the winning opening switch 30a in the winning path 1440a.

  In addition, on the left side of the winning path 1440a of the first winning path member 1450 when viewed from the back, a large winning opening path 1403a through which a game ball discharged from the outlet 1407 through the large winning path 1403 passes is formed. Yes. The game ball that has entered the big prize opening passage 1403a is detected by the third winning confirmation switch 23a attached to the big prize opening passage 1403a, and then released from the discharge opening 1453 provided in the lower part. Note that the winning award passage 1440a and the special winning opening passage 1403a are partitioned by a partition wall.

  Further, the special winning opening passage 1403a is bent to the left in the rear view at a position below the third winning confirmation switch 23a, and is discharged obliquely downward to the left. That is, a release direction changing surface 1453a for changing the release direction of the game ball to the left side is provided at a position below the third winning check switch 23a in the big winning opening passage 1403a.

  The second winning path member 1451 has a box shape with a front surface opened by a transparent synthetic resin material, and is formed in a size that allows the winning opening 29b to be covered from the back side. 6 is attached to the back. The game ball that has entered the winning hole 29b and is guided to the back side of the game board 6 flows into the lower winning path 1440b as it is and is detected by the winning port switch 30b attached to the winning path 1440b, and then provided at the lower part. The discharge port 1454 is discharged.

  The winning path 1440b is bent to the left in the rear view at a position below the winning opening switch 30b, and is discharged toward the lower left. That is, a release direction changing surface 1454a for changing the release direction of the game ball to the left side is provided at a position below the winning opening switch 30b in the winning path 1440b.

  Further, a first winning path 1360b through which a game ball that has passed through the first winning path 1360a passes is formed on the right side of the winning path 1440b in the second winning path member 1451 when viewed from the back. The game ball that has entered the first winning path 1360b is detected by the second winning confirmation switch 14b attached to the first winning path 1360b and then discharged from the discharge port 1455 provided in the lower portion. The winning path 1440b and the first winning path 1360b are partitioned by a partition wall.

  The first winning path 1360b is bent to the right in the rear view at a position below the second winning confirmation switch 14b, and is discharged obliquely downward to the right. That is, a release direction changing surface 1455a for changing the release direction of the game ball to the left is provided at a position below the second winning confirmation switch 14b in the first winning path 1360b.

  The game ball that has passed through the second winning confirmation switch 15b in the second winning path 1370b is discharged vertically downward from the discharge port 1456 without changing its direction.

  The game balls released from the discharge ports 1452 to 1456 fall into a collection basket 1500 (see FIG. 23) provided in the front frame 401, and are finally discharged from the game machine to a game machine installation island (not shown). It is collected in a collection path. The collection basket 1500 is formed in a funnel shape, and a bottom surface 1501 as a collection path surface is formed in an inclined plane shape that is inclined downward toward the central discharge path 1502, and is discharged from the discharge ports 1452 to 1456. The game ball is guided toward the discharge path 1502 and discharged.

  In the state where the game board 6 is attached to the front frame 401, the bottom surface 1501 is disposed immediately below each of the outlets 1452 to 1456, so that the game ball released from the outlets 1452 to 1456 and dropped on the bottom surface 1501 jumps up and down. However, it is expected that each of the discharge ports 1452 to 1455 except the discharge port 1456 arranged at a higher position than the other discharge ports is provided with discharge direction changing surfaces 1452a to 1455a. The game balls that have passed through the winning confirmation switch 14b, the third winning confirmation switch 23a, and the winning opening switches 30a and 30b are not released in the vertical direction. In other words, it is possible to prevent the game ball falling on the bottom surface 1501 from jumping and being detected again by the second winning confirmation switch 14b, the third winning confirmation switch 23a, and the winning opening switches 30a and 30b.

  In this embodiment, the discharge port 1456 from which the game ball detected by the second winning confirmation switch 15b is discharged is not provided with a discharge direction changing surface, but the discharge port 1456 also has a discharge direction changing surface 1452a. ˜1455a may be provided with a discharge direction changing surface, and in this way, it is prevented that the game ball dropped on the bottom surface 1501 jumps and is detected again by the second winning confirmation switch 14b. .

  Further, in this embodiment, the discharge direction changing surface is provided between each of the discharge ports 1452 to 1455 and the bottom surface 1501, but if provided between each winning confirmation switch and the bottom surface 1501, for example, Even if it is formed between each winning confirmation switch and each of the outlets 1452 to 1455, the same operation and effect as described above can be obtained.

  Next, based on FIGS. 34 to 37, the flow-down situation and the detection situation of the game balls that have entered the winning holes 13a, 13b, 23b, and 29a to 29d will be described.

  First, the game ball that has entered the first start winning opening 13a flows down on the guide path 1305 and flows into the first winning path 1360a on the back side of the game board 6, and then changes direction to the right when viewed from the front. It flows down along the back of the game board 6. Then, when the direction is changed further downward, it is detected by the first start port switch 14a, then the direction is changed again to the right side when viewed from the front, and flows down along the back of the game board 6, and the direction is changed downward to the first. It flows into the winning path 1360b. Then, after being detected by the first winning confirmation switch 14b, it is discharged from the discharge port 1455.

  The game balls that have entered the second start winning opening 13b flow down on the guide path 1308 and flow into the second winning path 1370a on the back side of the game board 6, and then flow downward along the back of the game board 6. After being detected by the second start port switch 15a, the direction is slightly changed to the rear side and flows into the second winning path 1370b. Then, after being detected by the second winning confirmation switch 15b, it is discharged from the discharge port 1456.

  The game ball that has entered the big prize opening 23b is guided to the back side of the game board 6 by the opening / closing plate 1406, flows down on the big prize path 1403, and is led to the left side when viewed from the front. Then, after being detected by the count switch 23, the direction is changed to the back side and flows into the big winning path 1403a. Then, after being detected by the third winning confirmation switch 23a in the big winning passage 1403a, it is discharged from the discharge port 1453.

  The game balls that have entered the winning openings 29a, 29c, and 29d are guided to the back side of the game board 6 and dropped onto the bottom surface 1450a, and then are guided toward the center, and then flow into the winning path 1440a, where the winning path After being detected only at the winning opening switch 30a at 1440a, it is discharged from the discharge port 1452. The game ball that has entered the winning opening 29b is guided to the back side of the game board 6, then falls downward and flows into the winning path 1440a, and is detected only by the winning slot switch 30b in the winning path 1440b. Thereafter, it is discharged from the discharge port 1454.

  As described above, in the present embodiment, the variable winning ball device 15 as the first winning device and the special variable winning ball device 20 as the second winning device are close to each other below the game area 7. By arranging them, it is possible to secure a wide range of arrangement space for the display part of the effect display device 9 provided in the game area 7 and for the accessory and decoration member arranged on the right side thereof. In the gaming area 7, it is possible to increase the size of the display unit, the accessory, the decorative member, and the like of the effect display device 9 as much as possible.

  The start winning unit 12 disposed above the special variable winning ball apparatus 20 has a first start winning port 13a and a second starting winning port 13b arranged above and below, particularly the first start winning port 13a. The second winning passages 1370a and 1370b through which the game balls won from the second starting winning hole 13b disposed closer to the special variable winning ball apparatus 20 than the first starting winning hole 13a pass through, A second start opening switch 15a as a first detection means and a second winning confirmation switch 15b as a second detection means are attached. If the second winning passages 1370a and 1370b are shortened, the second start opening switch 15a and It becomes difficult to arrange the 2-winning confirmation switch 15b. Therefore, the second winning path 1370b on the downstream side is provided on the back surface of the special variable winning ball apparatus 20, and the second winning confirmation switch 15b is attached to the second winning path 1370b, so that the second winning path 1370b is not limited. Since the variable winning ball device 15 and the special variable winning ball device 20 of the start winning unit 12 can be arranged with the smallest possible interval, the display unit of the effect display device 9 provided in the game area 7 and the right side thereof are arranged. It is possible to secure a wide range of arrangement space for an accessory or decorative member provided.

  Next, the unit member 460 attached to the back surface of the game board 6 will be briefly described with reference to FIGS. FIG. 38 is a front view showing the variable display control unit. FIG. 39A is a diagram showing a state in which the accessory provided in the variable display control unit has been raised, and FIG. 39B is a diagram showing a state in which the accessory has been released.

  The unit member 460 is formed in a box shape whose front surface is opened by a synthetic resin material, and is attached to the back surface of the game board 6 (see FIG. 23). The unit member 460 is provided with a variable display control unit including the effect display device 9, the effect control board 80, and the like, and in the present embodiment, an accessory unit 1600 is provided.

  The accessory unit 1600 includes an accessory 1601 that is an example of a decorative movable object that imitates a dagger. The right end portion of the accessory 1601 is pivotally supported, and the left end portion is provided so that it can be moved up and down by rotating a spiral bolt 1602 provided in the up and down direction by driving the lifting motor 1606. . The accessory 1601 includes a handle portion 1603 as a decorative portion and a sheath portion 1604. When the left end rises, the sheath portion 1604 is separated from the handle portion 1603 and extends from the handle portion 1603. The sword portion 1605 is exposed, and when the sword portion 1605 is exposed, an LED (not shown) built in the sword portion 1605 emits light and is decorated ( FIG. 39 (a)). In addition, the handle portion 1603 and the sheath portion 1604 are configured to be dividable in a direction orthogonal to the longitudinal direction of the sword portion 1605, and the inside of the sword portion 1605 and the handle portion 1603 is driven by the opening / closing motor 1607. It is designed to be opened.

  The accessory 1601 configured in this manner is moved in accordance with, for example, a change display of a symbol, or is moved in synchronization with an image effect by the effect display device 9, thereby suggesting the possibility of a big hit. It is used as an effect device that executes

  Further, the unit member 460 is provided with a magnet sensor 1610 and attached to the back surface of the game board 6 so as to cover the first winning path member 1450 and the second winning path member 1451 described above from the back side.

  In this embodiment, based on the fact that a game ball has won the first start winning opening 13a, the first special symbol display unit 8a starts the variable display of the first special symbol, and the second starting winning opening 13b. The second special symbol display 8b starts to display the variation of the second special symbol based on the fact that the game ball has won a prize, for example, the first start winning port 13a or the second starting winning port, for example. Based on the fact that the game ball has won 13b, the special symbol variable display may be started by one special symbol display. That is, you may provide two or more start winning openings corresponding to a single special symbol display.

  Next, the operation of the gaming machine will be described. FIG. 40 is a flowchart showing main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed at the time of power-on that is not the time of recovery from the stop of the power supply is performed. Execute.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. In addition, after setting in step S93, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above.

  Further, the CPU 56 sets the head address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  The CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, an initialization process is performed when the gaming machine is turned on by executing an information output process (see S31) described later based on the fact that a predetermined time is set in the security signal information timer in step S14a. Is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs settings in accordance with the random number circuit setting program 551 to make the random number circuits 503a and 503b update the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 according to the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs an initial setting so as to preferentially execute an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 according to the interrupt process priority order table. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  For example, in setting the internal device register, the CPU 56 sets the baud rate of the serial communication circuit 505. In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  For example, the CPU 56 sets the data format of data transmitted and received by the serial communication circuit 505. In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the use / nonuse of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505. In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the gaming control microcomputer 560 stores, in advance, a predetermined storage area in the ROM 54 for specifying information for specifying the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, the manufacturer of the gaming machine). I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. Note that the process of setting the initial value to the prize ball number counter may be executed, for example, in the process of sequentially setting each initial value in the work area of steps S92 and S12, until the process proceeds to steps S15 to S17. As long as it is running.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the first special symbol display 8a and the second special symbol display 8b. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . If a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. In addition, when an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process and reception) to be described later. Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the timer interrupt process will be described. FIG. 41 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Then, the CPU 56 via the switch circuit 58, the gate switch 32a, the first start opening switch 14a, the first winning check switch 14b, the second starting opening switch 15a, the second winning check switch 15b, the count switch 23, the third switch Detection signals of switches such as the winning confirmation switch 23a and the winning opening switches 30a and 30b are input to detect the input of each switch (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 performs display control to perform display control of the first special symbol display 8a, the second special symbol display 8b, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41. Processing is executed (step S22). For the first special symbol display 8a, the second special symbol display 8b, and the normal symbol display 10, a drive signal is output to each display according to the contents of the output buffer set in steps S36 and S37. Execute control.

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating each determination random number such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 and sending the effect control command (effect symbol command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 performs an information output process for outputting data such as a start port signal supplied to the hall management computer, a symbol determination number 1 signal, a jackpot 1 to 3 signal, a time reduction signal, a security signal, and the like (step S31). ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 30a, 30b, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switches 30a, 30b being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the connection signal and the contents related to the solenoid in the RAM area of the output port 0. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs a special symbol display control process for setting special symbol display control data for effect display of special symbols in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in the output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs frame state output processing for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to display the error state of the gaming machine to the production control microcomputer 100. Execute (Step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  Next, the prize ball process (step S32) in the main process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 42 is an explanatory diagram showing an example of the content of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 42, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. Is a signal (connection signal for the main board 31) for The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time one prize ball has been detected on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  FIG. 43 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with regard to “xxxx” in the second byte of the connection OK command, as shown in FIG. 44, a prize ball error (a prize ball payout operation based on winning or a ball lending operation based on a ball rental request cannot be performed normally). An abnormal state that has become a state: Specifically, when the main control unconnected error shown in FIG. 99, the payout switch abnormality detection error 1, the payout switch abnormality detection error 2, the payout case error, or the main control communication error) occurs. In this case, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 44, the connection OK command is set to a value indicating an error relating to payout (award ball error, full tank error, out of ball error, payout number error error) as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, three prize balls are paid out, and the game ball is detected by one of the winning port switches 30a and 30b. Then, 10 prize balls are paid out. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the first start port switch 14a and the second start port switch 15a, a prize ball number command “01010011” for notifying three prize balls is transmitted, and the prize opening switches 30a, 30a, When a game ball is detected in any of 30b, a prize ball number command “01011010” for notifying 10 prize balls is transmitted, and when a game ball is detected by the count switch 23, the number of prize balls is 15 A prize ball number command “01011111” for notifying the player is transmitted.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball number command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball number command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with respect to “xxxx” of the second byte of the command for preparing a prize ball, as shown in FIG. 44, when a prize ball error occurs, “1” is set to “x” of the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). The example shown in FIG. 44 shows a case where a value indicating a payout error (a prize ball error, a full tank error, an out of ball error, a payout number error error) is set as a control state in the command for preparing a prize ball. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control command, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number acceptance command, a payout end signal is realized by a prize ball end command, and a payout signal is realized by a prize ball preparation command.

  45 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 42 and the control command shown in FIG. As shown in FIG. 45, the connection signal is output by the game control microcomputer 560 via the output circuit 67A and is input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

  Of the control commands, the connection confirmation command and the winning ball number command are output from the serial circuit 505 built in the game control microcomputer 560 and input to the serial circuit 380 built in the payout control microcomputer 370. Of the control commands, the connection OK command, the prize ball number reception command, the prize ball end command, and the prize ball preparation command are output from the serial circuit 380 built in the payout control microcomputer 370, and the game control microcomputer 560 It is input to the built-in serial circuit 505. In FIG. 45, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. Although a signal line for transmitting a command from 370 to the game control microcomputer 560 side is shown, the payout control command is actually transmitted and received through one signal line. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, transmission / reception of a payout control command between the game control microcomputer and the payout control microcomputer during normal operation will be described. In this embodiment, a connection confirmation command and a prize ball number command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparation command are transmitted.

  FIG. 46 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 46, the game control microcomputer 560 is connected to the payout control microcomputer 370 via the serial communication circuit 505 to confirm whether or not the signal line is disconnected. A confirmation command is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  47 and 48 are sequence diagrams showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during the prize ball movement. As shown in FIGS. 47 and 48, when a winning occurs and a winning ball payout operation is executed, the game control microcomputer 560 is set with data indicating the number of winning balls via the serial communication circuit 505. The prize ball number command is transmitted to the payout control microcomputer 370. In this case, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the received connection OK command with respect to the previously transmitted connection confirmation command (see FIG. 44), and A winning ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received after the connection OK signal is received until 1 second elapses.

  Next, when the payout control microcomputer 370 receives the award ball number command, if the award ball operation can be executed immediately (that is, if the lending ball is not being dispensed and no error has occurred), the award A prize ball number reception command indicating that the number of balls has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) after the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the winning ball end command, as shown in FIG. 47, if the number of winning balls to be paid out is not yet stored, the gaming control microcomputer 560 outputs the winning ball end command. Transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 48, when the number of prize balls to be paid out has already been stored, a prize ball number command for immediately specifying the next prize ball number is issued without waiting for 1 s (1 second). This is sent to the payout control microcomputer 370. Also in this case, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or the winning ball preparation command (see FIG. 44), and The award ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received from the reception of the ball end command until 1 second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 49 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when the winning ball operation cannot be executed immediately. Even if the payout control microcomputer 370 receives the award ball number command, if it is in the lending ball payout operation or is in an error state, the award ball number specified by the received award ball number command. Unable to start the prize ball payout operation. In such a case, as shown in FIG. 49, even if the payout control microcomputer 370 receives the prize ball number command, it does not immediately send the prize ball number acceptance command, and the prize ball payout operation is completed. A command for preparing a prize ball for notifying that the game is not being sent is transmitted to the microcomputer 560 for game control. In this case, the payout control microcomputer 370 is in a state of preparing a prize ball at regular intervals (every 1 s) unless the payout operation of the lending ball is completed and the award ball action can be started or the error is not canceled. The command is transmitted to the game control microcomputer 560.

  Next, the payout control microcomputer 370 finishes the lending ball payout operation and becomes ready to start the next prize ball operation, or when the error is canceled, the prize indicating that the number of prize balls has been received is received. The ball number acceptance command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) after the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 50 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 50, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits the connection confirmation command again after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a prize when the connection confirmation communication process is not executed (between receiving the connection OK command and transmitting the next connection confirmation command), the game control microcomputer 560 The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of winning balls is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. In this case, the game control microcomputer 560 performs a process of subtracting the prize ball number storage based on the reception of the prize ball number reception command (specifically, 1 is subtracted from a prize ball command output counter described later). (See step S52404). Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command, and when the prize ball payout (prize ball payout operation) is completed, the prize ball end command is sent to the game control microcomputer. Send to computer 560. As described above, when the winning ball payout operation takes a long time, the payout control microcomputer 370 waits for 1 s (1 second) until the winning ball payout operation is completed. Is sent repeatedly. When the game control microcomputer 560 receives the prize ball end command, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. To do.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command and receiving the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 In this stage, the connection status is not confirmed, so the award ball number command is not immediately transmitted, but the process waits until the reception of the connection OK command can be confirmed. When the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and sets the set number of winning balls. The command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 performs the same processing, pays out the number of prize balls designated by the prize ball number command, and when the prize ball is paid out (prize ball payout operation), The ball end command is transmitted to the game control microcomputer 560.

  After receiving the winning ball end command, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 44). In addition, even when the start winning prize is received from the reception of the winning ball end command until 1 second elapses, the winning ball number command is transmitted to the payout control microcomputer 370. In other words, in this embodiment, the game control microcomputer 560 receives a prize ball end command from when a connection OK signal in which a value indicating an error is not set until one second elapses. The award ball number command can be transmitted until 1 second has elapsed.

  FIG. 51 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when an error occurs in the winning ball. As shown in FIG. 51, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a win when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and the set winning prize is set. The ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command. When executing the payout operation for the number of prize balls specified by the prize ball number command, a predetermined error (for example, an abnormal payout number error, a ball lending, a full tank, or an out of ball error) occurs. When the ball payout operation cannot be performed (abnormal state, error state), the payout control microcomputer 370 issues a prize ball preparing command for notifying that an error has occurred and the prize ball payout operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command to the game control microcomputer 560. The award ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after the award ball number acceptance command is transmitted. Further, while the game control microcomputer 560 is receiving a command for preparing a prize ball, the game control microcomputer 560 is controlled not to transmit a connection confirmation command. Specifically, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. Based on this, control is performed so as to return to a state in which a connection confirmation command is output every predetermined period (1S).

  FIG. 52 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during connection confirmation. As shown in FIG. 52, the game control microcomputer 560 has transmitted the connection confirmation command to the payout control microcomputer 370, but has not received the connection OK command from the payout control microcomputer 370, that is, When a connection state abnormality (communication error) occurs, the connection confirmation command is transmitted again after 10 s (10 seconds) have elapsed since the connection confirmation command was transmitted. In other words, if the process of transmitting the connection confirmation command every 1 s (1 second) when the connection OK command cannot be received is continued, the number of connection confirmation command transmissions is increased even though the communication state is unstable. Since it increases in vain, the transmission interval of the connection confirmation command is extended to 10 s (10 seconds), and the control is switched to transmitting the connection confirmation command with the minimum necessary number of transmissions until the communication state is recovered. If a winning occurs when a communication error has occurred, the game control microcomputer 560 will receive a connection OK command from the payout controlling microcomputer 370, even if a new winning occurs. Without transmitting the award ball number command, the connection confirmation command is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command.

  FIG. 53 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during the award ball number notification. As shown in FIG. 53, the game control microcomputer 560 has transmitted a prize ball number command based on the occurrence of a win, but has not received a prize ball number acceptance command from the payout control microcomputer 370. In this case, that is, when a connection state abnormality (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 s (10 seconds) until the communication state is recovered. Thereafter, when the communication error is canceled (resolved) and the connection OK command is received from the payout control microcomputer 370, the award game control microcomputer 560 returns to the normal (normal) operation, and the number of winning balls The command is retransmitted (retryed) to the payout control microcomputer 370. Specifically, the game control microcomputer 560 does not subtract the prize ball number storage if it does not receive the prize ball number acceptance command even after sending the prize ball number command (described later). If N in step S52403, the value of the prize ball command output counter in step S52404 is not subtracted by 1), and the value of the prize ball command output counter is maintained as it is when the prize ball number command is transmitted next time. The prize ball number command is retransmitted based on that (see steps S52301 to S52035 described later).

  Next, the prize ball process (step S32) will be described. FIG. 54 is a flowchart showing an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 55 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the prize ball command output counter, and the prize ball designation for designating the number of prize balls Data is set sequentially. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30) and a prize ball command output counter 4 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Based on the prize ball designation data for designating the number of prize balls (3), data indicating the number of prize balls (3) is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is issued. It transmits to the control microcomputer 370. In FIG. 55, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  FIG. 56 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 57 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 58 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the processing of steps S5227 and S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and Y in step S5227. When the determination is made, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integral multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 59 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 44) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the processing of steps S52313 and S52315 described later, and one second elapses without sending a prize ball number command, and Y in step S52313. If it is determined, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 60 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the processing from step S52303 is not performed. And control to suspend transmission of the prize ball number command.

  If the content of the frame state display buffer is 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs processing for outputting a prize ball number command in which the number of prize balls is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds have elapsed without receiving a prize ball number acceptance command or a prize ball preparation command. If it is timed out and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. (See steps S52403 to S52405) or by receiving the winning ball preparation command and repeating the winning ball receipt confirmation process (see steps S52406 to S52408), without returning to the winning ball transmission process 1 In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. Cases are also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the prize ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, the serial communication circuit of the transmission / reception channel with the effect control board 80 in the effect symbol command control process in step S30 An award ball shortage error command is output to the transmission data register 505, and the award ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command, which will be described later, the effect control microcomputer 100 issues an error notification of prize ball shortage or prize ball excess. However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, it is only necessary to add 10 to the value of the prize ball counter based on the input of the prize ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. In the process of step S5312 described later, if the value of the prize ball number counter is 501 or more, a prize ball What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, a value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 61 is a flowchart showing the winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 44) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. If time elapses and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 62 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 15). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 15). If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the prize ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a prize ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 44) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the processing of steps S52509 and S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time is out and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 63 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the prize ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the prize ball information input invalid timer (step S5310) and sets the value of the prize ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the effect symbol command control process in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. The award ball excessive error command is output to the transmission data register 505, and the award ball excessive error command is transmitted to the production control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 64 is a flowchart showing an example of the frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the content of the input port 0 (step S392) and logically ANDs the input port 0 content with a predetermined door opening signal confirmation mask value (specifically 01000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is to the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, in the effect symbol command control processing in step S30, the serial communication circuit 505 for the channel for transmission / reception with the effect control board 80 is performed. The frame state display command is output to the transmission data register, and the frame state display command is transmitted to the production control microcomputer 100.

  By executing the above processing, the error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 560 (the payout number error error, the ball running out error, the full tank error, the winning ball error) And the input state of the door opening signal are set in the frame state display command and transmitted to the production control microcomputer 100.

  Next, the special symbol process (step S28) in the main process will be described. FIG. 65 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. If the first start opening switch 14a for detecting that the game ball has won the first start winning opening 13a is turned on, that is, the CPU 56 of the game control microcomputer 560, that is, the first start winning opening 13a is connected. If a start winning has occurred, a first start port switch passing process is executed (steps S311 and S312). If the second start port switch 15a for detecting that the game ball has won the second start winning port 13b is turned on, that is, the start winning to the second start winning port 13b has occurred. Then, the second start port switch passage process is executed (steps S313, S314). Then, any one of steps S300 to S310 is performed. If the first start winning port switch 14a or the second start port switch 15a is not turned on, any one of steps S300 to S306 is performed according to the internal state. Note that the determinations in step S311 and step S313 may be made based on whether or not the switch-on buffer corresponding to the first start port switch 14a or the switch-on buffer corresponding to the second start port switch 15a is “0”. Good.

  Special symbol normal processing (step S300): A state in which variable symbol special display can be started (for example, the first special symbol indicator 8a or the second special symbol indicator 8b has no symbol variation, and the first special symbol is displayed). It waits for a predetermined period to have elapsed since the last symbol variation on the display 8a or the second special symbol display 8b has ended, and no big hit game. When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the number of starting winning prizes is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 503 stored in the special figure holding memory. Further, when it is determined to be a big hit, control for transmitting a display result designation command capable of specifying the determined display result to the microcomputer 100 for effect control is further determined, such as whether or not to make a probable big hit. I do. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Fluctuation time setting process (step S301): A variation pattern is determined, and a variation pattern in the variation pattern (variable display time: time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, control is performed to transmit a variation pattern command specifying the determined variation pattern to the effect control microcomputer 100, and a variation time timer for measuring the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Special symbol variation processing (step S302): When a predetermined time (the time indicated by the variation time timer in step S301) elapses, the internal state (special symbol process flag) is updated to shift to step S303.

  Special symbol stop process (step S303): An effect symbol stop command for instructing stop of the effect symbol is transmitted to the effect control board 80. Moreover, the special symbol in the 1st special symbol indicator 8a or the 2nd special symbol indicator 8b is stopped. If the stop symbol of the special symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to shift to step S304. If not, the internal state is updated to shift to step S300. In addition, it is good also as a structure which does not transmit an effect design stop command. In this case, the effect control board 80 sets the change time in the change time timer based on the change pattern command received from the main board 31 and updates the change time timer to uniquely change the change time of the effect symbol. Monitoring, and when it is determined that the fluctuation time has elapsed, a process of stopping the effect design may be performed.

  Preliminary winning opening opening process (step S304): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S305.

  Processing for opening a special prize opening (step S305): Control for sending a presentation control command for round display of the special prize opening to the production control board 80 and closing conditions for the special prize opening (for example, a predetermined number (for example, ten) for the special prize opening ) To confirm that the game ball has won a prize). When the closing condition for the big prize opening is satisfied, if there are still rounds, the internal state is updated to shift to step S304. When all the rounds have been completed, the internal state is updated to shift to step S306.

  Big hit end processing (step S306): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 66 is a flowchart showing the start-port switch passing process in steps S312 and S314. Among these, FIG. 66 (A) is a flowchart showing the first start port switch passing process of step S312. FIG. 66B is a flowchart showing the second start port switch passing process in step S314.

  First, the first start port switch passing process will be described with reference to FIG. In the first start port switch passing process executed when the first start port switch 14a is in the on state, the CPU 56 of the game control microcomputer 560 displays the first start winning memorized number (or the first start winning memorized counter) (or It is confirmed whether or not the first start winning memory number stored in the first special figure reservation memory has reached the maximum value of 4 (step S321A). If the first start winning memorized number has not reached 4, the CPU 56 reads the random R value stored as the random number value from the random number value memory circuit of the random number circuit 503 (step S322A). In addition, the CPU 56 stores the read random R value in a storage area (first special symbol determination buffer (first special diagram holding memory)) corresponding to the value of the number of start winning memories (step S323A). In this embodiment, the random number circuit 503 inputs an input signal from the first start port switch 14a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random value storage circuit (latch circuit) at the timing when the input signal is input from the first start port switch 14a. Then, the CPU 56 reads the value latched in the random value storage circuit of the random number circuit 503 as a random R in step S322A.

  When the random number circuit 503 is configured so that a new count value cannot be latched in the latch circuit even if a latch signal is output unless the count value latched in the random number value storage circuit (latch circuit) is read. As long as it is determined in step S321A that the starting prize storage number has reached the maximum value 4, the count value is not read from the latch circuit, and the new count value is not latched by the latch circuit. Therefore, even if the start winning memorized number is less than 4 and step S322A is executed and the count value is read out from the latch circuit, the old count value latched at a timing other than the original latch timing is read out. Thus, there is a risk that processing such as jackpot determination will be performed using a random number value based on the old count value. Therefore, if the random number circuit 503 is configured so that a new count value cannot be latched unless the count value latched in the latch circuit is read, even if it is determined in step S321A that it is N (start winning memory) Even when the number is less than 4, the process of step S322A may be executed to read the count value latched in the latch circuit (however, steps S323A to S325A are not executed). By doing so, it is possible to prevent a situation in which processing such as jackpot determination is performed using a random number value based on an old count value latched at a timing other than the original latch timing.

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the first special figure reservation memory (step S324A), and adds 1 to the count number of the first start winning counter. The first start winning memory number is increased by 1 (step S325A). In addition, when the first start winning memorized number does not reach 4 in step S321A, the first special symbol “first” is displayed in numerical order in the buffer area in which the special symbol variation order (1 to 8) can be specified. Set the data.

  Note that if the first start winning memory has reached the maximum value of 4 in step S321A, the first start port switch passing process is terminated as it is.

  Next, the second start port switch passage process will be described with reference to FIG. In the second start port switch passing process executed when the second start port switch 15a is in the ON state, the CPU 56 of the game control microcomputer 560 has a second start winning memorize number (or a second start memorizing memory counter). It is confirmed whether or not the second starting prize storage number stored in the second special figure holding memory has reached the maximum value of 4 (step S321B). If the second start winning storage number has not reached 4, the CPU 56 reads the random R value stored as the random value from the random value storage circuit of the random number circuit 503 (step S322B). Further, the CPU 56 stores the read random R value in a storage area (second special symbol determination buffer (second special symbol holding memory)) corresponding to the value of the number of start winning memories (step S323B). In this embodiment, the random number circuit 503 inputs an input signal from the second start port switch 15a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random value storage circuit (latch circuit) at the timing when the input signal is input from the second start port switch 15a. Then, the CPU 56 reads the value latched in the random value storage circuit of the random number circuit 503 as a random R in step S322B.

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area at the head of the empty entry in the second special figure reservation memory (step S324B), and adds 1 to the count number of the second start winning counter. The second start winning memory number is increased by 1 (step S325B). In addition, when the second start winning memorized number does not reach 4 in step S321B, the second special symbol “second” is displayed in numerical order in the buffer area in which the special symbol variation order (1 to 8) can be specified. Set the data.

  If the second start winning memory has reached the maximum value of 4 in step S321B, the second start port switch passing process is terminated as it is.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 67 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300). (Step S380), it is determined whether the first set data of the buffer area that can specify the variation order of the special symbol is “first” or “second”. The value of random R stored in correspondence with the holding number “1” is read from the first special figure holding memory, and in the case of “second”, the second special figure holding memory corresponds to the holding number “2”. The stored random R value is read (step S381). In this case, the CPU 56 shifts the data stored in order in the buffer area in which the change order of the special symbol can be specified one by one, and stores the reserved symbol by subtracting one from the count number of the corresponding start winning counter. Decrease the number by 1 and increase the value of random R stored in the second to fourth entries (holding numbers “2” to “4”) of the first special figure holding memory or the second special figure memory by one entry. (Step S382).

  In this embodiment, the change of the special symbol corresponding to the first set data of the buffer area in which the change order of the special symbol can be specified is started. When “1” and “second” are set, the variation of the second special symbol may be started with priority over the variation of the first special symbol.

  Further, the CPU 56 checks whether or not the probability variation flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the certain change state. When the probability variation flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability variation state, and determines whether or not the display result of the special symbol display 8a or the second special symbol display 8b is a big hit symbol. A normal jackpot determination table 571a (see FIG. 19A) is set as a table used to determine whether or not (step S384). When the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and determines whether or not the display result of the first special symbol display 8a or the second special symbol display 8b is a jackpot symbol. As a table used to determine whether or not, a probability change big hit determination table 571b (see FIG. 19B) is set (step S385).

  The CPU 56 determines whether or not the display result of the first special symbol display 8a or the second special symbol display 8b is to be a big hit symbol based on the random R value stored in the predetermined buffer area in the start port switch passing process. Is determined (step S386). In this case, the CPU 56 uses the normal-time big hit determination table 571a set in step S384 or the probability change big hit determination table 571b set in step S385 to determine whether or not to win.

  When determining that the display result of the first special symbol display 8a or the second special symbol display 8b is a big hit symbol, the CPU 56 turns on a big hit flag indicating that it is a big hit state (step S387). If it is determined that the display result of the first special symbol display 8a or the second special symbol display 8b is not to be a big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the variation time setting process (step S389).

  Although not shown in FIG. 67, in the special symbol normal processing, the display result of the first special symbol indicator 8a or the second special symbol indicator 8b is to be a big hit symbol (to be a big hit). When the determination is made, the CPU 56 also determines the big hit type (for example, the probability variation big hit, the normal big hit, or the sudden probability variation big hit) based on the random number for determining the big hit type. Then, the CPU 56 sets a value corresponding to the result of the jackpot determination or the determination result of the jackpot type in the jackpot symbol determination buffer formed in the RAM 55. For example, “1” is set for a normal big hit, “2” is set for a probable big hit, and “3” is set for a sudden probable big hit. Further, the CPU 56 performs control to transmit a display result designation command capable of specifying the determined display result to the effect control microcomputer 100.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch has been turned ON, and processing corresponding to the switch ON is started. FIG. 68 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer for storing the contents of the ports 0 and 1 input this time. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. The previous port buffer, port buffer, and switch-on buffer shown in FIG. 68 are prepared for each of the input ports 0 and 1. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 1 is the switch-on buffer 2. Set to

  FIG. 69 is a flowchart illustrating a processing example of the switch processing in step S21 in the game control processing. In the switch process, the game control microcomputer 560 first inputs data input to the input ports 0 and 1 (see FIG. 21) (step S101), and sets the input data in the port buffer (step S102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter reaches 0, the data of the input ports 0 and 1 are input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normal / abnormal check process (step S113).

  FIG. 70 is a flowchart showing a switch normal / abnormal check process. In the switch normal / abnormal check process shown in FIG. 70, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 1 (step S121). Then, it is confirmed whether or not the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (step S122). That is, it is confirmed whether or not the first start port switch 14a (proximity switch) provided in the first winning path 1360a of the first start winning port 13a is turned on (detects a game ball).

  When the value of bit 0 corresponding to the first start port switch 14a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first start port switch 14a is in the on state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S123).

  Further, the CPU 56 checks whether or not the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (step S124). That is, it is confirmed whether or not the first winning confirmation switch 14b (photo sensor) provided in the first winning passage 1360b of the first starting winning opening 13a is turned on (detects a game ball).

  When the value of bit 1 corresponding to the first winning confirmation switch 14b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the first winning confirmation switch 14b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S125).

  Further, the CPU 56 checks whether or not the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (step S126). That is, it is confirmed whether or not the second start port switch 15a (proximity switch) provided in the second winning path 1370a of the second start winning port 13b is turned on (detects a game ball).

  When the value of bit 2 corresponding to the second start port switch 15a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second start port switch 15a is in the ON state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S127).

  Further, the CPU 56 checks whether or not the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (step S128). That is, it is confirmed whether or not the second winning confirmation switch 15b (photo sensor) provided in the second winning passage 1370b of the second start winning opening 13b is turned on (detects a game ball).

  When the value of bit 3 corresponding to the second winning confirmation switch 15b in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the second winning confirmation switch 15b is in the ON state), it is formed in the RAM 55. The value of the switch counter is decreased by 1 (step S129).

  Further, the CPU 56 checks whether or not the value of the bit 4 corresponding to the count switch 23 in the switch-on buffer corresponding to the input port 1 is 0 (step S130). That is, it is confirmed whether or not the count switch 23a (proximity switch) provided in the big winning passage 1403 of the big winning opening 23b is turned on (detects a game ball).

  When the value of bit 4 corresponding to the count switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the count switch 23a is in the on state), the switch counter formed in the RAM 55 Is incremented by 1 (step S131).

  Further, the CPU 56 checks whether or not the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (step S132). That is, it is confirmed whether or not the third winning confirmation switch 23a (photo sensor) provided in the large winning passage 1403a of the large winning opening 23b is turned on (detects a game ball).

  When the value of bit 5 corresponding to the third winning confirmation switch 23a in the switch-on buffer corresponding to the input port 1 is 0 (that is, when the third winning confirmation switch 23a is in the ON state), it is formed in the RAM 55. The value of the switch counter that has been set is decremented by 1 (step S133).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S134). When the value of the switch counter is equal to or greater than the predetermined value, the CPU 56 has determined that an abnormal winning has occurred in any of the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23. The predetermined time (4 minutes in this example) is set in the security signal information timer (step S135). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the value of the switch counter has become 15 or more as a predetermined value. To do. In this embodiment, the information output process (see S31) is executed based on the setting of the predetermined time in the security signal information timer in step S135, whereby the first start winning opening 13a and the second start winning prize are obtained. When an abnormal winning is detected at the mouth 13b and the special winning opening 23, a security signal is externally output for a predetermined time (in this example, 4 minutes).

  In the process of step S134, for example, the CPU 56 detects an abnormality in the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23 based on the fact that the value of the switch counter becomes 10 or more. In addition to determining that a winning has occurred, the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23 are also determined based on the fact that the value of the switch counter becomes -10 or less. It may be determined that an abnormal prize has been won. In this case, if the switch counter value is configured so that it cannot be recognized that the value is negative, for example, 10 is set as the default value of the switch counter value. Based on the fact that the counter value becomes 0 or 20 or more, it may be determined that an abnormal winning has occurred in the first starting winning port 13a, the second starting winning port 13b, or the big winning port 23. .

  In this embodiment, even if a value is already set in the security signal information timer and the security signal is being output to the outside, if a new abnormal winning is detected, the process of step S127 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

  In this embodiment, the case where the abnormal winning to the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23 is detected using only one switch counter is shown. The number of detections of the start opening switch 14a and the number of detections of the first winning confirmation switch 14b or the number of detections of the second starting opening switch 15a and the number of detections of the second winning confirmation switch 15b or the number of detections of the count switch 23 and the third winning confirmation switch Different switch counters may be used depending on the number of detections 23b. In this case, for example, the value of the first switch counter is incremented by 1 each time the on state of the first start port switch 14a is detected, and every time the on state of the first winning confirmation switch 14b is detected. What is necessary is just to add 1 to the value of the counter for two switches. In step S134, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is greater than or equal to a predetermined value (for example, 15), the first start winning award 13a is entered. It may be determined that an abnormal winning is generated, and the process of step S135 is executed to output the security signal to the outside.

  If it is detected that an abnormal winning has occurred at the first start winning opening 13a, the processing of step S135 is executed to output a security signal to the outside, and a predetermined error notification command is sent to the effect control microcomputer. It is desirable that error notification can be performed by displaying a predetermined error screen on the effect display device 9 on the effect control microcomputer 100 side.

  Further, for example, in addition to abnormal winning at the first start winning opening 13a, the security signal is also detected when abnormal winning at the other winning openings 29a and 29b, abnormal magnetic error, abnormal radio wave error, or communication error is detected. When configured to output, a different error notification command for each type of error may be transmitted to the effect control microcomputer 100. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  71 and 72 are explanatory diagrams for explaining the switch normal / abnormality check processing. Of these, FIG. 71 shows an example of the switch normality / abnormality check process in a normal state, and FIG. 72 shows an example of the switch normality / abnormality check process when an illegal act leading to an abnormal winning is performed. Show.

  As shown in FIG. 71 and FIG. 72, for example, bit 0 of the switch-on buffer corresponding to input port 1 indicates that a game ball is detected by the first start port switch 14a (proximity switch) corresponding to bit 0. 0 ”. The bit 1 of the switch-on buffer corresponding to the input port 1 becomes “0” when a game ball is detected by the first winning confirmation switch 14 b (photo sensor) corresponding to the bit 1. If the switch is operating normally and has not received any fraudulent activity (an act of illegally turning on a detection signal from the switch or illegally turning on an on-state detection signal), the first Since the start opening switch 14a is disposed upstream of the first winning confirmation switch 14b, the first starting opening switch 14a (proximity switch) is first turned on, and then the first winning confirmation switch 14b (photo sensor). ) Should turn on. Accordingly, the value of the switch counter is first incremented to 1 based on the first start port switch 14a being turned on (see step S123), and then the switch is based on the first winning confirmation switch 14b being turned on. The counter value is decremented by 1 and returned to 0 (see step S125). Therefore, when the game ball passes through the switch, both the bit 0 and the bit 1 of the switch-on buffer corresponding to the input port 1 become “0”, and if it is in a normal operation state, the timing is shifted to the count-up timing ( However, as shown in FIG. 71, the value of the switch counter should be kept at zero.

  However, when a fraudulent act by radio waves is performed, as shown in FIG. 72, the off state is illegally interrupted by radio waves during the period when the first start switch 14a is turned on once, and the There is a possibility that an illegal act of recognizing the starter switch 14a as if it has been turned on twice is performed. Therefore, although the first start port switch 14a is turned on only once, it is misrecognized that the first start port switch 14a is turned on twice, and the value of the switch counter is 2 in total. It is added to 2 (step S123 is executed twice). On the other hand, the first winning confirmation switch 14b arranged on the downstream side is different in detection method from the electromagnetic first start port switch 14a, and uses an optical photosensor. Unaffected by actions. Therefore, as shown in FIG. 72, when one game ball is detected by the first start opening switch 14a, when the game ball is detected by the first winning confirmation switch 14b after a short delay, the first winning game is normally completed. The ON state of the confirmation switch 14b is detected only once, and the value of the switch counter is decremented by 1 to 1 (see step S125). Therefore, when a fraudulent act by radio waves is performed, there is a difference in the number of detections between the first start opening switch 14a and the first winning confirmation switch 14b having different detection methods, and as shown in FIG. On the other hand, based on the fact that the value of the switch counter is not maintained at 0 and the value of the switch counter is equal to or greater than a predetermined value (15 in this example) (the first start port switch 14a and the first prize confirmation switch 14b). Based on the fact that the cumulative value of the detection error between the first and second winning prizes is equal to or greater than a predetermined value (15 in this example), it is possible to detect that an abnormal winning at the first start winning opening 13a has occurred.

  Here, an example is shown in which an abnormal winning to the first starting winning opening 13a is detected based on the detection result of the first starting opening switch 14a and the detection result of the first winning confirmation switch 14b. Based on the detection result of the switch 15a and the detection result of the second winning confirmation switch 15b, it is possible to detect an abnormal winning to the second start winning opening 13b. Further, it is possible to detect an abnormal winning to the big winning opening 23b based on the detection result of the count switch 23 and the detection result of the third winning confirmation switch 23a.

  In addition, it is also conceivable that a similar illegal act is performed by an act of illegally irradiating light. In this case, during the period when the first winning confirmation switch 14b is turned on once, an illegal act that causes the off state to be illegally interrupted by light and to recognize that the first winning confirmation switch 14b is turned on twice. May be done. However, in this case, on the contrary, since the electromagnetic first start port switch 14a side can normally detect the game ball without being affected by the illegal act of light, the value of the switch counter is kept at 0 similarly. The cumulative value of the detection error between the first start port switch 14a and the first winning confirmation switch 14b is a predetermined value based on the fact that the value of the switch counter is not less than a predetermined value (15 in this example). It is possible to detect that an abnormal winning to the first start winning opening 13a has occurred (based on the fact that it is 15 or more in this example).

  In this embodiment, the outputs of the first start opening switch 14a and the first winning confirmation switch 14b are negative logic, but the outputs of the first starting opening switch 14a and the first winning confirmation switch 14b are shown. May be configured to be positive logic. In this case, for example, the output levels of the first start port switch 14a and the first winning confirmation switch 14b are logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  Further, in this embodiment, the value of the switch counter is not kept at 0 (a detection error has occurred between the first start port switch 14a and the first winning confirmation switch 14b) and immediately. It is not determined that an abnormal winning has occurred, but it is determined that an abnormal winning has occurred based on the value of the switch counter being equal to or greater than a predetermined value (15 in this example). Such a configuration prevents, for example, a case where a game ball has become clogged in the first start winning opening 13a from being determined as an abnormal winning due to an illegal act.

  FIG. 73 (a) is an explanatory diagram showing a case where a game ball has a clogged state in the first winning paths 1360a and 1360b through which the game ball won in the first start winning opening 13a passes. As shown in FIG. 73 (a), in the first winning passages 1360a and 1360b, the first start port switch 14a and the first winning confirmation switch 14b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the first start winning opening 13a is first detected by the first start opening switch 14a, and then detected by the first winning check switch 14b on the downstream side after a while. Therefore, when a game ball is jammed in the first winning passages 1360a and 1360b, the number of detections depends on the physical distance difference between the first start opening switch 14a and the first winning confirmation switch 14b. A difference occurs. In the first winning passages 1360a and 1360b, a maximum of nine detection errors occur between the first start port switch 14a and the first winning confirmation switch 14b.

  FIG. 73 (b) is an explanatory diagram showing a case where the game ball is in a clogged state in the second winning path 1370a, 1370b through which the game ball won in the second start winning opening 13b passes. As shown in FIG. 73 (b), in the second winning passages 1370a and 1370b, the second start port switch 15a and the second winning confirmation switch 15b are arranged at a certain distance in the vertical direction. Therefore, the game ball won in the second start winning opening 13b is first detected by the second start opening switch 15a, and then detected by the second winning check switch 15b on the downstream side after a while. Therefore, when the game ball is clogged in the second winning passages 1370a and 1370b, the number of detections depends on the physical distance difference between the second start opening switch 15a and the second winning confirmation switch 15b. A difference occurs. In the second winning passages 1370a and 1370b, a maximum of two detection errors occur between the second start port switch 15a and the second winning confirmation switch 15b.

  FIG. 73 (c) is an explanatory diagram showing a case where a game ball has become jammed in the big winning paths 1403 and 1403a through which the game ball won in the big winning opening 23b passes. As shown in FIG. 73 (c), the count switch 23 and the third winning confirmation switch 23a are arranged at a certain distance from side to side and front and rear in the big winning paths 1403 and 1403a. For this reason, the game ball won in the big winning opening 23b is first detected by the count switch 23, and then detected by the third winning check switch 23a on the downstream side after a while. Therefore, when the game ball is clogged in the big winning passages 1403 and 1403a, the difference in the number of detections is caused by the physical distance difference between the count switch 23 and the third winning confirmation switch 23a. It becomes a state. In the big winning paths 1403 and 1403a, a maximum of four detection errors occur between the count switch 23 and the third winning confirmation switch 23a.

  In the present embodiment, the value of the switch counter is an upstream proximity switch (a first winning path 1360a, 1360b, a second winning path 1370a, 1370b, and a large winning path 1403, 1403a). 14a, 15a, 23) and the first start in a ball clogged state in the first winning path 1360a, 1360b, which is the winning path having the largest physical distance difference between the downstream photosensors (14b, 15b, 23a). It is determined that an abnormal winning has occurred based on the fact that the detection error between the mouth switch 14a and the first winning confirmation switch 14b is greater than or equal to a predetermined value (15 in this example) with a sufficient margin. The first prize passages 1360a and 1360b, the second prize passages 1370a and 1370b, and the big prize passages 1403 and 1403a Etc. If the game ball caused the ball clogging state either is prevented from determining that an abnormality winning Fraud.

  In this embodiment, the predetermined value (15 in this example) is not less than a predetermined value with a sufficient margin for nine detection errors between the first start opening switch 14a and the first winning confirmation switch 14b in the ball jammed state. Although the case where it is determined that an abnormal winning has occurred based on the above is shown, the predetermined value used for determining the abnormal winning is not limited to that shown in this embodiment. For example, it is possible to prevent erroneous determination of an abnormal winning if the number is more than nine detection errors between the first start opening switch 14a and the first winning confirmation switch 14b in a ball jammed state. Alternatively, it may be determined that an abnormal winning has occurred based on the value of the switch counter being 10 or more.

  In addition, when the detection errors in the ball clogged state in a plurality of winning paths are the same number (for example, 3), the detection error has become a predetermined value (for example, 10) or more with a sufficient margin for the three detection errors. Based on the above, it may be determined that an abnormal winning has occurred.

  In addition, when it is configured to be able to detect abnormal winnings in a plurality of winning aisles, there are more than the total number of detection errors (9 + 2 + 4 = 15) in the ball clogged state in all these winning aisles. If the abnormal winning is determined using the number (for example, 20) as the predetermined value, it is possible to prevent the abnormal winning from being erroneously determined.

  In the present embodiment, the detection error in the ball clogged state in the plurality of winning paths can be detected by one switch counter, so that no switching counter corresponding to each winning path is provided. However, it was possible to detect abnormal winnings in each winning path, but provided a switch counter corresponding to each winning path, set a predetermined value corresponding to the detection error for each winning path, The detection error in the switch counter may be monitored to determine whether or not there is an abnormal prize. By doing in this way, it becomes possible to specify in which winning path the winning abnormality has occurred.

  FIG. 74 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 74, in this embodiment, from the gaming control microcomputer 560 mounted on the main board 31 to the terminal board 160, the start port signal, the symbol determination number of times 1 signal, the jackpot 1 signal, the jackpot Two signals, three jackpot signals, a time reduction signal, and a security signal are output by information output processing (see step S31) on the game control microcomputer 560 side. In this embodiment, a prize ball signal 1 and a gaming machine error status signal are sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. Is output by the information output process (see step S759) on the payout control microcomputer 370 side.

  The starting port signal is a signal for notifying the number of winnings to the first starting winning port 13a and the second starting winning port 13b. The symbol determination number 1 signal is a signal for notifying the number of changes in the special symbol. The jackpot 1 signal is a signal for notifying that the jackpot game is in progress (during the operation of the special variable winning ball apparatus). The jackpot 2 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) or that the special symbol variation time shortening function is in operation (during the short-time state). The jackpot 3 signal is a signal for notifying that a 15-round jackpot game is in progress. The time reduction signal is a signal for notifying that the special symbol variation time reduction function is operating (in the time reduction state).

  The security signal is a signal indicating the security state of the gaming machine. Specifically, based on the detection result of the first start opening switch 14a and the detection result of the first winning confirmation switch 14b, it is determined that an abnormal winning to the first start winning opening 13a has occurred, or the first 2 If it is determined that an abnormal winning to the second start winning opening 13b has occurred based on the detection result of the start opening switch 15a and the detection result of the second winning confirmation switch 15b, or the detection result of the count switch 23 Based on the detection result of the third winning confirmation switch 23a, when it is determined that an abnormal winning to the big winning opening 23b has occurred, a security signal is sent to an external device such as a hall computer for a predetermined period (for example, 4 minutes). Is output. Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only abnormal winning to the first starting winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b, but abnormal winning to the normal winning openings 29 and 30 can be detected and output as a security signal. You may comprise as follows. Also, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine, or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, the security signal can be output externally. Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. In this way, even if there is an abnormal winning entry, abnormal magnetic error, or abnormal radio wave error at the special winning opening, if it is configured so that it can be externally output as a security signal from the common connector CN7 of the terminal board 160, even one signal line can be connected. In this case, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In addition, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the security signal can be externally output from the common connector CN7 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN7 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any of the error bits of bits 0 to 4 of the status register A of the serial communication circuit 505 being set. The security signal may be externally output from the common connector CN7 of the terminal board 160.

  In addition to the signal line and connector CN7 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The prize ball signal 1 is a signal output every time one prize ball payout is detected. Further, the gaming machine error state signal is a signal indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). Instead of outputting the prize ball signal 1 to the outside every time one prize ball is detected, a certain prize ball signal is outputted every time a predetermined number (for example, 10) of prize balls is detected. Also good.

  75 to 78 are flowcharts showing the information output processing in step S31. Of the processes shown in FIGS. 75 to 78, steps S1002 to S1030 are processes for outputting the start port signal, and steps S1031 to S1036 are processes for outputting the symbol determination number 1 signal. S1050 to S1068 are processes for outputting one jackpot signal, two jackpot signals, three jackpot signals and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal.

  In the information output process, the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1001). Then, the address of the start port information setting table is set in the pointer (step S1002), and the number of processes pointed to by the pointer is loaded (step S1003). The number of processes (= 1) and the start port switch input bit (start port switch input bit determination value (01 (H)) are set in the start port information setting table. In step S1003, the pointer is set to the start port information setting. Since the address of the number of processes in the table is indicated, the data of the number of processes (= 1) in the start port information setting table is loaded.If the gaming machine has two start winning ports, In the start port information setting table, 2 may be set as the number of processes, and start port switch input bits for the two start winning ports may be set respectively.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). When the content of the switch-on buffer is 01 (H), that is, when the first start port switch 14a or the second start port switch 15a is on, the logical product operation result is 01 (H). When the first start port switch 14a or the second start port switch 15a is not turned on, the logical product operation result is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the result of the logical product is not 0 (N in step S1009), it is determined that a winning has occurred in the first starting winning port 13a or the second starting winning port 13b, and the starting port information storage counter is loaded into the register. (Step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine has only one first start winning opening 13a, 1 is set as the initial value of the number of processes, and it is always determined that the number of processes is 0 in step S1016. Will be.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 loads the start port information storage timer (step S1017), and reflects the state of the start port information storage timer in the flag register. (Step S1018), it is determined whether or not the start port signal is being output (step S1019). The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 200 ms and an off time of 200 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output.

  If the start port signal is being output (Y in step S1019), the process proceeds to step S1026. If the start port signal is not being output (N in step S1019), the CPU 56 loads the start port information storage counter (step S1020), and reflects the state of the start port information storage counter in the flag register (step S1021). Then, it is determined whether there is a remaining number of output times of the start port signal (step S1022). When the first start port switch 14a or the second start port switch 15a is turned on (N in step S1009), since the start port information storage counter is incremented by 1, there is a remaining number of output times of the start port signal. It will be determined.

  If there is no remaining number of output times of the start port signal (Y in step S1022), the process proceeds to step S1031. If there is a remaining number of output times of the start port signal (N in Step S1023), the CPU 56 subtracts 1 from the start port information storage counter (Step S1023), and the calculation result (the result of subtracting 1) is the start port information storage counter. (Step S1024). Then, the winning information operating time (100) is set in the register (step S1025). The winning information operating time (100) is a time for which a 4 ms timer interruption is executed 100 times, that is, a time of 0.400 seconds (400 ms).

  Next, if the winning information operating time is not set in step S1025, the CPU 56 subtracts 1 from the start port information storage timer, and if the winning information operating time is set in step S1025, the CPU 56 subtracts 1 from the winning information operating time. (Step S1026). Then, the calculation result (the result obtained by subtracting 1) is stored in the start port information storage timer (step S1027).

  The CPU 56 compares the calculation result with the winning information on time (50) (step S1029), and determines whether the calculating result is shorter than the winning information on time (step S1030). The winning information on time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms).

  If the calculation result is not shorter than the winning information on time, that is, if the calculation result (remaining time of the start port 1 information storage timer) is longer than the winning information on time (200 ms) (N in step S1029) The CPU 56 sets the start port output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 20) (step S1030). When the start port output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Will be output.

  By the processing of steps S1001 to S1030 described above, winning to the first starting winning opening 13a (turning on the first starting opening switch 14a) or winning to the second starting winning opening 13b (turning on the second start opening switch 15a) ) Occurs, a start port signal is output. That is, after the start port signal is turned on for 200 ms, it is turned off for 200 ms. By inputting this start port signal to the hall computer, it is possible to recognize the number of winnings to the first start winning port 13a or the second starting winning port 13b.

  Since the start port signal is turned on for 200 ms and then turned off for 200 ms, the next start port is turned on after the 200 ms off state even if a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output at intervals of at least 200 ms.

  Thus, since the start port signals are output at intervals of at least 200 ms, the hall computer can reliably grasp the total number of start winnings.

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation process (see step S302), when the variation time times out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0). .500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value of the 1 information timer is 0), it is determined that the symbol determination number 1 information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 1 of output port 1 in the example shown in FIG. 20) is set (step S1036). When the symbol determination number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  By the processing of steps S1031 to S1036 described above, every time the change of the special symbol is stopped (stopped symbol is fixed), the symbol determination number 1 signal is turned on.

  Next, the CPU 56 loads the special symbol process flag (step S1050), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1051), and the special symbol process flag. It is determined whether the value of is less than 4 (step S1052). When the value of the special symbol process flag is less than 4 (Y in step S1052), the process proceeds to step S1058. When the value of the special symbol process flag is 4 or more (N in step S1052), the output bit position of the big hit in the information buffer is set (step S1053). Further, the big output 2 output bit position of the information buffer is set (step S1054). When one output bit position of jackpot and two output bit positions of jackpot of the information buffer are set, the information buffer is set to an output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 executes a time reduction check process for confirming whether or not it is in the time reduction state (step S1058), and determines whether or not it is in the time reduction state (step S1059). Specifically, the CPU 56 determines whether or not it is in the time reduction state by checking whether or not the time reduction flag that is set when shifting to the time reduction state is set. If the time-short state is set (Y in step S1059), the time-short output bit position of the information buffer is set (step S1060). When the time-short output bit position is set, the time buffer signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102 and outputting the output value to the output port 1 in step S1103. (Turns on) Also, the big output 2 output bit position of the information buffer is set (step S1061). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, whereby the jackpot 2 signal is output from the output port 1. (Turns on).

  In addition, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“4”) (step S1063), and sets the special symbol process flag. It is determined whether or not the value is less than 4 (step S1064). When the value of the special symbol process flag is less than 4 (Y in step S1064), the process proceeds to step S1069. When the value of the special symbol process flag is 4 or more (N in step S1064), the contents of the big hit symbol determination buffer are loaded (step S1065), and it is confirmed whether or not it is a big hit of 15 rounds (step S1067). . Whether or not it is a big hit of 15 rounds can be determined, for example, by confirming the contents of the big hit symbol determination buffer set in the special symbol normal process. For example, the jackpot symbol determination buffer stores the contents of the jackpot type determined by the special symbol normal processing and the contents indicating the jackpot determination result. “3” is suddenly a big hit. If the contents of the big hit symbol determination buffer are “1” or “2”, it is determined that the number of rounds at the big hit is 15 rounds. In this case, the big output 3 output bit position of the information buffer is set (step S1068). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, so that the jackpot 3 signal is output from the output port 1. (Turns on).

  By the processing of steps S1050 to S1068 described above, one big hit signal, two big hit signals, three big hit signals, and a short time signal are output (turned on) according to the type of big hit and the gaming state.

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, it is determined that the detection difference between the start port switches 14a, 14b and the count switch 23 and the first to third winning confirmation switches 14b, 15b, 23a has reached a predetermined value (15 in this example) or more. If it is determined that an abnormal winning at the start winning opening or the big winning opening has occurred, a predetermined time (4 minutes in this example) is set in the security signal information timer (step S126 in the switch normal / abnormal check process). , S127), when the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  In this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of output port 1 in the example shown in FIG. 20) is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102, and outputting the output value to the output port 1 in the step S1103. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  By the process of steps S1069 to S1074 described above, until 4 minutes have elapsed since the abnormal winning at the first starting winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b is detected, or to the gaming machine A security signal is output using the common connector CN7 of the terminal board 160 until 30 seconds elapse after the initialization process is executed at the start of power supply. When a new abnormal winning is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have passed since the last abnormal winning was detected.

  Next, the security signal output timing will be described. FIG. 79 is an explanatory diagram of security signal output timing. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), a predetermined time (in this example, 30 seconds) is set in the security signal information timer. Based on the above (see step S14a), the information output process (see step S31) performs the processes of steps S1069 to S1103, and from the connector CN7 of the terminal board 160 to the hall computer or the like as shown in FIG. A security signal is output to the external device. Further, after the power supply to the gaming machine is started, a detection error between the detection numbers of the start port switches 14a and 14b and the count switch 23 and the detection numbers of the first to third winning confirmation switches 14b, 15b and 23a is predetermined. Even when it is determined that an abnormal winning has occurred in the first starting winning port 13a, the second starting winning port 13b, or the big winning port 23b based on the value (15 in this example) or more (step) Steps S1069 to S1103 are performed in the information output process (see Step S31) based on the fact that a predetermined time (in this example, 4 minutes) is set in the security signal information timer (see S121 to S126). As shown in FIG. 79A, the connector CN7 of the terminal board 160 is connected to an external device such as a hall computer. Kyuriti signal is output. As described above, in this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, and abnormal winning to the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b. Is detected, a security signal is externally output from the common connector CN7 of the terminal board 160.

  Further, in this embodiment, when the security signal is being externally output, when an abnormal winning is newly detected in the first starting winning port 13a, the second starting winning port 13b, or the big winning port 23b, The output period of the security signal is substantially extended, and finally a predetermined time (in this example, 4 minutes) is detected from the time when an abnormal winning to the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b is detected. ) Will continue to output security signals. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. Security signal output should continue. However, as shown in FIG. 79 (B), even before 30 seconds have elapsed, the detected numbers of the start port switches 14a and 14b and the count switch 23 and the first to third winning check switches 14b, 15b, It is determined that the detection error with respect to the number of detections 23a is equal to or greater than a predetermined value (15 in this example) and an abnormal winning is generated in the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b. there is a possibility. In this case, a predetermined time (in this example, 4 minutes) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S127), and the information output process (step S31). Step S1069 to S1103 are executed, and the output of the security signal is continued as shown in FIG. 79B. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 79 (B), the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening The output of the security signal is continued until 4 minutes have elapsed from the time when the abnormal winning to 23b is detected, and the output of the security signal is substantially extended.

  Also, for example, when the output of the security signal is started based on the detection of the abnormal winning to the first starting winning port 13a, the second starting winning port 13b, or the big winning port 23b, FIG. 79 (A). As shown, in principle, the output of the security signal should continue until 4 minutes have passed. However, as shown in FIG. 79 (C), even before four minutes have elapsed, the numbers detected by the start port switches 14a and 14b and the count switch 23 and the first to third winning confirmation switches 14b, 15b, The detection error with respect to the number of detections of 23a becomes equal to or greater than a predetermined value (15 in this example), and an abnormal prize is newly generated to the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b. May be judged. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S127), and information output processing ( In step S31), the processing in steps S1069 to S1103 is executed, and the output of the security signal is continued as shown in FIG. 79C. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 79 (C), the first start winning opening 13a, the second starting winning opening 13b, The output of the security signal is continued until 4 minutes have elapsed from the time when the abnormal winning to the winning opening 23b is detected, and the output of the security signal is substantially extended.

  If an abnormal winning is detected in the first start winning port 13a, the second starting winning port 13b, and the big winning port 23b when the security signal is already being output, the output of the security signal being output is terminated. However, in this embodiment, as shown in FIG. 79 (B) and FIG. 79 (C), the security signal being output can be started again. By extending the output time as it is, the processing load for the security signal output process is reduced and the program capacity for the security signal output process is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. In contrast, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S127), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  In this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, a security signal is output for 30 seconds, and the first start winning opening 13a and the second starting winning opening 13b are output. In the case where an abnormal winning to the big winning opening 23b is detected, the case where the security signal is output for 4 minutes is shown. However, the output time of the security signal is not limited to that shown in this embodiment. . That is, it is possible to recognize whether the initialization process has been executed or whether an abnormal winning to the first start winning opening 13a, the second starting winning opening 13b, or the big winning opening 23b has been detected. If a security signal is output over a different output time between when the first start winning opening 13a, the second starting winning opening 13b, and the abnormal winning opening 23b are detected. Good.

  In this embodiment, the output period of the security signal when the abnormal winning to the first starting winning port 13a, the second starting winning port 13b, and the big winning port 23b is detected is set to 4 minutes. In the case of abnormal winning to the start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b, the settable substantially maximum time is set so as to output the security signal for as long as possible. . That is, in this embodiment, since the game control microcomputer 560 can set a 2-byte value as the value of the security signal information timer, the maximum value is set to “FFFF (H) = 65535 in the security signal information timer. "Can be set. Therefore, in this embodiment, “60000”, which is almost the maximum value, is set in the security signal information timer, and the timer interruption period is 4 ms. Therefore, security is performed for 4 ms × 60000 = 4 minutes. A signal is output.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 80 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 80, each phase signal supplied to the payout motor 289 by the stepping motor is output from the output port 0. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 81 is an explanatory diagram showing an example of bit allocation of input ports in the payout control means. As shown in FIG. 81, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 82 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 380. In this case, in this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interruption process includes a payout control process for controlling the payout means (including a process for driving the ball payout device 97 at least in response to a command signal relating to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the computer may be included).

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 83 is a flowchart showing an example of timer interruption processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the state of bits 0 to 7 (see FIG. 81) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. The payout control process to be performed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, display control processing for performing a predetermined display on the error display LED 374 according to the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. Then, in the display control process of step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the error bit being set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 84 is a flowchart showing the main control communication process in step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 85 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command reception process, the payout control CPU 371 first checks whether or not a connection signal is input (step S7401). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S7402). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is under an abnormal state. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S7403), and checks whether or not the value of the main control communication control code is a value “0” indicating the main control connection confirmation process. (Step S7404).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S7404, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, when the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S7404, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S7405). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. Then, the payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S7406). If it is determined in step S7404 that the value of the main control communication control code is “0” indicating the main control connection confirmation process, the process proceeds to step S7406).

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that a connection signal is not input in step S7401, if the main control connection confirmation process is not being executed in step S7404, the connection signal is not displayed after power is turned on to the gaming machine. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S7406), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S7407). For example, the payout control CPU 371 receives the serial communication circuit 380 if a flag indicating a parity error, framing error, noise error, overrun error, or idle line error is set in the status register of the serial communication circuit 380. It is determined that there is an error state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S7408). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S7409).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S7410) and checks whether or not a connection confirmation command is received (step S7411). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 43). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S7414.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 43, the content of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is greater than or equal to the prize ball number command minimum value “51 (H)” (step S7412). Next, if the prize ball number command minimum determination value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum determination value “60 (H)”. It is confirmed whether or not (step S7413). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S7414.

  In step S7414, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 86 is a flowchart showing a main control connection confirmation process (step S741) executed when the value of the main control communication control code is 0. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) to the main control communication control timer (step S7417).

  87 and 88 are flowcharts showing main control communication normal processing (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, the fact that the main control communication control timer has timed out in step S7402 means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S7409) elapses well after 1 second from the transmission of the connection OK command. This is a case where reception was not possible. For this reason, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S7403), and returns to the main control connection confirmation process to wait for the recovery of the communication state. To do.

  The payout control CPU 371 clears the main control communication reception buffer if the main control communication control timer has timed out in step S74202. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the connection OK command in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (a bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after one second has elapsed after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  89 and 90 are flowcharts showing the main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, a command for preparing the next prize ball is issued if it is not yet ready to start a prize ball payout operation after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (a bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer. This is to prevent inconveniences in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number reception command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparation command is transmitted.

  FIG. 91 is a flowchart showing a main control communication end process (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process executed after receiving the prize ball number command and starting the prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, based on the value set in step S74414, after the command for preparing a prize ball is transmitted, if the prize ball payout operation is not yet completed after another one second, the next command for preparing a prize ball is transmitted. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 92 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 93 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725, which will be described later, it is determined that a payout number abnormality error has occurred based on the value of the payout number abnormality counter being 2000 or less. Good.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc., so when an abnormality in the number of payouts is detected, it is immediately determined as a payout number error. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset, and the payout number error error is not recovered. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it has once been determined as a payout number abnormality error, and to reduce the processing burden.

  Further, in this embodiment, “2000” corresponding to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store is set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 93 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is counted up without distinguishing between the payout with the winning ball and the payout with the lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and a payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 94 is a flowchart showing the payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the processing of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit in the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75016). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of prize balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball paying-out operation designation bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 95 is a flowchart showing a payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 in the port 0 buffer corresponding to the output state), and the payout motor ball biting release processing (ball biting state is released) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used for setting a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7527). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  96 to 98 are flowcharts showing the payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and the process proceeds to step S75306. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process ends.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. Even if the operation is finished, the detection by the payout number count switch 301 is not determined). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred, and indicates a payout number error error indicating that a payout number error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, the accumulated number is immediately counted as a cumulative number in the payout number abnormality counter, and the frequency determined as a payout number abnormality error is increased more than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined as Y in step S7502 shown in FIG. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the process of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally even though the first re-payout operation is executed. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting a process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by error processing described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. FIG. 99 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 99, when no error has occurred, “−” is displayed on the error display LED 374. When the cumulative count value of the payout number abnormality counter becomes 2000 or more and a payout number error is detected, the payout control CPU 371 of the payout control microcomputer 370 displays an error display LED 374 as a payout number error. Control to display “A” on the screen. If a payout number abnormality error occurs, the error state is continued until the power supply of the gaming machine is reset.

  When the connection signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main board non-connection error. Do.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  When a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display “5” on the error display LED 374 as a main control communication error. .

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, or a main control communication error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes ON state) The payout control means returns to the state before the error occurred.

  As described above, the payout control CPU 371 specifically displays an error on the error display LED 374 in accordance with the relationship shown in FIG. 99 in the display control process of the timer interrupt process (see step S760). For example, the payout control CPU 371 generates a prepaid card unit unconnected error in the display control process based on the setting of the prepaid card unit unconnected state designation bit in the error process described later (see step S7729). An error display “8” indicating that is displayed on the error display LED 374 is controlled. Further, for example, based on the fact that the full error specification bit is set in the error processing (see step S7714), an error display “6” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  100 and 101 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. The other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the error recovery time is set in the pre-error recovery timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state.

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not set is reset. As described above, in this embodiment, when an error (see FIG. 99) that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit of the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 96 to 98). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if the prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When detected (see step S75314 and subsequent steps in FIGS. 96 to 98), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), step S7501 shown in FIG. S7502 and S7506 are executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-off number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  In addition, even when it is confirmed that a game ball has been paid out as a result of executing the re-payout process in the payout passing waiting process shown in FIGS. 96 to 98, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents continued for longer than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset to the payout control CPU 371) is performed by operating the error release switch 375. However, when such a gaming machine is configured, When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728), and if the VL signal is not input (if it is in the off state), the prepaid card unit error flag The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process in step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (a prepaid card unit unconnected error and a prepaid card unit communication error) and other errors (see FIG. 99). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  102 and 103 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (15 in this example) (step S7906). If it is equal to or greater than the predetermined prize ball information output determination value (15 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 decrements the prize ball information output timer by 1 (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball information output bit (bit 7; see FIG. 80) of the output port 1.

  Next, if the payout control CPU 371 is set, the prize ball signal 1 output timer is decremented by 1 (step S7915), and it is confirmed whether or not the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball signal 1 output bit (bit 0; see FIG. 80) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input to the terminal board 160 from the payout control board 31 and output to the outside, but is input to the terminal board 160 once through the main board 31. Is output externally.

  Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 80) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 31 to the terminal board 160 but externally output, but is input to the terminal board 160 once via the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 104 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101a) as effect control means mounted on the effect control board 80. The effect control CPU 101a starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) (step S781). . Thereafter, the effect control CPU 101a proceeds to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101a clears the flag (step S783) and executes the following effect control process.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs effect control process processing (step S785). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S786). Thereafter, the process proceeds to step S782.

  FIG. 105 is a flowchart showing a specific example of command analysis processing (step S784). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  In FIG. 105, the processing when the command indicating an error relating to payout control is received among the effect control commands transmitted from the game control microcomputer 560 is shown. Various effect control commands such as a variation pattern command indicating a variation pattern and a display result specifying command indicating a display result indicating whether or not to win are transmitted from the game control microcomputer 560.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets a prize ball error bit (bit 0, see FIG. 44) in the lower 4 bits of the frame state display command. It is confirmed whether it has been done (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1, see FIG. 44) of the lower 4 bits of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  In addition, the effect control CPU 101a checks whether or not the ball break error bit (bit 2, see FIG. 44) in the lower 4 bits of the frame state display command is set (step S619). If set, the effect control CPU 101a performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the payout number abnormality error bit (bit 3; see FIG. 44) of the lower 4 bits of the frame state display command is set (step S621). If set, the effect control CPU 101a performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball shortage error command (step S623), the effect control CPU 101a performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S623). S624). For example, the effect control CPU 101 a performs control to display a character string such as “There was a shortage of prize balls” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the effect control CPU 101 a performs control to display a character string such as “There was an excessive prize ball error” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is another command, the effect control CPU 101a sets a flag corresponding to the received effect control command (step S627). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101a also performs processing for storing the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 106 is a flowchart showing the effect control process (step S785) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is reached, after the variation time is over, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  As described above, according to this embodiment, the gaming control microcomputer 560 is informed that the initialization process has been executed when the gaming machine is powered on and that a predetermined error (in this example, the first Based on the fact that a predetermined signal output condition is established, including that it is determined that an abnormal winning to the starting winning port 13a, the second starting winning port 13b, and the big winning port 23b has occurred. Outputs a security signal. In this case, the game control microcomputer 560 has a common output terminal (a terminal board of the terminal board) provided in the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. A security signal is output from the common connector CN7). In addition, a predetermined signal output condition is newly established when the security signal is output (in this example, an abnormal prize is newly given to the first start winning opening 13a, the second starting winning opening 13b, and the big winning opening 23b. If detected, the output time for outputting the security signal is extended. Therefore, by outputting a security signal based on the execution of the initialization process, it is possible to prevent an illegal act performed when the gaming machine is powered on. In addition, since the security signal is output to the common output terminal when the initialization process is executed and when it is determined that a predetermined error has occurred, the waste of the signal line for external output is reduced. Can do. Therefore, it is possible to reduce the waste of the signal line for external output while preventing an illegal act performed when the power to the gaming machine is turned on.

  Further, Patent Document 1 describes that an illegal act (radio wave or the like) input to the winning switch is prevented from operating a safe sensor so that an illegal act can be detected. Specifically, the use of a pass-type safe sensor is described. However, Patent Document 1 shows that the winning switch and the safe sensor are operated simultaneously by strong radio waves, so that the winning switch and the safe sensor have different detection performances. The same type of safe sensor is used. Patent Document 1 shows that all winning switches and safe sensors are operated at the same time, and that it is determined that an illegal act has been received. The winning switch and the safe sensor do not always operate simultaneously. Depending on the strength of the radio wave, it is assumed that all winning switches and safe sensors may or may not operate simultaneously. That is, the method disclosed in Patent Document 1 is insufficient for detecting fraud.

  According to this embodiment, the game control microcomputer 560 is based on the detection signal input from the first start port switch 14a (proximity switch) and the detection signal input from the first winning confirmation switch 14b (photo sensor). Thus, the difference between the number of game balls detected by the first start opening switch 14a and the number of game balls detected by the first winning confirmation switch 14b exceeds a predetermined threshold (in this example, 15 or more). If it is determined that an abnormal prize has been generated at the first start winning opening 13a as a predetermined error. In this embodiment, the first start port switch 14a and the first winning confirmation switch 14b are configured by sensors of different detection methods (in this example, a proximity switch and a photo sensor). For this reason, it is possible to more reliably detect fraudulent acts with respect to the switch that detects the game ball, and to take certain measures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 executes the special symbol variation display based on only the input of the detection signal from the first start port switch 14a and performs the winning ball payout process. Execute. Further, the detection signal input from the first winning confirmation switch 14b is used only for determining whether or not an abnormal winning to the first start winning opening 13a has occurred. Further, based on only the detection signal input from the second start port switch 15a, the special symbol variation display is executed and the prize ball payout process is executed. Further, the detection signal input from the second winning confirmation switch 15b is used only for determining whether or not an abnormal winning has occurred in the second start winning opening 13b. Therefore, since the special symbol variation display and the prize ball payout process are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing burden accompanying the strengthening of countermeasures against fraud.

  Further, according to this embodiment, the game control microcomputer 560 determines the difference between the number of game balls detected by the first start port switch 14a and the number of game balls detected by the first winning confirmation switch 14b. However, as a predetermined threshold, the number of detected game balls in the first start opening switch 14a and the number of detected game balls in the first winning confirmation switch 14b when the inside of the first winning passages 1360a, 1360b is in a blocked state It is determined whether or not a value (15 in this example) greater than the difference (for example, 9) is exceeded. Therefore, when the inside of the first start winning opening 13a is in a clogged state, it can be prevented that it is erroneously determined that an abnormal winning to the first starting winning opening 13a has occurred. Accordingly, it is possible to prevent erroneous determinations associated with strengthening countermeasures against fraud.

  Further, according to this embodiment, the gaming control microcomputer 560 has a predetermined error (in this example, the first start winning award 13a, the first number) when the initialization process is executed when the gaming machine is turned on. 2) A security signal is output over a different period of time when it is determined that an abnormal winning to the start winning opening 13b and the big winning opening 23b has occurred. Specifically, in this embodiment, when the initialization process is executed when the power to the gaming machine is turned on, a security signal is output to the outside for 30 seconds, and the first start winning opening 13a, the second start When an abnormal winning is detected at the winning opening 13b and the big winning opening 23b, a security signal is externally output for 4 minutes. Therefore, by determining the output time of the security signal, it is possible to determine whether the initialization process has been performed or a predetermined error has occurred in an external device such as a hall computer. It becomes.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. Further, the payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and receives a prize ball preparation command during execution of the payout control. The signal is transmitted to the game control microcomputer 560 every signal output period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

  In addition, according to this embodiment, the game control microcomputer 60 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, etc.) based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 60 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. For this reason, it is possible to prevent the inconvenience of transmitting the award ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command transmission. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter that is counted up cumulatively. Can be stopped. Accordingly, it is possible to more accurately prevent an act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power supply of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game ball.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payout control microcomputer 370 can confirm the communication connection state at any timing, the payout of the prize ball is performed when the communication connection state is abnormal. This can be surely prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

  Next, a modified example of the physical configuration of the terminal board 160 mounted on the gaming machine will be described. 107 and 108 are explanatory diagrams showing modifications of the physical configuration of the terminal board 160. The gaming machine is provided with a cover member 800 for covering and protecting each board such as the main board 31, the effect control board 80, and the payout control board 37, for example, as shown in FIG. 107 and FIG. As described above, the terminal board 160 may be embedded in the cover member 800. Also, a terminal board cover 801 for covering and protecting the terminal board 160 is attached to a portion of the cover member 800 where the terminal board 160 is attached. Here, FIG. 107 shows a state where the terminal board cover 801 is attached to the cover member 800, and FIG. 108 shows a state where the terminal board cover 801 is removed from the cover member 800. As shown in FIG. 108, two terminal claws 801a are provided on the upper part of the terminal board cover 801, and the terminal board is secured by inserting the claws 801a and fastening them with screws 801b. A cover 801 can be attached.

  As shown in FIGS. 107 and 108, a plurality of terminals 96a, 96b, 98a, 98b,... For connecting cables with external devices such as hall computers are provided on the terminal board 160. A terminal board 900 is provided. Further, the terminal board 900 has a two-stage configuration including a terminal row including terminals 96a, 96b,... And a terminal row including terminals 98a, 98b,. One set (set of signal line and ground line). For example, in the example shown in FIGS. 107 and 108, one set of terminals 96a and 96b arranged in the horizontal direction among the terminals in the upper row of terminals is one set, and the horizontal direction of the terminals in the lower row of terminals. One set of the terminal 98a and the terminal 98b arranged in a row. Further, the terminals 96a, 96b, 98a, 98b,... Provided on the terminal board 900 are respectively provided with knobs 95a, 95b, 99a, 99b, and the knobs 95a, 95b,. The terminals 96a, 96b, 98a, 98b... Are opened by performing operations such as pressing 99a, 99b. For example, when the upper knob 95a is pressed, the cable can be connected to the terminal 96a, and when the lower knob 99a is pressed, the cable can be connected to the terminal 98a. For example, when the upper knob 95b is pressed, the cable can be connected to the terminal 96b, and when the lower knob 99b is pressed, the cable can be connected to the terminal 98b.

  As shown in FIGS. 107 and 108, the knobs 95a, 95b, 99a, 99b,... Provided for each of the terminals 96a, 96b, 98a, 98b,. Has been. With such a configuration, it is possible to prevent inconveniences such as accidentally operating the knob for the adjacent terminal, and improve workability when performing the work of connecting the cable to the terminal board 900. be able to.

  FIG. 109 is an explanatory diagram showing a cross-sectional structure of a portion of the cover member 800 where the terminal board 160 is attached. As shown in FIG. 109, the terminal board 160 is sufficiently placed so that the terminal board 900 provided on the terminal board 160 is located inside the surface of the cover member 800 (the X surface shown in FIG. 109). The cover member 800 is attached to the back side. As such, since the terminal board 900 provided on the terminal board 160 is configured to be inside the surface of the cover member 800 (the X surface shown in FIG. 109), the game ball is mistakenly played during the game. It is possible to prevent the occurrence of inconvenience such as contact with the terminal board 900.

  Further, as shown in FIG. 109, the terminal board cover 801 is inclined so that the side wall portion 801c is gradually narrowed. Since the side wall 801c is inclined as described above, even when the terminal board cover 801 is attached, it is easy for a finger or the like to enter, and when connecting the cable to the terminal board 900, Workability can be improved.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines, arrange ball gaming machines, and sparrow ball gaming machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 13a 1st start winning opening 13b 2nd starting winning opening 14a 1st start opening switch 14b 1st winning check switch 15a 2nd start opening switch 15b 2nd winning check switch 15 Variable winning ball apparatus 20 Special variable winning ball device 23 Count switch 23a Third winning confirmation switch 23b Large winning port 31 Game control board (main board)
37 Dispensing control board 56 CPU
80 effect control board 100 effect control microcomputer 370 payout control microcomputer 560 game control microcomputer

Claims (5)

A gaming machine having a plurality of winning holes through which a game medium can be won, and paying out a prize game medium as a prize based on the winning of the game medium in any one of the plurality of winning holes,
Each of the plurality of winning prize openings is
First detection means for detecting a game medium and outputting a first detection signal;
A second detection means for detecting a game medium and outputting a second detection signal;
An abnormality determining means for determining an award abnormality in the winning opening based on the first detection signal output from the first detection means and the second detection signal output from the second detection means;
Transition means for shifting to a predetermined error state based on the fact that the abnormality determination means has determined that a winning abnormality has occurred,
The first detection means and the second detection means are composed of sensors of different detection methods,
The abnormality determination means is detected by the first detection means based on the first detection signal output from the first detection means and the second detection signal output from the second detection means. When the difference between the number of played game media and the number of game media detected by the second detection means exceeds a predetermined threshold value, it is determined that a prize abnormality has occurred in the prize opening,
The predetermined threshold value is determined between the first detection means and the second detection means at the winning opening where the flow distance of the game medium from the first detecting means to the second detecting means is the longest among the plurality of winning holes. A value greater than the difference between the number of detected game media in the first detecting means and the number of detected game media in the second detecting means when a plurality of game media stays in between.
A gaming machine characterized by that. A collection road surface disposed at a position below the second detection means and for collecting the game medium that has passed through the second detection means;
A direction changing portion provided between the second detection means and the recovery road surface so as to be in contact with the game medium that has passed through the second detection means and capable of changing the flow direction of the game medium;
The gaming machine according to claim 1. A normal winning opening provided separately from the plurality of winning openings;
A normal winning detection means for detecting a game medium won in the normal winning opening;
Payout control execution means for performing control for paying out a prize game medium as a prize based on detection of the game medium by the normal winning detection means,
The gaming machine according to claim 1 or 2, characterized in that. Comprising a large winning device that constitutes a large winning port among the plurality of winning ports;
The big prize device is
Based on the establishment of a predetermined condition, a movable member movable between an open state in which a game medium can win a prize winning opening and a closed state in which a prize cannot be won,
Electromagnetic driving means for driving the movable member,
The detection method of the first detection means for detecting the game medium won in the big prize opening is an electromagnetic type.
On both sides of the movable member, the first detection means and the electromagnetic driving means are arranged apart from each other,
A gaming machine according to any one of claims 1 to 3. Comprising a large winning device that constitutes a large winning port among the plurality of winning ports;
The big prize device is
Based on the establishment of a predetermined condition, a movable member movable between an open state in which a game medium can win a prize winning opening and a closed state in which a prize cannot be won,
Drive means for driving the movable member;
A link member provided so as to be movable up and down around a predetermined rotation axis, and movable up and down in accordance with the drive of the drive means, thereby moving the movable member between the open state and the closed state;
The link member is supported so as to be movable up and down, and is provided with a support member formed so as to be fitted into an opening for mounting formed in the game board,
The link member is formed such that a dimension in a thickness width direction of the game board is shorter than a thickness width dimension of the game board,
The support member is formed with an opening capable of accommodating at least a part of the link member in the closed position or the open position.
The gaming machine according to any one of claims 1 to 4, characterized in that.

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