JP2011160508A - Switching power unit - Google Patents

Switching power unit Download PDF

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JP2011160508A
JP2011160508A JP2010018132A JP2010018132A JP2011160508A JP 2011160508 A JP2011160508 A JP 2011160508A JP 2010018132 A JP2010018132 A JP 2010018132A JP 2010018132 A JP2010018132 A JP 2010018132A JP 2011160508 A JP2011160508 A JP 2011160508A
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circuit
voltage
power supply
switching
rectifier circuit
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JP5154588B2 (en
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Mitsuru Watanabe
満 渡邊
Takashi Saito
隆 斎藤
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TDK Lambda Corp
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a long-life and compact switching power unit that reduces a loss of standby electric power, allows a drive circuit to properly change a rectification system of a rectifying circuit in response to an input voltage without using any high breakdown-voltage electrolytic capacitors. <P>SOLUTION: The switching power unit includes a triac 8 for switching whether the rectifying circuit 2 is operated by a voltage doubler rectifier system and the drive circuit 31 for drive to turn on or off the triac 8. The drive circuit 31 includes the rectifying circuit 32 for rectifying the input voltage Vin and a trigger generation circuit 38 for generating a trigger current for turning on or off the triac 8 with a rectifying output from the rectifying circuit 32 as a supply voltage. Rectifying output from the rectifying circuit 32 is taken in as it is as a supply voltage of the trigger generation circuit 38, and the triac 8 is driven by the trigger current generated by the trigger generation circuit 38. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、各種電気機器の入力自動切換回路に関し、特に異なる入力電圧を検出して、その入力電圧に対応するように整流回路の動作を切換え制御する入力自動切換回路を備えたスイッチング電源装置に関する。   The present invention relates to an input automatic switching circuit for various electrical devices, and more particularly to a switching power supply apparatus including an input automatic switching circuit that detects a different input voltage and switches and controls the operation of a rectifier circuit so as to correspond to the input voltage. .

現在、世界の商用電源は100V系と200V系の二地域に分けられている。こうした異なる地域の入力電圧を検出して、その入力電圧に対応するように整流回路の動作を切換え制御する入力自動切換回路が、例えば特許文献1や特許文献2などに開示されている。   Currently, the world's commercial power supply is divided into two regions, 100V and 200V. For example, Patent Literature 1 and Patent Literature 2 disclose an input automatic switching circuit that detects input voltages in different regions and controls switching of the operation of the rectifier circuit so as to correspond to the input voltages.

これらの特許文献1や特許文献2では、何れも整流回路が4つのダイオードをブリッジ接続したダイオードブリッジで構成され、整流回路の出力端間には、2つの平滑コンデンサを直列接続した平滑回路が設けられている。また、整流回路の一方の入力端と対をなす平滑コンデンサの接続点との間には、入力自動切換回路の切換え素子としてトライアック(双方向三端子サイリスタ)が接続され、100V系の入力電圧の場合には切換え素子をオンにして、整流回路を倍電圧整流方式にする一方で、200V系の入力電圧の場合には切換え素子をオフにして、整流回路を全波整流方式にすることで、平滑回路の両端間に常に所望の直流電圧を得るようにしている。   In these Patent Documents 1 and 2, the rectifier circuit is configured by a diode bridge in which four diodes are bridge-connected, and a smoothing circuit in which two smoothing capacitors are connected in series is provided between the output terminals of the rectifier circuit. It has been. Further, a triac (bidirectional three-terminal thyristor) is connected as a switching element of the input automatic switching circuit between the connection point of the smoothing capacitor paired with one input terminal of the rectifier circuit, and the input voltage of the 100V system is In this case, the switching element is turned on and the rectifier circuit is set to a voltage doubler rectification method. On the other hand, when the input voltage is 200V, the switching element is turned off and the rectifier circuit is set to a full-wave rectification method. A desired DC voltage is always obtained between both ends of the smoothing circuit.

特許文献1の入力自動切換回路は、切換え素子の駆動回路にオペアンプなどの比較器が組み込まれている。この比較器は、平滑回路の両端間電圧を分圧した検出用電圧と、駆動回路の内部で設定された基準電圧とを比較するもので、当該比較器の動作電圧や基準電圧を生成するために、交流入力電圧を直流に整流してこれを駆動回路の電源電圧とする制御電源が設けられている。   In the automatic input switching circuit of Patent Document 1, a comparator such as an operational amplifier is incorporated in a switching element drive circuit. This comparator compares a detection voltage obtained by dividing the voltage across the smoothing circuit with a reference voltage set inside the drive circuit, and generates an operating voltage and a reference voltage for the comparator. In addition, a control power source is provided which rectifies the AC input voltage into DC and uses this as the power source voltage of the drive circuit.

また、特許文献2の入力自動切換回路も、切換え素子の駆動回路に同等の機能を有するオペアンプが組み込まれており、ここでは交流入力電圧を直流に整流して駆動回路の電源電圧とするために、ダイオード整流器と電解コンデンサからなる整流平滑回路が駆動回路に設けられている。   In addition, the input automatic switching circuit of Patent Document 2 also includes an operational amplifier having an equivalent function in the drive circuit of the switching element. Here, in order to rectify the AC input voltage to DC and use it as the power supply voltage of the drive circuit. A rectifying / smoothing circuit including a diode rectifier and an electrolytic capacitor is provided in the drive circuit.

特許第3024330号公報明細書Japanese Patent No. 3024330 特開昭63−89061号公報JP-A-63-89061

しかし、上記従来技術では次のような問題がある。   However, the above prior art has the following problems.

特許文献1の入力自動切換回路では、交流入力電圧を直流化した電圧を、駆動回路の電源電圧としているため、電源電圧を生成する制御電源において常に固定の損失(待機電力)が発生する。   In the automatic input switching circuit of Patent Document 1, since a voltage obtained by converting an AC input voltage into a direct current is used as the power supply voltage of the drive circuit, a fixed loss (standby power) always occurs in the control power supply that generates the power supply voltage.

また、特許文献2の入力自動切換回路では、交流入力電圧の印加に耐え得る高耐圧の電解コンデンサを用いる必要があり、駆動回路における部品の大型化と寿命が問題となる。   Further, in the automatic input switching circuit of Patent Document 2, it is necessary to use an electrolytic capacitor having a high withstand voltage that can withstand the application of an AC input voltage, and there is a problem in increasing the size and life of components in the drive circuit.

そこで本発明は、待機電力の損失低減を図り、且つ高耐圧の電解コンデンサを用いることなく、入力電圧に対応して駆動回路が整流回路の整流方式を適正に切り換えることができ、長寿命化および小型化が可能なスイッチング電源装置を提供することを、その目的とする。   Therefore, the present invention aims to reduce standby power loss and to appropriately switch the rectification method of the rectifier circuit in response to the input voltage without using a high-voltage electrolytic capacitor, thereby extending the life and It is an object of the present invention to provide a switching power supply device that can be miniaturized.

本発明のスイッチング電源装置は、上記目的を達成するために、交流電源からの入力電圧を整流する第1の整流回路に接続され、前記第1の整流回路を倍電圧整流方式で動作させるか否かを切換える切換え素子と、前記切換え素子をオンまたはオフに駆動する駆動回路と、を備えた入力自動切換回路において、前記駆動回路は、前記入力電圧を整流する第2の整流回路と、この第2の整流回路からの整流出力を電源電圧として、前記切換え素子をオンまたはオフにする駆動信号を生成する信号生成回路と、を備えている。   In order to achieve the above object, the switching power supply device of the present invention is connected to a first rectifier circuit that rectifies an input voltage from an AC power supply, and whether or not the first rectifier circuit is operated in a voltage doubler rectification system. In the automatic input switching circuit comprising a switching element for switching between and a drive circuit for driving the switching element on or off, the drive circuit includes a second rectifier circuit for rectifying the input voltage, And a signal generation circuit for generating a drive signal for turning on or off the switching element, using a rectified output from the rectifier circuit as a power supply voltage.

この場合、前記切換え素子は双方向三端子サイリスタであり、前記信号生成回路は、前記電源電圧が印加される発光素子と、前記双方向三端子サイリスタのゲートに接続する受光素子とからなる光結合素子を備えているのが好ましい。   In this case, the switching element is a bidirectional three-terminal thyristor, and the signal generation circuit is an optical coupling comprising a light emitting element to which the power supply voltage is applied and a light receiving element connected to the gate of the bidirectional three-terminal thyristor. It is preferable to provide an element.

また、前記切換え素子は電磁リレーのスイッチであり、この電磁リレーは前記スイッチを開閉させるコイルを備えていてもよい。   The switching element may be an electromagnetic relay switch, and the electromagnetic relay may include a coil for opening and closing the switch.

本発明のスイッチング電源装置によれば、交流電源からの入力電圧を整流平滑して直流電圧にすることなく、第2の整流回路からの整流出力をそのまま信号生成回路の電源電圧として取り入れることで、第1の整流回路を倍電圧整流方式で動作させるか否かを切換える切換え素子を、駆動回路の信号生成回路で生成した駆動信号で駆動させることができる。これにより、入力自動切換回路として待機電力の損失低減を図り、且つ従来のような平滑用の高耐圧の電解コンデンサを用いることなく、入力電圧に対応して駆動回路が第1の整流回路の整流方式を適正に切り換えることができ、長寿命化および小型化が可能になる。   According to the switching power supply device of the present invention, the rectified output from the second rectifier circuit is directly taken as the power supply voltage of the signal generation circuit without rectifying and smoothing the input voltage from the AC power supply into a DC voltage. The switching element for switching whether or not to operate the first rectifier circuit by the voltage doubler rectification method can be driven by the drive signal generated by the signal generation circuit of the drive circuit. As a result, standby power loss is reduced as an automatic input switching circuit, and the drive circuit rectifies the first rectifier circuit in response to the input voltage without using a smoothing high-voltage electrolytic capacitor as in the prior art. The system can be switched appropriately, and the life and size can be reduced.

また本発明の好ましいスイッチング電源装置によれば、入力電圧が何らかの原因で停止すると、第2の整流回路からの整流出力を電源電圧とする発光素子も同時に発光停止し、双方向三端子サイリスタを即時オフにすることができる。したがって、特に入力電圧の瞬停後再投入時に、双方向三端子サイリスタがオンし続けることに起因する突入電流の発生を防止することができる。   According to the preferred switching power supply device of the present invention, when the input voltage is stopped for some reason, the light emitting element having the rectified output from the second rectifier circuit as the power supply voltage is also stopped at the same time, and the bidirectional three-terminal thyristor is immediately Can be turned off. Therefore, it is possible to prevent the occurrence of an inrush current due to the bidirectional three-terminal thyristor being kept on, particularly when the input voltage is turned on again after a momentary power failure.

また本発明の好ましいスイッチング電源装置によれば、電磁リレーを利用して駆動回路が第1の整流回路の整流方式を適正に切り換えることが可能になる。   Further, according to the preferred switching power supply device of the present invention, the drive circuit can appropriately switch the rectification method of the first rectifier circuit using the electromagnetic relay.

本発明の第1実施例における入力自動切換回路を含むスイッチング電源装置の回路図である。1 is a circuit diagram of a switching power supply device including an automatic input switching circuit according to a first embodiment of the present invention. 同上、トリガ生成回路で生成されるトリガ電流の波形図である。FIG. 4 is a waveform diagram of a trigger current generated by the trigger generation circuit. 本発明の第2実施例における入力自動切換回路を含むスイッチング電源装置の回路図である。It is a circuit diagram of the switching power supply device including the input automatic switching circuit in 2nd Example of this invention.

以下、添付図面に基づき入力自動切換回路の好適な回路例を詳細に説明する。なお、各実施例において共通する構成には共通の符号を付し、同一箇所の説明は重複を避けるために極力省略する。   Hereinafter, a preferred circuit example of the automatic input switching circuit will be described in detail with reference to the accompanying drawings. In addition, the same code | symbol is attached | subjected to the same structure in each Example, and description of the same location is abbreviate | omitted as much as possible in order to avoid duplication.

図1は、本発明の第1実施例における入力自動切換回路を含むスイッチング電源装置の回路図である。同図において、1は入力電源であるAC100V系またはAC200V系の商用電源、2は商用電源1からの交流入力電圧Vinを整流する整流回路であり、これは4つのブリッジ接続されたダイオード(図示せず)などの整流素子を組み合わせて構成される。整流回路2の出力端間には、2つの平滑コンデンサ3,4を直列に接続した平滑回路5が接続配置され、この平滑回路5の両端間に発生する直流電圧Vcが、図示しない負荷(例えば、DC−DCコンバータ)の入力電圧として当該負荷に供給される。   FIG. 1 is a circuit diagram of a switching power supply apparatus including an automatic input switching circuit according to a first embodiment of the present invention. In the figure, reference numeral 1 is an AC 100V system or AC 200V system commercial power source, which is an input power source, and 2 is a rectifier circuit for rectifying an AC input voltage Vin from the commercial power source 1, which includes four bridge-connected diodes (not shown). Z)). A smoothing circuit 5 in which two smoothing capacitors 3 and 4 are connected in series is connected between the output terminals of the rectifier circuit 2, and a DC voltage Vc generated between both ends of the smoothing circuit 5 is applied to a load (for example, not shown) , A DC-DC converter) is supplied to the load as an input voltage.

前記整流回路2の一方の入力端と対をなす平滑コンデンサ3,4の接続点との間には、整流回路2を全波整流方式または倍電圧整流方式の何れかに切換える切換え素子として、トライアック(双方向三端子サイリスタ)8が接続される。ここでは、トライアック8の第1主端子が整流回路2の一方の入力端に接続され、トライアック8の第2主端子が平滑コンデンサ3,4の接続点に接続されるが、トライアック8の第1主端子とゲートとの間には、抵抗9とフォトトライアック11の受光素子13との直列回路が接続され、トライアック8の第2主端子とゲートとの間には、抵抗15とコンデンサ16とによる並列回路が接続される。これらの抵抗9,15およびコンデンサ16は、トライアック8の誤点弧防止回路として必要に応じて付加されるものであり、トライアック8やフォトトライアック11と共に、整流回路2の動作すなわち整流方式を切換え制御する入力自動切換回路21の一部を構成している。   As a switching element for switching the rectifier circuit 2 to either the full-wave rectifier system or the double voltage rectifier system between the connection points of the smoothing capacitors 3 and 4 paired with one input terminal of the rectifier circuit 2, a triac is used. (Bidirectional three-terminal thyristor) 8 is connected. Here, the first main terminal of the triac 8 is connected to one input terminal of the rectifier circuit 2, and the second main terminal of the triac 8 is connected to the connection point of the smoothing capacitors 3, 4. A series circuit of a resistor 9 and a light receiving element 13 of the phototriac 11 is connected between the main terminal and the gate, and a resistor 15 and a capacitor 16 are connected between the second main terminal of the triac 8 and the gate. A parallel circuit is connected. The resistors 9, 15 and the capacitor 16 are added as necessary to prevent erroneous firing of the triac 8, and together with the triac 8 and the photo triac 11, the operation of the rectifier circuit 2, that is, the rectification method is switched and controlled. A part of the automatic input switching circuit 21 is configured.

31は、前記交流入力電圧Vinを監視して、トライアック8をオンまたはオフに駆動する駆動回路である。駆動回路31は、交流入力電圧Vinを整流する整流回路32と、整流回路32からの整流電圧レベルを監視して、その電圧レベルが所定値に達すると、高入力すなわちAC200V系の商用電源1からの入力電圧Vinが印加されたと判断して信号を出力する高入力検出回路33と、整流回路32の出力端に抵抗34,フォトトライアック11の発光素子12,MOS型FET35,抵抗36を順に直列接続してなるトリガ生成回路38と、整流回路32からの整流電圧を電源電圧として、トリガ生成回路38で生成されるトリガ電流が定電流となるようにMOS型FET35を制御する定電流回路39と、前記高入力検出回路33が高入力と判断して、その検出端子Dからパルス信号が出力されるのを受けて、前記MOS型FET35をオフ状態に保持し、トリガ生成回路38に流れるトリガ電流を持続的に停止させるラッチ回路40とにより構成される。   Reference numeral 31 denotes a drive circuit that monitors the AC input voltage Vin and drives the triac 8 on or off. The drive circuit 31 monitors the rectification voltage 32 from the rectification circuit 32 that rectifies the AC input voltage Vin, and the rectification voltage level from the rectification circuit 32. A high-input detection circuit 33 that outputs a signal by judging that the input voltage Vin is applied, and a resistor 34, a light-emitting element 12 of the phototriac 11, a MOS-type FET 35, and a resistor 36 are sequentially connected in series to the output terminal of the rectifier circuit 32. And a constant current circuit 39 for controlling the MOS type FET 35 so that the trigger current generated by the trigger generation circuit 38 becomes a constant current using the rectified voltage from the rectifier circuit 32 as a power supply voltage, When the high input detection circuit 33 determines that the input is high and a pulse signal is output from the detection terminal D, the MOS FET 35 is turned on. Held in off state, composed of a latch circuit 40 for continuously stopping the trigger current flowing through the trigger generation circuit 38.

駆動回路31の各部の構成についてさらに説明すると、整流回路32は例えば4つのブリッジ接続されたダイオード(図示せず)を組み合わせて構成され、その出力端には全波整流された電圧が駆動回路31の電源電圧として発生する。なお、整流回路32の損失を低減するために、実施例中の全波整流方式に代わる別な整流方式を動作するものであってもよい。トリガ生成回路38を構成するフォトトライアック11は、このトリガ生成回路38で生成されるトリガ電流を電気的に絶縁してトライアック8のゲートに伝送するもので、具体的には発光ダイオードからなる発光素子12と光ゲート入力形トライアックからなる受光素子を光結合させた素子である。こうした光結合素子は他にも知られているが、切換え素子が主端子間で双方向に電流を流せるトライアック8である場合、トリガ生成回路38の光結合素子もフォトトライアック11を使用するのが好ましい。   The configuration of each part of the drive circuit 31 will be further described. The rectifier circuit 32 is configured by combining, for example, four bridge-connected diodes (not shown), and a full-wave rectified voltage is applied to the output terminal of the drive circuit 31. Generated as a power supply voltage. In addition, in order to reduce the loss of the rectifier circuit 32, another rectification method replacing the full-wave rectification method in the embodiment may be operated. The phototriac 11 constituting the trigger generation circuit 38 electrically insulates the trigger current generated by the trigger generation circuit 38 and transmits it to the gate of the triac 8. Specifically, the phototriac 11 is a light-emitting element made of a light-emitting diode. 12 and an optical gate input type triac. Other such optical coupling elements are known, but when the switching element is a triac 8 capable of flowing a current bidirectionally between main terminals, the optical coupling element of the trigger generation circuit 38 also uses the photo triac 11. preferable.

また、フォトトライアック11の発光素子12と直列に接続するMOS型FET35は、この発光素子12へのトリガ電流の流れ込みを可能または阻止するスイッチ素子として設けられる。ここでは、NチャネルのMOS型FET35のゲート電圧がH(高)レベルになると、MOS型FET35がオンして、整流回路32からの全波整流を電源としたトリガ電流が、抵抗34を介して発光素子12に流れ込む一方で、MOS型FET35のゲート電圧がL(低)レベルになると、MOS型FET35がオフして、発光素子12へのトリガ電流の流れ込みが遮断されるようになっている。スイッチ素子としては、MOS型FET35以外の各種制御端子付き半導体素子などを用いてもよい。   Further, the MOS FET 35 connected in series with the light emitting element 12 of the phototriac 11 is provided as a switching element that enables or prevents the trigger current from flowing into the light emitting element 12. Here, when the gate voltage of the N-channel MOS type FET 35 becomes H (high) level, the MOS type FET 35 is turned on, and the trigger current using the full-wave rectification from the rectifier circuit 32 as a power source is passed through the resistor 34. On the other hand, when the gate voltage of the MOS type FET 35 becomes L (low) level while flowing into the light emitting element 12, the MOS type FET 35 is turned off, and the flow of the trigger current to the light emitting element 12 is cut off. As the switch element, a semiconductor element with various control terminals other than the MOS FET 35 may be used.

定電流回路39は、整流回路32の出力端に、抵抗45と、ツェナーダイオード46,コンデンサ47,抵抗48からなる並列回路を直列に接続し、この抵抗45と並列回路の接続点に、抵抗49を介してMOS型FET35のゲートを接続することで構成される。ここでのコンデンサ47は、MOS型FET35や後述するラッチ回路40のトランジスタ51,52をオンし得る程度の電荷を蓄積できればよく、従来の電解コンデンサよりも遥かに低い耐圧のものを使用できる。   In the constant current circuit 39, a resistor 45 and a parallel circuit including a Zener diode 46, a capacitor 47, and a resistor 48 are connected in series to the output terminal of the rectifier circuit 32, and a resistor 49 is connected to a connection point of the resistor 45 and the parallel circuit. The gate of the MOS FET 35 is connected via Here, the capacitor 47 only needs to be able to store charges that can turn on the MOS FET 35 and transistors 51 and 52 of the latch circuit 40 to be described later, and can have a withstand voltage much lower than that of a conventional electrolytic capacitor.

ラッチ回路40は、PNP型トランジスタ51のベースとコレクタを、NPN型トランジスタ52のコレクタとベースにそれぞれ接続したサイリスタと、トランジスタ52のベースとエミッタ間に接続する抵抗53とにより構成され、サイリスタのゲートに相当するトランジスタ52のベースに、前記高入力検出回路33の検出端子Dが接続され、サイリスタのアノードに相当するトランジスタ51のエミッタに、MOS型FET35の制御端子であるゲートが接続される。   The latch circuit 40 includes a thyristor in which the base and collector of the PNP transistor 51 are connected to the collector and base of the NPN transistor 52, respectively, and a resistor 53 connected between the base and emitter of the transistor 52, and the gate of the thyristor. The detection terminal D of the high input detection circuit 33 is connected to the base of the transistor 52 corresponding to, and the gate which is the control terminal of the MOS type FET 35 is connected to the emitter of the transistor 51 corresponding to the anode of the thyristor.

次に、上記構成についてその作用を、図2の波形図に基づき説明する。なお、図2において、上段は整流回路32からの整流電圧波形であり、下段はトリガ生成回路38で生成されるトリガ電流の波形である。   Next, the operation of the above configuration will be described based on the waveform diagram of FIG. In FIG. 2, the upper stage is a rectified voltage waveform from the rectifier circuit 32, and the lower stage is a waveform of the trigger current generated by the trigger generation circuit 38.

商用電源1からの入力電圧Vinが印加され始めると、その入力電圧Vinが整流回路2および入力自動切換回路21の整流回路32でそれぞれ整流される。整流回路2からの整流電圧は、平滑コンデンサ3,4により平滑されるが、整流回路32からの整流電圧は、図2の波形図に示すように、高耐圧の電解コンデンサで平滑されることなく、トリガ生成回路38と定電流回路39にそのまま電源電圧として供給される。   When the input voltage Vin from the commercial power source 1 starts to be applied, the input voltage Vin is rectified by the rectifier circuit 2 and the rectifier circuit 32 of the input automatic switching circuit 21, respectively. The rectified voltage from the rectifier circuit 2 is smoothed by the smoothing capacitors 3 and 4, but the rectified voltage from the rectifier circuit 32 is not smoothed by the high withstand voltage electrolytic capacitor as shown in the waveform diagram of FIG. The power supply voltage is supplied to the trigger generation circuit 38 and the constant current circuit 39 as they are.

ここで、商用電源1がAC100V系の低入力である場合、高入力検出回路33では整流回路32からの整流電圧レベルが常に所定値以下となるため、検出端子Dからの検出用のパルス信号は出力されず、ラッチ回路40のサイリスタはオフして、定電流回路39はラッチ回路40の影響を受けずに動作するようになる。そのため定電流回路39は、整流回路32からの整流電圧が0Vから上昇すると、抵抗45を介してコンデンサ47を充電し、コンデンサ47の両端間電圧をツェナーダイオード46のツェナー電圧に維持すると共に、整流回路32からの整流電圧が下降して0Vに近づくと、コンデンサ47に蓄積した電荷を抵抗48で放電する動作を繰り返すことで、MOS型FET35のドレインからソースに流れる電流(すなわちトリガ生成回路38において、整流回路32から抵抗34,発光素子12を順に通ってMOS型FET35に流れ込むトリガ電流)が、入力電圧Vinのゼロクロス付近を除いて一定値となるように、抵抗49を介してコンデンサ47に接続するMOS型FET35のゲート電圧を制御する。   Here, when the commercial power supply 1 is an AC100V system low input, since the rectified voltage level from the rectifier circuit 32 is always below a predetermined value in the high input detection circuit 33, the detection pulse signal from the detection terminal D is The thyristor of the latch circuit 40 is turned off, and the constant current circuit 39 operates without being influenced by the latch circuit 40. Therefore, when the rectified voltage from the rectifier circuit 32 rises from 0 V, the constant current circuit 39 charges the capacitor 47 through the resistor 45, maintains the voltage across the capacitor 47 at the zener voltage of the zener diode 46, and rectifies When the rectified voltage from the circuit 32 decreases and approaches 0 V, the operation of discharging the charge accumulated in the capacitor 47 with the resistor 48 is repeated, so that the current flowing from the drain to the source of the MOS FET 35 (that is, in the trigger generation circuit 38). The trigger current flowing from the rectifier circuit 32 through the resistor 34 and the light emitting element 12 into the MOS type FET 35 in this order is connected to the capacitor 47 via the resistor 49 so that it becomes a constant value except near the zero cross of the input voltage Vin. The gate voltage of the MOS type FET 35 to be controlled is controlled.

こうして、トリガ生成回路38に図2に示すような定電流制御されたトリガ電流が発生すると、そのトリガ電流はフォトトライアック11の発光素子12から受光素子13に信号伝送される。したがって、トリガ電流が増加してトライアック8のトリガレベルに達すると、当該トライアック8がオンして、整流回路2の一方の入力端と平滑コンデンサ3,4の接続点との間が導通し、整流回路2は直列接続された平滑コンデンサ3,4の作用による倍電圧整流を行ない、平滑コンデンサ3,4の両端間に所要の直流電圧Vcを発生させる。   Thus, when a trigger current under constant current control as shown in FIG. 2 is generated in the trigger generation circuit 38, the trigger current is signal-transmitted from the light emitting element 12 of the phototriac 11 to the light receiving element 13. Therefore, when the trigger current increases and reaches the trigger level of the triac 8, the triac 8 is turned on, and the connection between one input terminal of the rectifier circuit 2 and the connection point of the smoothing capacitors 3 and 4 is conducted. The circuit 2 performs voltage doubler rectification by the action of the smoothing capacitors 3 and 4 connected in series, and generates a required DC voltage Vc across the smoothing capacitors 3 and 4.

一方、商用電源1がAC200V系の高入力である場合、高入力検出回路33では整流回路32からの整流電圧レベルが周期的に所定値を越え、その検出端子Dからパルス信号が繰り返し出力される。こうなると、ラッチ回路40を構成するサイリスタのゲートにパルス信号が印加され、当該サイリスタがターンオンして、定電流制御しているMOS型FET35のゲート電圧をLレベルにし、MOS型FET35をオフにする。   On the other hand, when the commercial power source 1 is an AC200V system high input, the high input detection circuit 33 periodically exceeds the predetermined value of the rectified voltage level from the rectifier circuit 32, and a pulse signal is repeatedly output from the detection terminal D. . When this happens, a pulse signal is applied to the gate of the thyristor constituting the latch circuit 40, the thyristor is turned on, the gate voltage of the MOS FET 35 under constant current control is set to L level, and the MOS FET 35 is turned off. .

ラッチ回路40によってMOS型FET35がオフ状態を維持すると、トリガ生成回路38にはトリガ電流が発生せず、トライアック8はオフ状態となり、整流回路2の一方の入力端と平滑コンデンサ3,4の接続点との間が非導通になる。したがって、この場合は整流回路2で全波整流された電圧が平滑コンデンサ3,4により平滑化され、倍電圧整流時と同等の直流電圧Vcが平滑コンデンサ3,4の両端間に発生する。   When the MOS type FET 35 is kept off by the latch circuit 40, no trigger current is generated in the trigger generation circuit 38, the triac 8 is turned off, and the connection between one input terminal of the rectifier circuit 2 and the smoothing capacitors 3 and 4 is established. It becomes non-conductive between points. Therefore, in this case, the voltage that has been full-wave rectified by the rectifier circuit 2 is smoothed by the smoothing capacitors 3 and 4, and a DC voltage Vc equivalent to that during double voltage rectification is generated across the smoothing capacitors 3 and 4.

また、図1に示すトライアック8とフォトトライアック11を組み合わせた回路構成では、入力電圧Vinが何らかの原因で停止した場合、トライアック8が即時オフする。これはフォトトライアック11の発光素子12を動作させる電源電圧が、整流回路32からの全波整流電圧であるため、入力電圧Vinが停止すると同時に全波整流電圧も停止して、発光素子12の発光が止まるからである。そのため、入力電圧Vinが瞬間的に停止後、再投入したときに、入力電圧Vinの遮断時にオフしたトライアック8が、入力電圧Vinの再投入時にフォトトライアック11によるゼロクロス検出により再びオンして、整流回路2による倍電圧整流方式の動作を再開させることができる。つまり、入力電圧Vinの瞬停時において、整流回路2による倍電圧整流方式の動作が直ちに停止せず、トライアック8がオン状態を維持したまま入力電圧Vinを再投入すると、負荷に対して突入電流が発生する場合があるが、図1に示す回路では、整流回路32からの整流電圧がフォトトライアック11の発光素子12を動作させる電源電圧となっているため、そうした突入電流の発生を防ぐことができる。   In the circuit configuration in which the triac 8 and the photo triac 11 shown in FIG. 1 are combined, when the input voltage Vin is stopped for some reason, the triac 8 is immediately turned off. This is because the power supply voltage for operating the light-emitting element 12 of the phototriac 11 is the full-wave rectified voltage from the rectifier circuit 32, so that the full-wave rectified voltage is also stopped at the same time as the input voltage Vin is stopped. Because it stops. Therefore, when the input voltage Vin is momentarily stopped and then turned on again, the triac 8 turned off when the input voltage Vin is turned off is turned on again by zero cross detection by the phototriac 11 when the input voltage Vin is turned on again, and rectified. The operation of the voltage doubler rectification method by the circuit 2 can be resumed. That is, when the input voltage Vin is instantaneously stopped, the operation of the voltage doubler rectification method by the rectifier circuit 2 does not stop immediately, and if the input voltage Vin is turned on again while the triac 8 is kept on, the inrush current to the load In the circuit shown in FIG. 1, since the rectified voltage from the rectifier circuit 32 is a power supply voltage for operating the light emitting element 12 of the phototriac 11, it is possible to prevent such an inrush current from occurring. it can.

以上のように本実施例では、交流電源である商用電源1からの入力電圧Vinを整流する第1の整流回路たる整流回路2に接続され、この整流回路2を倍電圧整流方式で動作させるか否かを切換える切換え素子としてのトライアック8と、トライアック8をオンまたはオフに駆動する駆動回路31とを備えたスイッチング電源装置の入力自動切換回路21において、入力電圧Vinを整流する第2の整流回路たる整流回路32と、この整流回路32からの整流出力を電源電圧として、トライアック8をオンまたはオフにするための駆動信号(トリガ電流)を生成する信号生成回路としてのトリガ生成回路38とを、駆動回路31が備えている。   As described above, in this embodiment, the rectifier circuit 2 is connected to the rectifier circuit 2 that is the first rectifier circuit that rectifies the input voltage Vin from the commercial power source 1 that is an AC power source. A second rectifier circuit for rectifying the input voltage Vin in the input automatic switching circuit 21 of the switching power supply device including the triac 8 as a switching element for switching whether or not and the drive circuit 31 for driving the triac 8 on or off. A rectifier circuit 32, and a trigger generation circuit 38 as a signal generation circuit that generates a drive signal (trigger current) for turning on or off the triac 8 using a rectified output from the rectifier circuit 32 as a power supply voltage, The drive circuit 31 is provided.

この場合、交流入力電圧Vinを整流平滑して直流電圧にすることなく、整流回路32からの整流出力をそのままトリガ生成回路38の電源電圧として取り入れることで、整流回路2を倍電圧整流方式で動作させるか否かを切換えるトライアック8を、駆動回路31のトリガ生成回路38で生成したトリガ電流で駆動させることができる。そのため、入力自動切換回路21として待機電力の損失低減を図り、且つ従来のような平滑用の高耐圧の電解コンデンサを用いることなく、入力電圧Vinに対応して駆動回路31が整流回路2の整流方式を適正に切り換えることが可能になる。   In this case, the AC input voltage Vin is not rectified and smoothed into a DC voltage, but the rectified output from the rectifier circuit 32 is directly used as the power supply voltage of the trigger generation circuit 38, so that the rectifier circuit 2 operates in a voltage doubler rectification system. The TRIAC 8 that switches whether or not to be driven can be driven by the trigger current generated by the trigger generation circuit 38 of the drive circuit 31. Therefore, the standby power loss is reduced as the automatic input switching circuit 21 and the drive circuit 31 rectifies the rectifier circuit 2 in response to the input voltage Vin without using a conventional high-voltage electrolytic capacitor for smoothing. It becomes possible to switch the method appropriately.

また、特に本実施例の切換え素子はトライアック8であり、トリガ生成回路38は、前記電源電圧が印加される発光素子12と、トライアック8のゲートに接続する受光素子13とからなる光結合素子としてのフォトトライアック11を備えている。   In particular, the switching element of the present embodiment is a triac 8, and the trigger generation circuit 38 is an optical coupling element including the light emitting element 12 to which the power supply voltage is applied and the light receiving element 13 connected to the gate of the triac 8. The photo triac 11 is provided.

この場合、入力電圧Vinが何らかの原因で停止すると、整流回路32からの整流出力を電源電圧とする発光素子12も同時に発光停止し、トライアック8を即時オフにすることができる。したがって、特に入力電圧Vinの瞬停後再投入時に、トライアック8がオンし続けることに起因する突入電流の発生を防止することができる。   In this case, when the input voltage Vin stops for some reason, the light emitting element 12 using the rectified output from the rectifier circuit 32 as the power supply voltage also stops light emission at the same time, and the triac 8 can be immediately turned off. Therefore, it is possible to prevent the occurrence of an inrush current due to the TRIAC 8 being kept on, particularly when the input voltage Vin is turned on again after a momentary power failure.

図3は、本発明の第2実施例における入力自動切換回路を含む電源装置の回路図である。同図において、ここでは切換え素子がトライアック8ではなく電磁リレー61のスイッチ62で構成され、またトリガ生成回路38が、電磁リレー61のコイル63と、MOS型FET35と、抵抗36を順に直列接続して構成される。電磁リレー61のコイル63はコアである鉄芯(図示せず)に巻回され、コイル63に流れるトリガ電流によって、電磁気的にスイッチ62を開閉するようになっており、トリガ電流が所定値以下ではスイッチ62が開いてオフし、トリガ電流が所定値を越えるとスイッチ62が閉じてオンする。なお、それ以外の構成は前記第1実施例と共通している。   FIG. 3 is a circuit diagram of a power supply apparatus including an automatic input switching circuit according to the second embodiment of the present invention. In this figure, the switching element is not a triac 8 but a switch 62 of an electromagnetic relay 61, and a trigger generation circuit 38 connects a coil 63 of the electromagnetic relay 61, a MOS type FET 35, and a resistor 36 in series. Configured. The coil 63 of the electromagnetic relay 61 is wound around an iron core (not shown) as a core, and the switch 62 is electromagnetically opened and closed by a trigger current flowing through the coil 63. The trigger current is less than a predetermined value. Then, the switch 62 is opened and turned off, and when the trigger current exceeds a predetermined value, the switch 62 is closed and turned on. Other configurations are the same as those in the first embodiment.

そして本実施例においても、商用電源1からの入力電圧Vinが印加され始めると、その入力電圧Vinが整流回路2および入力自動切換回路21の整流回路32でそれぞれ整流される。整流回路2からの整流電圧は、平滑コンデンサ3,4により平滑されるが、整流回路32からの整流電圧は、図2の波形図に示すように、高耐圧の電解コンデンサで平滑されることなく、トリガ生成回路38と定電流回路39にそのまま電源電圧として供給される。   Also in this embodiment, when the input voltage Vin from the commercial power source 1 starts to be applied, the input voltage Vin is rectified by the rectifier circuit 2 and the rectifier circuit 32 of the input automatic switching circuit 21, respectively. The rectified voltage from the rectifier circuit 2 is smoothed by the smoothing capacitors 3 and 4, but the rectified voltage from the rectifier circuit 32 is not smoothed by the high withstand voltage electrolytic capacitor as shown in the waveform diagram of FIG. The power supply voltage is supplied to the trigger generation circuit 38 and the constant current circuit 39 as they are.

ここで、商用電源1がAC100V系の低入力である場合、高入力検出回路33の検出端子Dからはパルス信号は出力されず、ラッチ回路40のサイリスタはオフして、定電流回路39はラッチ回路40の影響を受けずに動作するようになる。そのため定電流回路39は、整流回路32から電磁リレー61のコイル63を順に通ってMOS型FET35に流れ込むトリガ電流が、入力電圧Vinのゼロクロス付近を除いて一定値となるように、MOS型FET35のゲート電圧を制御する。そして、トリガ生成回路38に図2に示すような定電流制御されたトリガ電流が発生し、そのトリガ電流が一定値を越えると電磁リレー61のスイッチ62が閉じる。それにより、整流回路2の一方の入力端と平滑コンデンサ3,4の接続点との間が導通し、整流回路2は直列接続された平滑コンデンサ3,4の作用による倍電圧全波整流を行ない、平滑コンデンサ3,4の両端間に所要の直流電圧Vcを発生させる。   Here, when the commercial power source 1 is an AC100V low input, no pulse signal is output from the detection terminal D of the high input detection circuit 33, the thyristor of the latch circuit 40 is turned off, and the constant current circuit 39 is latched. The circuit 40 operates without being affected by the circuit 40. Therefore, the constant current circuit 39 is configured so that the trigger current flowing from the rectifier circuit 32 through the coil 63 of the electromagnetic relay 61 into the MOS FET 35 in order is a constant value except for the vicinity of the zero cross of the input voltage Vin. Control the gate voltage. 2 is generated in the trigger generation circuit 38, and when the trigger current exceeds a certain value, the switch 62 of the electromagnetic relay 61 is closed. As a result, the connection between one input terminal of the rectifier circuit 2 and the connection point of the smoothing capacitors 3 and 4 is conducted, and the rectifier circuit 2 performs double voltage full-wave rectification by the action of the smoothing capacitors 3 and 4 connected in series. The required DC voltage Vc is generated between both ends of the smoothing capacitors 3 and 4.

一方、商用電源1がAC200V系の高入力である場合、高入力検出回路33の検出端子Dからパルス信号が繰り返し出力されるので、定電流制御しているMOS型FET35のゲート電圧はLレベルになり、MOS型FET35はオフする。ラッチ回路40によってMOS型FET35がオフ状態を維持すると、トリガ生成回路38にはトリガ電流が発生せず、電磁リレー61のスイッチ62は開いて、整流回路2の一方の入力端と平滑コンデンサ3,4の接続点との間が非導通になる。したがって、この場合は整流回路2で全波整流された電圧が平滑コンデンサ3,4により平滑化され、倍電圧整流時と同等の直流電圧Vcが平滑コンデンサ3,4の両端間に発生する。   On the other hand, when the commercial power source 1 is an AC200V system high input, since the pulse signal is repeatedly output from the detection terminal D of the high input detection circuit 33, the gate voltage of the MOS FET 35 under constant current control is set to the L level. Thus, the MOS FET 35 is turned off. When the MOS FET 35 is kept off by the latch circuit 40, no trigger current is generated in the trigger generation circuit 38, the switch 62 of the electromagnetic relay 61 is opened, and one input terminal of the rectifier circuit 2 and the smoothing capacitor 3, No connection between the four connection points. Therefore, in this case, the voltage that has been full-wave rectified by the rectifier circuit 2 is smoothed by the smoothing capacitors 3 and 4, and a DC voltage Vc equivalent to that during double voltage rectification is generated across the smoothing capacitors 3 and 4.

なお、図2の波形図では、入力電圧Vinのゼロクロス付近でトリガ電流が所定値以下となるが、ここで使用する電磁リレー61は、コイル63を流れる電流が変化してからスイッチ62の開閉が切り換わるまでのタイムラグが大きいので、入力電圧Vinのゼロクロス付近であってもスイッチ62はオフにならない。これにより、スイッチ62が周期的に開閉することによる電磁リレー61の寿命低下を防ぐことができる。   In the waveform diagram of FIG. 2, the trigger current is below a predetermined value near the zero cross of the input voltage Vin, but the electromagnetic relay 61 used here opens and closes the switch 62 after the current flowing through the coil 63 changes. Since the time lag until switching is large, the switch 62 does not turn off even near the zero cross of the input voltage Vin. Thereby, the lifetime reduction of the electromagnetic relay 61 by the switch 62 opening and closing periodically can be prevented.

また別な手段として、入力電圧Vinのゼロクロス付近でトリガ電流のレベルを持ち上げる回路を、駆動回路31に組み込んでもよい。この場合、スイッチ62がオフからオンに切換わるトリガ電流のレベルよりも、スイッチ62がオンからオフに切換わるトリガ電流のレベルが低い電磁リレー61を用いれば、同様の原因に基づく電磁リレー61の寿命低下を確実に防ぐことができる。   As another means, a circuit that raises the trigger current level near the zero cross of the input voltage Vin may be incorporated in the drive circuit 31. In this case, if the electromagnetic relay 61 having a lower trigger current level at which the switch 62 is switched from on to off than the trigger current level at which the switch 62 is switched from off to on, the electromagnetic relay 61 based on the same cause is used. It is possible to reliably prevent a decrease in life.

以上のように、本実施例では交流電源である商用電源1からの入力電圧Vinを整流する整流回路2に接続され、この整流回路2を倍電圧整流方式で動作させるか否かを切換える切換え素子としての電磁リレー61のスイッチ62と、当該スイッチ62をオンまたはオフに駆動する駆動回路31とを備えた入力自動切換回路21において、入力電圧Vinを整流する整流回路32と、この整流回路32からの整流出力を電源電圧として、電磁リレー61のスイッチ62をオンまたはオフにするためのトリガ電流を生成するトリガ生成回路38とを、駆動回路31が備えている。   As described above, in this embodiment, the switching element is connected to the rectifier circuit 2 that rectifies the input voltage Vin from the commercial power source 1 that is an AC power source, and switches whether the rectifier circuit 2 is operated by the double voltage rectification method. In the automatic input switching circuit 21 including a switch 62 of the electromagnetic relay 61 and a drive circuit 31 that drives the switch 62 on or off, a rectifier circuit 32 that rectifies the input voltage Vin, The drive circuit 31 includes a trigger generation circuit 38 that generates a trigger current for turning on or off the switch 62 of the electromagnetic relay 61 using the rectified output of the power supply voltage as a power supply voltage.

この場合、交流入力電圧Vinを整流平滑して直流電圧にすることなく、整流回路32からの整流出力をそのままトリガ生成回路38の電源電圧として取り入れることで、整流回路2を倍電圧整流方式で動作させるか否かを切換える電磁リレー61のスイッチ62を、駆動回路31のトリガ生成回路38で生成したトリガ電流で駆動させることができる。そのため、入力自動切換回路21として待機電力の損失低減を図り、且つ従来のような平滑用の高耐圧の電解コンデンサを用いることなく、入力電圧Vinに対応して駆動回路31が整流回路2の整流方式を適正に切り換えることができ、長寿命化および小型化が可能になる。   In this case, the AC input voltage Vin is not rectified and smoothed into a DC voltage, but the rectified output from the rectifier circuit 32 is directly used as the power supply voltage of the trigger generation circuit 38, so that the rectifier circuit 2 operates in a voltage doubler rectification system. It is possible to drive the switch 62 of the electromagnetic relay 61 that switches whether or not to perform the trigger current generated by the trigger generation circuit 38 of the drive circuit 31. Therefore, the standby power loss is reduced as the automatic input switching circuit 21 and the drive circuit 31 rectifies the rectifier circuit 2 in response to the input voltage Vin without using a conventional high-voltage electrolytic capacitor for smoothing. The system can be switched appropriately, and the life and size can be reduced.

また、本実施例の切換え素子は電磁リレー61のスイッチ62であり、この電磁リレー61はスイッチ62を開閉させるためのコイル63を備えており、トリガ生成回路38は、前記電源電圧が印加される電磁リレー61のコイル63を備えている。   The switching element of this embodiment is a switch 62 of an electromagnetic relay 61. The electromagnetic relay 61 includes a coil 63 for opening and closing the switch 62, and the trigger generation circuit 38 is applied with the power supply voltage. A coil 63 of the electromagnetic relay 61 is provided.

この場合、電磁リレー61を利用して駆動回路31が整流回路2の整流方式を適正に切り換えることが可能になる。   In this case, the drive circuit 31 can appropriately switch the rectification method of the rectifier circuit 2 using the electromagnetic relay 61.

なお本発明は、本実施例に限定されるものではなく、本発明の要旨の範囲内で種々の変形実施が可能である。ここでいう倍電圧とは、2倍に限らずそれ以上の整数倍の電圧も含む。また整流回路2は、実施例中の全波整流方式に代わる別な整流方式を動作するものであってもよい。   The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention. The voltage double here is not limited to twice, but also includes a voltage of an integer multiple higher than that. Moreover, the rectifier circuit 2 may operate another rectification method instead of the full-wave rectification method in the embodiment.

1 商用電源(交流電源)
2 整流回路(第1の整流回路)
8 トライアック(切換え素子)
11 フォトトライアック(光結合素子)
12 発光素子
13 受光素子
32 整流回路(第2の整流回路)
38 トリガ生成回路(信号生成回路)
61 電磁リレー
62 スイッチ(切換え素子)
63 コイル
1 Commercial power supply (AC power supply)
2 Rectifier circuit (first rectifier circuit)
8 Triac (switching element)
11 Phototriac (Optical coupling device)
12 Light emitting element 13 Light receiving element 32 Rectifier circuit (second rectifier circuit)
38 Trigger generation circuit (signal generation circuit)
61 Electromagnetic relay 62 Switch (switching element)
63 coils

Claims (3)

交流電源からの入力電圧を整流する第1の整流回路に接続され、前記第1の整流回路を倍電圧整流方式で動作させるか否かを切換える切換え素子と、
前記切換え素子をオンまたはオフに駆動する駆動回路と、を備えたスイッチング電源装置において、
前記駆動回路は、前記入力電圧を整流する第2の整流回路と、この第2の整流回路からの整流出力を電源電圧として、前記切換え素子をオンまたはオフにする駆動信号を生成する信号生成回路と、を備えたことを特徴とするスイッチング電源装置。
A switching element that is connected to a first rectifier circuit that rectifies an input voltage from an AC power supply, and that switches whether or not the first rectifier circuit is operated in a double voltage rectifier system;
In a switching power supply device comprising: a drive circuit that drives the switching element on or off;
The drive circuit includes a second rectifier circuit that rectifies the input voltage, and a signal generation circuit that generates a drive signal for turning on or off the switching element using a rectified output from the second rectifier circuit as a power supply voltage. And a switching power supply device.
前記切換え素子は双方向三端子サイリスタであり、
前記信号生成回路は、前記電源電圧が印加される発光素子と、前記双方向三端子サイリスタのゲートに接続する受光素子とからなる光結合素子を備えたことを特徴とする請求項1記載のスイッチング電源装置。
The switching element is a bidirectional three-terminal thyristor;
2. The switching according to claim 1, wherein the signal generation circuit includes an optical coupling element including a light emitting element to which the power supply voltage is applied and a light receiving element connected to a gate of the bidirectional three-terminal thyristor. Power supply.
前記切換え素子は電磁リレーのスイッチであり、この電磁リレーは前記スイッチを開閉させるコイルを備えたことを特徴とする請求項1記載のスイッチング電源装置。   2. The switching power supply device according to claim 1, wherein the switching element is a switch of an electromagnetic relay, and the electromagnetic relay includes a coil for opening and closing the switch.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017181076A1 (en) * 2016-04-15 2017-10-19 Emerson Electric Co. Power factor correction circuits and methods including partial power factor correction operation for boost and buck power converters
US9933842B2 (en) 2016-04-15 2018-04-03 Emerson Climate Technologies, Inc. Microcontroller architecture for power factor correction converter
US9965928B2 (en) 2016-04-15 2018-05-08 Emerson Climate Technologies, Inc. System and method for displaying messages in a column-by-column format via an array of LEDs connected to a circuit of a compressor
US10075065B2 (en) 2016-04-15 2018-09-11 Emerson Climate Technologies, Inc. Choke and EMI filter circuits for power factor correction circuits
US10277115B2 (en) 2016-04-15 2019-04-30 Emerson Climate Technologies, Inc. Filtering systems and methods for voltage control
US10284132B2 (en) 2016-04-15 2019-05-07 Emerson Climate Technologies, Inc. Driver for high-frequency switching voltage converters
US10305373B2 (en) 2016-04-15 2019-05-28 Emerson Climate Technologies, Inc. Input reference signal generation systems and methods
CN110224691A (en) * 2019-07-10 2019-09-10 常州机电职业技术学院 Work long hours and operating current variation equipment power off in standby state of electric energy-saving circuit
US10656026B2 (en) 2016-04-15 2020-05-19 Emerson Climate Technologies, Inc. Temperature sensing circuit for transmitting data across isolation barrier
US10763740B2 (en) 2016-04-15 2020-09-01 Emerson Climate Technologies, Inc. Switch off time control systems and methods
JP2022514866A (en) * 2019-02-12 2022-02-16 エフィー カンパニー リミテッド Triac module

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746675A (en) * 1980-09-01 1982-03-17 Tdk Corp Power circuit
JPH01138969A (en) * 1987-11-26 1989-05-31 Nec Corp Power supply circuit
JPH02299473A (en) * 1989-05-11 1990-12-11 Murata Mfg Co Ltd Power source circuit
JPH0391083U (en) * 1989-12-26 1991-09-17
JPH0530729A (en) * 1991-07-18 1993-02-05 Yutaka Denki Seisakusho:Kk Switching circuit for rectifying circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5746675A (en) * 1980-09-01 1982-03-17 Tdk Corp Power circuit
JPH01138969A (en) * 1987-11-26 1989-05-31 Nec Corp Power supply circuit
JPH02299473A (en) * 1989-05-11 1990-12-11 Murata Mfg Co Ltd Power source circuit
JPH0391083U (en) * 1989-12-26 1991-09-17
JPH0530729A (en) * 1991-07-18 1993-02-05 Yutaka Denki Seisakusho:Kk Switching circuit for rectifying circuit

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10320322B2 (en) 2016-04-15 2019-06-11 Emerson Climate Technologies, Inc. Switch actuation measurement circuit for voltage converter
US9965928B2 (en) 2016-04-15 2018-05-08 Emerson Climate Technologies, Inc. System and method for displaying messages in a column-by-column format via an array of LEDs connected to a circuit of a compressor
WO2017181076A1 (en) * 2016-04-15 2017-10-19 Emerson Electric Co. Power factor correction circuits and methods including partial power factor correction operation for boost and buck power converters
US10437317B2 (en) 2016-04-15 2019-10-08 Emerson Climate Technologies, Inc. Microcontroller architecture for power factor correction converter
US10277115B2 (en) 2016-04-15 2019-04-30 Emerson Climate Technologies, Inc. Filtering systems and methods for voltage control
US10284132B2 (en) 2016-04-15 2019-05-07 Emerson Climate Technologies, Inc. Driver for high-frequency switching voltage converters
US10305373B2 (en) 2016-04-15 2019-05-28 Emerson Climate Technologies, Inc. Input reference signal generation systems and methods
US10312798B2 (en) 2016-04-15 2019-06-04 Emerson Electric Co. Power factor correction circuits and methods including partial power factor correction operation for boost and buck power converters
US11387729B2 (en) 2016-04-15 2022-07-12 Emerson Climate Technologies, Inc. Buck-converter-based drive circuits for driving motors of compressors and condenser fans
US9933842B2 (en) 2016-04-15 2018-04-03 Emerson Climate Technologies, Inc. Microcontroller architecture for power factor correction converter
US10075065B2 (en) 2016-04-15 2018-09-11 Emerson Climate Technologies, Inc. Choke and EMI filter circuits for power factor correction circuits
US10656026B2 (en) 2016-04-15 2020-05-19 Emerson Climate Technologies, Inc. Temperature sensing circuit for transmitting data across isolation barrier
US10763740B2 (en) 2016-04-15 2020-09-01 Emerson Climate Technologies, Inc. Switch off time control systems and methods
US10770966B2 (en) 2016-04-15 2020-09-08 Emerson Climate Technologies, Inc. Power factor correction circuit and method including dual bridge rectifiers
US10928884B2 (en) 2016-04-15 2021-02-23 Emerson Climate Technologies, Inc. Microcontroller architecture for power factor correction converter
JP2022514866A (en) * 2019-02-12 2022-02-16 エフィー カンパニー リミテッド Triac module
JP7153405B2 (en) 2019-02-12 2022-10-14 エフィー カンパニー リミテッド triac module
CN110224691A (en) * 2019-07-10 2019-09-10 常州机电职业技术学院 Work long hours and operating current variation equipment power off in standby state of electric energy-saving circuit

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