JP2011160491A - Decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve throughput while repeating decoding processing in a decoding processing section. <P>SOLUTION: In this decoder 5, the decoding processing section 11 repeats decoding processing to encoded input data. The decoding processing section 11 includes a plurality of stages 11a, 11b, 11c for sequentially executing a plurality of pieces of partial processing, where the decoding processing is divided. The final stage 11c is connected to the beginning stage 11a to repeat the decoding processing. The decoder is structured such that new input data are processed at the beginning stage at timing before the completion of the repetition of the decoding processing to the input data previously input to the decoding processing section, and at which processing data for the input data previously input to the decoding processing section exist at a stage other than the beginning stage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a decoder in which a decoding processing unit repeatedly performs decoding processing on input data.

In the field of digital communication, high-speed communication, low power consumption, and high communication quality (bit error rate) are desired regardless of wired or wireless. Error correction technology is widely used in wireless, wired, and recording systems as one of the technologies for satisfying these requirements.
As one of such error correction techniques, attention is paid to a low-density parity check (LDPC) code and a sum-product decoding method that is a decoding method thereof (Patent Document 1). And Non-Patent Documents 1 and 2).

With this LDPC code, it is known that a decoding characteristic of 0.004 dB can be obtained up to the Shannon limit of a white Gaussian channel (Non-patent Document 3).
In addition, since the sum program decoding method performs decoding processing by parallel processing, the code length can be increased and the processing capability can be improved. As a decoding method, a mini-sum decoding method that is a simplified sum product decoding method is also known.

In the above decoding method, the log likelihood ratio calculated from the received signal is given to a decoding processing unit that performs decoding processing including row processing and column processing, and the decoding processing of the row processing and column processing is repeatedly performed in the decoding processing unit. Error correction. A decoder that performs error correction decoding of such an LDPC code is disclosed in Patent Document 1.
In the decoder as described above, the decoding process of the row process and the column process is repeatedly performed repeatedly. Then, if the number of repetitions of row processing and column processing reaches a predetermined value (number of repetitions), or if a predetermined condition is satisfied even before reaching the predetermined value, the repetition of row processing and column processing ends. .

JP 2007-325011 A

Wadayama Tadashi "Low Density Parity Check Code and its Decoding" IEICE Tech. Engling Yeo “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels” IEEE Trans. On Magnetics, vol.37, NO2. March 2001 S.Y.Chung “On the design of low-density parity-check codes within 0.0045dB of the Shannon limit” IEEE Communications Letters, Vol. 5, No. 2, February 2001

In the case where the decoding process needs to be repeated, such as an LDPC code decoder, there is a problem that the processing speed of the entire decoder decreases due to the repetition of the decoding process.
For example, as illustrated in FIG. 10, a decoder 100 is assumed in which a decoding processing unit (Decoder) 101 repeats decoding processing for performing input error correction 10 times.

Note that the decoding processing unit 101 in FIG. 10 is of a fully parallel type, and can process one parallel code data in a fully parallel manner.
10, an S / P conversion unit (serial / parallel conversion unit) 102 is provided on the input side of the decoding processing unit 101, and a P / S conversion unit is provided on the output side of the decoding processing unit 102. A (parallel / serial conversion unit) 103 is provided. The S / P converter 102 converts the serial input data into parallel input data. The decoding processing unit 101 performs decoding processing on parallel input data in parallel, and outputs parallel output data. The parallel output data is converted into serial output data by the P / S conversion unit 103.

In the case of FIG. 10, since the input data to be decoded has been repeatedly processed in the decoding processing unit 101, the data being processed for the input data remains in the decoding processing unit 101 until 10 iterations are completed. It stays.
Therefore, new input data cannot be given to the decoding processing unit 101 until the iteration in the decoding processing unit 101 is completed.

For this reason, the processing capability of the fully parallel decoder of FIG. 10 is calculated by the following formula.
Processing capacity = (F × code length) / (N × Y)
However,
“F” is the operation clock frequency of the decoding processing unit 101 “N” is the number of iterations of the decoding process “Y” is the number of cycles required for one decoding process (the number of required clocks)
It is.

For example, assuming that the operating clock frequency F is 100 [MHz], the code length is 1000 [bit], the number of iterations N is 10, and the required cycle number Y of the decoding process is 1, the processing capability of the decoder 100 is as follows: Street.
Processing capacity = (100 [MHz] × 1000 [bit]) / (10 × 1)
= 10 [Gbit / s]

According to the above formula relating to processing capability, in order to improve the processing capability at a certain code length, (1) increase the operating clock frequency F, (2) reduce the number of iterations N, and (3) the required cycle of decoding processing. Three things can be considered to reduce the number Y.
However, it is necessary to wait for the progress of semiconductor circuit technology to increase the operating clock frequency F, and it is not a category measure that can be dealt with by improving the decoder itself.
In addition, if the number of iterations N of the decoding process is reduced, the decoding accuracy is lowered. Therefore, it is difficult to adopt a measure for increasing the processing capacity of the decoder until the decoding accuracy is lowered. Specifically, the number of iterations is the worst case, and for example, it is desired to secure about 10 times.

  Then, from the viewpoint of the above formula, reducing the required number of cycles (number of required clocks) Y for one decoding process is the only practical improvement in the decoder itself for improving the processing capability. It becomes a policy.

  However, even if the required number of cycles Y of the decoding process is reduced, the required number of cycles Y of the decoding process is “1” which is the minimum value. The processing capacity cannot be improved. That is, about 10 [Gbit / s] obtained by the above numerical example is a practical limit processing capability (limit speed).

Of course, if the decoder has a plurality of decoding processing units (for example, 10 decoding processing units) arranged for the number of iterations of the decoding process (hereinafter referred to as “super-parallel decoder”), each decoding process is performed. It is also conceivable to improve the processing capability as a whole by performing pipeline processing in a plurality of decoding processing units without repeating decoding processing. In this case, since there is no repetition, the processing capability can be further improved.
However, the decoding processing unit is originally a large-scale circuit, and providing a plurality of such decoding processing units increases the circuit scale unrealistically.
Therefore, a massively parallel decoder is not a realistic measure.

  Therefore, an object of the present invention is to provide a decoder or the like that can improve the processing capability while iterating the decoding process in the decoding processing unit.

(1) The present invention is a decoder in which a decoding processing unit repeatedly performs decoding processing on encoded input data, and the decoding processing unit is divided into the decoding processing to be repeated. A plurality of stages for sequentially executing a plurality of partial processes in accordance with an operation clock of a decoding processing unit, wherein the plurality of stages includes a first stage for executing a first partial process in the decoding process; A final stage that performs a final partial process, and the final stage and the leading stage are connected to give the output of the final stage to the leading stage so that the decoding process can be repeated, The input before the repetition of the decoding process on the input data previously input to the decoding processing unit ends, and the input previously input to the decoding processing unit Processing data for over data is, at the timing that is present in the stage other than the first stage, a decoder, characterized in that it is configured to the new input data is processed in the first stage.

  According to the present invention, the decoding process for the next input data can be started without waiting for the end of the repetition of the decoding process for certain input data. Therefore, the processing capability of the decoder can be improved.

(2) An input time interval in which the input data is given to the decoding processor is X,
Let Y be the repetition time interval of the decoding process,
When the number of times the decoding process can be repeated is N,
A decoder configured to satisfy the following equation is preferred.
Formula: (Y × N) <Least common multiple of X and Y In this case, data collision can be reliably avoided.

(3) In the above (2), it is preferable that X and Y are relatively prime. In this case, the least common multiple of X and Y increases, and Y × N can be increased.
(4) In any one of the above (1) to (3), a means for adjusting an operation clock frequency of the decoding processing unit and adjusting an input time interval at which the input data is given to the decoding processing unit. It is preferable to provide. In this case, the input time interval can be adjusted by adjusting the operation clock frequency.

  According to the present invention, it is possible to improve the processing capability while repeating the decoding process in the decoding processing unit.

It is a schematic block diagram of the communication system of 1st embodiment. It is a figure which shows an example of a response | compatibility with transmission data and demodulation data. It is a block diagram of a decoder. It is a figure which shows an example of a check matrix. 5 is a Tanner graph of the parity check matrix shown in FIG. It is a detailed block diagram of a decoder. It is explanatory drawing of the input space | interval to a decoding process part. It is a figure which shows the flow of a process in a decoding process part. It is a figure which shows the flow of a process in a decoding process part. It is a basic block diagram of the decoder which performs iterative decoding processing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of a communication system having a decoder according to an embodiment of the present invention. As shown in FIG. 1, the communication system includes a transmission device (transmission-side communication device) S that transmits encoded data, and a reception device (reception-side communication device) R that receives and decodes the encoded data. ing.

The transmission device S adds a redundant bit for error correction to transmission information to generate a transmission code (encoded data), and a predetermined (K + M) bit code from the encoder 1 And a modulator 2 that modulates and outputs to the communication path 3 in accordance with the above method.
The encoder 1 adds M bits of redundant bits for parity calculation to the K bits of information to generate (K + M) bits of LDPC (low density parity check) encoded data. In the low density parity check matrix, rows correspond to redundant bits and columns correspond to code bits.

It should be noted that, in which bits of the (K + M) bits of LDPC encoded data, the K information bits and the M redundant bits are arranged as determined by the transmission side and the reception side. Also good.
The modulator 2 performs modulation such as amplitude modulation, phase modulation, code modulation, frequency modulation or orthogonal frequency division multiplexing modulation according to the configuration of the communication path 3.

  For example, when the communication path 3 is an optical fiber, the modulator 2 performs light intensity modulation (a kind of amplitude modulation) by changing the luminance of the laser diode according to the transmission information bit value. In other words, when the transmission data bit is “0”, it is converted to “+1”, and the light emission intensity of the laser diode is increased for transmission. When the transmission data bit is “1”, it is changed to “−1”. After conversion, the emission intensity of the laser diode is weakened and transmitted.

The receiving device R demodulates the modulated signal transmitted via the communication path 3 to demodulate the (K + M) bit digital code, and the (K + M) bit from the demodulator 4. And a decoder 5 that reproduces the original K-bit information by subjecting the code to a decoding process based on a parity check matrix.
The demodulator 4 performs demodulation processing according to the transmission form in the communication path 3. For example, in the case of amplitude modulation, phase modulation, code modulation, frequency modulation, orthogonal frequency division multiplexing modulation, etc., the demodulator 4 performs processing such as amplitude demodulation, phase demodulation, code demodulation, and frequency demodulation.

FIG. 2 is a diagram showing a list of correspondence relationships between output data of the modulator 2 and the demodulator 4 when the communication path 3 is an optical fiber.
In FIG. 2, as described above, when the communication path 3 is an optical fiber, the modulator 2 converts the transmission data to “1” when the transmission data is “0”, and the transmission laser diode (light emitting diode) When the emission intensity increases and the transmission data bit is “1”, it is converted to “−1”, and the emission intensity of the laser diode is reduced to transmit.

The light intensity transmitted to the demodulator 4 due to transmission loss in the communication path 3 has an analog intensity distribution from the strongest intensity to the weakest intensity. The demodulator 4 performs a quantization process (analog / digital conversion) on the input optical signal to detect the received light level.
FIG. 2 shows the received signal intensity when the light reception level is quantized in eight steps. That is, when the light reception level is data “7”, the light emission intensity is considerably high, and when the light reception level is “0”, the light intensity is considerably low.

Each received light level is associated with signed data and output from the demodulator 4. The output of the demodulator 4 is data “3” when the light reception level is “7”, and data “−4” when the light reception level is “0”. Therefore, the demodulator 4 outputs a multilevel quantized signal with respect to the 1-bit received signal.
The decoder 5 receives (K + M) -bit received encoded data (each bit includes multi-value information) given from the demodulator 4 and receives a sum-product decoding method, or An LDPC parity check matrix is applied in accordance with a mini-sum decoding method or a fast mini-sum decoding method, which is a modified algorithm of this, to restore (error correction) the original K-bit information.

In FIG. 2, the demodulator 4 generates bits quantized to 8 levels. However, in general, the demodulator 4 can perform decoding using bits quantized to L values (L ≧ 2).
In FIG. 2, a binary signal may be generated by using a comparator to determine the level of the received signal using a certain threshold value.

FIG. 3 is a diagram schematically showing the basic functions of the decoder 5.
In FIG. 3, the demodulator 4 and the communication path 3 are also shown.
The demodulator 4 includes a demodulation circuit 4a that demodulates a signal applied from the communication path 3, and an analog / digital conversion circuit 4b that converts an analog demodulated signal generated by the demodulation circuit 4a into a digital signal. Output data (encoded data) Xn from the digital conversion circuit 4 b is supplied to the decoder 5.

  The encoded data Xn given to the decoder 5 is L value (L ≧ 2) data. Since the encoded data Xn is multilevel quantized data, hereinafter, the data Xn may be referred to as a symbol.

The decoder 5 performs a decoding process on the input symbol Xn according to a decoding method such as a so-called sum product decoding method or minisum decoding method, and generates a code bit Cn as decoded data.
The decoder 5 also includes a log likelihood ratio calculation unit 6 (which may be simply referred to as the calculation unit 6) that generates a log likelihood ratio λn of the demodulated symbol Xn from the demodulator 4, and a calculation unit 6. The S / P conversion unit 7 that converts the serial log likelihood ratio λn output from the parallel log data to the code length, and the log likelihood ratio storage unit 8 that can store a plurality of parallel log likelihood ratio λn data. And a decoding processing unit 11 (which may be simply referred to as the processing unit 11) that performs decoding processing using the parallel log likelihood ratio λn as input data.

The log likelihood ratio λn calculator 6 generates the log likelihood ratio λn independently of the noise information of the received signal. Normally, when noise information is considered, the log likelihood ratio λn is given by Xn / (2 · σ · σ). Here, σ represents noise variance.
However, in this embodiment, the log likelihood ratio calculation unit 6 is formed by a constant multiplication circuit, and the log likelihood ratio λn is given by Xn · f. Here, f is a non-zero positive number.

The decoding processing unit 11 includes a row processing unit 9 for performing a parity check matrix row process and a column processing unit 10 for performing a parity check matrix column process.
In the decoding processing unit 11 of this embodiment, the output of the column processing unit 10 is fed back to the row processing unit 9. That is, the row processing unit 9 and the column processing unit 10 are connected in a loop.

When the decoding method is the sum product decoding method, the row processing unit 9 and the column processing unit 10 perform arithmetic processing according to the following formulas (1) and (2), and perform processing on each element of the parity check matrix row ( Row processing) and processing (column processing) for each element for the column are repeatedly executed.
Specifically, the row processing unit 9 performs an operation for calculating the external value logarithmic ratio (first variable) αmn according to the equation (1), and the column processing unit 10 calculates the prior value logarithmic ratio βmn according to the equation (2). Perform the calculation.

In the above formulas (1) and (2), n′εA (m) \ n and m′εB (n) \ m mean elements other than themselves. For the external value log ratio αmn, n ′ ≠ n, and for the prior value log ratio βmn, m ′ ≠ m.
Further, the subscript “mn” indicating the position in the matrix of α and β is usually indicated by a subscript, but in this specification, it is indicated by “horizontal characters” for the sake of readability.
In the equation (1), f is a Gallager f function, and the function sign (x) is defined by the following equation (3).

In addition, the sets A (m) and B (n) have the set [1, N] = {1, 2, when the binary M · N matrix H = [Hmn] is the parity check matrix of the LDPC code to be decoded. .., N}.
A (m) = {n: Hmn = 1} (4)
B (n) = {m: Hmn = 1} (5)

That is, the subset A (m) means a set of column indexes where 1 (non-zero element) stands in the m-th row of the parity check matrix H, and the subset B (n) A set of row indexes where 1 (non-zero element) stands in the n-th column is shown.
In order to explain more specifically, for example, a check matrix H shown in FIG. 4 is considered.
In the parity check matrix H of FIG. 4, “1” is set in the first to third columns of the first row, “1” is set in the third and fourth columns of the second row, and the third “1” stands in the fourth column to the sixth column of the row. Therefore, in this case, the subset A (m) is as follows.

A (1) = {1, 2, 3}
A (2) = {3,4}
A (3) = {4, 5, 6}

Similarly, the subset B (n) is as follows.
B (1) = B (2) = {1}
B (3) = {1, 2}
B (4) = {2,3}
B (5) = B (6) = {3}

In the parity check matrix H, when a Tanner graph is used, the connection relationship between a variable node corresponding to a column and a check node corresponding to a row is indicated by “1”. This is referred to as “1” stands ”in this specification.
That is, as shown in FIG. 5, the variable nodes 1, 2, and 3 are connected to the check node X (first row), and the variable nodes 3 and 4 are connected to the check node Y (second row). The variable nodes 4, 5, and 6 are connected to the check node Z (third row).

This variable node corresponds to a column of the check matrix H, and check nodes X, Y, and Z correspond to each row of the check matrix H. Therefore, the parity check matrix shown in FIG. 4 is applied to a code having a code length of 6 bits in total including 3 information bits and 3 redundant bits.
In the LDPC parity check matrix H, the number of “1” s is small, and the parity check matrix is a low density, thereby reducing the amount of calculation. Each condition probability P (Xi | Yi) is propagated between the variable node and the check node, and a likely code is determined for each variable node according to the MAP algorithm. Here, the conditional probability P (Xi | Yi) indicates the probability of being Xi under the condition of Yi.

On the other hand, when the decoding method is the minisum decoding method, the row processing unit 9 and the column processing unit 10 perform arithmetic processing according to the following equations (6) and (7).

As is clear from the comparison of the equations (1) and (6), the minisum decoding method is the one in which the term relating to the Galaga f function is replaced with an approximate value in the calculation of the external value logarithmic ratio αmn. Calculation load is reduced. Therefore, the minisum decoding method is one simple implementation form of the sum product decoding method.
In equation (6), the function min is an operator for obtaining the minimum value. Also, the equation (2) of the sum product decoding method and the equation (7) of the minisum decoding method are the same.

As shown in FIG. 3, the decoder 5 includes a determination unit 12 that determines the end of repetition of a decoding operation including row processing and column processing.
The determination unit 13 determines whether or not the number of iterations of the decoding process (decoding operation) including the row process and the column process has reached the end number, and when the number of iterations of the row process and the column process reaches the end number. Then, the decoding processing section 11 repeats the decoding process. Note that even before the number of iterations reaches a predetermined number of terminations, if a sufficiently accurate decoding result is obtained, the iterations may be controlled to abort the iteration.

The determination unit 12 has a function of determining a code using the external value logarithmic ratio αmn (or the prior value logarithmic ratio βmn) and the log likelihood ratio λn after the decoding operation is repeated.
Specifically, the determination unit 12 calculates Qn according to the following equation (8).

Furthermore, the determination unit 12 calculates an estimated code Cn that is decoded data according to the following equation (9).

  The calculated estimated code Cn (parallel data) is converted into serial data by the P / S converter 13 and output from the decoder 5.

Next, based on the basic function of the decoder 5 described above, the decoder 5 of the present embodiment will be described in more detail with reference to FIG.
In the decryption processing unit 11 of FIG. 3, focusing on the functional aspect, the row processing unit 9 and the column processing unit 10 are written separately, but in FIG. 6, a plurality of hardware configurations of the decryption processing unit 11 are divided. Showed the stage. The decoding processing unit 11 of the present embodiment has three stages 11a, 11b, and 11c.
Each of these three stages 11a, 11b, and 11c is for executing a partial process obtained by dividing one decoding process (one row process and one column process). For example, among the plurality of stages, the first stage 11a executes the first half of the row processing, the second stage 11b executes the second half of the row processing, and the final stage 11c executes the entire column processing.

Since the first stage 11a receives as input the sum of λn output from the log likelihood ratio storage unit 8 and βmn (initial value is 0) output from the final stage 11c, the output of the final stage 11c, The input of the leading stage 11a is connected via an adding unit 16 for adding λn and βmn. Thereby, the decoding process part 11 can repeat and perform a decoding process based on the output (beta) mn of the last stage 11c.
Note that the adding unit 16 may be considered as a part of the leading stage 11a. In this way, the leading stage 11a accepts λn and βmn as inputs.

Each of the stages 11a, 11b, and 11c sequentially executes the process in each stage according to the operation clock 15. In other words, each stage is configured to require one clock for each stage to output a processing result based on each input given to each stage 11a, 11b, 11c.
Accordingly, the decoding processing unit 11 in FIG. 6 requires 3 clocks (3 cycles) to complete one decoding process (one iteration process).

In addition, in the sum product decoding method and the minisum decoding method, the column processing can be performed only by addition. The addition can be realized by a combinational logic circuit without using a sequential circuit. In a column processing circuit configured by a combinational logic circuit, when an input is given, an operation result is output without waiting for a clock.
On the other hand, the stages 11a, 11b, and 11c according to the present embodiment perform calculations related to the partial processing that the stage is in charge of according to the input when the clock is given, and output the calculation results.
Therefore, in addition to the column processing circuit constituted by the combinational logic circuit, a memory for outputting after waiting for the clock is added to the final stage 11c that performs column processing.

Note that the number of stages in FIG. 6 is merely an example, and is not limited to this. The number of stages may be two or four or more.
Further, it is sufficient that the decoding process is executed by a plurality of stages, and it is not necessary to divide the row process and / or the column process. For example, a plurality of stages may be configured by one stage that can execute row processing and column processing in one clock (one cycle) and one or a plurality of stages including delay circuits.
Furthermore, when row processing and column processing are divided, each divided partial processing does not need to be a functionally meaningful unit.

The log likelihood ratio storage unit (input data storage unit) 8 stores a log likelihood ratio λn (parallel data) to be given to the input of the leading stage 11a. The log-likelihood ratio (input data) λn output from the log-likelihood ratio storage unit 8 is given to the leading stage 11a or other stages and used for calculations in the leading stage 11a and the like.
The log likelihood ratio storage unit 8 can store a plurality of log likelihood ratios (parallel data) λn-A, λn-B, and λn-C. One log-likelihood ratio can be selectively given to the required stage 11a. In the log likelihood ratio storage unit 8, log likelihood ratios that can be stored in the log likelihood ratio storage unit 8 so that all the input data (log likelihood ratios) to be processed in the decoding processing unit 11 can be stored. Is set to a number equal to or greater than the number of stages.

The log likelihood ratio output from the log likelihood ratio storage unit 8 to the leading stage 11 a is selected by the control unit 14. The control unit 14 selects a log-likelihood ratio required for calculation in the first stage 11 a and the like from the plurality of log-likelihood ratios stored, and outputs the log-likelihood ratio from the storage unit 8.
In FIG. 6, the range operated by the operation clock 15 is shown as the iterative processing unit 20. The iterative processing unit 20 includes those necessary for iterative processing such as the log likelihood ratio storage unit 8, the decoding processing unit 11, the determination unit 12, and the control unit 14.

FIG. 7 shows an input interval X at which parallel input data (log likelihood ratio λn) is input in the iterative processing unit 20 of FIG. Here, the code length of the LDPC code is 550 bits, and the transmission rate of the communication path of the receiver R is 10 Gbit / s.
In this case, when the frequency (processing speed) of the operation clock 15 in the iterative processing unit 20 is 200 MHz, parallel input data (log likelihood ratio λn) to be processed by the decoding processing unit 11 from the S / P conversion unit. However, the interval (input interval) X output from the S / P converter 7 and given to the iterative processor 20 is 11 cycles (11 clocks) as shown in the following equation.
Input interval X = (550 bits / 10 GHz) / (1/200 MHz) = 11 cycles

  FIG. 7 shows the input interval X in the above example. One scale of the horizontal axis in FIG. 7 is one cycle (one clock of the operation clock 15), and input data is generated and supplied to the leading stage 11a of the decoding processing unit 11 every 11 cycles.

  8 and 9 show a processing flow of the decoding processing unit 11 of the present embodiment. 8 and 9, three circles connected in a loop form the first stage 11a, the second stage 11b, and the final stage 11c. Also, □ with an internal number indicates the processing data at the stage for the first input data, △ with an internal number indicates the processing data at the stage for the second input data, and ○ with the internal number indicates the third input data. Process data at the relevant stage for 、, and ◇ with internal numbers indicate the process data at the relevant stage for the fourth input data. Each numerical value in □, △, ○, and ◇ indicates the number of iterations of the decoding process.

  First, at CLK = 0, the first input data □ is given to the input side of the leading stage 11a, and the first decoding process is performed between CLK = 1 to CLK3. At CLK = 1, the partial process shared by the leading stage 11a is performed in the decoding process, and the processing result is output from the leading stage 11a. At CLK = 2, the calculation of the partial process shared by the second stage 11b is performed in the decoding process, and the processing result is output from the second stage 11b. At CLK = 3, a partial process shared by the final stage 11c is performed in the decoding process, and the processing result (βmn) is output from the final stage 11c and given to the head stage 11a side. Thus, the first decoding process of the decoding process is completed.

  Further, the second decoding process for the first input data □ is performed between CLK = 4 and CLK = 6. At CLK = 4, the calculation result (βmn) of the first decoding process and the log likelihood ratio λn as the first input data selectively output from the log likelihood ratio storage unit 8 are used in the first stage 11a. Partial calculation is performed, and the same processing as the first decoding processing is performed.

  Further, the third decoding process for the first input data □ is performed during CLK = 7 to CLK9, and the fourth decoding process for the first input data □ is performed during CLK = 10 to CLK12. Is called. During the above, the log likelihood ratio storage unit 8 always outputs the log likelihood ratio λn as the first input data.

  At CLK = 11 during the fourth decoding process, second input data Δ is given as new input data from the log likelihood ratio storage unit 8 to the input side of the leading stage 11a. The calculation (first decoding process) of the leading stage 11a is performed on the two input data Δ. Since the processing data for the first input data □ is present in the final stage 11c at the time of CLK = 12, the collision between the processing data for the first input data and the processing data for the second input data is avoided. .

At CLK = 13, in the fifth decoding process for the first input data □, the calculation in the leading stage 11a is executed. At this time, the log-likelihood ratio storage unit 8 selectively outputs the log-likelihood ratio λn as the first input data for use in the calculation in the leading stage 11a.
Although not shown, when the process for the second input data Δ is performed in the leading stage 11a at CLK = 15 or the like, the log likelihood ratio storage unit 8 receives the log likelihood as the second input data. The power ratio λn is selectively output.

  As described above, the sixth decoding process for the first input data is performed at CLK = 16 to CLK = 18, and the seventh decoding process for the first input data is performed at CLK = 19 to CLK = 21. Decryption processing is performed. At the same time, the second to fourth decoding processes for the second input data also proceed.

Further, at CLK = 22 to CLK = 24, the eighth decoding process for the first input data is performed. At CLK = 22 during the eighth decoding process, third input data ◯ is given as new input data from the log likelihood ratio storage unit 8 to the input side of the leading stage 11a, and at CLK = 23, The calculation (first decoding process) of the first stage 11a is performed on the third input data ○.
Since the processing data for the first input data □ exists in the second stage 11b and the processing data for the second input data Δ exists in the final stage 11c at the time of this CLK = 23, it is new input data. Collision between the processing data for the third input data and the processing data of the first and second data input previously is avoided.

At CLK = 24, in the fifth decoding process for the second input data Δ, the calculation in the leading stage 11a is executed. At this time, the log-likelihood ratio storage unit 8 selectively outputs the log-likelihood ratio λn as the second input data for use in the calculation in the leading stage 11a.
Further, when the process for the first input data □ is performed in the leading stage 11a at CLK = 25, 28, etc., the log likelihood ratio storage unit 8 receives the log likelihood ratio λn as the first input data. Are selectively output.
Further, when the processing for the third input data ○ is performed in the leading stage 11a at CLK = 26, 29, etc., the log likelihood ratio storage unit 8 receives the log likelihood ratio λn as the third input data. Are selectively output.

  As described above, when CLK = 25 to CLK = 27, the ninth decoding process for the first input data □ is performed, and for CLK = 28 to CLK = 30, the 10th for the first input data □. A second decoding process is performed. At the same time, the fifth to seventh decoding processes for the second input data Δ and the first to third decoding processes for the third input data ◯ proceed.

At CLK = 30, fourth input data ◇ is given as new input data from the log likelihood ratio storage unit 8 to the input side of the leading stage 11a. At CLK = 31, the leading stage 11a with respect to the fourth input data ◇. (The first decoding process) is performed.
At the time of CLK = 30, the process in the final stage 11c of the 10th decoding process (upper limit of the number of iterations) for the first input data □ is completed. For this reason, the processing data for the first input data is discarded and is not reflected in the input of the leading stage 11a. Therefore, at the next CLK = 31, there is no data being processed in the first stage 11a.
Therefore, collision between the newly input fourth input data and the previously input data is avoided.

  As described above, in the decoding processing unit 11 according to the present embodiment, the collision between the processing data for the previously input data and the newly input data is avoided. Before the decoding process is completed, the next data can be received by the decoding processing unit 11 to process a plurality (three) of input data.

  Therefore, when processing a large number of input data, the processing speed of the decoder 5 according to the present embodiment is on the order of (frequency of the operation clock 15) × (code length), and the number of decoding processing iterations N or 1 The processing speed does not deteriorate due to the required number of cycles (number of required clocks) Y of the decoding process.

  In addition, in the decoding processing unit 11 of the present embodiment, data collision can be avoided without performing special control such as control of timing for giving input data to the decoding processing unit 11. In other words, in the present embodiment, even if input data that is sequentially generated is simply processed sequentially by the decoding processing unit 11, processing data for the data previously input to the decoding processing unit 11 and newly input data Collisions can be avoided.

Conditions for avoiding this collision are as shown in the following conditional expression.
Conditional expression: (Y × N) <Least common multiple of X and Y
X: Input time interval at which input data is given to the first stage Y: Repetition time interval of decoding process (number of stages)
N: Number of times the decoding process can be repeated In the example of FIG. 6, X = 11, Y = 3, and N = 10.

“Y × N”, which is the left side of the conditional expression, is the maximum time that the processing data for one input data stays in the decoding processing unit 11 for repeated decoding processing.
Further, “the least common multiple of X and Y” = LCM (Y, X), which is the right side of the conditional expression, is an interval at which the input to the decoding processing unit 11 collides with the iteration in the decoding processing unit.
The collision occurs by shortening the maximum time that the processing data for a certain input data stays in the decoding processing unit 11 for repeated decoding processing, compared to the collision interval obtained by LCM (Y, X). Before, the stage of the decoding processing unit 11 can be opened to new input data, and data collision can be prevented.

  In the example of FIG. 6, LCM (3, 11) = 33 cycles. The 33rd cycle (CLK = 33) corresponds to the 11th iteration in terms of the first input data, but in the example of FIG. 6, the maximum number of iterations N is set to 10, so FIG. As shown, the processing data for the first input data is erased from the decoding processing unit 11 before the 11th iteration where the collision occurs (at the end of the 10th iteration), and the collision is avoided.

  By setting each value of X, Y, and N so as to satisfy the above conditional expression, a decoder having an excellent processing speed can be designed. At this time, in order to increase the repeatable number of times N, it is preferable that X and Y are relatively prime. If X and Y are relatively prime, LCM (Y, X) increases, and the repeatable number N can be increased.

  According to the present embodiment, high-speed processing can be realized and the design of the decoding processing unit 11 is easy even if the time Y for performing one decoding processing in the decoding processing unit 11 is not set to the minimum value “1”. become.

  Here, when the desired number of iterations N is first determined when the decoder 5 is designed, the minimum decoding process iteration interval (stage) for obtaining the desired iteration number N at a predetermined input interval X. Number) Y may be set.

  Further, in designing the decoder 5, in order to adjust the input interval X, the frequency of the operation clock 15 may be adjusted without changing the design of the decoding processing unit 11.

(Example 1)
For example, consider the case where it is desired to increase the transmission speed of the communication path 4 in FIG. 6 after the decoder 5 in FIG. 6 is designed. When the transmission speed is increased, the cycle interval (number of clocks) at which parallel input data is output from the S / P converter 7 is reduced if the operation clock frequency is the same.
If the input interval X in FIG. 6 where X = 11 is 9 cycles, LCM (Y, X) = LCM (3,9) = 9. In this case, when the maximum value of the repeatable number N is obtained from the above conditional expression, the repeatable number N = 2.

That is, conditional expression: (Y × N) <Least common multiple of X and Y
3 × N <LCM (3,9) = 9
N <3

(Example 2)
Also, consider a case where it is desired to further increase the transmission speed of the communication path 4 in FIG. When the transmission speed is further increased, if the operation clock frequency is the same, the cycle interval (number of clocks) at which parallel input data is output from the S / P converter 7 is further reduced. Here, it is assumed that the input interval X = 8. In this case, the repeatable number of times N = 8.

In this case, the conditional expression: (Y × N) <Least common multiple of X and Y
3 × N <LCM (3,8) = 24
N <9

  In the case of FIG. 6, the number of repetitions of 10 was ensured, but in Example 1 above, the number of repetitions N was reduced because the transmission speed was increased. As a result, the decoding accuracy is lowered due to the insufficient number of iterations. On the other hand, in Example 2 above, when the transmission rate was further increased than in Example 1, the number of repeatable times N was larger than in Example 1.

  Therefore, in the case of Example 1, the frequency of the operation clock 15 is lowered, the operation speed of the decoding processing unit 15 is lowered, and the input interval X is further lowered than 9, and X = 8 as in Example 2. Thus, as in Example 2, the repeatable number of times N = 8. Thus, by changing the frequency of the operation clock, it is possible to secure an appropriate numerical value as the repeatable number N without changing the configuration of the decoding processing unit 11.

Contrary to Examples 1 and 2, when the transmission speed becomes low, the input interval X becomes large. When the input interval X is increased and LCM (Y, X) is also increased, the number of repeatable times N can be increased. However, when a certain number of times (for example, 10 times) is performed, the number of repetitions is more than that. Therefore, it is not possible to expect improvement in restoration accuracy, and so many iterations are not required.
Therefore, when the transmission rate is low and the sufficient number of repetitions can be ensured, the frequency of the operation clock 15 is intentionally reduced to prevent the input interval X from increasing (for example, X = 11). In this case, since the operation clock frequency can be lowered, the power consumption of the decoder 5 can be suppressed.

  In the present embodiment, the control unit 14 has a function of adjusting the frequency of the operation clock 15 according to the transmission speed of the communication path. Therefore, during the operation of the decoder 5, the input interval (number of cycles) X can be dynamically adjusted to secure the necessary number of iterations, and the power consumption of the decoder 5 can be reduced.

The embodiments disclosed thus far are all illustrative and not restrictive. The scope of the present invention is indicated by the scope of claims for patent, and all modifications within the scope equivalent to the structure of the claims for patent are included in the present invention.
For example, the decoder of the decoder of the present invention is not limited to an LDPC code decoder, and may be another iterative decoding type decoder such as a turbo decoder.
In the above embodiment, the log likelihood ratio storage unit 8 outside the decoding processing unit 11 gives the log likelihood ratio λn to the first stage 11a, but each stage 11a, 11, 11c has a storage unit of λn. The log likelihood ratio λn for the input data to be processed may be stored as part of the processing data so that each stage 11a, 11b, 11c can hold the log likelihood ratio λn. Further, as a decoding process, the log likelihood ratio storage unit 8 is not required when a method that uses the log likelihood ratio in the first iteration but does not use the log likelihood ratio λn in the second iteration.
Furthermore, in the above-described embodiment, the decoding processing unit 11 is shown as a fully parallel type, but may be a partially parallel type.

1: Encoder 2: Modulator 3: Communication Channel 4: Demodulator 4a: Demodulator 4b: Analog / Digital Converter 5: Decoder 6: Log Likelihood Ratio Calculator 7: S / P Converter 8: Log Likelihood ratio storage unit 9: row processing unit 10: column processing unit 11: decoding processing unit 11a: first stage 11b: second stage 11c: final stage 12: determination unit
13: P / S conversion unit 14: Control unit 15: Operation clock 16: Addition unit 20: Repetition processing unit S: Transmission device R: Reception device Xn: Encoded data Cn: Decoded data λn: Log likelihood ratio

Claims (1)

The decoding processing unit is a decoder that repeatedly performs decoding processing on encoded input data,
The decoding processing unit includes a plurality of stages for sequentially executing a plurality of partial processes obtained by dividing the decoding process to be repeated according to an operation clock of the decoding processing unit,
The plurality of stages includes a first stage that executes a first partial process in the decoding process, and a final stage that executes a last partial process in the decoding process,
The final stage and the leading stage are connected to give the output of the final stage to the leading stage so that the decoding process can be repeated,
It is a timing before the end of the iteration of the decoding process on the input data previously input to the decoding processing unit, and the processing data for the input data previously input to the decoding processing unit is other than the first stage A decoder configured to process new input data in the first stage at a timing existing in the stage.

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