JP2011159773A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board for appropriately operating a semiconductor integrated circuit element by fully supplying power to the semiconductor integrated circuit element. <P>SOLUTION: In the wiring board, via lands 3L for grounding, formed within a power plane 3P and vias 6 connected to the via lands 3L for grounding are thinned out and formed to correspond to only partial pads in each row of semiconductor element connection pads 7G for grounding, and a conducting path from each row of the semiconductor element connection pads 7P for power supplies to through holes 5P for power supplies are formed to pass through the thinned-out parts in the power plane 3P. A number of power supply paths to the semiconductor element connection pads 7 are secured, and then fully supplies power to the semiconductor integrated circuit element S, so that the semiconductor integrated circuit element S is appropriately operated. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a wiring board for mounting a semiconductor integrated circuit element.

  Conventionally, a wiring board formed by a build-up method is known as a wiring board for mounting a semiconductor integrated circuit element. FIG. 9 is a schematic cross-sectional view showing an example of a conventional wiring board formed by a build-up method, and FIG. 10 is a schematic top view of the main part of the wiring board shown in FIG. In FIG. 9, hatching is omitted.

  As shown in FIG. 9, the conventional wiring substrate 30 has the build-up insulating layers 22 and the build-up wiring layers 23 alternately stacked on the upper and lower surfaces of the core substrate 21, and the semiconductor integrated circuit element S at the center of the upper surface. Has a mounting portion 30a.

  A core conductor layer 24 made of copper foil or a copper plating layer is deposited on the upper and lower surfaces of the core substrate 21. In addition, a large number of through-holes 25 are formed from the upper surface to the lower surface of the core substrate 21 to which a copper plating layer that functions as a part of the core conductor layer 24 is deposited.

  A plurality of via holes 26 are formed in each of the build-up insulating layers 22, and a build-up wiring layer 23 made of a copper plating layer is deposited on the surface of each build-up insulating layer 22 including the via holes 26. Yes. The build-up wiring layer 23 is electrically connected to the through-hole 25 while the upper and lower layers are connected to each other through the via hole 26. Further, a part of the buildup wiring layer 23 deposited on the outermost buildup insulating layer 22 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 30a. The circular semiconductor element connection pads 27 are formed, and these semiconductor element connection pads 27 are arranged in a lattice pattern corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . Further, a part of the lower surface side deposited on the outermost buildup insulating layer 22 is a circular external connection pad 28 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of lines 28 are arranged in a lattice pattern.

  Further, a solder resist layer 29 for exposing the semiconductor element connection pads 27 and the external connection pads 28 is deposited on the outermost buildup insulating layer 22 and the buildup wiring layer 23 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 27, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 28 via the solder ball. Are electrically connected.

  By the way, the semiconductor integrated circuit element S is provided with a large number of electrode terminals T for grounding and power supply alternately in the central portion of the lower surface in order to ensure sufficient power supply from the wiring board 30 and on the outer peripheral portion of the lower surface. Increasing use is made of a terminal arrangement in which a large number of signal electrode terminals are provided. When such a semiconductor integrated circuit element S is mounted, the arrangement of the semiconductor element connection pads 27 on the wiring board 30 is also arranged at the center of the mounting portion 30a corresponding to the electrical terminal T of the semiconductor integrated circuit element S for grounding and power supply. A large number of semiconductor element connection pads 27 are arranged, and a large number of signal semiconductor element connection pads 27 are arranged on the outer peripheral portion of the mounting portion 30a.

  FIG. 11 shows only the grounding and power supply semiconductor element connection pads 27 in the central portion of the mounting portion 30a. In FIG. 11, the semiconductor element connection pad 27 indicated by G is a ground semiconductor element connection pad 27G, and the semiconductor element connection pad 27 indicated by P is a power supply semiconductor element connection pad 27P. As shown in FIG. 11, the semiconductor element connection pads 27G for grounding and the semiconductor element connection pads 27P for power supply are alternately arranged in a grid-like arrangement so as to form diagonal rows. At the same time, the semiconductor element connection pads 27 in each row are integrated one by one as a band-like integrated pattern.

  These grounding and power supply semiconductor element connection pads 27 are electrically connected to the through holes 25 through the underlying buildup wiring layer 23 as shown in FIG. FIG. 12 is a perspective view showing a part of the semiconductor element connection pads 27 and the corresponding lower build-up wiring layer 23 and core conductor layer 24 shown in FIG. The position of the via 26 to be connected to is indicated, and the mark x indicates the position to which the via 26 from the upper layer is connected.

  The next build-up wiring layer 23 to which the semiconductor element connection pad 27 is connected is mainly a ground plane 23G, in which a via land 23L connected to the power supply semiconductor element connection pad 27P is arranged via a clearance 23C. It is installed. The via lands 23L are arranged in a one-to-one manner so as to form a row at a position corresponding to the power supply semiconductor element connection pad 27P of each row, and the clearance 23C of each row of the via land 23L is connected to one. Therefore, the ground plane 23G is in a state of being separated in a strip shape so as to correspond to each row of the grounding semiconductor element connection pads 27G by a single clearance 23C. The grounding semiconductor element connection pad 27G is connected to the band-shaped portion sandwiched by the clearance 23C of the ground plane 23G via the via 26 from each grounding semiconductor element connection pad 27G, and the semiconductor element connection for power supply The pads 27P are connected to the corresponding via lands 23L via the vias 26 on a one-to-one basis.

  The lower build-up wiring layer 23 is mainly a power plane 23P, and a via land 23L connected to the upper ground plane 23G is disposed therethrough via a clearance 23C. The via lands 23L are arranged in a one-to-one manner so as to form a column at a position corresponding to the grounding semiconductor element connection pad 27G in each column, and in the same manner as in the upper build-up wiring layer 23, The clearance 23C is connected to one. Therefore, the power supply plane 23P is in a state of being separated in a band shape so as to correspond to each row of the power supply semiconductor element connection pads 27 by a single clearance 23C. The upper ground plane 23G is connected to the via land 23L corresponding to the ground semiconductor element connection pad 27G via the via 26, and is connected to the power semiconductor element connection pad 27P. The via land 23L is connected to a band-like portion sandwiched by the clearance 23C of the power plane 23P via a via 26 from the upper via land 23L.

  The lower core conductor layer 24 is mainly a ground plane 24G, and the ground plane 24G is connected to a grounding through hole 25G and a through hole land 24L connected to a power supply through hole 25P therein. Is disposed via a clearance 24C. The upper via land 23L connected to the ground plane 23G is connected to the ground plane 24G via the via 26, and the upper power plane 23P is connected to the through-hole land 34L via the via 26. As a result, the grounding semiconductor element connection pad 27G is electrically connected to the grounding through hole 25G, and the power supply semiconductor element connection pad 27P is electrically connected to the power supply through hole 25P. Become.

  However, since the pitch of the through holes 25 is generally larger than the pitch of the semiconductor element connection pads 27, for example, taking the row of the semiconductor element connection pads 27P for power supply indicated by A in FIG. The through hole 25P for power supply is not located below the band-like portion of the power supply plane 23P connected to the semiconductor element connection pad 27P in this column. As a result, in this portion, the current path to the power supply through hole 25P largely bypasses the clearance 23C of the power supply plane 23P. Since a large number of vias 36 for connecting to the power supply semiconductor element connection pads 27P in the column A are connected to this portion, a large current flows in a concentrated manner in this largely detoured current path. As a result, sufficient power cannot be supplied to the semiconductor element connection pads 27P for power supply in the column A through this current path, and good operation of the semiconductor integrated circuit element S is impaired.

JP 2003-332377 A

  The problem to be solved by the present invention is to secure a large number of power supply paths from the through holes in the core substrate to the semiconductor element connection pads to supply sufficient power to the semiconductor integrated circuit element. An object of the present invention is to provide a wiring board that can be operated satisfactorily.

  The wiring board of the present invention includes a core substrate having a plurality of first through holes connected to the first potential and a plurality of second through holes connected to the second potential, and an upper surface of the core substrate. A plurality of stacked build-up insulating layers and a plurality of one-by-one or a plurality of build-up insulating layers arranged in a grid pattern on the upper surface of the uppermost build-up insulating layer are arranged in a row, A first semiconductor element connection pad electrically connected to the first through hole and a second semiconductor element connection pad electrically connected to the second through hole, and the buildup insulating layer. A first power supply plane electrically connected to the first semiconductor element connection pad through a via connected to a position corresponding to each column of the first semiconductor element connection pad, and Second semiconductor Via lands that are electrically connected to the second semiconductor element connection pads through vias connected to positions corresponding to the respective rows of the child connection pads and surrounded by the first power supply plane through clearances The via land and the via connected to the via land are thinned out so as to correspond to only some of the pads in each column of the second semiconductor element connection pads. And a conductive path from each row of the first semiconductor element connection pads to the first through hole is formed so as to pass through the thinned portion of the first power plane. It is what.

  According to the wiring board of the present invention, in the above configuration, the via land and the via connected to the via land are thinned out so as to correspond to only a part of the pads in each row of the second semiconductor element connection pads. And a conductive path from each column of the first semiconductor element connection pads to the first through hole is formed so as to pass through the thinned portion of the first power plane. As a result, a large number of power supply paths from the first through hole to the first semiconductor element connection pad are secured, and sufficient power is supplied to the semiconductor integrated circuit element so that the semiconductor integrated circuit element is good. Can be operated.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 3 is an enlarged view of a main part of FIG. FIG. 4 is an exploded perspective view of main parts of the wiring board shown in FIGS. 1 and 2. FIG. 5 is a schematic sectional view showing another example in the embodiment of the wiring board of the present invention. 6 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 7 is an enlarged view of a main part of FIG. FIG. 8 is an exploded perspective view of a main part of the wiring board shown in FIGS. 5 and 6. FIG. 9 is a schematic cross-sectional view showing a conventional wiring board. FIG. 10 is a schematic top view of the main part of the wiring board shown in FIG. FIG. 11 is an enlarged view of a main part of FIG. FIG. 12 is an exploded perspective view of a main part of the wiring board shown in FIGS. 9 and 10.

  Next, an example of an embodiment of the wiring board according to the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing an example of the wiring board of this example formed by the build-up method, and FIG. 2 is a schematic top view of the main part of the wiring board shown in FIG. 3 is an enlarged view of a main part in FIG. 2, and FIG. 4 is an exploded perspective view of a main part in the wiring board shown in FIGS. In FIG. 1, hatching is omitted.

  As shown in FIG. 1, a wiring board 10 of this example has build-up insulating layers 2 and build-up wiring layers 3 alternately stacked on the upper and lower surfaces of a core substrate 1, and a semiconductor integrated circuit element at the center of the upper surface. A mounting portion 10a for mounting S is provided.

  The core substrate 1 has a thickness of about 50 to 800 μm, and is made of an electrically insulating material in which a glass cloth in which glass fiber bundles are woven vertically and horizontally is impregnated with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. A large number of core conductor layers 4 made of copper foil or copper plating layers are deposited on the upper and lower surfaces, and copper plating layers that function as a part of the core conductor layers 4 are deposited from the upper surface to the lower surface of the insulating substrate. A through hole 5 is formed. The diameter of the through hole 5 is about 100 to 300 μm, and the inside is filled with resin.

  The build-up insulating layer 2 is made of an insulating material containing a thermosetting resin such as an epoxy resin, and a plurality of via holes 6 are formed in each, and the surface of each build-up insulating layer 2 including the via holes 6 is plated with copper. A build-up wiring layer 3 composed of layers is deposited. The build-up wiring layer 3 is electrically connected to the through hole 5 while being connected to each other through the via hole 6. Further, a part of the buildup wiring layer 3 deposited on the outermost buildup insulating layer 2 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 10a. The circular semiconductor element connection pads 7 are formed, and these semiconductor element connection pads 7 are formed in a lattice arrangement corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . The semiconductor element connection pads 7 have a large number of grounding and power supply semiconductor element connection pads 7 arranged at the center of the mounting part 10a, and a large number of signal semiconductor element connection pads 7 arranged at the outer periphery of the mounting part 10a. ing. Also, a part of the lower surface side deposited on the outermost buildup insulating layer 2 is a circular external connection pad 8 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of grids 8 are formed in a grid.

  Further, a solder resist layer 9 for exposing the semiconductor element connection pads 7 and the external connection pads 8 is deposited on the outermost buildup insulating layer 2 and the buildup wiring layer 3 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 9, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 8 via the solder ball. Are electrically connected.

  FIG. 3 shows only the grounding and power supply semiconductor element connection pads 7 in the center of the mounting portion 10a. In FIG. 3, the semiconductor element connection pad 7 indicated by G is a semiconductor element connection pad 7G for grounding, and the semiconductor element connection pad 7 indicated by P is a semiconductor element connection pad 7P for power supply. As shown in FIG. 3, the semiconductor element connection pads 7G for grounding and the semiconductor element connection pads 7P for power supply are alternately arranged in a grid-like arrangement so as to form diagonal rows. At the same time, the semiconductor element connection pads 7 in each row are integrated as a single band-like pattern one row at a time.

  These grounding semiconductor element connection pads 7G and power supply semiconductor element connection pads 7P are electrically connected to the through holes 5 through the underlying buildup wiring layer 3 as shown in FIG. Yes. FIG. 4 is a perspective view showing a part of the semiconductor element connection pads 7 in FIG. 3 and the corresponding build-up wiring layer 3 and core conductor layer 4 corresponding to the extracted semiconductor element connection pads 7. The position of the via 6 to be connected to is indicated, and the mark x indicates the position to which the via 6 from the upper layer is connected.

  The next build-up wiring layer 3 to which the semiconductor element connection pad 7 is connected is mainly a ground plane 3G, in which via lands 3L connected to the power supply semiconductor element connection pad 7P are arranged via a clearance 3C. It is installed. The via lands 3L are thinned out and arranged in rows corresponding to every other power supply semiconductor element connection pads 7P in each row, and the clearance 3C of each row is provided between each via land 3L. Are independent such that the ground plane 3G is interposed therebetween. For this reason, the ground plane 3G is connected to one another so as to pass between the clearances 3C surrounding the via land 3L. The grounding semiconductor element connection pad 7G is connected to the ground plane 3G via the via 6 from each grounding semiconductor element connection pad 7G, and the power supply semiconductor element connection pad 7P is connected to the via land 3L via the via 6. Every other one is connected.

  The lower build-up wiring layer 3 is mainly a power plane 3P, in which via lands 3L connected to the upper ground plane 3G are arranged via a clearance 3C. The via lands 3L are arranged in such a manner that they are thinned out so as to form rows at positions corresponding to every other semiconductor element connection pad 7G for grounding in each row, and the clearance 3C of each row is provided between each via land 3L. Are independent such that a power plane 3P is interposed therebetween. Therefore, the power planes 3P are connected together so as to pass between the clearances 3C surrounding the via land 3L. The upper ground plane 3G is connected to the via land 3L corresponding to every other semiconductor element connection pad 7G for grounding through the via 6, and the upper via land connected to the power supply semiconductor element connection pad 7 is connected. 3L is connected to the power plane 3P via a via 6 from the upper via land 3L.

  The lower core conductor layer 4 is mainly a ground plane 4G. The ground plane 4G is connected to a grounding through hole 5G, and a through hole land 4L connected to a power supply through hole 5P therein. Is disposed via a clearance 4C. The upper via land 3L connected to the ground plane 3G is connected to the ground plane 4G via the via 6, and the upper power plane 3P is connected to the through-hole land 4L via the via 6. As a result, the grounding semiconductor element connection pad 7G is electrically connected to the grounding through hole 5G, and the power supply semiconductor element connection pad 7P is electrically connected to the power supply through hole 5P. Become.

  In the wiring board of this example, as described above, the ground via land 3L and the via 6 provided in the power supply plane 3P are connected to some of the ground semiconductor element connection pads 7G in each column. It is important that only the thinned out so as to correspond. With such a configuration, a large number of conductive paths from each column of the power supply semiconductor element connection pads 7P to the power supply through holes 5P pass through the portion where the via land 3L is thinned out in the power supply plane 3P. . Therefore, a large number of power supply paths from the power supply through hole 5P in the core substrate 1 to the power supply semiconductor element connection pads 7P are secured to supply sufficient power to the semiconductor integrated circuit element S, thereby providing a semiconductor integrated circuit. The element S can be operated satisfactorily. According to the simulation performed by the present inventor using the DC current density simulator, the grounding through hole 5G and the power supply through hole are connected to the grounding semiconductor element connection pad 7G and the power supply semiconductor element connection pad 7P. Although the number of vias 6 for connection to 5P is reduced, it has been confirmed that the voltage drop when a transient current flows in the power supply to the semiconductor integrated circuit element S is greatly improved.

  Next, another example of the embodiment of the wiring board according to the present invention will be described with reference to FIGS. FIG. 5 is a schematic cross-sectional view showing an example of the wiring board of this example formed by the build-up method, and FIG. 6 is a schematic top view of the main part of the wiring board shown in FIG. 7 is an enlarged view of a main part in FIG. 6, and FIG. 8 is an exploded perspective view of a main part in the wiring board shown in FIGS. In FIG. 5, hatching is omitted.

  As shown in FIG. 5, in the wiring board 20 of this example, the build-up insulating layers 12 and the build-up wiring layers 13 are alternately laminated on the upper and lower surfaces of the core substrate 11, and the semiconductor integrated circuit element is located at the center of the upper surface. A mounting portion 20a for mounting S is provided.

  The core substrate 11 has a core conductor layer 14 made of copper foil or a copper plating layer applied to the upper and lower surfaces thereof, and a copper plating layer that functions as a part of the core conductor layer 14 from the upper surface to the lower surface of the insulating substrate. A number of through-holes 15 are formed.

  A plurality of via holes 16 are formed in each of the build-up insulating layers 12, and a build-up wiring layer 13 made of a copper plating layer is deposited on the surface of each build-up insulating layer 12 including the via holes 16. . The build-up wiring layer 13 is electrically connected to the through hole 15 while the upper and lower layers are connected to each other through the via hole 16. Further, a part of the buildup wiring layer 13 deposited on the outermost buildup insulating layer 12 on the upper surface side is electrically connected to the electrode terminal T of the semiconductor integrated circuit element S in the mounting portion 20a. The circular semiconductor element connection pads 17 are formed, and these semiconductor element connection pads 17 are arranged in a lattice shape corresponding to the electrode terminals T of the semiconductor integrated circuit element S as shown in FIG. . The semiconductor element connection pads 17 have a large number of grounding and power supply semiconductor element connection pads 17 arranged at the center of the mounting portion 20a, and a large number of signal semiconductor element connection pads 17 arranged at the outer periphery of the mounting portion 20a. ing. Further, a part of the lower surface side deposited on the outermost buildup insulating layer 12 is a circular external connection pad 18 that is electrically connected to the wiring conductor of the external electric circuit board. A plurality of 18 are formed in a grid.

  Further, a solder resist layer 19 that exposes the semiconductor element connection pads 17 and the external connection pads 18 is deposited on the outermost buildup insulating layer 12 and the buildup wiring layer 13 thereon. The electrode terminal T of the semiconductor integrated circuit element S is electrically connected to the exposed portion of the semiconductor element connection pad 17, and the wiring conductor of the external electric circuit board (not shown) is connected to the exposed portion of the external connection pad 18 via the solder ball. Are electrically connected.

  FIG. 7 shows only the grounding and power supply semiconductor element connection pads 17 in the center of the mounting portion 20a. In FIG. 7, the semiconductor element connection pad 17 indicated by G is a semiconductor element connection pad 17G for grounding, and the semiconductor element connection pad 17 indicated by P is a semiconductor element connection pad 17P for power supply. As shown in FIG. 7, the grounding semiconductor element connection pads 17G and the power supply semiconductor element connection pads 17P are alternately arranged in groups of four in a grid-like arrangement. In addition, the grounding semiconductor element connection pads 17G of each set are integrated as a net-like integrated pattern, and the power supply semiconductor element connection pads 17P of each set are integrated as four patterns. Integrated.

  The grounding semiconductor element connection pad 17G and the power supply semiconductor element connection pad 17P are electrically connected to the through hole 15 via the underlying buildup wiring layer 13 as shown in FIG. Yes. 8 is a perspective view showing a part of the semiconductor element connection pads 17 in FIG. 7 and the corresponding build-up wiring layer 13 and core conductor layer 14 corresponding to the semiconductor element connection pads 17 in FIG. The position of the via 16 to be connected to is indicated, and the mark x indicates the position to which the via 16 from the upper layer is connected.

  The next build-up wiring layer 13 to which the semiconductor element connection pads 17 are connected is mainly a ground plane 13G, in which via lands 13L connected to the power supply semiconductor element connection pads 17P are arranged via a clearance 13C. It is installed. The via lands 13L are arranged in a one-to-one manner so as to form a row at a position corresponding to the power supply semiconductor element connection pad 17P of each row, and the clearance 13C of each row is connected to one. Therefore, the ground plane 13G is in a state of being separated in a band shape so as to correspond to each row of grounding semiconductor element connection pads 17G by a clearance 13C connected to one. The grounding semiconductor element connection pad 17G is connected to the band-like portion sandwiched between the clearances 13C of the ground plane 13G via the vias 16 from the grounding semiconductor element connection pads 17G. The pad 17P is connected to the via land 13L via the via 16.

  The lower build-up wiring layer 13 is mainly a power supply plane 13P, and a via land 13L connected to the upper ground plane 13G is disposed therethrough via a clearance 13C. One via land 13L is thinned out in a row so as to form a row at a position corresponding to three of the four semiconductor element connection pads 17G in each group of grounding semiconductor element connection pads 17G. The clearance 13C of each row is independent so that the power plane 13P is interposed between each via land 13L of each set. For this reason, the power planes 13P are connected together so as to pass between the clearances 13C surrounding the respective via lands 13L. The upper-layer ground plane 13G is connected to the via land 13L corresponding to three of the four semiconductor element connection pads 17G in each set of the semiconductor element connection pads 17G for grounding via the vias 16. The upper via land 13L connected to the semiconductor element connection pad 17P is connected to the power supply plane 13P via the via 16 from the upper via land 13L.

  The lower core conductor layer 14 is mainly a ground plane 14G. The ground plane 14G is connected to a grounding through hole 15G, and a through hole land 14L connected to a power supply through hole 15P therein. Is disposed via a clearance 14C. The upper via land 13L connected to the ground plane 13G is connected to the ground plane 14G via the via 16, and the upper power plane 13P is connected to the through-hole land 14L via the via 16. As a result, the grounding semiconductor element connection pad 17G is electrically connected to the grounding through hole 15G, and the power supply semiconductor element connection pad 17P is electrically connected to the power supply through hole 15P. Become.

  In the wiring board of this example, as described above, the ground via land 3L and the via 6 provided in the power supply plane 13P are part of the ground semiconductor element connection pads 7G in each column. It is important that only the thinned out so as to correspond. With such a configuration, a large number of conductive paths from each row of the power supply semiconductor element connection pads 17P to the power supply through holes 15P pass through the portion where the via land 13L is thinned out in the power supply plane 13P. . Therefore, as in the case of the above-described embodiment, a large number of power supply paths from the power supply through hole 15P to the power supply semiconductor element connection pad 17P are secured, and sufficient power is supplied to the semiconductor integrated circuit element S. The semiconductor integrated circuit element S can be satisfactorily operated by supplying the power. Needless to say, the present invention is also applied to the case where the grounding potential and the power supply potential are interchanged.

DESCRIPTION OF SYMBOLS 1,11 Core board | substrate 2,12 Buildup insulating layer 3,13 Buildup wiring layer 5,15 Through hole 6,16 Via 7,7 Semiconductor element connection pad

Claims (1)

  A core substrate having a plurality of first through-holes connected to the first potential and a plurality of second through-holes connected to the second potential, and a multi-layer build stacked on the upper surface of the core substrate The upper insulating layer and the uppermost build-up insulating layer are arranged in a grid pattern on the upper surface so that one or more of them are alternately arranged in rows. A first semiconductor element connection pad electrically connected and a second semiconductor element connection pad electrically connected to the second through-hole, and the buildup insulating layer; First power plane and second semiconductor element connection pads electrically connected to the first semiconductor element connection pads via vias connected to positions corresponding to respective columns of one semiconductor element connection pad Each column A wiring board having a via land that is electrically connected to the second semiconductor element connection pad through a via connected to a corresponding position and surrounded by the first power supply plane through a clearance. The via land and the via connected to the via land are thinned out so as to correspond to only a part of the pads in each column of the second semiconductor element connection pads, and the first land A wiring board, wherein a conductive path from each row of the semiconductor element connection pads to the first through hole is formed so as to pass through the thinned portion of the first power supply plane.

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