JP2011158965A - Logic simulation system and logic simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic simulation system for reducing man-hours required for checking a part different from an expected value. <P>SOLUTION: The logic simulation system is provided with: a timing check expected value comparison means 16 for performing timing check on the processing result of a pre-stage logic circuit block 4 to determine whether the processing result is a timing error or not, and for, when determining that the processing result is the timing error, checking the operation or state of the processing result to determine whether the processing result is a true error or not; and a timing check signal value fixing means 17 for, when it is determined that the processing result is the true error by the timing check expected value comparison means 16, rewriting the processing result of the pre-stage logic circuit block 4 with a preset expected value 13, and for output of it as a signal value to a post-stage logic circuit block 5. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a logic simulation system and a logic simulation method for verifying the operation of a logic circuit, and more particularly to a logic simulation system and a logic simulation method for checking timing errors of a plurality of stages of logic circuit blocks.

  A logic circuit designed for LSI (Large Scale Integration) is subjected to a logic simulation to verify the operation in order to confirm the reliability. In recent years, with the increase in the size of logic circuits, the number of man-hours for confirming the results of logic simulations has increased, and the need to reduce (reduce) the man-hours for confirming whether device operation matches the logic simulation results has increased. ing.

  In such a growing demand, for example, in Patent Document 1, in order to reduce the simulation execution time and the number of times, the operation of a logic circuit composed of a plurality of successive logic circuit blocks 104 and 105 is confirmed. Expected value for sequentially comparing the processing result of the previous logic circuit block 104 and the expected value 113 in a simulation in which sequential processing is performed from the logic circuit block 104 and the processing result is transferred to the subsequent logic circuit block 105. There is disclosed a simulation system having a comparison means 108 and provided with a signal value fixing means 109 for replacing the signal value passed to the subsequent logic circuit block 105 with an expected value 113 (see FIG. 9). The expected value comparison means 108 compares the expected value corresponding to the expected value 113 with the timing of the falling edge 125 of the clock signal 120 and the extracted signal value 127 of the signal 121 from the logic circuit block 104 to the logic circuit block 105. A mismatch is determined (see FIG. 10). When there is a mismatch, the signal value fixing means 109 signals the signal value 128 that does not match the expected value of the signal 122 from the logic circuit block 104 to the logic circuit block 105 to the expected value 129 obtained from the expected value 113. Overwrite the value. According to this simulation system, the logic circuit block 105 at the subsequent stage receives and processes the signal value replaced with the expected value 113 by the signal value fixing means 109, thereby using the correct input value for obtaining the expected value 115. The simulation by the expected value comparing means 110 is effective.

JP 2004-355433 A (FIGS. 1 and 2)

  However, the simulation system described in Patent Document 1 has a problem in that manual confirmation work for locations where the expected values of the logic simulation do not match increases. In other words, in the simulation system described in Patent Document 1, when the expected value mismatch occurs as a result of the logic simulation, all the simulation results are replaced with the expected value 113. If all the simulation results are replaced with the expected value 113, it is necessary to manually check whether the expected value mismatch is really a circuit error. The mismatch of expected values includes a true error due to a mistake in the circuit and a pseudo error that does not cause a problem in the circuit, so it is necessary to manually check whether the error is a true error or a pseudo error. This is necessary and increases the number of confirmation work steps. As the number of mismatched portions increases, the number of confirmation work steps increases, and when all the circuits in the mismatched portion are corrected, the number of steps required for correction becomes enormous. Further, if all the mismatched portions are determined as pseudo errors and the circuit is not corrected, the created circuit may not operate correctly.

  The main subject of this invention is providing the logic simulation system and the logic simulation method which can reduce the man-hour for the confirmation work by the manual part of the mismatching part of expected value.

  In the first aspect of the present invention, in the logic simulation system, it is determined whether or not the processing result is a timing error by performing a timing check on the processing result of the preceding logic circuit block, and the processing result is a timing error. Timing check expected value comparison means for determining whether or not the processing result is a true error by checking the operation or state of the processing result when it is determined that there is an error; and timing check expected value comparison means A timing check signal for rewriting the processing result of the preceding logic circuit block to a preset expected value and outputting it as a signal value to the succeeding logic circuit block when the processing result is determined to be a true error at And a value fixing means.

  In the logic simulation system of the present invention, the timing check signal value fixing means may be configured such that when the processing result is determined not to be a timing error or a true error by the timing check expected value comparison means, the preceding logic circuit block Is preferably output as a signal value to the subsequent logic circuit block without being rewritten to the expected value.

  In the logic simulation system of the present invention, when the timing check expected value comparison means performs the timing check, a change time difference of a signal between terminals that are timing check targets of the logic circuit block in the previous stage is set in advance. It is preferable to determine whether or not it is a timing error by determining whether or not it is within the specification value.

  In the logic simulation system of the present invention, the expected timing check value comparing means, when confirming the operation or state of the processing result, at the time of the last change of the terminals subject to the timing check of the preceding logic circuit block It is preferable to determine whether or not the processing result is a true error by confirming whether the output value of the preceding logic circuit block can be determined when the state is active.

  In the logic simulation system of the present invention, the expected timing check value comparing means, when confirming the operation or state of the processing result, of the evaluation terminal among the terminals to be subjected to the timing check of the logic circuit block in the previous stage. It is preferable to determine whether or not the processing result is a true error by checking the number of operations within the specification value.

  In the logic simulation system of the present invention, it is preferable that the terminal that is the timing check target of the preceding logic circuit block is a clock terminal, a set terminal, or a reset terminal.

  In a second aspect of the present invention, in the logic simulation method, a step of determining whether or not the processing result is a timing error by performing a timing check on a processing result of the preceding logic circuit block; A step of determining whether or not the processing result is a true error by checking an operation or a state of the processing result when it is determined that it is a timing error; and the processing result is determined to be a true error. A process result of the preceding logic circuit block is rewritten to an expected value and output as a signal value to the succeeding logic circuit block.

  In the logic simulation method of the present invention, when it is determined that the processing result is not a timing error or a true error, the processing result of the preceding logic circuit block is not rewritten to the expected value, and the succeeding logic circuit block It is preferable to include a step of outputting as a signal value.

  According to the present invention, since the expected value mismatch due to the timing error is eliminated, it is possible to reduce the pseudo error, to reduce the man-hours for the verification time manually by the expected value mismatch location, and to reduce the circuit correction man-hour.

1 is a block diagram schematically illustrating a configuration of a logic simulation system according to a first embodiment of the present invention. 3 is a flowchart schematically showing processing operations of a timing check expected value comparison unit and a timing check signal value fixing unit in the logic simulation system according to the first embodiment of the present invention. It is a 1st timing chart for demonstrating the recovery error of D_FF with reset in the logic simulation system which concerns on Example 1 of this invention. It is a 2nd timing chart for demonstrating the recovery error of D_FF with reset in the logic simulation system which concerns on Example 1 of this invention. It is a 1st timing chart for demonstrating the removal error of D_FF with reset in the logic simulation system which concerns on Example 1 of this invention. It is a 2nd timing chart for demonstrating the removal error of D_FF with reset in the logic simulation system which concerns on Example 1 of this invention. It is the flowchart which showed typically the processing operation of the timing check expected value comparison means and timing check signal value fixing means in the logic simulation system which concerns on Example 2 of this invention. It is a timing chart for demonstrating the pulse width error of D-latch with a reset in the logic simulation system based on Example 2 of this invention. It is the block diagram which showed typically the structure of the logic simulation system which concerns on the prior art example 1. FIG. 10 is a timing chart schematically showing the operation of signal value fixing means in the logic simulation system according to Conventional Example 1.

  In the logic simulation system according to the first embodiment of the present invention, it is determined whether or not the processing result is a timing error by performing a timing check on the processing result of the preceding logic circuit block (4 in FIG. 1). Timing check expected value comparison means (16 in FIG. 1) that determines whether or not the processing result is a true error by checking the operation or state of the processing result when it is determined that the processing result is a timing error. ), And when the processing result is determined to be a true error by the timing check expected value comparing means, the processing result of the preceding logic circuit block is rewritten to a preset expected value, and the succeeding logic circuit block Timing check signal value fixing means (17 in FIG. 1) for outputting as a signal value to.

  In the logic simulation method according to the second embodiment of the present invention, a process of determining whether or not the processing result is a timing error by performing a timing check on the processing result of the preceding logic circuit block (steps A1 to A5 in FIG. 2). And a step of determining whether or not the processing result is a true error by confirming the operation or state of the processing result when the processing result is determined to be a timing error (step of FIG. 2). A6 to A9) and a step of rewriting the processing result of the preceding logic circuit block to an expected value and outputting it as a signal value to the succeeding logic circuit block when the processing result is determined to be a true error (FIG. 2 step B3).

  A logic simulation system according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram schematically showing the configuration of the logic simulation system according to the first embodiment of the present invention.

  The logic simulation system is a system for simulating operation confirmation of a logic circuit composed of a first logic circuit block 4 and a second logic circuit block 5 in two stages. In the logic simulation system, in the test bench 1 for executing the logic simulation, the input signal value 2 is given to the first logic circuit block 4 at the first stage for each clock, so that the processing results of the first logic circuit block 4 are sequentially obtained at the subsequent stage. The configuration is such that an output signal value 7 that is input to the second logic circuit block 5 and the processing result of the second logic circuit block 5 is the final processing result is generated. The logic simulation system is a computer that performs processing such as storage, calculation, and comparison based on a program. The logic simulation system includes an input signal value 2, a signal value input means 3, a first logic circuit block 4, a second logic circuit block 5, a signal value output means 6, and an output signal value as main components. 7, non-timing check expected value comparing means 8, non-timing check signal value fixing means 9, expected value comparing means 10, message output means 11, message output suppressing means 12, first expected value 13, It has a message maximum output count 14, a second expected value 15, a timing check expected value comparison means 16, and a timing check signal value fixing means 17.

  The input signal value 2 is a signal value input to the first logic circuit block 4. The input signal value 2 is stored in a storage unit (not shown) in the logic simulation system.

  The signal value input means 3 is a means for inputting the input signal value 2 to the first logic circuit block 4 for each clock.

  The first logic circuit block 4 reads the first logic circuit diagram stored in the storage unit (not shown), and inputs the input signal value 2 from the signal value input means 3 to the first logic circuit diagram. This is a block for executing the logic simulation of the first logic circuit diagram.

  The second logic circuit block 5 reads the second logic circuit stored in the storage unit (not shown), and the processing result of the first logic circuit block 4 or non-timing is displayed in the second logic circuit diagram. In this block, the first expected value 13 overwritten by the check signal value fixing means 9 is sequentially input, and the logic simulation of the second logic circuit is executed.

  The signal value output means 6 is a means for generating an output signal value 7 as a final processing result based on the processing result of the second logic circuit block 5 and outputting it to the outside.

  The output signal value 7 is a signal value output from the signal value output means 6.

  The non-timing check expected value comparison means 8 is a means for comparing the signal value related to the processing result of the first logic circuit block 4 with the first expected value 13 (value other than the timing check). The non-timing check expected value comparison means 8 compares the first expected value 13 with the signal value relating to the processing result of the first logic circuit block 4 to determine whether or not they are inconsistent.

  When the non-timing check signal value fixing unit 9 determines that the first expected value 13 and the signal value related to the processing result of the first logic circuit block 4 do not match, the non-timing check expected value comparison unit 8 This is means for rewriting the signal value related to the processing result of the logic circuit block 4 to the first expected value 13 and outputting it. Thereby, even if the first expected value 13 and the signal value related to the processing result of the first logic circuit block 4 do not match, the signal value related to the processing result of the second logic circuit block 5 in the expected value comparing means 10 And the signal value obtained from the value of the second expected value 15 are effective. When the non-timing check signal value fixing unit 9 determines that the first expected value 13 and the signal value related to the processing result of the first logic circuit block 4 match with each other, the first timing check value comparison unit 8 The signal value related to the processing result of the logic circuit block 4 is output without being changed.

  The expected value comparison means 10 is a means for comparing the processing result of the second logic circuit block 5 with the expected value. The expected value comparison means 10 compares the second expected value 15 with the signal value related to the processing result of the second logic circuit block 5 and determines whether or not they are inconsistent.

  The message output means 11 is a means for outputting the mismatch information in the non-timing check expected value comparison means 8 and the timing check expected value comparison means 16 to the outside as an error message.

  The message output suppression unit 12 counts the number of times of mismatch based on the mismatch information from the message output unit 11, compares the counted number of mismatches with the value of the maximum message output count 14, and determines the number of mismatches When the message exceeds the maximum message output count of 14, the output of error messages to the outside is suppressed. However, it is possible to output the number of mismatches at the end of the simulation.

  The first expected value 13 is an expected value used when compared by the non-timing check expected value comparison means 8, and is set in advance prior to the logic simulation. The first expected value 13 includes an expected value related to the timing check and an expected value other than the timing check. The first expected value 13 is stored in a storage unit (not shown) in the logic simulation system.

  The maximum message output count 14 is information used when compared by the message output suppression unit 12 and is set in advance prior to the logic simulation. The maximum message output count 14 is stored in a storage unit (not shown) in the logic simulation system.

  The second expected value 15 is information used when compared by the expected value comparing means 10, and is set in advance prior to the logic simulation. The second expected value 15 is stored in a storage unit (not shown) in the logic simulation system.

  The timing check expected value comparison means 16 is a means for timing checking the processing result of the first logic circuit block 4. The timing check expected value comparison means 16 determines whether or not the processing result is a timing error by performing a timing check on the processing result of the first logic circuit block 4. In addition, when the timing check expected value comparison unit 16 determines that the processing result of the first logic circuit block 4 is a timing error, the processing result is a true error by confirming the operation or state of the processing result. It is determined whether or not there is. Details of the operation of the timing check expected value comparison means 16 will be described later.

  The timing check signal value fixing unit 17 presets the processing result of the first logic circuit block 4 when the timing check expected value comparison unit 16 determines that the processing result of the first logic circuit block 4 is a true error. The first expected value 13 is rewritten and output as a signal value to the subsequent logic circuit block. The timing check signal value fixing unit 17 determines the processing result of the first logic circuit block 4 when the timing check expected value comparison unit 16 determines that the processing result of the first logic circuit block 4 is not a timing error or a true error. Is output as a signal value to the second logic circuit block 5 without being rewritten to the first expected value 13. The details of the operation of the timing check signal value fixing means 17 will be described later.

  The processing of the timing check expected value comparison means 16 and the timing check signal value fixing means 17 when the timing check expected value comparison means 16 determines a true error is the non-timing check expected value comparison means 8 and the non-timing. This is similar to the processing of the check signal value fixing means 9.

  Next, the operation of the logic simulation system according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a flowchart schematically showing processing operations of the timing check expected value comparison unit and the timing check signal value fixing unit in the logic simulation system according to the first embodiment of the present invention. FIG. 3 is a timing chart for explaining a recovery error of D_FF with reset (delay flip-flop with reset terminal) in the logic simulation system according to the first embodiment of the present invention.

  In FIG. 3, the waveform at the output terminal A is an output waveform by the logic simulation according to the first embodiment, and the waveform at the output terminal B is an output waveform indicating the result of the original device (hereinafter referred to as device logic). Yes, the waveform of the output terminal C is an output waveform by the logic simulation according to the conventional example 1. In the following description, processes such as storage, calculation, and comparison are all performed by a storage unit, a calculation unit, and a comparison unit that are not described in the logic simulation system.

  First, the timing check expected value comparison means 16 stores a terminal (hereinafter referred to as “recovery / removal terminal”) to be a recovery / removal timing check (see step A1 in FIG. 2). That is, the timing path is stored. In FIG. 3, a clock terminal serving as a reference terminal and a reset terminal serving as an evaluation terminal are stored as recovery / removal timing check targets.

  Next, the timing check expected value comparing means 16 obtains and stores the recovery / removal terminal specification value stored in step A1 from the SDF file 16a (see step A2 in FIG. 2). The SDF (Standard Delay Format) file 16a is a standard format file of delay information used in an EDA (Electronic Design Automation) tool for automating and supporting electrical design work. In FIG. 3, the value of the specification value T1 of the timing of the clock terminal and the reset terminal is stored.

  Next, the timing check expected value comparison means 16 stores the change time of the input waveform input from the first logic circuit block 4 to the recovery / removal terminal (see step A3 in FIG. 2). In FIG. 3, the clock terminal change time T4 and the reset terminal change times T2 and T3 are stored.

  Next, the timing check expected value comparison means 16 calculates the difference in change time of the recovery / removal terminal (change time difference), and compares the calculated change time difference with the spec value stored in step A2 ( (See step A4 in FIG. 2). In FIG. 3, the difference (change time difference) between the change time T4 of the clock terminal and the change time T2 of the reset terminal is obtained, and the change time difference is compared with the specification value T1.

  Next, the timing check expected value comparison means 16 determines whether or not the change time difference is equal to or less than the specification value (see step A5 in FIG. 2). If the change time difference is less than or equal to the specification value (YES in step A5), a recovery / removal timing error is detected, and the process proceeds to step A6. If the change time difference is not less than or equal to the specification value (the specification value is smaller) (NO in step A5), it means that no recovery / removal timing error has been detected, and the process proceeds to step B1.

  When the change time difference is equal to or less than the specification value (YES in step A5), that is, when a recovery / removal timing error is detected, the timing check expected value comparison means 16 includes the timing specification value from the logic simulation result. The number of operations of the evaluation terminal is counted, and the counted number of operations is stored (see step A6 in FIG. 2). In FIG. 3, since the change times of the reset terminal serving as the evaluation terminal are T2 and T3, the number of operations is two.

  After step A6, the timing check expected value comparison means 16 determines whether or not the number of operations of the evaluation terminal stored in step A6 is two or more in the specification value stored in step A3 (FIG. 2). Step A7). When the number of operations is 2 or more (YES in step A7), this is a case where a glitch signal (voltage fluctuation signal) is input to the reset terminal serving as the evaluation terminal, and the process proceeds to step A8. When the number of operations is not two times or more (NO in step A7), a true error is detected among the recovery / removal timing errors, and the process proceeds to step B3.

  When the number of operations is two times or more (YES in step A7), that is, when a glitch signal (voltage fluctuation signal) is input to the evaluation terminal, the timing check expected value comparison means 16 performs the operation at the time of the final change of the evaluation terminal. The value is stored (see step A8 in FIG. 2). In FIG. 3, the value “High” at the time of the final change of the reset terminal serving as the evaluation terminal is stored.

  After step A8, the timing check expected value comparison means 16 determines whether or not the value of the output terminal A can be determined because the value at the time of the last change of the evaluation terminal stored in step A8 is active ( (See step A9 in FIG. 2). When the value of the output terminal A can be determined (YES in step A9), the process proceeds to step A10. If the value of the output terminal A is not determinable (NO in step A9), this is a case where a true error is detected among the recovery / removal timing errors, and the process proceeds to step B3. In FIG. 3, since the value of the reset terminal serving as the evaluation terminal is “High”, the value of the output terminal A can be determined.

  When the value of the output terminal A can be determined (YES in step A9), the timing check expected value comparison unit 16 stores the input signal value of the data terminal at the time of the final change of the evaluation terminal (step A10 in FIG. 2). reference). In FIG. 3, the input signal value “Low” of the data terminal at the time T3 of the final change is stored.

  After step A10, the timing check expected value comparing means 16 determines whether the input signal value of the data terminal at the time of the final change of the evaluation terminal stored in step A10 is the same as the value of the output terminal A ( (See step A11 in FIG. 2). When the input signal value and the value of the output terminal A are the same (YES in step A11), the process proceeds to step B1. If the input signal value and the value of the output terminal A are not the same (NO in step A11), the process proceeds to step B2. In FIG. 3, since the input signal value of the data terminal at the final change time T3 is “Low” and the value at the final change time T3 of the reset terminal serving as the evaluation terminal is “High”, the value of the output terminal A Can be determined to be “Low”, the input signal value and the value of the output terminal A are determined to be the same.

  When the input signal value and the value of the output terminal A are the same (YES in step A11), the timing check signal value fixing means 17 has the number of operations of the reset terminal twice or more within the timing specification value T1 (FIG. 3). Then, since it is T2 and T3), it means that a glitch signal (voltage fluctuation signal) has been input. If the value of the data terminal is output due to the change of the clock terminal T4, the final change of the reset terminal Since the output value at the time T3 is not active is the same, the value of the output terminal A can be determined. Therefore, the recovery / removal timing error is set as a pseudo error, and the value of the output terminal A is output as the determined value. (See step B1 in FIG. 2).

  If the change time difference is not less than the specification value (NO in step A5), that is, if the recovery / removal timing error is not detected, the timing check signal value fixing means 17 outputs the value of the output terminal A as the final value. (See step B1 in FIG. 2), and then the process ends.

  In step B1, the output terminal C of the logic simulation of the conventional example 1 outputs an indefinite value to the output terminal C after the time T5, whereas the output terminal A of the logic simulation of the first example uses the device logic. As with the output value of the output terminal B, a definite value can be output.

  When the input signal value and the value of the output terminal A are not the same (NO in step A11), the timing check signal value fixing means 17 once outputs an indefinite value as a result of the output terminal A, and then sets the determined value. Output (see step B2 in FIG. 2), and then the process ends.

  When the number of operations is not two times or more (NO in step A7), that is, when a true error is detected, the timing check signal value fixing unit 17 sets the indefinite value as the first expected value as a result of the output terminal A. 13 is rewritten and output (see step B3 in FIG. 2), and then the process ends.

  If the value of the output terminal A is not determinable (NO in step A9), that is, if a true error is detected, the timing check signal value fixing means 17 uses the first value as the result of the output terminal A as the first value. The value is rewritten to the expected value 13 and output (see step B3 in FIG. 2), and then the process ends.

  Next, the operation at the timing error of the logic simulation system according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a second timing chart for explaining the recovery error of D_FF with reset in the logic simulation system according to the first embodiment of the present invention. FIG. 5 is a first timing chart for explaining a removal error of D_FF with reset in the logic simulation system according to the first embodiment of the present invention. FIG. 6 is a second timing chart for explaining a removal error of D_FF with reset in the logic simulation system according to the first embodiment of the present invention. 4 to 6, the waveform at the output terminal A is an output waveform by the logic simulation according to the first embodiment, and the waveform at the output terminal B indicates the result of the original device (hereinafter referred to as device logic). This is an output waveform, and the waveform at the output terminal C is an output waveform by the logic simulation according to Conventional Example 1.

  FIG. 4 is a timing chart in the case where the clock terminal is rising edge active, the reset terminal is High, and the data terminal is High or indefinite in the recovery timing check.

  In the example of FIG. 4, first, the timing check expected value comparison means (16 in FIG. 2) stores a clock terminal and a reset terminal as terminals for recovery / removal timing check (see step A1 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) obtains and stores the specification value (T6) of the clock terminal and the reset terminal stored in step A1 from the SDF file (16a in FIG. 2) (FIG. 2). 2 step A2).

  Next, the timing check expected value comparison means (16 in FIG. 2) changes the input waveform change time (clock terminal change time T9) input from the first logic circuit block (4 in FIG. 1) to the clock terminal and the reset terminal. , Reset terminals T7 and T8) are stored (see step A3 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) calculates the difference (change time difference) between the clock terminal change time (T9) and the reset terminal change time (T7), and the calculated change time difference. Is compared with the spec value (T6) stored in step A2 (see step A4 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) determines whether or not the change time difference (T9−T7) is equal to or less than the specification value (T6) (see step A5 in FIG. 2). In the case of FIG. 4, the change time difference (T9−T7) is equal to or less than the specification value (T6).

  In FIG. 4, since the change time difference (T9-T7) is equal to or less than the specification value (T6) (YES in step A5), a recovery / removal timing error occurs, and the timing check expected value comparison means (16 in FIG. 2) In the specification value (T6), the number of operations of the reset terminal is counted from the logic simulation result, and the counted number of operations (two times at T7 and T8) is stored (see step A6 in FIG. 2).

  After step A6, the timing check expected value comparison means (16 in FIG. 2) indicates that the number of operations (2 times) of the reset terminal stored in step A6 is two times or more in the specification value (T6) stored in step A3. (See step A7 of FIG. 2).

  In FIG. 4, since the number of operations (twice) is two times or more (YES in step A7), that is, a glitch signal (voltage fluctuation signal) is input to the reset terminal serving as the evaluation terminal, so the timing check expected value comparison The means (16 in FIG. 2) stores the value (High) at the time of the final change of the reset terminal (T8) (see step A8 in FIG. 2).

  After step A8, the timing check expected value comparison means (16 in FIG. 2) determines that the value at the time of the last change of the reset terminal (T8) stored in step A8 is active (High), and the output terminal A Is determined (see step A9 in FIG. 2).

  In FIG. 4, since the value at the final change of the reset terminal (T8) is active (High), the value of the output terminal A can be determined (YES in Step A9), so the timing check expected value comparison means (16 in FIG. 2) stores the input signal value (indefinite value) of the data terminal at the time of the final change of the reset terminal (T8) (see step A10 in FIG. 2).

  After step A10, the timing check expected value comparison means (16 in FIG. 2) inputs the input signal value (undefined value) of the data terminal at the time of the final change of the reset terminal stored in step A10 (T8) and the output terminal A. It is determined whether or not the value (Low) is the same (see step A11 in FIG. 2).

  In FIG. 4, since the input signal value (undefined value) and the value (Low) of the output terminal A are not the same (NO in Step A11), the timing check signal value fixing means (17 in FIG. 2) is the result of the output terminal A. First, an indefinite value is output, and then a definite value (Low) is output (see step B2 in FIG. 2). That is, the number of operations of the reset terminal within the timing specification value (T6) is two times or more, and a glitch signal (voltage fluctuation signal) is input. Therefore, it is assumed that the time (T9) of the clock terminal changes. Because the output value differs when the value of the data terminal is output and the value at the time of the final change of the reset terminal (T8) is active (High), due to the recovery / removal timing error, At time T10, the output terminal A outputs an indefinite value, and then the value at the last change (T8) of the reset terminal is active (High). ) Is output.

  In the operation of step B2, the output terminal C outputs an indefinite value at the time T10 in the result of the logic simulation of the conventional example 1, whereas the output value of the device logic of the output terminal B is the data terminal. When the value T12 that is High or an indefinite value is input at the time T12, the indefinite value is once output like the value of the time T10, and then the reset terminal is active (High). become. As for the value of the output terminal A in the logic simulation of the first embodiment, a definite value can be output at the time T11, similarly to the output value of the output terminal B of the device logic.

  3 and 4 are descriptions of the case of the reset terminal, the same idea applies to the case of the set terminal.

  FIG. 5 is a timing chart when the clock terminal is rising edge active, the reset terminal is High, and the data terminal is Low in the removal timing check.

  In the example of FIG. 5, first, the timing check expected value comparison means (16 in FIG. 2) stores a clock terminal and a reset terminal as terminals to be subjected to recovery / removal timing check (see step A1 in FIG. 2).

  Next, the timing check expected value comparing means (16 in FIG. 2) obtains and stores the clock terminal and reset terminal specification values (T25) stored in step A1 from the SDF file (16a in FIG. 2) (FIG. 2). 2 step A2).

  Next, the timing check expected value comparison means (16 in FIG. 2) changes the time of the input waveform input from the first logic circuit block (4 in FIG. 1) to the clock terminal and reset terminal (clock terminal change time T26). , The reset terminals T27 and T28) are stored (see step A3 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) calculates the difference (change time difference) between the clock terminal change time (T26) and the reset terminal change time (T27), and the calculated change time difference. And the spec value (T25) stored in step A2 are compared (see step A4 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) determines whether or not the change time difference (T26−T27) is equal to or less than the specification value (T25) (see step A5 in FIG. 2). In the case of FIG. 5, the change time difference (T26−T27) is equal to or less than the specification value (T25).

  In FIG. 5, since the change time difference (T26-T27) is less than or equal to the specification value (T25) (YES in step A5), a recovery / removal timing error occurs, and the timing check expected value comparison means (16 in FIG. 2) In the specification value (T25), the number of operations of the reset terminal is counted from the logic simulation result, and the counted number of operations (two times at T27 and T28) is stored (see step A6 in FIG. 2).

  After step A6, the timing check expected value comparison means (16 in FIG. 2) indicates that the number of operations (2 times) of the reset terminal stored in step A6 is two times or more in the specification value (T25) stored in step A3. (See step A7 of FIG. 2).

  In FIG. 5, since the number of operations (two times) is two or more (YES in step A7), that is, since the glitch signal (voltage fluctuation signal) is input to the evaluation terminal, the timing check expected value comparison means (FIG. 2). 16) stores the value (High) at the time of the final change of the reset terminal (T28) (see step A8 in FIG. 2).

  After step A8, the timing check expected value comparing means (16 in FIG. 2) determines that the value at the time of the final change of the reset terminal (T28) stored in step A8 is active (High), and the output terminal A Is determined (see step A9 in FIG. 2).

  In FIG. 5, since the value of the output terminal A can be determined because the value at the final change of the reset terminal (T28) is active (High), the timing check expected value comparison means (16 in FIG. 2) stores the input signal value (Low) of the data terminal at the time of the final change of the reset terminal (T28) (see step A10 in FIG. 2).

  After step A10, the timing check expected value comparison means (16 in FIG. 2) inputs the data terminal input signal value (Low) at the time of the final change of the reset terminal stored in step A10 (T28) and the output terminal A It is determined whether or not the value (Low) is the same (see step A11 in FIG. 2).

  In FIG. 5, since the input signal value (Low) and the value (Low) of the output terminal A are the same (YES in Step A11), the timing check signal value fixing means (17 in FIG. 2) is the value of the output terminal A. (Low) is output as a definite value (see step B1 in FIG. 2). That is, since the reset terminal has changed twice or more within the timing specification value (T25), a glitch signal (voltage fluctuation signal) has been input, and the change in the clock terminal change time (T26) is assumed. Therefore, the value of the output terminal A is determined because the output value is the same when the value of the data terminal is output and when the value of the last change of the reset terminal (T28) is active (High). Therefore, the recovery / removal timing error is treated as a pseudo error, and the output terminal A also outputs a definite value (Low).

  The operation of step B1 is that the output terminal C outputs an indefinite value after time T29 in the result of the logic simulation of Conventional Example 1, whereas the output value (time T29) of the device logic of output terminal B ( Similarly to (Low), the value after time T29 of the output terminal A of the logic simulation of the first embodiment can output a definite value (Low).

  FIG. 6 is a timing chart when the clock terminal is active at the rising edge, the reset terminal is High, the data terminal is High, or an indefinite value is input in the removal timing check.

  In the example of FIG. 6, first, the timing check expected value comparison means (16 in FIG. 2) stores a clock terminal and a reset terminal as terminals to be subjected to recovery / removal timing check (see step A1 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) obtains and stores the specification values (T30) of the clock terminal and the reset terminal stored in step A1 from the SDF file (16a in FIG. 2) (FIG. 2). 2 step A2).

  Next, the timing check expected value comparison means (16 in FIG. 2) changes the input waveform change time (clock terminal change time T31) input from the first logic circuit block (4 in FIG. 1) to the clock terminal and the reset terminal. , Reset terminals T32 and T33) (see step A3 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) calculates the difference (change time difference) between the clock terminal change time (T31) and the reset terminal change time (T32), and the calculated change time difference. And the spec value (T30) stored in step A2 are compared (see step A4 in FIG. 2).

  Next, the timing check expected value comparison means (16 in FIG. 2) determines whether or not the change time difference (T32−T31) is equal to or less than the specification value (T30) (see step A5 in FIG. 2). In the case of FIG. 6, the change time difference (T32−T31) is equal to or less than the specification value (T30).

  In FIG. 6, since the change time difference (T32-T31) is equal to or less than the specification value (T30) (YES in step A5), a recovery / removal timing error occurs, and the timing check expected value comparison means (16 in FIG. 2) In the specification value (T30), the number of operations of the reset terminal is counted from the logic simulation result, and the counted number of operations (two times at T32 and T33) is stored (see step A6 in FIG. 2).

  After step A6, the timing check expected value comparison means (16 in FIG. 2) indicates that the number of operations (2 times) of the reset terminal stored in step A6 is two times or more in the specification value (T30) stored in step A3. (See step A7 of FIG. 2).

  In FIG. 6, since the number of operations (two times) is two or more (YES in step A7), that is, since the glitch signal (voltage fluctuation signal) is input to the evaluation terminal, the timing check expected value comparison means (FIG. 2). 16) stores the value (High) at the time of the final change of the reset terminal (T33) (see step A8 in FIG. 2).

  After step A8, the timing check expected value comparison means (16 in FIG. 2) determines that the value at the time of the last change of the reset terminal (T33) stored in step A8 is active (High), and the output terminal A Is determined (see step A9 in FIG. 2).

  In FIG. 6, since the value of the output terminal A can be determined because the value at the time of the last change of the reset terminal (T33) is active (High), the timing check expected value comparison means (16 in FIG. 2) stores the input signal value (undefined value) of the data terminal at the time of the final change of the reset terminal (T33) (see step A10 in FIG. 2).

  After step A10, the timing check expected value comparison means (16 in FIG. 2) inputs the input signal value (undefined value) of the data terminal at the time of the final change of the reset terminal stored in step A10 (T33) and the output terminal A. It is determined whether or not the value (Low) is the same (see step A11 in FIG. 2).

  In FIG. 6, since the input signal value (undefined value) and the value (Low) of the output terminal A are not the same (NO in Step A11), the timing check signal value fixing means (17 in FIG. 2) First, an indefinite value is output, and then a definite value (Low) is output (see step B2 in FIG. 2). That is, since the reset terminal has changed twice or more within the timing specification value (T30), a glitch signal (voltage fluctuation signal) has been input, and temporarily changes at the clock terminal time (T31). Because of the difference between the output value when the value of the data terminal is output and the value when the value at the final change of the reset terminal (T33) becomes active (High), the recovery / removal timing error causes Then, an indefinite value is output to the output at time T34, and then the value at the time of the final change of the reset terminal (T33) is active (High), so that the output terminal has a definite value (Low) at time T35. Output.

  The operation of step B2 is that the output terminal C output an indefinite value at time T34 in the result of the logic simulation of the conventional example 1, whereas the output value of the device logic of the output terminal B is the data terminal. When High at time T31 or T36, which is an indefinite value, is input, an indefinite value is once output like the value at time T34, and then the reset terminal is active (High). In the same way as the output value of the logic simulation output terminal A of the first embodiment at the time T34, a definite value (Low) can be output at the time T11 at the time T35, similar to the output value of the device logic output terminal B. .

  According to the first embodiment, the following effects can be obtained.

  The first effect is that the expected value mismatch due to the recovery / removal timing error can be eliminated, so that the pseudo error can be reduced, and the number of man-hours for the verification time by hand for the portion where the expected value does not match can be reduced. . The reason is that the glitch is input because the reset terminal and the set terminal have changed several times within the specification value of the timing when a recovery / removal timing error has occurred in order to determine a pseudo error. And when the glitch is input, the value at the time of the last change of the reset and set terminals is in the active state, and the reset terminal and the set terminal are in the active state, so that the output can always be determined This is because it is possible to eliminate an expected value mismatch due to a pseudo error. That is, in the logic simulation process, step A7 for determining that the reset terminal stored in step A6 in FIG. 2 has changed two or more times within the specification value of the timing stored in step A2, and FIG. By having step A9 that determines whether the output logic can be determined even if a recovery / removal timing error has occurred, based on the input logic of the reset terminal stored in step A8, a pseudo error in the recovery / removal timing error has occurred. This is because the output logic can be determined.

  As a second effect, there is an effect that the number of circuit correction steps can be reduced. In other words, in the first conventional example, all the expected value mismatched circuits including the pseudo error location are corrected, but in the first embodiment, the true error location circuit among the expected value mismatched locations is corrected. Because it becomes.

  A logic simulation system according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart schematically showing processing operations of the timing check expected value comparison unit and the timing check signal value fixing unit in the logic simulation system according to the second embodiment of the present invention. FIG. 8 is a timing chart for explaining a pulse width error of the D-latch with reset in the logic simulation system according to the second embodiment of the present invention.

  The second embodiment is a modification of the first embodiment, and the timing check expected value comparison unit 16 determines the pulse width timing check instead of determining the recovery / removal timing check as in the first embodiment. The logic simulation system according to the second embodiment is the same as that of the first embodiment (see FIG. 1) except for the operation of the timing check expected value comparison means 16. The operation of the logic simulation system according to the second embodiment will be described below.

  In FIG. 8, the waveform at the output terminal A ′ is an output waveform by the logic simulation according to the second embodiment, and the waveform at the output terminal B is an output waveform indicating the result of the original device (hereinafter referred to as device logic). The waveform at the output terminal C is an output waveform by the logic simulation according to Conventional Example 1. Further, the calculation and comparison processing stored in the following description are all performed by a storage unit, a calculation unit, and a comparison unit, which are not described in the logic simulation system.

  The timing check expected value comparison means (16 in FIG. 7) stores the reset terminal as a terminal to be subjected to the pulse width timing check (see step C1 in FIG. 7).

  Next, the timing check expected value comparison means (16 in FIG. 7) obtains and stores the specification value (T49) of the reset terminal stored in step C1 from the SDF file (16b in FIG. 7) (step in FIG. 7). C2).

  Next, the timing check expected value comparison means (16 in FIG. 7) stores the change time (T50, T51) of the input waveform input to the reset terminal from the first logic circuit block (4 in FIG. 1) (FIG. 7). 7 step C3).

  Next, the timing check expected value comparison means (16 in FIG. 7) calculates the difference (change time difference) of the change time (T50, T51) of the reset terminal, and the calculated change time difference (T51−T50), The specification value (T49) stored in step C2 is compared (see step C4 in FIG. 7).

  Next, the timing check expected value comparison means (16 in FIG. 7) determines whether or not the change time difference (T51−T50) is equal to or less than the specification value (T49) (see step C5 in FIG. 7). In the case of FIG. 8, since the change time difference (T51-T50) is equal to or smaller than the specification value (T49) (YES in step C5), the process proceeds to step C6. If the change time difference is not less than the specification value (NO in step C5), the process proceeds to step B1.

  When the change time difference (T51-T50) is equal to or less than the specification value (T49) (YES in step C5), a pulse width timing error occurs, and the timing check expected value comparison means (16 in FIG. 7) performs the time T51 of the gate terminal. Is stored (see Step C6 in FIG. 7).

  After step C6, the timing check expected value comparison means (16 in FIG. 7) stores the value (Low) at the time of the final change (T51) of the reset terminal serving as the evaluation terminal (see step C7 in FIG. 7).

  After step A8, the timing check expected value comparison means (16 in FIG. 7) stores the value at the time of the final change of the reset terminal (T51) stored in step C7 inactive (Low) and stores it in step C6. It is determined whether or not the value of the output terminal A is determinable because the value of the gate terminal at time T51 is active (High) (see step C8 in FIG. 7). In the case of FIG. 8, the value at the time of the final change of the reset terminal (T51) is active (High), and the value at the time T51 of the gate terminal is active (High). Since the value can be determined (YES in step C8), the process proceeds to step B2. If the value of the output terminal A is not determinable (NO in step C8), the process proceeds to step B3.

  When the change time difference is not less than the specification value (NO in step C5), that is, when the pulse width timing error is not detected, the timing check signal value fixing means (17 in FIG. 7) determines the value of the output terminal A. Since this is possible, the pulse width timing error is treated as a pseudo error, the output terminal A also outputs a definite value (see step B1 in FIG. 7), and then the process ends.

  When the value of the output terminal A is determinable (YES in Step C8), the timing check signal value fixing means (17 in FIG. 7) once outputs an indefinite value as a result of the output terminal A, and then confirms. The value (T55) is output (see step B2 in FIG. 7), and then the process ends. That is, the value at the time T51 of the last change of the reset terminal stored in Step C7 is inactive (Low), and the value at the time T51 of the gate terminal stored in Step C6 is active (High). As a result of the terminal A, an indefinite value is output once, and then a value T55 at the data terminal time T50 is output at time T54.

  The operation of step B2 is that the output terminal C outputs an indefinite value after time T53 in the logic simulation result of the conventional example 1, whereas the output value of the device logic of the output terminal B is at time T53. Although an indefinite value is output once, the value T55 of the data terminal at time T50 is output as it is at time T54 because the gate terminal is active (High) after that according to the determination result of step C8. As with the output value of the output terminal B of the device logic, the value of the output terminal A in the logic simulation according to the first embodiment can output the definite value T55 at time T54.

  When the value of the output terminal A is not determinable (NO in step C8), the timing check signal value fixing means (17 in FIG. 7) rewrites the indefinite value to the first expected value 13 as the result of the output terminal A and outputs it. (See step B3 in FIG. 7), and then the process ends.

  Note that FIG. 8 illustrates the case of the reset terminal, but the same idea applies to the case of the set terminal.

According to the second embodiment, since the expected value mismatch due to the pulse width timing error can be eliminated, the pseudo error can be reduced similarly to the first embodiment, and the number of man-hours for the verification time by manual operation at the location where the expected value does not match. And circuit modification man-hours can be reduced.
Has an effect.

DESCRIPTION OF SYMBOLS 1,101 Test bench 2,102 Input signal value 3,103 Signal value input means 4,104 First logic circuit block (previous logic circuit block)
5, 105 Second logic circuit block (following logic circuit block)
6, 106 Signal value output means 7, 107 Output signal value 8 Non-timing check expected value comparison means 9 Non-timing check signal value fixing means 10, 110 Expected value comparison means 11, 111 Message output means 12, 112 Message output suppression means 13 , 15, 113, 115 Expected value 14, 114 Maximum message output count 16 Timing check expected value comparison means 16a, 16b SDF file 17 Timing check signal value fixing means 108 Expected value comparison means 109 Signal value fixing means 120 Clock signal 121, 122 Signal between logical blocks 123, 126 Rising edge 124 Delta delay 125 Falling edge 127, 129 Value that matches expected value 128 Value that does not match expected value

Claims (8)

It is determined whether or not the processing result is a timing error by performing a timing check on the processing result of the logic circuit block in the previous stage, and the operation or state of the processing result when it is determined that the processing result is a timing error A timing check expected value comparing means for determining whether or not the processing result is a true error by checking
When the timing check expected value comparison means determines that the processing result is a true error, the processing result of the preceding logic circuit block is rewritten to a preset expected value, and a signal is sent to the succeeding logic circuit block. Timing check signal value fixing means for outputting as a value;
A logic simulation system comprising:   The timing check signal value fixing means converts the processing result of the preceding logic circuit block to the expected value when the timing check expected value comparing means determines that the processing result is not a timing error or a true error. 2. The logic simulation system according to claim 1, wherein the logic simulation system outputs the signal value to the subsequent logic circuit block without rewriting.   When the timing check expected value comparing means performs the timing check, it is determined whether or not the change time difference of the signal between the terminals subjected to the timing check of the preceding logic circuit block is within a preset specification value. 3. The logic simulation system according to claim 1, wherein it is determined whether or not a timing error has occurred.   When the timing check expected value comparison means confirms the operation or state of the processing result, the state at the time of the final change of the timing check target terminals of the logic circuit block in the previous stage is active. 4. The logic simulation system according to claim 3, wherein whether or not the processing result is a true error is determined by confirming whether or not the output value of the logic circuit block at the preceding stage can be determined.   The expected timing check value comparing means, when confirming the operation or state of the processing result, confirms the number of operations within the specification value of the evaluation terminal among the terminals subjected to the timing check of the logic circuit block in the previous stage The logic simulation system according to claim 3, wherein it is determined whether or not the processing result is a true error.   6. The logic simulation system according to claim 3, wherein the terminal to be subjected to the timing check of the preceding logic circuit block is a clock terminal, a set terminal, or a reset terminal. Determining whether the processing result is a timing error by performing a timing check on the processing result of the logic circuit block in the previous stage; and
Determining whether the processing result is a true error by confirming the operation or state of the processing result when it is determined that the processing result is a timing error;
When the processing result is determined to be a true error, the process result of the previous logic circuit block is rewritten to an expected value and output as a signal value to the subsequent logic circuit block;
A logic simulation method comprising:   A step of outputting the processing result of the preceding logic circuit block as a signal value to the subsequent logic circuit block without rewriting the expected value when it is determined that the processing result is not a timing error or a true error. The logic simulation method according to claim 7, further comprising:

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