JP2011155387A - Integrated circuit device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device and an electronic device, etc., capable of executing calibration using its own transmission signals. <P>SOLUTION: The integrated circuit device 100 includes: a transmission circuit 300 for outputting transmission signals to an antenna 360; a reception circuit 200 which has a reception side amplifier circuit 230 including a reception side inductor and a reception side capacitor, and to which reception signals from the antenna 360 are inputted; and a control circuit 350. The transmission circuit 300 transmits the transmission signals for calibration during a calibration period. The reception circuit 200 receives the transmission signals for the calibration during the calibration period. The control circuit 350 sets at least one of the inductance value of the reception side inductor and the capacitance value of the reception side capacitor during the calibration period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an integrated circuit device, an electronic device, and the like.

  In recent years, in the field of wireless communication, a frequency hopping method has attracted attention as a wireless communication method that efficiently uses a limited frequency band. In this frequency hopping method, since the carrier frequency is frequently changed, there is a problem that it is difficult to calibrate the reception circuit and the transmission circuit every time the carrier frequency is switched.

  For example, Patent Document 1 discloses a technique for generating a test signal for calibrating a reception-side demodulated signal processing circuit and transmitting the signal by a transmission circuit.

  However, this method has a problem that it is difficult to cope with a wide range of frequencies.

JP 2008-124965 A

  According to some embodiments of the present invention, it is possible to provide an integrated circuit device, an electronic device, and the like that can be calibrated using their own transmission signals.

  One embodiment of the present invention includes a transmission circuit that outputs a transmission signal to an antenna, a reception-side amplifier circuit that includes a reception-side inductor and a reception-side capacitor, and a reception circuit that receives the reception signal from the antenna; The transmission circuit transmits a calibration transmission signal during a calibration period, the reception circuit receives the calibration transmission signal during the calibration period, and the control circuit includes: The present invention relates to an integrated circuit device that sets at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor during the calibration period.

  According to an aspect of the present invention, the reception circuit receives a calibration transmission signal from the transmission circuit and sets at least one of the inductance value of the reception-side inductor and the capacitance value of the reception-side capacitor during the calibration period. be able to. As a result, a special circuit for generating a calibration transmission signal is not required, so that the circuit configuration can be simplified and power consumption can be reduced.

  In one embodiment of the present invention, the reception circuit includes a reception-side amplitude detection circuit that detects a voltage amplitude of an amplified signal in the reception-side amplification circuit, and the control circuit is a detection result of the reception-side amplitude detection circuit. Based on the above, it is possible to set at least one of the inductance value of the receiving-side inductor and the capacitance value of the receiving-side capacitor, and perform a process of bringing the voltage amplitude value of the amplified signal close to the maximum value.

  In this way, at least one of the inductance value of the reception-side inductor and the capacitance value of the reception-side capacitor can be set so that the voltage amplitude of the amplified signal from the reception-side amplifier circuit approaches the maximum value. As a result, it is possible to reduce the influence of manufacturing variations, temperature, power supply voltage, and the like, and to realize a stable integrated circuit device with high amplification efficiency.

  In the aspect of the invention, the reception-side amplifier circuit includes an amplification transistor that amplifies an input signal, and at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor is variably set. Also good.

  In this way, the resonance frequency of the LC load circuit including the reception-side capacitor and the reception-side inductor can be variably set, so that the frequency characteristic of the reception-side amplifier circuit can be variably set.

  In one embodiment of the present invention, the reception-side capacitor is provided between a first capacitor provided between a first power supply node and a control node, and between the control node and an output node of the amplification transistor. The capacitance value of the first capacitor is variably set by the voltage of the control node, and the receiving inductor is interposed between the output node and the second power supply node. It may be provided.

  In this way, the capacitance value of the first capacitor can be variably set according to the voltage of the control node, so that the resonance frequency of the LC load circuit including the reception side capacitor and the reception side inductor can be variably set. it can.

  In the aspect of the invention, the reception-side amplifier circuit includes a variable current source for causing a current to flow through the amplification transistor, and the control circuit is configured based on a detection result of the reception-side amplitude detection circuit. Control for setting the current value of the variable current source may be performed.

  In this way, the control circuit can set the value of the current flowing through the amplification transistor based on the detection result of the reception-side amplitude detection circuit.

  In one embodiment of the present invention, the control circuit may set at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor every time the frequency of the carrier wave of the transmission circuit changes. .

  In this way, in a wireless communication system using a plurality of carrier frequencies, each time the carrier frequency is switched, at least one of the inductance value of the reception-side inductor and the capacitance value of the reception-side capacitor is set, and the reception-side amplifier circuit The voltage amplitude of the amplified signal can be made close to the maximum value. As a result, stable wireless communication with high amplification efficiency can be realized even in a wireless system that frequently changes the frequency, such as a frequency hopping system.

  In one embodiment of the present invention, the transmission circuit includes a transmission side amplifier circuit having a transmission side inductor and a transmission side capacitor, and the control circuit includes the inductance value of the transmission side inductor and the transmission during the calibration period. At least one of the capacitance values of the side capacitors may be set.

  In this way, at least one of the inductance value of the transmission-side inductor and the capacitance value of the transmission-side capacitor can be set so that the voltage amplitude of the amplified signal of the transmission-side amplifier circuit approaches a maximum value. As a result, it is possible to reduce an influence due to manufacturing variations, temperature, power supply voltage, and the like, and to realize a stable integrated circuit device with high amplification efficiency.

  In the aspect of the invention, the control circuit may perform control so that the amplitude of the calibration transmission signal in the calibration period is smaller than the amplitude of the transmission signal in the normal wireless transmission period.

  In this way, the amplitude of the signal received by the receiving circuit during the calibration period can be made smaller than the amplitude of the transmission signal during the normal wireless transmission period, so that the receiving-side amplifier circuit is saturated by an excessively large signal. Can be prevented. In addition, since transmission with more power than necessary can be suppressed in the calibration period, it is possible to reduce power consumption and further reduce interference with other wireless devices.

  Another aspect of the present invention includes a transmission circuit that outputs a transmission signal to an antenna, a reception circuit that receives a reception signal from the antenna, and a control circuit. The transmission circuit is calibrated during a calibration period. A transmission signal for calibration, the reception circuit receives the calibration transmission signal during the calibration period, and the control circuit determines the amplitude of the calibration transmission signal during the calibration period, The present invention relates to an integrated circuit device that performs control to make it smaller than the amplitude of a transmission signal in a normal wireless transmission period.

  According to another aspect of the present invention, the reception circuit can calibrate the reception circuit by receiving a calibration transmission signal from the transmission circuit during the calibration period. As a result, a special circuit for generating a calibration transmission signal is not required, so that the circuit configuration can be simplified and power consumption can be reduced. Furthermore, since the amplitude of the signal received by the receiving circuit during the calibration period can be made smaller than the amplitude of the transmitting signal during the normal wireless transmission period, it is possible to prevent the receiving circuit from being saturated by an excessively large signal. it can.

  Another aspect of the present invention relates to an electronic apparatus including the integrated circuit device described above.

2 shows a basic configuration example of an integrated circuit device. 1 is a first configuration example of a reception side amplifier circuit; 2 is a configuration example of a reception side amplitude detection circuit. 4A and 4B are diagrams illustrating the operation of the reception-side amplitude detection circuit. The 2nd structural example of a receiving side amplifier circuit. 6 is another configuration example of a reception-side amplitude detection circuit. The figure explaining operation | movement of a receiving side amplitude detection circuit. 8A and 8B are examples of frequency characteristics of the voltage amplitude of the amplified signal. An example of the flowchart of the process which sets L value and C value. An example of the flowchart of the process which sets the electric current value of a variable current source. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Basic Configuration Example FIG. 1 shows a basic configuration example of the integrated circuit device of this embodiment. The integrated circuit device of this embodiment includes a receiving circuit 200, a transmitting circuit 300, and a control circuit 350. The reception circuit 200 receives a reception signal from the antenna 360 and includes a reception side amplification circuit 230, a frequency conversion circuit 240, a filter 250, a reception side amplitude detection circuit 260, and a demodulation circuit 270. The reception side amplifier circuit 230 includes a reception side inductor and a reception side capacitor. The transmission circuit 300 outputs a transmission signal to the antenna 360, and includes a transmission side amplification circuit 310, a modulation circuit 320, an oscillation circuit (PLL circuit) 330, and a transmission side amplitude detection circuit 340. The transmission side amplifier circuit 310 includes a transmission side inductor and a transmission side capacitor. The integrated circuit device of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components, replacing them with other components, and adding other components. Implementation is possible.

  The frequency conversion circuit 240 performs frequency conversion from the reception frequency to the intermediate frequency. The filter 250 removes unnecessary frequency components and outputs a desired signal. The demodulation circuit 270 demodulates the desired wave signal and extracts necessary data.

  The oscillation circuit (PLL circuit) 330 generates a signal having a necessary frequency (such as a carrier wave frequency) from the reference clock. The modulation circuit 320 modulates the carrier wave (for example, frequency modulation) based on the transmission data.

  The control circuit 350 performs wireless communication control processing and data communication with an external circuit (such as a host) of the integrated circuit device 100. In particular, in the integrated circuit device of the present embodiment, as described below, control processing such as calibration of the reception side amplification circuit 230 is performed based on the detection result of the reception side amplitude detection circuit 260 in the calibration period.

  The transmission circuit 300 transmits a calibration transmission signal during the calibration period, and the reception circuit 200 receives the calibration transmission signal during the calibration period. The control circuit 350 sets at least one of the inductance value (L value) of the receiving-side inductor and the capacitance value (C value) of the receiving-side capacitor during the calibration period.

  By doing in this way, the receiving circuit 200 can set at least one of the L value and the C value of the receiving side amplification circuit 230 in response to the calibration transmission signal from the transmission circuit 300 during the calibration period. it can. As a result, a special circuit for generating a calibration transmission signal is not required, so that the circuit configuration can be simplified and power consumption can be reduced.

  The reception side amplitude detection circuit 260 detects the voltage amplitude of the amplified signal in the reception side amplification circuit 230. Based on the detection result of the reception-side amplitude detection circuit 260, the control circuit 350 performs processing for bringing the voltage amplitude value of the amplified signal close to the maximum value, and at least one of the inductance value of the reception-side inductor and the capacitance value of the reception-side capacitor. Set. The configuration of the reception-side amplitude detection circuit 260 and the processing performed by the control circuit 350 will be described later.

  By doing so, at least one of the L value of the receiving inductor and the C value of the receiving capacitor can be set so that the voltage amplitude of the amplified signal from the receiving side amplification circuit 230 approaches the maximum value. As a result, it is possible to reduce influences due to manufacturing variations and environmental fluctuations (eg, fluctuations in temperature, power supply voltage, etc.), and to realize stable and efficient wireless communication.

  The control circuit 350 sets at least one of the inductance value of the reception-side inductor and the capacitance value of the reception-side capacitor every time the carrier frequency of the transmission circuit 300 changes.

  In this way, in a wireless communication system using a plurality of carrier frequencies, each time the carrier frequency is switched, at least one of the L value of the receiving inductor and the C value of the receiving capacitor is set, and the receiving side amplification circuit The voltage amplitude of the amplified signal from 230 can be brought close to the maximum value. As a result, stable wireless communication with high amplification efficiency can be realized even in a wireless system such as a frequency hopping system that frequently changes the frequency.

  The control circuit 350 sets at least one of the inductance value of the transmission-side inductor and the capacitance value of the transmission-side capacitor during the calibration period.

  In this way, at least one of the L value of the transmission side inductor and the C value of the transmission side capacitor can be set so that the voltage amplitude of the amplified signal of the transmission side amplification circuit 310 approaches the maximum value. As a result, it is possible to reduce the influence of manufacturing variations and environmental fluctuations (for example, fluctuations in temperature, power supply voltage, etc.), and to realize stable wireless communication with high amplification efficiency.

  In addition, the control circuit 350 performs control to make the amplitude of the calibration transmission signal in the calibration period smaller than the amplitude of the transmission signal in the normal wireless transmission period.

  In this way, the amplitude of the signal received by the reception circuit 200 during the calibration period can be made smaller than the amplitude of the transmission signal during the normal wireless transmission period. Can be prevented from being saturated. In addition, since transmission with more power than necessary can be suppressed during the calibration period, it is possible to reduce power consumption and further reduce interference with other wireless devices.

  Although not shown in FIG. 1, a changeover switch or the like may be provided so that a transmission signal from the transmission circuit 300 is not input to the reception circuit 200 during the normal wireless transmission period. However, when a changeover switch or the like is provided, it is necessary to control the changeover switch or the like so that a transmission signal from the transmission circuit 300 is input to the reception circuit 200 during the calibration period.

  As described above, according to the integrated circuit device of this embodiment, in the calibration period, the reception circuit 200 can perform calibration by receiving the calibration transmission signal from the transmission circuit 300. As a result, a special circuit for generating a calibration transmission signal is not required, so that the circuit configuration can be simplified and power consumption can be reduced.

  Further, during the calibration period, at least one of the L value of the inductor and the C value of the capacitor of each amplifier circuit is set so that the voltage amplitude of the amplified signal of the reception side amplification circuit 230 and the transmission side amplification circuit 310 approaches the maximum value. can do. As a result, it is possible to reduce the influence of manufacturing variations and environmental fluctuations (for example, fluctuations in temperature, power supply voltage, etc.), and to realize stable wireless communication with high amplification efficiency.

  Furthermore, according to the integrated circuit device of the present embodiment, the amplitude of the signal received by the receiving circuit 200 during the calibration period can be made smaller than the amplitude of the transmission signal during the normal wireless transmission period. It is possible to prevent the reception side amplification circuit 230 from being saturated. In addition, since transmission with more power than necessary can be suppressed during the calibration period, it is possible to reduce power consumption and further reduce interference with other wireless devices.

2. Amplification Circuit and Amplitude Detection Circuit FIG. 2 shows a first configuration example of the reception side amplification circuit 230 of the present embodiment. The reception side amplification circuit 230 of the present embodiment includes the amplification transistor 10 and the LC load circuit 20. The amplifying transistor 10 includes two cascode-connected N-type transistors T1 and T2, and amplifies an input signal. The bias voltages VB1 and VB2 are for setting the gate voltages of the transistors T1 and T2 to appropriate voltage values, respectively.

  The receiving-side amplifier circuit of the present embodiment is not limited to the configuration shown in FIG. 2, and various components such as omitting some of the components, replacing them with other components, and adding other components. Variations are possible. For example, the amplifying transistor 10 may be composed of a single transistor or may be composed of a P-type transistor.

  The LC load circuit 20 includes a reception-side inductor and a reception-side capacitor, and at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor is variably set. Specifically, the LC load circuit 20 includes, for example, a varactor (varicap, voltage control variable capacitor) CA (first capacitor in a broad sense), a capacitor CB (second capacitor in a broad sense), and an inductor (coil) LA. including.

  The varactor CA is provided between the low potential side power supply node VSS (first power supply node in a broad sense) and the control node NC, and the capacitance value (capacitance value) is variably set by the voltage of the control node NC. By changing the capacitance value of the varactor CA, the resonance frequency of the LC load circuit 20 changes, so that the frequency characteristic of the LC load circuit 20 changes. The capacitor CB is for cutting off the DC component, and is provided between the control node NC and the output node NP of the amplifying transistor 10. The inductor LA is provided between the output node NP and the high potential side power supply node VDD (second power supply node in a broad sense).

  The reception side amplitude detection circuit 260 detects the voltage amplitude of the amplified signal VP and outputs a detection output voltage VD as a detection result. A detailed configuration example of the reception-side amplitude detection circuit 260 will be described with reference to FIG.

  Based on the detection result of the reception-side amplitude detection circuit 260, the control circuit 350 performs a process of setting the voltage amplitude value of the amplified signal VP close to the maximum value and sets at least one of the inductance value and the capacitance value. For example, in FIG. 2, the control circuit 350 sets the capacitance value of the varactor CA by changing the LC control voltage VT applied to the control node NC. The control circuit 350 includes an A / D converter 41, a logic circuit 42, and a D / A converter 43. The A / D converter 41 converts the detected output voltage VD (detection result), which is analog data, into digital data, and the logic circuit 42 performs processing based on the converted digital data. The D / A converter 43 generates and outputs the LC control voltage VT based on the output of the logic circuit 42.

  In this way, at least one of the inductance value and the capacitance value of the LC load circuit 20 can be set so that the voltage amplitude value of the amplified signal VP approaches the maximum value. As a result, it is possible to correct deterioration in the characteristics of the amplifier circuit due to manufacturing variations and environmental fluctuations (for example, fluctuations in temperature, power supply voltage, etc.), thereby realizing a stable integrated circuit device for wireless communication with high amplification efficiency. . Furthermore, even when the frequency of the input signal changes, the voltage amplitude value can be made close to the maximum value with respect to the changed frequency, and therefore, an integrated circuit device for wireless communication having a high amplification efficiency can be realized for a wide range of frequencies. Can do.

  Also, by setting the resonance frequency of the LC load circuit variably, compared with the conventional method of variably setting the load impedance, a relatively high amplification efficiency can be achieved within the limited device capability of the amplifying transistor. There is an advantage that can be obtained. Or if it is equivalent element performance, there exists an advantage that it can be made to operate | move to a higher frequency.

  FIG. 3 shows a configuration example of the reception-side amplitude detection circuit 260 of the present embodiment. The reception-side amplitude detection circuit 260 includes an AC coupling capacitor CC, a bias voltage setting circuit 60, an amplitude detection transistor TA, an amplitude detection current source IS, a smoothing capacitor CF, and an impedance conversion circuit 70.

  Note that the reception-side amplitude detection circuit of the present embodiment is not limited to the configuration of FIG. 3, and various components such as omitting some of the components, replacing them with other components, and adding other components. Can be implemented.

  AC coupling capacitor CC is provided between output node NP and input node NI, and allows the AC component of amplified signal VP to pass therethrough. The bias voltage setting circuit 60 is for applying the bias voltage VBIAS to the input node NI.

  The amplitude detection transistor TA is provided between the high potential side power supply node VDD (second power supply node in a broad sense) and the detection node NQ, and the gate is controlled by the voltage of the input node NI. With the bias voltage VBIAS, the voltage of the input node NI can be set to a voltage value at which the amplitude detection transistor TA can operate. Thus, an AC voltage having the same amplitude as that of the amplified signal VP is generated at the detection node NQ with VBIAS-VTH (VTH is a threshold voltage of TA) as a center voltage.

  The amplitude detection current source IS is provided between the detection node NQ and the low potential side power supply node VSS (first power supply node in a broad sense). The amplitude detection current source IS is for ensuring the drain current of the amplitude detection transistor TA.

  The smoothing capacitor CF is provided between the detection node NQ and the low potential side power supply node VSS. The smoothing capacitor CF smoothes the voltage at the detection node NQ, so that a voltage corresponding to the voltage amplitude of the amplified signal VP is generated at the detection node NQ.

  The impedance conversion circuit 70 receives the voltage of the detection node NQ, converts the impedance, and outputs the detection output voltage VD to the control circuit 350. Since the signal generated at the detection node NQ is high impedance, it is converted to low impedance by the impedance conversion circuit 70 and output to the control circuit 350. For example, as shown in FIG. 3, the impedance conversion circuit 70 can be configured by a voltage follower-connected operational amplifier OPA.

  4A and 4B are diagrams illustrating the operation of the reception-side amplitude detection circuit 260. FIG. FIG. 4A shows an example of waveforms of the amplified signal VP, the voltage V (NI) of the input node NI, and the voltage V (NQ) (detected output voltage VD) of the detection node NQ. An AC voltage having the bias voltage VBIAS as a center voltage is generated at the input node NI in accordance with the amplified signal VP. A voltage obtained by smoothing an AC signal having VBIAS-VTH as a center voltage is output to the detection node NQ. This smoothed voltage is output as the detection output voltage VD.

  For example, when the voltage amplitude of VP is large, the waveforms shown in C1, C2, and C3 in FIG. 4A are obtained. When the voltage amplitude of VP is small, D1, D2, and D3 in FIG. It becomes the waveform shown in. If the frequency of the amplified signal is sufficiently high, a substantially constant voltage value is output by smoothing.

  FIG. 4B shows an example of the relationship between the detected output voltage VD and the voltage amplitude of the amplified signal VP. As shown in FIG. 4B, the reception-side amplitude detection circuit 260 outputs a signal whose change voltage from the voltage VBIAS-VTH increases as the voltage amplitude of the amplified signal VP increases, as a detection output voltage VD (in a broad sense). Detection result signal). In this way, the voltage amplitude value of the amplified signal VP can be obtained from the voltage difference between the detected output voltage VD and VBIAS-VTH.

  For example, when the voltage amplitude of VP is large, the voltage indicated by C4 in FIG. 4B is output, and when the voltage amplitude of VP is small, the voltage indicated by D4 in FIG. 4B is output. .

  Note that when the voltage amplitude of the amplified signal VP is large, the detected output voltage VD may be saturated as shown by the broken line in FIG. However, saturation of VD can be avoided by setting the bias voltage VBIAS to an appropriate voltage.

  FIG. 5 shows a second configuration example of the reception side amplifier circuit 230 of the present embodiment. The receiving side amplifier circuit of the second configuration example amplifies the differential input signal. The amplifier circuit of the second configuration example includes an amplifying transistor 10, an LC load circuit 20, and a variable current source 50.

  The amplifying transistor 10 includes cascode-connected N-type transistors T11 and T12 and T21 and T22. The LC load circuit 20 includes varactors CA1 and CA2 (first capacitor in a broad sense), capacitors CB1 and CB2 (second capacitor in a broad sense), and an inductor (coil) LB.

  The varactor CA1 is provided between the low potential side power supply node VSS (first power supply node in a broad sense) and the control node NC1, and the capacitance value (capacitance value) is variably set by the voltage of the control node NC1. The capacitor CB1 is for cutting off the DC component, and is provided between the control node NC1 and the output node NP1 of the amplifying transistor 10. The inductor LB is provided between the output node NP1 and another output node NP2, and the intermediate tap of the inductor LB is connected to the high potential side power supply node VDD (second power supply node in a broad sense).

  The varactor CA2 is provided between the low potential side power supply node VSS and the control node NC2, and the capacitance value (capacitance value) is variably set by the voltage of the control node NC2. The capacitor CB2 is for cutting off the direct current component, and is provided between the control node NC2 and the output node NP2 of the amplifying transistor 10.

  Since the resonance frequency of the LC load circuit 20 is changed by changing the capacitance values of the two varactors CA1 and CA2, the frequency characteristic of the LC load circuit 20 is changed.

  The reception-side amplitude detection circuit 260 detects the voltage amplitudes of the differential amplification signals VP1 and VP2, and outputs a detection output voltage VD as a detection result. A detailed configuration example of the reception-side amplitude detection circuit 260 will be described with reference to FIG.

  Based on the detection result of the reception-side amplitude detection circuit 260, the control circuit 350 performs processing for bringing the voltage amplitude values of the differential amplification signals VP1 and VP2 close to the maximum value, and sets at least one of the inductance value and the capacitance value. Take control. For example, in FIG. 5, the control circuit 350 sets the capacitance values of the varactors CA1 and CA2 by changing the LC control voltage VT applied to the control nodes NC1 and NC2.

  Further, after setting at least one of the inductance value and the capacitance value, the control circuit 350 performs a process of bringing the voltage amplitude values of the amplified signals VP1 and VP2 closer to the target amplitude value, thereby setting the current value IA of the variable current source 50. Take control. For example, in FIG. 5, the control circuit 350 performs control to set the current value IA of the variable current source 50 by changing the current source control voltage VA. Specifically, the current value IA increases by increasing the current source control voltage VA, and the voltage amplitude values of the amplified signals VP1 and VP2 increase by increasing the current value IA. On the contrary, the current value IA is decreased by decreasing the current source control voltage VA, and the voltage amplitude values of the amplified signals VP1 and VP2 are decreased by decreasing the current value IA.

  The control circuit 350 can be composed of an A / D converter 41, a logic circuit 42, and D / A converters 43 and 44. The A / D converter 41 converts the detected output voltage VD (detection result), which is analog data, into digital data, and the logic circuit 42 performs processing based on the converted digital data. The D / A converter 43 generates and outputs a current source control voltage VA based on the output of the logic circuit 42, and the D / A converter 44 generates and outputs an LC control voltage VT based on the output of the logic circuit 42. .

  The variable current source 50 is for causing a current to flow through the amplifying transistor 10, and is constituted by a transistor T31, for example, as shown in FIG. The current value IA of the variable current source 50 can be variably set by changing the current source control voltage VA applied to the gate of T31. Note that the variable current source 50 is not limited to the configuration shown in FIG. 5. For example, a plurality of current mirror circuits may be provided and their connection may be switched by a switch element or the like.

  In this way, at least one of the inductance value and the capacitance value of the LC load circuit 20 can be set so that the voltage amplitude values of the differential amplification signals VP1 and VP2 are close to the maximum value. As a result, it is possible to correct the deterioration of the characteristics of the amplifier circuit due to manufacturing variations and environmental fluctuations (for example, fluctuations in temperature, power supply voltage, etc.), thereby realizing a wireless communication integrated circuit device with stable characteristics and high amplification efficiency. be able to. Furthermore, even when the frequency of the input signal changes, the voltage amplitude value can be made close to the maximum value with respect to the changed frequency, and therefore, an integrated circuit device for wireless communication having a high amplification efficiency can be realized for a wide range of frequencies. Can do. Further, after setting at least one of the inductance value and the capacitance value, the voltage amplitude value can be brought close to the target amplitude value, so that the voltage amplitude value can be set to an appropriate value according to the use of the integrated circuit device. Become.

  FIG. 6 shows another configuration example of the reception-side amplitude detection circuit 260 of the present embodiment. The reception-side amplitude detection circuit 260 shown in FIG. 6 is a circuit that detects the voltage amplitude of the differential amplification signals VP1 and VP2, and includes AC coupling capacitors CC1 and CC2, a bias voltage setting circuit 60, amplitude detection transistors TA1 and TA2, An amplitude detection current source IS, a smoothing capacitor CF, and an impedance conversion circuit 70 are included.

  AC coupling capacitors CC1 and CC2 are provided between output node NP1 and input node NI1, and between output node NP2 and input node NI2, respectively, and allow the AC components of differential amplification signals VP1 and VP2 to pass therethrough. The bias voltage setting circuit 60 is for applying the bias voltage VBIAS to the input nodes NI1 and NI2.

  The amplitude detection transistors TA1 and TA2 are provided between the high potential side power supply node VDD (second power supply node in a broad sense) and the detection node NQ. The gate of TA1 is controlled by the voltage of the input node NI1, and the gate of TA2 is controlled by the voltage of the input node NI2. With the bias voltage VBIAS, the voltages at the input nodes NI1 and NI2 can be set to voltage values at which the amplitude detection transistors TA1 and TA2 can operate. By doing so, an AC voltage having the same amplitude as that of the amplified signals VP1 and VP2 is generated at the detection node NQ with VBIAS-VTH (VTH is a threshold voltage of TA1 and TA2) as a center voltage.

  The amplitude detection current source IS is provided between the detection node NQ and the low potential side power supply node VSS (first power supply node in a broad sense). The amplitude detection current source IS is for securing the drain current of the amplitude detection transistors TA1 and TA2.

  The smoothing capacitor CF is provided between the detection node NQ and the low potential side power supply node VSS. The smoothing capacitor CF smoothes the voltage at the detection node NQ, so that a voltage corresponding to the voltage amplitude of the differential amplification signals VP1 and VP2 is generated at the detection node NQ.

  The impedance conversion circuit 70 receives the voltage of the detection node NQ, converts the impedance, and outputs the detection output voltage VD to the control circuit 350. Since the signal generated at the detection node NQ is high impedance, it is converted to low impedance by the impedance conversion circuit 70 and output to the control circuit 350. For example, as shown in FIG. 6, the impedance conversion circuit 70 can be configured by a voltage follower-connected operational amplifier OPA.

  FIG. 7 is a diagram for explaining the operation of the reception-side amplitude detection circuit 260 (FIG. 6). The differential amplification signals VP1 and VP2, the voltages V (NI1) and V (NI2) of the input nodes NI1 and NI2, and the detection thereof. An example of a waveform of voltage V (NQ) (detection output voltage VD) of node NQ is shown. An AC voltage having a bias voltage VBIAS as a center voltage is generated at the input node NI1 according to the amplified signal VP1. Similarly, an AC voltage having a bias voltage VBIAS as a center voltage is generated at the input node NI2 in accordance with the amplified signal VP2. A smoothed voltage having VBIAS-VTH as a reference voltage is output to the detection node NQ. This smoothed voltage is output as the detection output voltage VD.

  For example, when the voltage amplitudes of the differential amplification signals VP1 and VP2 are large (E1 and E3 in FIG. 7), the voltages V (NI1) and V (NI2) at the input nodes NI1 and NI2 are E2 and FIG. The waveform indicated by E4 is obtained, and the voltage V (NQ) of NQ becomes the waveform indicated by E5 in FIG. On the other hand, when the voltage amplitudes of the differential amplification signals VP1 and VP2 are small (F1 and F3 in FIG. 7), the waveforms are as shown in F2 and F4 in FIG. Is the waveform indicated by F5 in FIG. If the frequency of the amplified signal is sufficiently high, a substantially constant voltage value is output by smoothing.

  The relationship between the detected output voltage VD thus obtained and the voltage amplitude of the amplified signal VP is the same as that shown in FIG. The reception-side amplitude detection circuit 260 outputs a signal whose change voltage from the voltage VBIAS-VTH increases as the detection signal voltage VD (detection result in a broad sense) as the voltage amplitude of the amplified signals VP1 and VP2 increases. In this way, the voltage amplitude values of the amplified signals VP1 and VP2 can be obtained from the voltage difference between the detected output voltage VD and VBIAS-VTH.

  8A and 8B show examples of frequency characteristics of the voltage amplitude of the amplified signal. 8A shows a frequency characteristic before setting at least one of an inductance value (L value) and a capacitance value (C value) of the LC load circuit 20 (shown by a broken line) and a frequency characteristic after setting (shown by a solid line). Show).

  For example, before setting at least one of the L value and the C value, the voltage amplitude value at the used frequency (carrier frequency) fc is a value indicated by A1 in FIG. Based on the detection result of the reception-side amplitude detection circuit 260, the control circuit 350 sets at least one of the L value and the C value so that the voltage amplitude value approaches the maximum value. Specifically, by performing control to reduce at least one of the L value and the C value of the LC load circuit 20, the resonance frequency of the LC load circuit 20 is shifted to a higher one. As a result, the voltage amplitude value at fc approaches the maximum value, and becomes, for example, a value indicated by A2 in FIG.

  Although not shown, when the resonance frequency before setting is higher than the frequency fc to be used, the LC load circuit 20 is controlled by increasing at least one of the L value and the C value of the LC load circuit 20. The resonance frequency of 20 shifts to the lower side. As a result, the voltage amplitude value at fc approaches the maximum value.

  FIG. 8B shows frequency characteristics of voltage amplitude values when the current value IA of the variable current source 50 is changed after the above setting. For example, the voltage amplitude value at fc when at least one of the L value and the C value of the LC load circuit 20 is set is a value indicated by B1 in FIG. By increasing the current value IA of the variable current source 50, the gain of the amplifier circuit increases, so that the voltage amplitude value at fc increases, for example, a value indicated by B2 in FIG. 8B. Conversely, by reducing the current value IA of the variable current source 50, the gain of the amplifier circuit decreases, so the voltage amplitude value at fc decreases, for example, the value indicated by B3 in FIG. 8B.

  As described above, according to the integrated circuit device of the present embodiment, at least one of the inductance value and the capacitance value of the LC load circuit can be set so that the voltage amplitude value of the amplified signal approaches the maximum value. As a result, the characteristic deterioration of the amplifier circuit due to manufacturing variations and environmental fluctuations (eg, fluctuations in temperature, power supply voltage, etc.) can be corrected, thereby realizing a wireless communication integrated circuit device with stable characteristics and high amplification efficiency. be able to. Further, even when the frequency of the input signal changes, the voltage amplitude value can be set to the maximum value with respect to the changed frequency, so that an integrated circuit device for wireless communication with high amplification efficiency can be realized for a wide range of frequencies. be able to. Furthermore, by setting the current value of the variable current source after setting at least one of the inductance value and the capacitance value, the voltage amplitude value can be brought close to the target amplitude value. It becomes possible to set the value to an appropriate value.

  The above description is for the reception side amplification circuit 230 and the reception side amplitude detection circuit 260, but the transmission side amplification circuit 310 and the transmission side amplitude detection circuit 340 have the same circuit configuration and operation. Is omitted.

  FIG. 9 is an example of a flowchart of processing for setting at least one of the above-described inductance value and capacitance value. Although FIG. 9 shows a case where a capacitance value (C value) is set as an example, the same control flow is performed when an inductance value (L value) is set. Below, the process which sets C value according to step P1-P13 shown in FIG. 9 is demonstrated.

  First, the C value is set to the initial value C0 (step P1). Next, the voltage amplitude value VPA at the initial value C0 is acquired based on the detection result from the reception side amplitude detection circuit 260 (or the transmission side amplitude detection circuit 340) (step P2). Next, the C value is increased by the increment value ΔC (step P3), and the subsequent voltage amplitude value VPA is acquired (step P4). Then, it is determined whether or not the voltage amplitude value VPA has increased (step P5).

  When the voltage amplitude value VPA increases, the C value is further increased by the increment value ΔC (step P6), and the subsequent voltage amplitude value VPA is acquired (step P7). Then, it is determined whether or not the voltage amplitude value VPA has increased (step P8). When the voltage amplitude value VPA increases, the process returns to step P6, and the C value is further increased by the increment value ΔC. After this is repeated, if the voltage amplitude value VPA does not increase in the determination of step P8, the C value is returned to the previous value (C−ΔC) (step P9), and the setting is completed.

  On the other hand, if the voltage amplitude value VPA does not increase in the determination of step P5, the C value is decreased by the increment value ΔC (step P10), and the subsequent voltage amplitude value VPA is acquired (step P11). Then, it is determined whether or not the voltage amplitude value VPA has increased (step P12). When the voltage amplitude value VPA increases, the process returns to Step P10, and the C value is further decreased by the increment value ΔC. After repeating this, if the voltage amplitude value VPA does not increase in the determination of step P12, the C value is returned to the previous value (C + ΔC) (step P13), and the setting is completed.

  By doing so, it is possible to set the capacitance value of the LC load circuit by performing processing for bringing the voltage amplitude value of the amplified signal close to the maximum value. Further, the inductance value of the LC load circuit can be set by performing the same processing.

  FIG. 10 is an example of a flowchart of processing for setting the voltage value VPA to the target amplitude value VPAset by setting the current value IA of the variable current source 50 after setting at least one of the inductance value and the capacitance value. Below, the process which sets electric current value IA according to step S1-S9 shown in FIG. 10 is demonstrated.

  First, the current value IA is set to the initial value IA0 (step S1). Next, based on the detection result from the reception side amplitude detection circuit 260 (or the transmission side amplitude detection circuit 340), the voltage amplitude value VPA at the initial value IA0 is acquired (step S2). Then, it is determined whether or not the voltage amplitude value VPA is smaller than the target amplitude value VPAset (step S3).

  When the voltage amplitude value VPA is smaller than the target amplitude value VPAset, the current value IA is increased by the increment value ΔIA (step S4), and the subsequent voltage amplitude value VPA is acquired (step S5). Then, it is determined whether or not the difference between the voltage amplitude value VPA and the target amplitude value VPAset is smaller than a predetermined value Ve (step S6). The predetermined value Ve determines the upper limit of the error between the voltage amplitude value VPA actually set by this processing and the target amplitude value VPAset. If the difference between the voltage amplitude value VPA and the target amplitude value VPAset is smaller than the predetermined value Ve, the setting is terminated. If the difference between VPA and VPAset is not smaller than the predetermined value Ve, the process returns to step S4 and is repeated.

  On the other hand, if it is determined in step S3 that the voltage amplitude value VPA is not smaller than the target amplitude value VPAset, the current value IA is decreased by the increment value ΔIA (step S7), and the subsequent voltage amplitude value VPA is acquired (step S7). S8). Then, it is determined whether or not the difference between the voltage amplitude value VPA and the target amplitude value VPAset is smaller than a predetermined value Ve (step S9). If the difference between the voltage amplitude value VPA and the target amplitude value VPAset is smaller than the predetermined value Ve, the setting is terminated. If the difference between VPA and VPAset is not smaller than the predetermined value Ve, the process returns to step S7 and is repeated.

  By doing so, it is possible to set the current value of the variable current source by performing processing for bringing the voltage amplitude value of the amplified signal close to the target amplitude value.

3. Electronic Device FIG. 11 shows a configuration example of an electronic device 400 including the integrated circuit device 100. The electronic device 400 includes an integrated circuit device 100, a sensor unit 410, an A / D converter 420, a storage unit 430, a host 440, and an operation unit 450.

  The electronic device 400 is, for example, a temperature / humidity meter, a pulse meter, a pedometer, and the like, and can transmit the detected data wirelessly. The sensor unit 410 includes a temperature sensor, a humidity sensor, a gyro sensor, an acceleration sensor, a photo sensor, a pressure sensor, and the like, and a sensor corresponding to the application of the electronic device 400 is used.

  The sensor unit 410 amplifies the output signal (sensor signal) of the sensor and removes noise using a filter. The A / D converter 420 converts the amplified signal into a digital signal and outputs it to the integrated circuit device 100. The host 440 is configured by, for example, a microcomputer and performs control processing of the electronic device 400 based on digital signal processing or setting information stored in the storage unit 430 and a signal from the operation unit 450. The storage unit 430 is configured by a flash memory, for example, and stores setting information, detected data, and the like. The operation unit 450 includes, for example, a keypad and is used for a user to operate the electronic device 400.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or the drawings, terms (low potential side power supply node VSS, high potential side power supply node VDD) described together with different terms (first power supply node, second power supply node) having a broader meaning or the same meaning at least once in the specification or the drawings. ) May be replaced by the different terms anywhere in the specification or drawings. The configurations and operations of the amplifier circuit, the integrated circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

10 Amplifying transistor, 20 LC load circuit, 41 A / D converter,
42 logic circuit, 43, 44 D / A converter, 50 variable current source,
60 bias voltage setting circuit, 70 impedance conversion circuit,
100 integrated circuit device, 200 receiving circuit, 230 receiving side amplifier circuit,
240 frequency conversion circuit, 250 filter, 260 reception side amplitude detection circuit,
270 demodulation circuit, 300 transmission circuit, 310 transmission side amplification circuit, 320 modulation circuit,
330 oscillation circuit (PLL circuit), 340 transmission side amplitude detection circuit, 350 control circuit,
360 antenna, 400 electronic device, 410 sensor unit, 420 A / D converter,
430 storage unit, 440 host, 450 operation unit,
CA varactor, CB capacitor, LA inductor, NC control node,
NP output node, VD detection output voltage, VP amplification signal, VT LC control voltage

Claims (10)

A transmission circuit for outputting a transmission signal to the antenna;
A reception circuit having a reception side amplifier circuit including a reception side inductor and a reception side capacitor, and a reception signal from the antenna;
Control circuit,
The transmission circuit transmits a calibration transmission signal during a calibration period,
The receiving circuit receives the calibration transmission signal during the calibration period;
The integrated circuit device, wherein the control circuit sets at least one of an inductance value of the receiving-side inductor and a capacitance value of the receiving-side capacitor during the calibration period. In claim 1,
The reception circuit includes a reception side amplitude detection circuit that detects a voltage amplitude of an amplified signal in the reception side amplification circuit,
The control circuit sets at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor based on a detection result of the reception-side amplitude detection circuit, and sets a voltage amplitude value of the amplified signal to a maximum value. An integrated circuit device characterized by performing a process of approaching. In claim 1 or 2,
The receiving side amplifier circuit includes an amplifying transistor for amplifying an input signal,
An integrated circuit device, wherein at least one of an inductance value of the receiving-side inductor and a capacitance value of the receiving-side capacitor is set variably. In claim 3,
The reception-side capacitor includes a first capacitor provided between a first power supply node and a control node, and a second capacitor provided between the control node and the output node of the amplification transistor. And
The capacitance value of the first capacitor is variably set by the voltage of the control node,
The integrated circuit device, wherein the reception-side inductor is provided between the output node and a second power supply node. In claim 3 or 4,
The receiving-side amplifier circuit includes a variable current source for causing a current to flow through the amplifying transistor,
The integrated circuit device, wherein the control circuit performs control to set a current value of the variable current source based on a detection result of the reception-side amplitude detection circuit. In any one of Claims 1 thru | or 5,
The integrated circuit device, wherein the control circuit sets at least one of an inductance value of the reception-side inductor and a capacitance value of the reception-side capacitor every time the frequency of the carrier wave of the transmission circuit changes. In any one of Claims 1 thru | or 6.
The transmission circuit includes a transmission side amplification circuit having a transmission side inductor and a transmission side capacitor,
The integrated circuit device, wherein the control circuit sets at least one of an inductance value of the transmission-side inductor and a capacitance value of the transmission-side capacitor during the calibration period. In any one of Claims 1 thru | or 7,
The integrated circuit device, wherein the control circuit performs control to make the amplitude of the calibration transmission signal in the calibration period smaller than the amplitude of the transmission signal in the normal wireless transmission period. A transmission circuit for outputting a transmission signal to the antenna;
A reception circuit to which a reception signal from the antenna is input;
Control circuit,
The transmission circuit transmits a calibration transmission signal during a calibration period,
The receiving circuit receives the calibration transmission signal during the calibration period;
The integrated circuit device, wherein the control circuit performs control to make the amplitude of the calibration transmission signal in the calibration period smaller than the amplitude of the transmission signal in the normal wireless transmission period.   An electronic device comprising the integrated circuit device according to claim 1.

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