JP2011154105A - Liquid crystal display device and bias current adjusting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of optimizing current consumption and sufficiently reducing the power consumption, and a bias current adjusting method. <P>SOLUTION: The liquid crystal display device 100 includes: a source output circuit 102 for outputting a source output voltage 118 on the basis of a gradation voltage 117 and a bias current 116; a voltage comparison circuit 104 for comparing the source output voltage 118 with a source output amplitude maximum reference voltage 111 or a source output amplitude minimum reference voltage 112 to output a comparison result; a bias current setting generation circuit 105 for outputting, when the comparison result shows that the source output voltage 118 does not match the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112, a bias current setting signal 115 for adjusting the current value of the bias current 116; and a bias current generation circuit 103 for generating the bias current 116 of a current value based on the bias current setting signal 115. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a bias current adjustment method, and more particularly to optimization of power consumption in a liquid crystal display device.

In recent years, the panels of liquid crystal display devices have become larger and the operating frequency has been increased. For this reason, in order to control the display portion in the liquid crystal display device, it is necessary to perform high-speed operation of the source output. And the high-speed operation | movement was implement | achieved by improving the drive capability for charging / discharging an electric charge to the liquid crystal panel load with respect to a source output.
In order to sufficiently satisfy the display quality of the liquid crystal display device, a bias current having a margin in consideration of variations in liquid crystal panel loads and IC manufacturing variations is selected. Thereby, drive capability can be improved. However, by selecting a bias current having a margin, excessive current consumption occurs and the bias current increases. In the field of portable devices that require battery driving, if power consumption increases due to an increase in the bias current, the usage time and the like are affected. Therefore, low power consumption is required.

  For example, Patent Document 1 describes a bias circuit unit used for a horizontal driver IC. FIG. 3 of Patent Document 1 describes a circuit diagram of the bias circuit section. As shown in FIG. 3 of Patent Document 1, the bias circuit unit described in Patent Document 1 includes two P-channel MOS transistors connected in series as a bias current source. Further, in Patent Document 1, a bias adjustment terminal is connected to each of the source and drain of any P-channel MOS transistor. Thus, in Patent Document 1, the state between the bias adjustment terminals is set to any one of an open state, a short-circuit state, and a state in which adjustment is performed by an external resistor, so that the horizontal driver IC is connected to the load of the liquid crystal panel. It can be driven according to the size.

JP 2000-267064 A

However, in the prior art described in Patent Document 1, it is necessary to adjust the bias current for each liquid crystal display device. Therefore, there is a problem that power consumption cannot be reduced.
Specifically, in the prior art described in Patent Document 1, the bias current is adjusted by an external resistor. Similarly in Patent Document 1, it is necessary to cope with a shortage of bias current due to variations in panel load and IC manufacturing. Therefore, it is necessary to set the resistance value of the external resistor to a resistance value with a margin so that a bias current having a margin in consideration of variations in liquid crystal panel loads and IC manufacturing variations flows. Therefore, in the prior art described in Patent Document 1, it is difficult to set an optimal current consumption, and the power consumption cannot be sufficiently reduced.

  A liquid crystal display device according to a first aspect of the present invention includes a source output circuit, a voltage comparison circuit, a bias current setting generation circuit, and a bias current generation circuit. The source output circuit outputs a source output voltage based on the gradation voltage and the bias current. The voltage comparison circuit compares the source output voltage with a plurality of source output amplitude reference voltages and outputs a comparison result. The bias current setting generation circuit is configured to adjust a bias current setting for adjusting a current value of the bias current when the comparison result indicates that the source output voltage does not match the source output amplitude reference voltage. Output a signal. The bias current generation circuit generates the bias current having a current value based on the bias current setting signal.

  In the first aspect of the present invention, the current value of the bias current is adjusted only when the source output voltage does not match the source output amplitude reference voltage. Therefore, the current value according to the load of the liquid crystal display device can be selected. As a result, excess or deficiency in the current consumption of the amplifier of the source output circuit can be suppressed. Therefore, the current consumption of the liquid crystal display device can be optimized, and the power consumption can be sufficiently reduced.

  In the bias current adjustment method according to the second aspect of the present invention, the liquid crystal display device executes a source output process, a voltage comparison process, a bias current setting generation process, and a bias current generation process. In the source output process, the liquid crystal display device outputs a source output voltage based on the gradation voltage and the bias current. In the voltage comparison process, the liquid crystal display device compares the source output voltage with a plurality of source output amplitude reference voltages, and outputs a comparison result. The liquid crystal display device adjusts the current value of the bias current when the comparison result indicates that the source output voltage does not match the source output amplitude reference voltage in the bias current setting generation process. To output a bias current setting signal. The liquid crystal display device generates the bias current having a current value based on the bias current setting signal in the bias current generation process.

  In the second aspect of the present invention, the current value of the bias current is adjusted only when the source output voltage does not match the source output amplitude reference voltage. Therefore, the current value according to the load of the liquid crystal display device can be selected. As a result, excess or deficiency in the current consumption of the amplifier of the source output circuit can be suppressed. Therefore, the current consumption of the liquid crystal display device can be optimized, and the power consumption can be sufficiently reduced.

  According to the present invention, the current consumption of the liquid crystal display device can be optimized, and the power consumption can be sufficiently reduced.

It is a block diagram which shows an example of the liquid crystal display device concerning Embodiment 1 of this invention. 3 is a flowchart illustrating a control method for the liquid crystal display device according to the first exemplary embodiment of the present invention; 6 is a timing chart for explaining a bias current adjustment operation in the liquid crystal display device according to the first exemplary embodiment of the present invention; 6 is a timing chart for explaining a bias current adjustment operation in the liquid crystal display device according to the first exemplary embodiment of the present invention; 4 is a timing chart showing a source output voltage when the bias current value includes an operation margin and a source output voltage when the bias current value does not include an operation margin. It is a block diagram which shows an example of the liquid crystal display device concerning Embodiment 2 of this invention. It is a flowchart which shows the control method of the liquid crystal display device concerning Embodiment 2 of this invention.

Hereinafter, embodiments to which the present invention can be applied will be described. Note that the present invention is not limited to the following embodiments.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing an example of a liquid crystal display device 100 according to Embodiment 1 of the present invention.
As shown in FIG. 1, the liquid crystal display device 100 includes a gradation voltage generation circuit 101, a source output circuit 102, a bias current generation circuit 103, a voltage comparison circuit 104, a bias current setting generation circuit 105, a determination timing generation circuit 106, and the like. Have.
The liquid crystal display device 100 includes a control unit (not shown) including a CPU (Central Processor Unit), a recording medium (not shown), and the like. The recording medium stores various programs (not shown) for controlling the liquid crystal display device 100, data (not shown), and the like. Then, the control unit controls each unit of the liquid crystal display device 100 by executing various programs stored in the recording medium. The control unit may be configured by an FPGA (Field Programmable Gate Array) or the like.

  The gradation voltage generation circuit 101 inputs the gradation voltage 117 to the source output circuit 102. Further, the gradation voltage generation circuit 101 inputs the source output amplitude maximum reference voltage 111 (source output amplitude reference voltage) and the source output amplitude minimum reference voltage 112 (source output amplitude reference voltage) to the voltage comparison circuit 104.

  The source output circuit 102 inputs the source output voltage 118 to the voltage comparison circuit 104 based on the gradation voltage 117 and the bias current 116 input from the bias current generation circuit 103.

  The bias current generation circuit 103 inputs a bias current 116 to the source output circuit 102 based on the bias current setting signal 115 input from the bias current setting generation circuit 105.

  The voltage comparison circuit 104 receives the source output amplitude maximum reference voltage 111 and the source output amplitude minimum reference voltage 112 from the gradation voltage generation circuit 101. Further, the source output voltage 118 is input from the source output circuit 102 to the voltage comparison circuit 104. The voltage comparison determination timing signal 114 is input from the determination timing generation circuit 106 to the voltage comparison circuit 104. Then, the voltage comparison circuit 104 compares the source output voltage 118 with the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 at the timing based on the voltage comparison determination timing signal 114, and based on the comparison result. Thus, the bias current adjustment determination signal 113 is input to the bias current setting generation circuit 105.

A bias current adjustment determination signal 113 is input from the voltage comparison circuit 104 to the bias current setting generation circuit 105. Further, the interface input signal 120 is input to the bias current setting generation circuit 105 from the outside. The bias current setting generation circuit 105 inputs the bias current setting signal 115 to the bias current generation circuit 103 based on the bias current adjustment determination signal 113.
Specifically, when the bias current adjustment determination signal 113 indicating that the source output voltage 118 does not match the source output amplitude maximum reference voltage 111 at the rising edge of the source output voltage 118 is input, the bias current setting generation circuit 105 The bias current setting signal 115 for increasing the bias current is input to the bias current generating circuit 103. Thus, the bias current is adjusted so that the source output voltage 118 matches the source output amplitude maximum reference voltage 111.
On the other hand, when the bias current adjustment determination signal 113 indicating that the source output voltage 118 does not match the minimum source output amplitude reference voltage 112 is input at the fall of the source output voltage 118, the bias current setting generation circuit 105 A bias current setting signal 115 for decreasing the current is input to the bias current generation circuit 103. Thus, the bias current is adjusted so that the source output voltage 118 matches the source output amplitude minimum reference voltage 112.
A signal similar to the bias current adjustment determination signal 113 may be input to the bias current setting generation circuit 105 as the interface input signal 120.

A clock 119 is input to the determination timing generation circuit 106. Then, the determination timing generation circuit 106 inputs the voltage comparison determination timing signal 114 to the voltage comparison circuit 104 based on the clock 119.
In addition, the determination timing generation circuit 106 adjusts the timing for generating the voltage comparison determination timing signal 114 so that the voltage comparison circuit 104 has the source output voltage 118 and the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage. 112 is adjusted.

Next, a method for controlling the liquid crystal display device 100 according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart illustrating a method for controlling the liquid crystal display device 100. Specifically, FIG. 2 shows a bias current adjustment method among the control methods of the liquid crystal display device 100. 3 and 4 are timing charts for explaining the bias current adjustment operation in the liquid crystal display device 100. FIG.
As shown in FIG. 2, first, the source output circuit 102 starts a display operation with automatic bias current adjustment, and inputs the source output voltage 118 to the voltage comparison circuit 104 (step S1).

Next, the voltage comparison circuit 104 determines whether or not the voltage comparison determination timing signal 114 is input from the determination timing generation circuit 106 (step S2).
In step S2, when the voltage comparison circuit 104 determines that the voltage comparison determination timing signal 114 is not input (step S2; No), the process returns to step S1.
When the voltage comparison circuit 104 determines in step S2 that the voltage comparison determination timing signal 114 is input (step S2; Yes), the voltage comparison circuit 104 has a timing based on the voltage comparison determination timing signal 114. The source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 is compared with the source output voltage 118 (step S3).

In step S3, if the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 and the source output voltage 118 do not match (step S3; No), the comparison result is used as the bias current adjustment determination signal 113. Is input to the bias current setting generation circuit 105 (step S4). Thereby, the bias current is adjusted.
In step S3, when the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 and the source output voltage 118 match (step S3; Yes), this process ends.

Next, the operation of the liquid crystal display device 100 when the bias current adjustment process (the process of step S4) is executed will be described with reference to the timing chart shown in FIG.
First, before the time T11, the source output voltage 118 is substantially the same as the source output amplitude minimum reference voltage 112. At time T11, the source output voltage 118 starts to rise.

  Next, at time T12, based on the clock 119, the voltage comparison determination timing signal 114 generated by the determination timing generation circuit 106 rises, and at time T13, the voltage comparison determination timing signal 114 falls. That is, the pulse width of the voltage comparison determination signal 114 is equal to the time between time T12 and time T13.

  Then, the voltage comparison circuit 104 compares the source output voltage 118 and the source output amplitude maximum reference voltage 111 in the time between time T12 and time T13. When there is a potential difference between the source output voltage 118 and the source output amplitude maximum reference voltage 111, the voltage comparison circuit 104 starts from time T13 until the potential difference between the source output voltage 118 and the source output amplitude maximum reference voltage 111 disappears. That is, the bias current adjustment determination signal 113 is input to the bias current setting generation circuit 105 until time T14. That is, the pulse width of the bias current adjustment determination signal is equal to the time between time T13 and time T14.

  Then, the bias current setting generation circuit 105 increases the bias current 116 so that the bias current 116 input from the bias current generation circuit 103 to the source output circuit 102 increases at the rising edge of the bias current adjustment determination signal 113, that is, at time T13. The bias current setting signal 115 input from the current setting generation circuit 105 to the bias current generation circuit 103 is changed.

  Further, between time T14 and time T15, the source output voltage 118 is substantially the same as the source output amplitude maximum reference voltage 111. At time T15, the source output voltage 118 starts to fall.

  Next, at time T16, based on the clock 119, the voltage comparison determination timing signal 114 generated by the determination timing generation circuit 106 rises, and at time T17, the voltage comparison determination timing signal 114 falls. That is, the pulse width of the voltage comparison determination signal 114 is equal to the time between time T16 and time T17.

  Then, the voltage comparison circuit 104 compares the source output voltage 118 and the source output amplitude minimum reference voltage 112 during the time between time T16 and time T17. When there is a potential difference between the source output voltage 118 and the source output amplitude minimum reference voltage 112, the voltage comparison circuit 104 starts from time T17 until the potential difference between the source output voltage 118 and the source output amplitude minimum reference voltage 112 disappears. That is, the bias current adjustment determination signal 113 is input to the bias current setting generation circuit 105 until time T18. That is, the pulse width of the bias current adjustment determination signal is equal to the time between time T17 and time T18.

  Then, the bias current setting generation circuit 105 performs bias adjustment so that the bias current 116 input from the bias current generation circuit 103 to the source output circuit 102 decreases at the rising edge of the bias current adjustment determination signal 113, that is, at time T17. The bias current setting signal 115 input from the current setting generation circuit 105 to the bias current generation circuit 103 is changed.

Next, the operation of the liquid crystal display device 100 when the bias current adjustment process (the process of step S4) is not executed will be described with reference to the timing chart shown in FIG.
First, before the time T21, the source output voltage 118 is substantially the same as the source output amplitude minimum reference voltage 112. At time T21, the source output voltage 118 starts to rise.

  Next, at time T22, based on the clock 119, the voltage comparison determination timing signal 114 generated by the determination timing generation circuit 106 rises, and at time T23, the voltage comparison determination timing signal 114 falls. That is, the pulse width of the voltage comparison determination signal 114 is equal to the time between time T22 and time T23.

  Then, the voltage comparison circuit 104 compares the source output voltage 118 with the source output amplitude maximum reference voltage 111 in the time between time T22 and time T23. In the case of FIG. 4, the source output voltage 118 rises to substantially the same voltage as the source output amplitude maximum reference voltage 111 at a certain time between time T21 and time T22. Therefore, there is almost no potential difference between the source output voltage 118 and the source output amplitude maximum reference voltage 111 in the time between time T22 and time T23. For this reason, the voltage comparison circuit 104 does not input the bias current adjustment determination signal 113 to the bias current setting generation circuit 105. Therefore, in the bias current setting generation circuit 105, the bias current setting signal 115 input to the bias current generation circuit 103 is not changed. As a result, the bias current 116 input from the bias current generation circuit 103 to the source output circuit 102 is not adjusted.

  In addition, the source output voltage 118 is substantially the same as the source output amplitude maximum reference voltage 111 from a certain time between time T21 and time T22 to time T24. At time T24, the source output voltage 118 starts to fall.

  Next, at time T25, based on the clock 119, the voltage comparison determination timing signal 114 generated by the determination timing generation circuit 106 rises, and at time T26, the voltage comparison determination timing signal 114 falls. That is, the pulse width of the voltage comparison determination signal 114 is equal to the time between time T25 and time T26.

  Then, the voltage comparison circuit 104 compares the source output voltage 118 and the source output amplitude minimum reference voltage 112 during the time between time T25 and time T26. In the case of FIG. 4, the source output voltage 118 falls to substantially the same voltage as the source output amplitude minimum reference voltage 112 at a certain time between time T24 and time T25. Therefore, there is almost no potential difference between the source output voltage 118 and the source output amplitude minimum reference voltage 112 in the time between time T25 and time T26. For this reason, the voltage comparison circuit 104 does not input the bias current adjustment determination signal 113 to the bias current setting generation circuit 105. Therefore, in the bias current setting generation circuit 105, the bias current setting signal 115 input to the bias current generation circuit 103 is not changed. As a result, the bias current 116 input from the bias current generation circuit 103 to the source output circuit 102 is not adjusted.

  Next, effects obtained by the liquid crystal display device 100 according to Embodiment 1 of the present invention will be described with reference to FIG. 5 shows the source output voltage 118 when the bias current value includes an operation margin, and FIG. 5 shows the source output voltage 118 when the bias current value does not include an operation margin. Show.

First, the source output voltage 118 shown in the upper part of FIG. 5 when the bias current value includes an operation margin will be described. As shown in the upper part of FIG. 5, the source output voltage 118 rises from the source output amplitude minimum reference voltage 112 to the source output amplitude maximum reference voltage 111 from time T31 to time T32. Here, a period from time T31 to time T32 is referred to as a rising period TM1 of the source output voltage 118.
Further, as shown in the upper part of FIG. 5, the source output voltage 118 is substantially the same as the source output amplitude maximum reference voltage 111 from time T32 to time T35. The source output voltage 118 falls from the source output amplitude maximum reference voltage 111 to the source output amplitude minimum reference voltage 112 from time T35 to time T36. Here, a period from time T35 to time T36 is referred to as a falling period TM3 of the source output voltage 118.
As shown in the upper part of FIG. 5, the source output voltage 118 is substantially the same as the source output amplitude minimum reference voltage 112 from time T36 to time T39.

5, the period from time T32 to time T33 is the rising margin period TM5, the period from time T33 to time T34 is the setup period, and the period from time T34 to time T35 is the hold period. It is. The margin period TM5 is provided so that the source output voltage 118 becomes the source output amplitude maximum reference voltage 111 in the setup period from time T33 to time T34 and in the hold period from time T34 to time T35.
Similarly, in the upper part of FIG. 5, the period from time T36 to time T37 is the falling margin period TM6, the period from time T37 to time T38 is the setup period, and the period from time T38 to time T39. Is a hold period. The margin period TM6 is provided so that the source output voltage 118 becomes the source output amplitude minimum reference voltage 112 in the setup period from time T37 to time T38 and in the hold period from time T38 to time T39.

Next, the source output voltage 118 shown in the lower part of FIG. 5 when the operation current is not included in the bias current value will be described. As shown in the lower part of FIG. 5, the source output voltage 118 rises from the source output amplitude minimum reference voltage 112 to the source output amplitude maximum reference voltage 111 from time T31 to time T33. Here, a period from time T31 to time T33 is referred to as a rising period TM2 of the source output voltage 118.
Further, as shown in the lower part of FIG. 5, the source output voltage 118 is substantially the same as the source output amplitude maximum reference voltage 111 from time T33 to time T35. Then, the source output voltage 118 falls from the source output amplitude maximum reference voltage 111 to the source output amplitude minimum reference voltage 112 from time T35 to time T37. Here, a period from time T35 to time T37 is referred to as a falling period TM4 of the source output voltage 118.
Further, as shown in the lower part of FIG. 5, the source output voltage 118 is substantially the same as the source output amplitude minimum reference voltage 112 from time T37 to time T39.

  Also in the lower stage of FIG. 5, as in the upper stage of FIG. 5, the period from time T33 to time T34 is a setup period, and the period from time T34 to time T35 is a hold period. Similarly, a period from time T37 to time T38 is a setup period, and a period from time T38 to time T39 is a hold period. Unlike the source output voltage 118 shown in the upper part of FIG. 5, the source period 118 shown in the lower part of FIG. 5 is not provided with the margin period TM5 and the margin period TM6.

In both the source output voltage 118 shown in the upper part of FIG. 5 and the source output voltage 118 shown in the lower part of FIG. 5, in the setup period from time T33 to time T34 and in the hold period from time T34 to time T35, In order for the source output voltage 118 to become the source output amplitude maximum reference voltage 111, the source output voltage 118 must rise to the source output amplitude maximum reference voltage 111 by time T33.
Therefore, in the source output voltage 118 shown in the upper part of FIG. 5, the operation margin is included in the bias current value so that the source output voltage 118 becomes the source output amplitude maximum reference voltage 111 during the margin period TM5. That is, the margin period TM5 has a length in consideration of the operation margin.

Similarly, in both the source output voltage 118 shown in the upper part of FIG. 5 and the source output voltage 118 shown in the lower part of FIG. 5, the setup period from time T37 to time T38 and the hold from time T38 to time T39 are held. In order for the source output voltage 118 to become the source output amplitude minimum reference voltage 112 in the period, the source output voltage 118 must rise to the source output amplitude minimum reference voltage 112 by time T37.
Therefore, in the source output voltage 118 shown in the upper part of FIG. 5, the operation current is included in the bias current value so that the source output voltage 118 becomes the source output amplitude minimum reference voltage 112 during the margin period TM6. That is, the margin period TM6 has a length in consideration of the operation margin.

  For example, here, the rising period TM2 of the source output voltage 118 shown in the lower part of FIG. 5 is twice the rising period TM1 of the source output voltage 118 shown in the upper part of FIG. 5, and the source shown in the lower part of FIG. Assume that the falling period TM4 of the output voltage 118 is twice the falling period TM3 of the source output voltage 118 shown in the upper part of FIG. Further, the consumption current of the amplifier of the source output circuit 102 necessary for the source driving capability in the rising period TM1 and the falling period TM3 is 1 mA. Further, the source driving capability is proportional to the bias current 116. Therefore, the consumption current of the amplifier of the source output circuit 102 necessary for the source driving capability of the rising period TM2 and the falling period TM4 is equal to that of the amplifier of the source output circuit 102 required for the source driving capability of the rising period TM1 and the falling period TM3. Half of the current consumption. Therefore, in the case shown in FIG. 5, the consumption current of the amplifier of the source output circuit 102 necessary for the source driving capability in the rising period TM2 and the falling period TM4 is 0.5 mA. As described above, by suppressing the excess or deficiency of the operation margin included in the bias current value, the current consumption of the liquid crystal display device 100 can be optimized and the current consumption can be reduced.

  As described above, according to the liquid crystal display device 100 according to the first embodiment of the present invention, the source output voltage 118 does not match the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112. Only, the current value of the bias current 116 is adjusted. Therefore, a current value corresponding to the load of the liquid crystal display device 100 can be selected. As a result, excess or deficiency in the current consumption of the amplifier of the source output circuit 102 can be suppressed. Therefore, the current consumption of the liquid crystal display device 100 can be optimized, and the power consumption can be sufficiently reduced.

The voltage comparison circuit 104 compares the source output voltage 118 with the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 at an arbitrary timing.
As a result, a voltage difference is generated between the source output voltage 118 and the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 due to load variation, manufacturing variation, or IC manufacturing variation of the liquid crystal display device 100. Even so, the current value of the bias current 116 is adjusted so that the voltage difference is eliminated. Therefore, the display quality of the liquid crystal display device 100 can be optimized even if there are load fluctuations, manufacturing variations, or IC manufacturing variations in the liquid crystal display device 100.

In addition, the determination timing generation circuit 106 adjusts the timing for generating the voltage comparison determination timing signal 114 so that the voltage comparison circuit 104 has the source output voltage 118 and the source output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112. Adjust the timing to compare with.
As a result, even if it is necessary to increase the source drive speed by changing the system frequency by changing the panel size or the like, the voltage comparison circuit 104 generates the source output voltage 118 and the source according to each liquid crystal panel. The timing for comparing the output amplitude maximum reference voltage 111 or the source output amplitude minimum reference voltage 112 can be set to an optimum timing.

Embodiment 2. FIG.
Unlike the liquid crystal display device 100 according to the first embodiment, the liquid crystal display device 200 according to the second embodiment of the present invention includes, for each of a plurality of source output amplitude reference voltages, a voltage comparison circuit, a bias current setting generation circuit, A bias current generation circuit. In the liquid crystal display device 200 according to the second embodiment, the voltage comparison circuit inputs the comparison result obtained by comparing the corresponding source output amplitude reference voltage and the source output voltage to the corresponding bias current setting generation circuit. To do. The bias current setting generation circuit outputs a bias current setting signal when the corresponding source output amplitude reference voltage does not match the source output voltage.
Hereinafter, an example of the liquid crystal display device 200 according to Embodiment 2 will be described in detail.
FIG. 6 is a block diagram showing an example of a liquid crystal display device 200 according to Embodiment 2 of the present invention. In the liquid crystal display device 100 shown in FIG. 6, the same components as those of the liquid crystal display device 100 shown in FIG.
As shown in FIG. 6, the liquid crystal display device 200 according to the second embodiment includes a gradation voltage generation circuit 101, a source output circuit 201, a maximum voltage comparison circuit 202 (voltage comparison circuit), and a minimum voltage comparison circuit 203 (voltage comparison). Circuit), rising side bias current setting generation circuit 204 (bias current setting generation circuit), falling side bias current setting generation circuit 205 (bias current setting generation circuit), rising side bias current generation circuit 206 (bias current generation circuit), A falling-side bias current generation circuit 207 (bias current generation circuit), a determination timing generation circuit 208, and the like are included.
The liquid crystal display device 200 includes a control unit (not shown) including a CPU (Central Processor Unit), a recording medium (not shown), and the like. The recording medium stores various programs (not shown) for controlling the liquid crystal display device 200, data (not shown), and the like. Then, the control unit controls each unit of the liquid crystal display device 200 by executing various programs stored in the recording medium. The control unit may be configured by an FPGA (Field Programmable Gate Array) or the like.

  The source output circuit 201 includes a gradation voltage 117 and a rising side bias current 215 (bias current) input from the rising side bias current generation circuit 206 or a falling side bias current input from the falling side bias current generation circuit 207. The source output voltage 118 is input to the maximum voltage comparison circuit 202 and the minimum voltage comparison circuit 203 based on 216 (bias current).

  The maximum voltage comparison circuit 202 receives the source output amplitude maximum reference voltage 111 from the gradation voltage generation circuit 101. Further, the source output voltage 118 is input from the source output circuit 201 to the maximum voltage comparison circuit 202. Further, the rising side voltage comparison determination timing signal 217 (voltage comparison determination timing signal) is input to the maximum voltage comparison circuit 202 from the determination timing generation circuit 208. The maximum voltage comparison circuit 202 compares the source output voltage 118 with the source output amplitude maximum reference voltage 111 at the timing based on the rising-side voltage comparison determination timing signal 217, and based on the comparison result, the rising-side bias The current adjustment determination signal 211 is input to the rising side bias current setting generation circuit 204.

  The minimum voltage comparison circuit 203 receives the source output amplitude minimum reference voltage 112 from the gradation voltage generation circuit 101. Further, the source output voltage 118 is input from the source output circuit 201 to the minimum voltage comparison circuit 203. The minimum voltage comparison circuit 203 also receives a falling-side voltage comparison determination timing signal 218 (voltage comparison determination timing signal) from the determination timing generation circuit 208. Then, the minimum voltage comparison circuit 203 compares the source output voltage 118 with the source output amplitude minimum reference voltage 112 at the timing based on the falling-side voltage comparison determination timing signal 218, and falls based on the comparison result. The side bias current adjustment determination signal 212 is input to the falling side bias current setting generation circuit 205.

  The rising side bias current setting generation circuit 204 receives the rising side bias current adjustment determination signal 211 from the maximum voltage comparison circuit 202. Further, the rising side bias current setting generation circuit 204 receives an interface input signal 120 from the outside. Then, the rising side bias current setting generation circuit 204 inputs the rising side bias current setting signal 213 (bias current setting signal) to the rising side bias current generation circuit 206 based on the rising side bias current adjustment determination signal 211. Note that a signal similar to the rising side bias current adjustment determination signal 211 may be input to the rising side bias current setting generation circuit 204 as the interface input signal 120.

  The falling side bias current setting generation circuit 205 receives the falling side bias current adjustment determination signal 212 from the minimum voltage comparison circuit 203. Further, the falling-side bias current setting generation circuit 205 receives an interface input signal 120 from the outside. Then, the falling side bias current setting generation circuit 205 sends a falling side bias current setting signal 214 (bias current setting signal) to the falling side bias current generation circuit 207 based on the falling side bias current adjustment determination signal 212. Enter. Note that a signal similar to the falling-side bias current adjustment determination signal 212 may be input to the falling-side bias current setting generation circuit 205 as the interface input signal 120.

  The rising side bias current generation circuit 206 inputs the rising side bias current 215 to the source output circuit 201 based on the rising side bias current setting signal 213 input from the rising side bias current setting generation circuit 204.

  The falling side bias current generation circuit 207 inputs the falling side bias current 216 to the source output circuit 201 based on the falling side bias current setting signal 214 input from the falling side bias current setting generation circuit 205.

A clock 119 is input to the determination timing generation circuit 208. Based on the clock 119, the determination timing generation circuit 208 inputs the rising side voltage comparison determination timing signal 217 to the maximum voltage comparison circuit 202 and inputs the falling side voltage comparison determination timing signal 218 to the minimum voltage comparison circuit 203. To do.
Further, the determination timing generation circuit 208 adjusts the timing for generating the rising side voltage comparison determination timing signal 217 so that the maximum voltage comparison circuit 202 compares the source output voltage 118 with the source output amplitude maximum reference voltage 111. Adjust the timing.
Similarly, the determination timing generation circuit 208 adjusts the timing of generating the falling-side voltage comparison determination timing signal 218 so that the minimum voltage comparison circuit 203 has the source output voltage 118, the source output amplitude minimum reference voltage 112, Adjust the timing for comparison.

Next, a method for controlling the liquid crystal display device 200 according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 7 is a flowchart showing a method for controlling the liquid crystal display device 200. Specifically, FIG. 7 shows a bias current adjustment method among the control methods of the liquid crystal display device 200.
As shown in FIG. 7, first, the source output circuit 201 starts a display operation with automatic bias current adjustment, and inputs the source output voltage 118 to the maximum voltage comparison circuit 202 and the minimum voltage comparison circuit 203 (step S101). ).

  Next, the maximum voltage comparison circuit 202 determines whether or not the rising side voltage comparison determination timing signal 217 is input from the determination timing generation circuit 208, and the minimum voltage comparison circuit 203 falls from the determination timing generation circuit 208. It is determined whether or not the side voltage comparison determination timing signal 218 is input (step S102).

  In step S102, the maximum voltage comparison circuit 202 determines that the rising side voltage comparison determination timing signal 217 is not input, and the minimum voltage comparison circuit 203 receives the falling side voltage comparison determination timing signal 218. If it is determined that there is not (step S102; No), the process returns to step S101.

  In step S102, the maximum voltage comparison circuit 202 determines that the rising side voltage comparison determination timing signal 217 is input, or the minimum voltage comparison circuit 203 receives the falling side voltage comparison determination timing signal 218. (Step S102; Yes), and when the rising side voltage comparison determination timing signal 217 is input (step S103; Yes), the maximum voltage comparison circuit 202 determines the rising side voltage comparison determination timing signal 217. The source output amplitude maximum reference voltage 111 is compared with the source output voltage 118 at a timing based on (step S104).

In step S104, when the source output amplitude maximum reference voltage 111 and the source output voltage 118 do not match (step S104; No), the comparison result is used as the rising side bias current adjustment determination signal 211, and the rising side bias current. The setting is input to the setting generation circuit 204 (step S105).
In step S104, when the source output amplitude maximum reference voltage 111 and the source output voltage 118 match (step S104; Yes), the process proceeds to step S108.

  In step S102, the maximum voltage comparison circuit 202 determines that the rising side voltage comparison determination timing signal 217 is input, or the minimum voltage comparison circuit 203 receives the falling side voltage comparison determination timing signal 218. Is determined (step S102; Yes), and when the falling voltage comparison determination timing signal 218 is input to the minimum voltage comparison circuit 203 (step S103; No), the minimum voltage comparison circuit 203 The source output amplitude minimum reference voltage 112 and the source output voltage 118 are compared with each other at the timing based on the downstream voltage comparison determination timing signal 218 (step S106).

In step S106, when the source output amplitude minimum reference voltage 112 and the source output voltage 118 do not match (step S106; No), the comparison result is used as the falling-side bias current adjustment determination signal 212, and the falling-side Input to the bias current setting generation circuit 205 (step S107).
In step S106, when the source output amplitude minimum reference voltage 112 and the source output voltage 118 match (step S106; Yes), the source output voltage 118 becomes the source output amplitude maximum reference at the rising edge of the source output voltage 118. It is determined whether or not the source output voltage 118 has fallen to the source output amplitude minimum reference voltage 112 when the source output voltage 118 has risen to the voltage 111 and the source output voltage 118 has fallen (step S108).

In step S 108, the source output voltage 118 does not rise to the source output amplitude maximum reference voltage 111 at the rise of the source output voltage 118, and the source output voltage 118 becomes the source output amplitude minimum reference at the fall of the source output voltage 118. When the source output voltage 118 has not fallen to the voltage 112, or when the source output voltage 118 has not risen to the source output amplitude maximum reference voltage 111 at the rise of the source output voltage 118, or at the fall of the source output voltage 118, When the voltage 118 has not fallen to the source output amplitude minimum reference voltage 112 (step S108; No), the process returns to step S101.
In step S108, the source output voltage 118 rises to the source output amplitude maximum reference voltage 111 at the rise of the source output voltage 118, and the source output voltage 118 becomes the source output amplitude minimum reference at the fall of the source output voltage 118. If it has fallen to the voltage 112 (step S108; Yes), this process ends.

  As described above, according to the liquid crystal display device 200 according to the second embodiment of the present invention, it is possible to obtain the same effect as that of the liquid crystal display device 100 according to the first embodiment. The adjustment of the bias current 215 at the rising edge of the source output voltage 118 and the adjustment of the bias current 216 at the falling edge of the source output voltage 118 can be performed individually. Therefore, even if there is a difference between the drive capability of the amplifier of the source output circuit 201 at the rise of the source output voltage 118 and the drive capability of the amplifier of the source output circuit 201 at the fall of the source output voltage 118, the source output The bias current can be adjusted only at the timing at which adjustment is required, at the time of rising and falling of the voltage 118. For this reason, it is not necessary to flow an excessive bias current at the timing when adjustment is not required during the rise and fall of the source output voltage 118, and the power consumption can be further reduced.

  In the embodiment of the present invention described above, the source output amplitude reference voltage is described by taking the source output amplitude maximum reference voltage 111 and the source output amplitude minimum reference voltage 112 as examples. The amplitude reference voltage is not limited to these two reference voltages.

101 gradation voltage generation circuit 102, 201 source output circuit 103 bias current generation circuit 104 voltage comparison circuit 105 bias current setting generation circuit 106, 208 determination timing generation circuit 111 source output amplitude maximum reference voltage (source output amplitude reference voltage)
112 Source output amplitude minimum reference voltage (source output amplitude reference voltage)
114 Voltage comparison determination timing signal 115 Bias current setting signal 116 Bias current 117 Gradation voltage 118 Source output voltage 119 Clock 202 Maximum voltage comparison circuit (voltage comparison circuit)
203 Minimum voltage comparison circuit (voltage comparison circuit)
204 Rising side bias current setting generation circuit (bias current setting generation circuit)
205 Falling-side bias current setting generation circuit (bias current setting generation circuit)
206 Rise side bias current generation circuit (bias current generation circuit)
207 Falling side bias current generation circuit (bias current generation circuit)
213 Rise side bias current setting signal (bias current setting signal)
214 Falling-side bias current setting signal (bias current setting signal)
215 Rise side bias current (bias current)
216 Falling side bias current (bias current)
217 Rise side voltage comparison determination timing signal (voltage comparison determination timing signal)
218 Falling-side voltage comparison determination timing signal (voltage comparison determination timing signal)
100, 200 Liquid crystal display device

Claims (8)

A source output circuit that outputs a source output voltage based on the gradation voltage and the bias current;
A voltage comparison circuit that compares the source output voltage with a plurality of source output amplitude reference voltages and outputs a comparison result;
A bias current setting generation circuit for outputting a bias current setting signal for adjusting a current value of the bias current when the comparison result indicates that the source output voltage and the source output amplitude reference voltage do not match; ,
A bias current generation circuit for generating the bias current having a current value based on the bias current setting signal;
A liquid crystal display device comprising: A determination timing generation circuit that generates a voltage comparison determination timing signal that defines a timing at which the voltage comparison circuit compares the source output voltage and the source output amplitude reference voltage based on a clock;
The determination timing generation circuit adjusts a timing at which the voltage comparison circuit compares the source output voltage with the source output amplitude reference voltage by adjusting a timing at which the voltage comparison determination timing signal is generated. A liquid crystal display device according to 1.   The liquid crystal display device according to claim 1, further comprising a gradation voltage generation circuit that generates the gradation voltage and a plurality of the source output amplitude reference voltages. For each of the plurality of source output amplitude reference voltages, the voltage comparison circuit, the bias current setting generation circuit, and the bias current generation circuit,
The voltage comparison circuit inputs the comparison result obtained by comparing the corresponding source output amplitude reference voltage and the source output voltage to the corresponding bias current setting generation circuit,
4. The liquid crystal according to claim 1, wherein the bias current setting generation circuit outputs the bias current setting signal when the corresponding source output amplitude reference voltage does not match the source output voltage. 5. Display device. Liquid crystal display device
Source output processing for outputting a source output voltage based on the gradation voltage and the bias current;
A voltage comparison process for comparing the source output voltage with a plurality of source output amplitude reference voltages and outputting a comparison result;
A bias current setting generation process for outputting a bias current setting signal for adjusting a current value of the bias current when the comparison result indicates that the source output voltage does not match the source output amplitude reference voltage; ,
A bias current generation process for generating the bias current having a current value based on the bias current setting signal;
Perform bias current adjustment method. The liquid crystal display device further executes a determination timing generation process for generating a voltage comparison determination timing signal that defines a timing for executing the voltage comparison process based on a clock,
The bias current adjustment method according to claim 5, wherein in the determination timing generation process, the liquid crystal display device adjusts a timing of executing the voltage comparison process by adjusting a timing of generating the voltage comparison determination timing signal. .   The bias current adjusting method according to claim 5 or 6, wherein the liquid crystal display device further executes a gradation voltage generation process for generating the gradation voltage and a plurality of the source output amplitude reference voltages. The liquid crystal display device executes the voltage comparison process, the bias current setting generation process, and the bias current generation process for each of the plurality of source output amplitude reference voltages,
In the voltage comparison process, the liquid crystal display device compares the corresponding source output amplitude reference voltage and the source output voltage, and outputs the comparison result,
8. The bias current setting generation process, wherein the liquid crystal display device outputs the bias current setting signal when the corresponding source output amplitude reference voltage does not match the source output voltage. The bias current adjustment method according to one item.

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