JP2011151668A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device capable of properly correcting defects, corresponding to a reading system of the solid-state imaging device. <P>SOLUTION: The solid-state imaging device includes: a pixel group in which a plurality of pixels are arranged in a two-dimensional matrix, each pixel having a photoelectric conversion unit for generating charges corresponding to a subject image, a memory for storing the charges, a charge transfer unit for transferring the charges to the memory, an amplifier for amplifying the charges of the memory, a selector for output of an amplified signal as a pixel signal, a first resetter for resetting the charges of the memory and a second resetter for resetting the photoelectric conversion unit; a mode setting unit for setting a first mode for sequentially resetting the photoelectric conversion units per line and a second mode for simultaneously resetting all the photoelectric conversion units; a signal reading unit for reading a pixel signal at the set mode; and a defect detecting and correcting unit for correcting defective pixels and correcting the pixel signal. The defect detecting and correcting unit detects defective pixels corresponding to the mode, and corrects the pixel signal on the basis of information of the defective pixels corresponding to the mode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device used for a digital camera or the like.

2. Description of the Related Art MOS (Metal Oxide Semiconductor) type solid-state imaging devices are attracting attention as solid-state imaging devices used in imaging devices that convert light into electrical signals and output image signals, such as digital still cameras. In this MOS type solid-state imaging device, reading is generally performed by a rolling shutter (hereinafter referred to as “RS”) method in which accumulation is performed in units such as pixel rows and columns. In recent years, research has been conducted on a MOS type solid-state imaging device that performs readout by a global shutter (hereinafter referred to as “GS”) system in which all pixels are stored simultaneously. Furthermore, there is a MOS type solid-state imaging device capable of switching between RS readout and GS readout (see Patent Document 1).
In the following description, the term “solid-state imaging device” refers to a MOS type solid-state imaging device.

  FIG. 6 is a block diagram illustrating an example of a schematic configuration of a solid-state imaging device capable of switching between RS readout and GS readout. As shown in FIG. 6, the solid-state imaging device capable of switching between RS readout and GS readout is a photo that performs photoelectric conversion for each unit pixel (unit pixels P11 to P22 in FIG. 6). A diode PD and an in-pixel memory FD that temporarily holds photoelectric conversion signal charges generated in the photodiode PD for a predetermined period are provided. In addition, based on a control signal from the vertical scanning unit 2, a function of resetting the photoelectric conversion signal charge generated in the photodiode PD, and a function of transferring the photoelectric conversion signal charge generated in the photodiode PD to the in-pixel memory FD And a function of resetting photoelectric conversion signal charges temporarily held in the in-pixel memory FD.

  FIG. 7 is a timing chart showing the timing of the read operation in the solid-state imaging device shown in FIG. FIG. 7A schematically shows an example of signal readout timing by the RS method of the solid-state imaging device. FIG. 7B schematically shows an example of signal readout timing by the GS method of the solid-state imaging device. In addition, the horizontal axis of Fig.7 (a) and FIG.7 (b) represents time, and has shown a mode that the several image is taken in continuously.

  First, the RS read operation shown in FIG. 7A will be described. In the RS readout in the solid-state imaging device, first, a rolling reset is performed. In this rolling reset, photoelectric conversion signal charges in the photodiode PD and unnecessary charges such as a leak current generated in the pixel memory FD are sequentially reset while a unit pixel is selected for each row. Thereafter, the reset photodiode PD sequentially starts accumulation (exposure operation) of photoelectric conversion signal charges generated by photoelectrically converting incident light. Then, after a predetermined exposure time has elapsed, rolling transfer is performed. In this rolling transfer, photoelectric conversion signal charges generated during the exposure time of the photodiode PD are sequentially transferred to the intra-pixel memory FD while the unit pixel is selected for each row. Thereafter, pixel signals corresponding to the photoelectric conversion signal charges transferred to the in-pixel memory FD are sequentially read out for each row.

  As described above, in the RS readout operation, as shown in FIG. 7A, the rolling reset, the photodiode PD exposure operation, the rolling transfer, and the pixel signal readout operation are performed for each row of unit pixels. It is done sequentially. That is, in the RS readout operation, the time for which the in-pixel memory FD holds the photoelectric conversion signal charge transferred from the photodiode PD is the same time for all the unit pixels. Further, the photoelectric conversion signal charge holding time by the in-pixel memory FD is a relatively short time. Thereby, in RS readout, an image with less leakage current and optical noise generated when photoelectric conversion signal charges are held in the in-pixel memory FD can be obtained.

  However, in this RS readout operation, since exposure is performed sequentially for each row of unit pixels, images exposed by the photodiode PD at different times for each row are obtained. For this reason, in the RS readout operation, when a fast moving subject is exposed, the resulting image is blurred. For example, as shown in FIG. 7A, the lower pixel row (unit pixels P21 to P22 in FIG. 6) to the upper pixel row (unit pixels P11 to P12 in FIG. 6) of the solid-state imaging device. When the RS method is sequentially read out, a time a has elapsed from the time when the lowermost pixel row is first exposed to the time when the uppermost pixel row is finally exposed. If the subject moves during this time period a, the final image will be blurred.

  As an exposure method that does not cause blurring in a finally obtained image when an object with a fast movement is exposed, there is GS readout. Next, the read operation of the GS method shown in FIG. In the GS readout in the solid-state imaging device, first, a global reset is performed. In this global reset, all unit pixels are selected at the same time, and photoelectric conversion signal charges in each photodiode PD and unnecessary charges such as a leak current generated in each pixel memory FD are simultaneously reset. Thereafter, the reset photodiode PD simultaneously starts accumulating (exposure operation) photoelectric conversion signal charges generated by photoelectrically converting incident light. Then, global transfer is performed after a predetermined exposure time has elapsed. In this global transfer, unit pixels are simultaneously selected, and photoelectric conversion signal charges generated by each photodiode PD during the exposure time are simultaneously transferred to the in-pixel memory FD. Thereafter, pixel signals corresponding to the photoelectric conversion signal charges transferred to the in-pixel memory FD are sequentially read out for each row.

  Thus, in the GS read operation, as shown in FIG. 7B, the global reset, the exposure operation of the photodiode PD, and the global transfer are performed simultaneously in all the unit pixels. Thereafter, the pixel signal reading operation is sequentially performed for each row of the unit pixels. That is, in the GS read operation, exposure by the photodiode PD is performed at the same time, so that an image without blurring can be obtained even when a fast-moving subject is exposed.

  However, in this GS read operation, the in-pixel memory FD cannot be reset until all pixel signals have been read. For this reason, the time for which the in-pixel memory FD holds the photoelectric conversion signal charge transferred from the photodiode PD is longer than that in the RS method. Thereby, when the photoelectric conversion signal charge is held in the in-pixel memory FD, there is a high possibility that the pixel signal is deteriorated due to the influence of the leakage current and optical noise. For example, as shown in FIG. 7B, the lower pixel row (unit pixels P21 to P22 in FIG. 6) to the upper pixel row (unit pixels P11 to P12 in FIG. 6) of the solid-state imaging device. When the pixel signals are sequentially read out, the pixel signal is retained after the pixel signal of the lowermost pixel row is read first until the pixel signal of the uppermost pixel row is finally read. It takes time b. For this reason, the in-pixel memory FD of the uppermost pixel row that is read last needs to hold the photoelectric conversion signal charge during the period of the pixel signal holding time b, which is affected by the influence of leakage current and optical noise. The possibility that the pixel signal is most deteriorated is increased. The lower the luminance of the subject (the darker subject), the more noticeably the deterioration of the pixel signal appears, and the quality of the finally obtained image is lowered.

  Therefore, in the solid-state imaging device, the signal quality of the pixel signal is improved by switching between the RS readout and the GS readout according to the luminance of the subject, and the quality of the finally obtained image is improved. It has improved.

JP 2007-28337 A

  However, the cause of lowering the quality of the finally obtained image is not only due to the deterioration of the pixel signal as described above. As a cause of lowering the quality of an image finally obtained, it is conventionally known that a false signal such as a white point is generated due to characteristics (defects) of the photodiode PD. A technique for correcting a defective pixel having a false signal due to the characteristic (defect) of the photodiode PD is also known.

  However, as described above, in the GS read operation, the time in which the in-pixel memory FD holds the photoelectric conversion signal charge is longer than that in the RS read operation. For this reason, depending on the characteristics (defects) of the in-pixel memory FD, the influence of the leak current generated in the in-pixel memory FD becomes large, and the unit pixel having the in-pixel memory FD having a large leak current has a false signal. There is a problem that it becomes a defective pixel.

  Further, such a false signal due to the characteristic (defect) of the in-pixel memory FD cannot be corrected only by correction corresponding to the characteristic (defect) of the photodiode PD, and the quality of the finally obtained image is low. There is a problem that it falls.

  The present invention has been made based on the above problem recognition, and in a solid-state imaging device capable of switching between RS readout and GS readout, appropriate defect correction corresponding to each readout scheme is performed. An object of the present invention is to provide a solid-state imaging device capable of performing the above.

  In order to solve the above problems, a solid-state imaging device of the present invention temporarily holds a photoelectric conversion unit that generates a photoelectric conversion signal charge corresponding to a subject image, and the photoelectric conversion signal charge generated by the photoelectric conversion unit. The memory unit, a charge transfer unit that transfers the photoelectric conversion signal charge to the memory unit, an amplification unit that outputs an amplification signal corresponding to the amount of charge held in the memory unit, and the amplification unit A pixel having at least a selection unit that outputs the amplified signal as a pixel signal, a first reset unit that resets the charge of the memory unit, and a second reset unit that resets the photoelectric conversion unit is 2 A plurality of pixel groups arranged in a dimensional matrix, a first mode for sequentially resetting the photoelectric conversion units in units of rows of the pixel groups, and a second mode for simultaneously resetting all the photoelectric conversion units of the pixel groups. A mode setting unit for setting a mode, a signal reading unit for reading the pixel signal from the pixel group in the mode set by the mode setting unit, and the pixel signal read from the pixel group by the signal reading unit A defect detection correction unit that detects a defective pixel included in the pixel group and corrects the pixel signal corresponding to the defective pixel based on information on the detected defective pixel, and The defect detection and correction unit detects a first defective pixel based on the pixel signal read from the pixel group in the first mode, and is read from the pixel group in the second mode. A second defective pixel is detected based on the pixel signal, and the pixel signal read from the pixel group in the first mode is corrected based on information on the first defective pixel. The pixel signals the read out from the pixel group in the second mode, is corrected based on the second defective pixel information, characterized in that.

  The defect detection and correction unit of the present invention includes at least a first defect memory that holds information on the first defective pixel, and a second defect memory that holds information on the second defective pixel. And correcting the pixel signal read from the pixel group in the first mode based on the information of the first defective pixel held in the first defective memory, the second mode Sometimes, the pixel signal read from the pixel group is corrected based on the information on the second defective pixel held in the second defective memory.

  Further, the first defective memory of the present invention has a recording capacity smaller than that of the second defective memory.

  In addition, the defect detection and correction unit according to the present invention includes a first defective memory that holds information about the first defective pixel, and information other than the information about the first defective pixel held in the first defective memory. At least a second defective memory that holds information on the second defective pixel, and the pixel signal read from the pixel group in the first mode is held in the first defective memory. The first defective pixel is corrected based on the information on the first defective pixel, and the pixel signal read from the pixel group in the second mode is stored in the first defective memory. And the information of the second defective pixel held in the second defective memory are corrected.

  According to the present invention, in a solid-state imaging device capable of switching between RS-type readout and GS-type readout, information on defective pixels corresponding to each readout method can be recorded, so that appropriate defect correction is performed. The effect that it can be performed is acquired.

It is the block diagram which showed schematic structure of the solid-state imaging device by embodiment of this invention. It is the block diagram which showed schematic structure of the 1st defect detection correction | amendment part in embodiment of this invention. It is the flowchart which showed the process sequence of the 1st defect detection correction | amendment in embodiment of this invention. It is the block diagram which showed schematic structure of the 2nd defect detection correction | amendment part in embodiment of this invention. It is the flowchart which showed the process sequence of the 2nd defect detection correction | amendment in embodiment of this invention. It is the block diagram which showed an example of schematic structure of the conventional solid-state imaging device. It is a timing chart which showed the timing of read-out operation in the conventional solid imaging device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of a solid-state imaging device 100 capable of switching between RS readout and GS readout according to the present embodiment. In FIG. 1, a solid-state imaging device 100 outputs a pixel signal (analog signal) of each unit pixel corresponding to the amount of incident light, and mode setting for switching between an exposure mode and a readout mode of the solid-state imaging element 1. Unit 8, an AD conversion unit 9 that converts a pixel signal (analog signal) of each unit pixel output from solid-state imaging device 1 into a digital signal, and each unit pixel output from AD conversion unit 9 And a defect detection and correction unit 10 for detecting and correcting defective pixels from the digital signal.

  The solid-state imaging device 1 supplies unit pixels P11 to P22 arranged two-dimensionally in a row direction and a column direction (2 rows and 2 columns in FIG. 1) and a drive pulse for driving the unit pixels P11 to P22. Vertical signal lines 3_1 and 3_2 for transmitting signals read from the unit pixels P11 to P22, a constant current source IBIAS for supplying a constant current to the vertical signal lines 3_1 and 3_2, and a vertical signal line 3_1. , 3_2 and column circuits 4_1 and 4_2 for performing signal processing such as suppression of noise components included in signals read from the unit pixels P11 to P22, and signal processing processed by the column circuits 4_1 and 4_2 Column selection pulses φH1 and φH2 are sequentially supplied to column selection switches M6_1 and M6_2 for sequentially outputting subsequent signals to the horizontal signal line 5, and column selection switches M6_1 and M6_2. It comprises a horizontal scanning unit 6 for supplying, and an output amplifier 7 for amplifying signals sequentially output to the horizontal signal line 5 and outputting pixel signals (analog signals) of each unit pixel.

In the solid-state imaging device 1 illustrated in FIG. 1, the numbers following “_: underbar” after each symbol indicate the column numbers of unit pixels arranged in the solid-state imaging device 1. For example, the vertical signal line 3 in the second column to which the unit pixel P12 and the unit pixel P22 in the second column are connected is represented as “vertical signal line 3_2”. When the column number of the unit pixel is not specified, “_: underbar” after each code and the subsequent number are not written.
1 shows an example in which unit pixels are arranged in two rows and two columns, the number of unit pixels arranged in the solid-state imaging device 1 in the row direction and the column direction is the number of pixels of the solid-state imaging device 100. In the following description, when a specific unit pixel is not indicated, it is referred to as “unit pixel P” because it differs depending on the number.

  Each unit pixel P in the solid-state imaging device 1 includes a photodiode PD that performs photoelectric conversion, an in-pixel memory FD that temporarily stores photoelectric conversion signal charges generated in the photodiode PD in a predetermined period, PD reset transistor M5 for resetting photoelectric conversion signal charges generated in the photodiode PD, transfer transistor M4 for transferring photoelectric conversion signal charges from the photodiode PD to the in-pixel memory FD, and FD reset for resetting the in-pixel memory FD The transistor M2, the amplification transistor M1 for amplifying and reading out the voltage level of the in-pixel memory FD, and the row selection transistor M3 for selecting and reading out the output of the amplification transistor M1 to the vertical signal lines 3_1 and 3_2.

  The vertical scanning unit 2 in the solid-state imaging device 1 also includes transfer pulses φTX1 and φTX2, FD reset pulses φRST1 and φRST2, PD reset pulses φFT1 and φFT2, and row selection pulses for driving the unit pixels P11 to P22 in units of rows. φROW1 and φROW2 are output to the unit pixels P11 to P22.

  The AD conversion unit 9 converts the pixel signal (analog signal) of each unit pixel input from the solid-state imaging device 1 into a digital signal, and outputs the digital signal to the defect detection correction unit 10.

  The mode setting unit 8 sets the exposure mode of the solid-state image sensor 1. The mode setting unit 8 is an exposure mode when the solid-state imaging device 100 detects a defective pixel (hereinafter referred to as “defect detection mode”) or an exposure mode when the solid-state imaging device 100 performs normal exposure (hereinafter referred to as “ One of the exposure modes is determined. Then, the mode setting unit 8 outputs information on the determined exposure mode of the solid-state imaging device 100 to the solid-state imaging device 1 and the defect detection and correction unit 10. As a result, the solid-state imaging device 1 performs exposure in the exposure mode input from the mode setting unit 8. For example, when the exposure mode of the solid-state imaging device 100 is set to the defect detection mode, exposure is performed in a state where incident light incident on the solid-state imaging device 100 is shielded. For example, when the exposure mode of the solid-state imaging device 100 is set to the normal exposure mode, the incident light of the subject incident on the solid-state imaging device 100 is exposed.

  The mode setting unit 8 sets the reading mode of the solid-state image sensor 1. The mode setting unit 8 is a reading mode when the solid-state imaging device 100 performs reading in the RS method (hereinafter referred to as “RS mode”) or a reading mode when performing reading in the GS method (hereinafter referred to as “GS mode”). ) Is determined. Then, the mode setting unit 8 outputs information on the read mode of the determined solid-state imaging device 100 to the solid-state imaging device 1 and the defect detection and correction unit 10. Thereby, the solid-state imaging device 1 reads out the pixel signal (analog signal) of each unit pixel exposed in the defect detection mode or the normal exposure mode based on the readout mode information input from the mode setting unit 8, and performs AD conversion. To the unit 9.

  The pixel signal (analog signal) readout method in the solid-state imaging device 1 is the same as that in the conventional solid-state imaging device, but specific readout operations in the RS mode and the GS mode will be described with reference to FIG.

  First, a read operation in the RS mode will be described with reference to FIG. In the RS mode reading in the solid-state imaging device 1, first, a rolling reset for resetting the charge of the photodiode PD is performed. In this rolling reset, the unit pixel P is selected for each row by the row selection pulses φROW1 and 2, and the photoelectric conversion signal charge in the photodiode PD selected by the transfer pulses φTX1 and 2 and the FD reset pulses φRST1 and 2 and Unnecessary charges such as leak current generated in the in-pixel memory FD are sequentially reset. This rolling reset is performed at a predetermined interval prior to the reading operation of the photoelectric conversion signal charge generated by the photodiode PD, and then the photodiode PD whose reset is canceled by the transfer pulses φTX1 and φTX2 is applied to the incident light. Accumulation (exposure operation) of photoelectric conversion signal charges generated by photoelectric conversion is started. In the in-pixel memory FD, the reset for each row is performed by the FD reset pulses φRST1 and φ2 immediately before the photoelectric conversion signal charge generated by the photodiode PD is read. Then, after a predetermined exposure time has elapsed, rolling transfer is performed. In this rolling transfer, photoelectric conversion signal charges generated in the photodiode PD are sequentially transferred to the in-pixel memory FD for each row selected by the transfer pulses φTX1 and φTX2. In the intra-pixel memory FD, the reset is sequentially released for each row selected by the FD reset pulses φRST1 and φ2 immediately before the photoelectric conversion signal charge is transferred from the photodiode PD. Then, the photoelectric conversion signal charge transferred to the in-pixel memory FD is amplified by the amplification transistor M1, and the amplified signal is selected for each row by the row selection pulses φROW1, 2 while being applied to the vertical signal lines 3_1 and 3_2. Read out. Then, the signals read out to the vertical signal lines 3_1 and 3_2 are subjected to analog processing in the column circuits 4_1 and 4_2, respectively, and then sequentially read by the column selection pulses φH1 and 2 from the horizontal scanning unit 6. And output through the output amplifier 7. Thus, in the RS mode readout operation, pixel signals corresponding to the photoelectric conversion signal charges sequentially exposed by the photodiode PD are sequentially read out for each row.

  Subsequently, a read operation in the GS mode will be described with reference to FIG. In the GS mode readout in the solid-state imaging device 1, first, global reset for resetting the charge of the photodiode PD is performed. In this global reset, PD reset transistors M5 and FD reset transistors M2 of all unit pixels P are simultaneously turned ON by PD reset pulses φFT1 and φ2 and FD reset pulses φRST1 and φ2. As a result, the photoelectric conversion signal charges in the photodiode PD and unnecessary charges such as a leak current generated in the in-pixel memory FD are reset simultaneously for all the pixels. Thereafter, the reset of all the photodiodes PD is canceled by the PD reset pulses φFT1, 2 and all the photodiodes PD simultaneously accumulate (exposure operation) photoelectric conversion signal charges generated by photoelectrically converting incident light. Start. In all the in-pixel memories FD, the resetting is performed by the FD reset pulses φRST1 and φ2 just before the photoelectric conversion signal charge generated by the photodiode PD is read out. Then, global transfer is performed after a predetermined exposure time has elapsed. In this global transfer, transfer transistors M4 of all unit pixels P are simultaneously turned on by transfer pulses φTX1 and φTX2. Thereby, the photoelectric conversion signal charge generated in the photodiode PD is simultaneously transferred to the in-pixel memory FD. In all the in-pixel memories FD, the reset is canceled by the FD reset pulses φRST1 and φ2 just before the photoelectric conversion signal charge is transferred from the photodiode PD. Then, the photoelectric conversion signal charge transferred to the in-pixel memory FD is amplified by the amplification transistor M1. Then, by sequentially turning on the row selection transistor M3 for each row by the row selection pulses φROW1 and φROW1, signals amplified by the amplification transistor M1 are sequentially read out to the vertical signal lines 3_1 and 3_2, respectively. Then, the signals read out to the vertical signal lines 3_1 and 3_2 are subjected to analog processing in the column circuits 4_1 and 4_2, respectively, and then sequentially read by the column selection pulses φH1 and 2 from the horizontal scanning unit 6. And output through the output amplifier 7. Thus, in the GS mode readout operation, pixel signals corresponding to the photoelectric conversion signal charges simultaneously exposed by the photodiode PD are sequentially read out row by row.

  The defect detection and correction unit 10 detects whether or not the unit pixel P in the solid-state imaging device 1 is a defective pixel based on the digital signal input from the AD conversion unit 9, and information on the position of the detected defective pixel Is recorded as a defective address. Further, the defect detection and correction unit 10 corrects the digital signal of the defective pixel, for example, by replacing the digital signal of the defective pixel with the digital signal of the adjacent pixel based on the recorded defect address.

<First defect detection correction unit>
Next, the defect detection correction unit in the solid-state imaging device according to the present embodiment will be described. FIG. 2 is a block diagram illustrating a schematic configuration of the defect detection and correction unit 10 in the solid-state imaging device 100 of the present embodiment. In FIG. 2, the defect detection and correction unit 10 includes a defect detection unit 11, a defect correction unit 12, an address memory 13, and an address memory 14.

  The defect detection unit 11 detects defective pixels. Specifically, for example, the defect detection unit 11 detects a digital signal whose digital signal value input from the AD conversion unit 9 is equal to or greater than a predetermined reference value, and outputs the detected digital signal. The unit pixel thus determined is defined as a defective pixel. Then, a defective pixel address which is information on the position of the defective pixel is calculated. Further, the defect detection unit 11 outputs the calculated defective pixel address to the address memory 13 when the read mode determined by the mode setting unit 8 is the RS mode. In addition, when the read mode determined by the mode setting unit 8 is the GS mode, the defect detection unit 11 outputs the calculated defective pixel address to the address memory 14.

  Each of the address memory 13 and the address memory 14 records the defective pixel address input from the defect detection unit 11. The defective pixel address recorded in the address memory 13 is a defective pixel address of a defective pixel detected according to the characteristic (defect) of the photodiode PD. Further, the defective pixel address recorded in the address memory 14 corresponds to the characteristic (defect) of the in-pixel memory FD in addition to the defective pixel address of the defective pixel detected according to the characteristic (defect) of the photodiode PD. This is the defective pixel address of the detected defective pixel. Accordingly, the recording capacity of the address memory 13 is smaller than the recording capacity of the address memory 14.

  The defect correction unit 12 corrects the value of the digital signal input from the AD conversion unit 9. Specifically, when the exposure mode determined by the mode setting unit 8 is the normal exposure mode and the readout mode determined by the mode setting unit 8 is the RS mode, the defect correction unit 12 records the data in the address memory 13. Based on the defective pixel address thus corrected, the value of the digital signal input from the AD conversion unit 9 is corrected, and the corrected digital signal is output as an image signal of the solid-state imaging device 100. In addition, the defect correction unit 12 has a defect recorded in the address memory 14 when the exposure mode determined by the mode setting unit 8 is the normal exposure mode and the read mode determined by the mode setting unit 8 is the GS mode. Based on the pixel address, the value of the digital signal input from the AD converter 9 is corrected, and the corrected digital signal is output as an image signal of the solid-state imaging device 100.

  Next, a processing procedure for defect detection correction in the solid-state imaging device 100 of the present embodiment will be described. FIG. 3 is a flowchart illustrating a processing procedure of the solid-state imaging device 100 including the defect detection correction unit 10.

  When the mode setting unit 8 sets the exposure mode and the readout mode, first, in step S1100, the defect detection / correction unit 10 confirms whether or not the exposure mode determined by the mode setting unit 8 is the defect detection mode. . If the exposure mode is the defect detection mode, the process proceeds to step S1200. If the exposure mode is not the defect detection mode, that is, the normal exposure mode, the process proceeds to step S1300.

  Subsequently, in step S1200, the defect detection correction unit 10 confirms whether or not the read mode determined by the mode setting unit 8 is the RS mode. If the read mode is the RS mode, the process proceeds to step S1210. If the read mode is not the RS mode, that is, the GS mode, the process proceeds to step S1250.

  Subsequently, in step S <b> 1210, the solid-state imaging device 1 performs exposure in the defect detection mode, reads the pixel signal (analog signal) of each exposed unit pixel by the RS method, and outputs it to the AD conversion unit 9.

  Subsequently, in step S1220, the defect detection unit 11 detects a defective pixel based on the digital signal input from the AD conversion unit 9, and calculates a defective pixel address based on information on the position of the detected defective pixel. In step S1230, the defect detection unit 11 records the calculated defective pixel address in the address memory 13 and completes the process.

  In step S1200, when the readout mode determined by the mode setting unit 8 is not the RS mode, in step S1250, the solid-state imaging device 1 performs exposure in the defect detection mode, and the pixel signal (analogue) of each exposed unit pixel. Signal) is read out by the GS method and output to the AD conversion unit 9.

  Subsequently, in step S1260, the defect detection unit 11 detects a defective pixel based on the digital signal input from the AD conversion unit 9, and calculates a defective pixel address based on information on the position of the detected defective pixel. In step S1270, the defect detection unit 11 records the calculated defective pixel address in the address memory 14 and completes the process.

  In step S1100, when the exposure mode determined by the mode setting unit 8 is not the defect detection mode, in step S1300, the defect detection correction unit 10 determines that the read mode determined by the mode setting unit 8 is the RS mode. Check whether or not. If the read mode is the RS mode, the process proceeds to step S1310. If the read mode is not the RS mode, that is, the GS mode, the process proceeds to step S1350.

  Subsequently, in step S1310, the solid-state imaging device 1 performs exposure in the normal exposure mode, reads out the pixel signal (analog signal) of each exposed unit pixel by the RS method, and outputs it to the AD conversion unit 9.

  Subsequently, in step S1320, the defect correction unit 12 corrects the digital signal input from the AD conversion unit 9 based on the defective pixel address recorded in the address memory 13. In step S1400, the defect correction unit 12 outputs the corrected digital signal as an image signal of the solid-state imaging device 100, and the process is completed.

  In step S1300, when the readout mode determined by the mode setting unit 8 is not the RS mode, in step S1350, the solid-state imaging device 1 performs exposure in the normal exposure mode, and the pixel signal (analogue) of each exposed unit pixel. Signal) is read out by the GS method and output to the AD conversion unit 9.

  Subsequently, in step S 1360, the defect correction unit 12 corrects the digital signal input from the AD conversion unit 9 based on the defective pixel address recorded in the address memory 14. In step S1400, the defect correction unit 12 outputs the corrected digital signal as an image signal of the solid-state imaging device 100, and the process is completed.

  As described above, according to the first defect detection and correction unit of the present invention, it is possible to correct a false signal due to characteristics (defects) of the photodiode PD, similarly to the defect correction in the conventional solid-state imaging device. Further, according to the first defect detection and correction unit of the present invention, it is possible to further correct a false signal due to the characteristic (defect) of the in-pixel memory FD. Thereby, the image signal which performed the appropriate defect correction | amendment corresponding to each of reading mode (RS mode and GS mode) of the solid-state imaging device 100 can be output.

<Second defect detection correction unit>
Next, another embodiment of the defect detection and correction unit will be described. FIG. 4 is a block diagram illustrating a schematic configuration of the defect detection correction unit 20 in the solid-state imaging device 100 of the present embodiment. In FIG. 4, the defect detection / correction unit 20 includes a defect detection unit 21, a defect correction unit 22, an address memory 13, an address memory 25, and a defect address comparison unit 26.

  In the present embodiment, the defect detection / correction unit 10 in the solid-state imaging device 100 shown in FIG. 1 is replaced by the defect detection / correction unit 20, but the other components and operations are the same. Description is omitted.

  The defect detection unit 21 detects defective pixels. Specifically, similarly to the defect detection unit 11 shown in FIG. 2, the defect detection unit 21 detects a defective pixel and calculates a defective pixel address of the detected defective pixel. Further, when the read mode determined by the mode setting unit 8 is the RS mode, the defect detection unit 21 outputs the calculated defective pixel address to the address memory 13 in the same manner as the defect detection unit 11 illustrated in FIG. . In addition, when the read mode determined by the mode setting unit 8 is the GS mode, the defect detection unit 21 outputs the calculated defective pixel address to the defect address comparison unit 26.

  The defective address comparison unit 26 compares the defective pixel address input from the defect detection unit 21 with the defective pixel address recorded in the address memory 13, and among the defective pixel addresses input from the defect detection unit 21, A defective pixel address not recorded in the address memory 13 is output to the address memory 25.

  The address memory 13 records the defective pixel address input from the defect detection unit 21 in the same manner as the address memory 13 shown in FIG. The address memory 25 records the defective pixel address input from the defective address comparison unit 26. The defective pixel address recorded in the address memory 13 is a defective pixel address of a defective pixel detected according to the characteristic (defect) of the photodiode PD. The defective pixel address recorded in the address memory 25 is a defective pixel address other than the defective pixel address of the defective pixel detected according to the characteristic (defect) of the photodiode PD. That is, unlike the address memory 14 shown in FIG. 2, the address memory 25 records only defective pixel addresses of defective pixels detected according to the characteristics (defects) of the in-pixel memory FD.

  The defect correction unit 22 corrects the value of the digital signal input from the AD conversion unit 9. Specifically, in the defect correction unit 22, the exposure mode determined by the mode setting unit 8 is the normal exposure mode as in the defect correction unit 12 illustrated in FIG. 2, and the reading determined by the mode setting unit 8 is performed. When the mode is the RS mode, the digital signal value input from the AD conversion unit 9 is corrected based on the defective pixel address recorded in the address memory 13, and the corrected digital signal is used as the image signal of the solid-state imaging device 100. Output as. The defect correction unit 22 is input from the AD conversion unit 9 when the exposure mode determined by the mode setting unit 8 is the normal exposure mode and the reading mode determined by the mode setting unit 8 is the GS mode. The value of the digital signal is corrected based on the defective pixel address recorded in the address memory 13 or the defective pixel address recorded in the address memory 25, and the corrected digital signal is output as an image signal of the solid-state imaging device 100.

  Next, another processing procedure for defect detection and correction in the solid-state imaging device 100 of the present embodiment will be described. FIG. 5 is a flowchart illustrating a processing procedure of the solid-state imaging device 100 including the defect detection correction unit 20.

  When the mode setting unit 8 sets the exposure mode and the reading mode, first, in step S2100, the defect detection correction unit 20 confirms whether or not the exposure mode determined by the mode setting unit 8 is the defect detection mode. . If the exposure mode is the defect detection mode, the process proceeds to step S2200. If the exposure mode is not the defect detection mode, that is, the normal exposure mode, the process proceeds to step S2300.

  Subsequently, in step S2200, the defect detection correction unit 20 checks whether or not the read mode determined by the mode setting unit 8 is the RS mode. If the read mode is the RS mode, the process proceeds to step S2210. If the read mode is not the RS mode, that is, if it is the GS mode, the process proceeds to step S2250.

  Subsequently, in step S2210, the solid-state imaging device 1 reads exposure and pixel signals (analog signals) according to the exposure mode and readout mode determined by the mode setting unit 8 as in step S1210 shown in FIG. And output to the AD conversion unit 9.

  Subsequently, in step S2220 and step S2230, the defect detection unit 21 detects defective pixels and detects defects based on the digital signal input from the AD conversion unit 9, similarly to step S1220 and step S1230 illustrated in FIG. The pixel address is calculated, the defective pixel address is recorded in the address memory 13, and the process is completed.

  If the readout mode determined by the mode setting unit 8 is not the RS mode in step S2200, the solid-state imaging device 1 is determined by the mode setting unit 8 in step S2250 as in step S1250 shown in FIG. The exposure and the readout of the pixel signal (analog signal) according to the exposure mode and the readout mode are performed and output to the AD converter 9.

  Subsequently, in step S2260, similarly to step S1260 shown in FIG. 3, the defect detection unit 21 detects a defective pixel and calculates a defective pixel address based on the digital signal input from the AD conversion unit 9. The defective pixel address is output to the defective address comparator 26.

  Subsequently, in step S <b> 2270, the defective address comparison unit 26 reads the defective pixel address recorded in the address memory 13, and reads the defective pixel address read from the address memory 13 from the defective pixel address input from the defect detection unit 21. And the remaining defective pixel address is recorded in the address memory 25, and the process is completed.

  In step S2100, when the exposure mode determined by the mode setting unit 8 is not the defect detection mode, in step S2300, the defect detection correction unit 20 determines that the read mode determined by the mode setting unit 8 is the RS mode. Check whether or not. If the read mode is the RS mode, the process proceeds to step S2310. If the reading mode is not the RS mode, that is, the GS mode, the process proceeds to step S2350.

  Subsequently, in step S2310, the solid-state imaging device 1 reads exposure and pixel signals (analog signals) according to the exposure mode and readout mode determined by the mode setting unit 8, as in step S1310 illustrated in FIG. And output to the AD conversion unit 9.

  Subsequently, in step S2320, the defect correction unit 22 corrects the digital signal input from the AD conversion unit 9 based on the defective pixel address recorded in the address memory 13, as in step S1320 illustrated in FIG. To do. In step S2400, the defect correction unit 22 outputs the corrected digital signal as an image signal of the solid-state imaging device 100, and the process is completed.

  If the readout mode determined by the mode setting unit 8 is not the RS mode in step S2300, the solid-state imaging device 1 is determined by the mode setting unit 8 in step S2350, similarly to step S1350 shown in FIG. The exposure and the readout of the pixel signal (analog signal) according to the exposure mode and the readout mode are performed and output to the AD converter 9.

  Subsequently, in step S <b> 2360, the defect correction unit 22 corrects the digital signal input from the AD conversion unit 9 based on the defective pixel address recorded in the address memory 13.

  Subsequently, in step S <b> 2370, the defect correction unit 22 corrects the digital signal input from the AD conversion unit 9 based on the defective pixel address recorded in the address memory 25. In step S2400, the defect correction unit 22 outputs the digital signal corrected based on the defective pixel address recorded in the address memory 13 or the address memory 25 as an image signal of the solid-state imaging device 100, and completes the process. .

  As described above, according to the second defect detection and correction unit, similarly to the first defect detection and correction unit, correction of a false signal due to characteristics (defects) of the photodiode PD in the conventional solid-state imaging device, and pixels It is possible to correct a false signal based on the characteristic (defect) of the internal memory FD. Thereby, the image signal which performed the appropriate defect correction | amendment corresponding to each of reading mode (RS mode and GS mode) of the solid-state imaging device 100 can be output.

  In addition, since the address memory 25 in the second defect detection and correction unit records defective pixel addresses other than the defective pixel address recorded in the address memory 13, the address memory 14 in the first defect detection and correction unit is recorded. The recording capacity can be reduced compared to the capacity. Therefore, the recording capacities of the address memory 13 and the address memory 25 can be used efficiently, and a defect detection / correction unit can be configured with a smaller area.

  In the defective pixel detection process in the second defect detection and correction unit, since the defective pixel address detected in the RS mode is excluded from the defective pixel address detected in the GS mode, the defective pixel detection in the RS mode is performed first. After performing, it is desirable to perform defective pixel detection in the GS mode.

  As described above, according to the embodiment for carrying out the present invention, it is possible to correct a digital signal in accordance with the characteristic (defect) of the photodiode PD, similarly to the conventional solid-state imaging device. The digital signal can be corrected according to the characteristics (defects) of the in-pixel memory FD. Thereby, defect correction in switching of the readout mode (RS mode and GS mode) of the solid-state imaging device can be optimally performed corresponding to each readout mode. This also improves the quality of the finally obtained image.

  Note that the defective pixel detection processing of the present embodiment is performed at a timing such as when the digital camera is shipped or when the digital camera is turned on, for example, when the solid-state imaging device 100 of the present invention is mounted on a digital camera. Is desirable. Furthermore, for example, when the temperature of the digital camera or the solid-state imaging device 100 of the present invention is detected and the detected temperature rises above a predetermined temperature, it can be performed periodically based on the temperature rise or the like. is there.

  In the present embodiment, the address memory 13 and the address memory 14 or the address memory 13 and the address memory 25 are described as separate components. However, the address memory 13 and the address memory 14 or the address memory are described. 13 and the address memory 25 may be the same memory, and the recording area in this memory may be different.

  In the present embodiment, the solid-state imaging device 1, the mode setting unit 8, the AD conversion unit 9, and the defect detection / correction unit 10 or the defect detection / correction unit 20 in the solid-state imaging device 100 are configured as separate components. However, it is also possible to make these components into components in the same chip, such as SOC (System On Chip).

  Further, in the present embodiment, an example of two rows and two columns is shown regarding the arrangement of the unit pixels P in the row direction and the column direction, but the arrangement of the unit pixels P in the row direction and the column direction implements the present invention. For example, the number of unit pixels P in the row direction and the column direction can be changed without departing from the spirit of the present invention.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

DESCRIPTION OF SYMBOLS 100 ... Solid-state imaging device 1 ... Solid-state image sensor (pixel group)
2. Vertical scanning unit (signal reading unit)
3_1, 3_2, vertical signal lines 4_1, 4_2, column circuit 5, horizontal signal line 6, horizontal scanning section (signal readout section)
7 ... Output amplifier 8 ... Mode setting unit 9 ... AD conversion unit 10, 20 ... Defect detection correction unit 11, 21 ... Defect detection unit (defect detection correction unit)
12, 22 ... Defect correction unit (defect detection correction unit)
13: Address memory (first defective memory)
14: Address memory (second defective memory)
25 ... Address memory (second defective memory)
26: Defect address comparison unit (defect detection correction unit)
P, P11, P12, P21, P22... Unit pixel (pixel)
PD ・ ・ ・ Photodiode (photoelectric conversion part)
FD: In-pixel memory (memory unit)
M1... Amplification transistor (amplification unit)
M2... FD reset transistor (first reset unit)
M3... Row selection transistor (selection unit)
M4: Transfer transistor (charge transfer unit)
M5 PD reset transistor (second reset unit)
M6_1, M6_2 ... Column selection switch

Claims (4)

A photoelectric conversion unit that generates a photoelectric conversion signal charge corresponding to a subject image, a memory unit that temporarily holds the photoelectric conversion signal charge generated by the photoelectric conversion unit, and the photoelectric conversion signal charge that is transferred to the memory unit A charge transfer unit that performs amplification, an amplification unit that outputs an amplification signal corresponding to the amount of charge held in the memory unit, a selection unit that outputs the amplification signal amplified by the amplification unit as a pixel signal, and the memory unit A pixel group in which a plurality of pixels having at least a first reset unit that resets the electric charge and a second reset unit that resets the photoelectric conversion unit are arranged in a two-dimensional matrix,
A mode setting unit for setting a first mode for sequentially resetting the photoelectric conversion units in units of rows of the pixel group and a second mode for simultaneously resetting all the photoelectric conversion units of the pixel group;
A signal readout unit that reads out the pixel signal from the pixel group in a mode set by the mode setting unit;
Based on the pixel signal read from the pixel group by the signal readout unit, a defective pixel included in the pixel group is detected, and the defective pixel is dealt with based on information on the detected defective pixel. A defect detection correction unit that corrects the pixel signal;
With
The defect detection correction unit is
Detecting a first defective pixel based on the pixel signal read from the pixel group in the first mode;
Detecting a second defective pixel based on the pixel signal read from the pixel group in the second mode;
Correcting the pixel signal read from the pixel group in the first mode based on the information of the first defective pixel;
Correcting the pixel signal read from the pixel group in the second mode based on information on the second defective pixel;
A solid-state imaging device. The defect detection correction unit is
A first defective memory for holding information on the first defective pixel;
A second defective memory for holding information on the second defective pixel;
Comprising at least
Correcting the pixel signal read from the pixel group in the first mode based on the information of the first defective pixel held in the first defective memory;
Correcting the pixel signal read from the pixel group in the second mode based on information of the second defective pixel held in the second defective memory;
The solid-state imaging device according to claim 1. The first defective memory is
Less recording capacity than the second defective memory,
The solid-state imaging device according to claim 2. The defect detection correction unit is
A first defective memory for holding information on the first defective pixel;
A second defective memory for holding information on the second defective pixel other than the information on the first defective pixel held in the first defective memory;
Comprising at least
Correcting the pixel signal read from the pixel group in the first mode based on the information of the first defective pixel held in the first defective memory;
The pixel signal read from the pixel group in the second mode is used as information on the first defective pixel held in the first defective memory and the information held in the second defective memory. Correcting based on the information of the second defective pixel,
The solid-state imaging device according to claim 1.

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