JP2011151518A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To greatly reduce power supply noise such as power supply resonance noise by using a parasitic capacitance in a logical circuit block in a sleep state. <P>SOLUTION: A power supply noise measurement circuit 9 monitors a power supply voltage VDD, and outputs a control signal CON when the power supply voltage VDD becomes an arbitrary reference voltage or more, and a switch controller 8 discharges charge accumulated in a virtual reference potential VSSA, lowers/raises the reference potential VSSA and the potential of the power supply voltage VDD by controlling the switch 6 so as to accumulate charge in the virtual reference potential VSSA to cancel power supply resonance noise of the power supply voltage VDD when an arbitrary period later passes. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for reducing power supply noise in a semiconductor integrated circuit device, and in particular, a technique effective for reducing power supply noise in a semiconductor integrated circuit device in which the voltage level of a power supply voltage is arbitrarily varied by DVS (Dynamic Voltage Scaling) or the like. About.

  In recent years, in semiconductor integrated circuit devices typified by system LSIs used for mobile devices and the like, the demand for low power consumption has become very strong. For example, DVS is known as a technique for reducing the power consumption of this type of semiconductor integrated circuit device.

  DVS is a technique for dynamically changing the voltage of a circuit block such as a processor according to the processing capability requirement of the circuit block.

  In addition, as a noise reduction technique in this type of semiconductor integrated circuit device, for example, active decoupling (for example, see Non-Patent Document 1) using static capacitance and a mirror capacitance by negative feedback of an operational amplifier for noise reduction is used. A decoupling technique using a capacitance (for example, see Non-Patent Document 2) is known.

Jie Gu; Harjani, R .; Kim, CH, “Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 17, Issue 2, Feb. 2009, PP. 292-301. Xiongfei Meng; Saleh, R., “An Improved Active Decoupling Capacitor for“ Hot-Spot ”Supply Noise Reduction in ASIC Designs”, IEEE Journal of Solid-State Circuits (JSSC), Volume 44, Issue 2, PP. 584-593 .

  However, the present inventors have found that there are the following problems in the technique for varying the power supply voltage in the semiconductor integrated circuit device using DVS as described above.

  That is, when the power supply voltage supplied to an arbitrary circuit block is changed by DVS, or when the circuit block is changed from a sleep (pause) state to an active (operation) state, the period of the power supply voltage is set. Power supply resonance noise is generated, which not only affects the operation of the circuit block, but in some cases, the device may be destroyed.

  Further, even when the circuit block operates from the sleep state, noise of the power supply voltage due to a sudden change in current occurs, which adversely affects the operation of the circuit block.

  An object of the present invention is to provide a technique capable of significantly reducing noise generated in a power supply voltage such as power supply resonance noise by using a parasitic capacitance in a logic circuit block in a sleep state.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention includes a first power supply line to which a power supply voltage is supplied, a second power supply line to which a power supply voltage having a voltage level lower than the power supply voltage supplied to the first power supply line is supplied, Low power consumption is connected between a third power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the second power supply line is supplied, and between the first power supply line and the second power supply line. A logic circuit block to be controlled, a switch unit connected between the second power supply line and the third power supply line, and performing low power consumption control of the logic circuit block based on a switch control signal; A power supply noise measuring unit that monitors a voltage level of a power supply voltage supplied to one power supply line and outputs a control signal according to a change in the voltage level of the power supply voltage supplied to the first power supply line; Control signal output from measurement unit and operation of logic circuit block And a switch controller that outputs a switch control signal to the switch unit based on the status signal indicating the status, and the power source noise measuring unit includes power source noise such as power source resonance noise in the power source voltage supplied to the first power source line. When an undesired power fluctuation occurs, a control signal is output, and the switch controller is connected to an arbitrary logic circuit block that is in a sleep state according to the control signal output from the power supply noise measurement unit. The switch unit is operated to suppress power supply noise such as power supply resonance noise and undesired potential fluctuations by using a parasitic capacitance parasitic to the logic circuit block in the sleep state.

  The present invention also includes a first power supply line to which a power supply voltage is supplied, a second power supply line to which a power supply voltage having a voltage level lower than the power supply voltage supplied to the first power supply line is supplied, A third power supply line to which a power supply voltage having a lower voltage level than the power supply voltage supplied to the second power supply line is supplied, and connected between the second power supply line and the third power supply line, A logic circuit block subject to power consumption control, and a switch unit connected between the first power supply line and the second power supply line and performing low power consumption control of the logic circuit block based on a switch control signal; A power supply noise measuring unit that monitors a voltage level of a power supply voltage supplied to the first power supply line and outputs a control signal according to a change in the voltage level of the power supply voltage supplied to the first power supply line; Control signal and logic circuit block output from power supply noise measurement unit A switch controller that outputs a switch control signal to the switch unit based on a state signal indicating an operation state, and the power source noise measuring unit supplies power source noise such as power source resonance noise to the power source voltage supplied to the first power source line. When an undesired potential fluctuation occurs, a control signal is output, and the switch controller is connected to an arbitrary logic circuit block that is in a sleep state according to the control signal output from the power supply noise measurement unit. The power supply noise such as power supply resonance noise and undesired potential fluctuations are suppressed by utilizing the parasitic capacitance parasitic to the logic circuit block in the sleep state.

  Furthermore, the present invention provides a first power supply line to which a power supply voltage is supplied, a second power supply line to which a power supply voltage having a voltage level lower than the power supply voltage supplied to the first power supply line is supplied, A third power supply line to which a power supply voltage having a lower voltage level than the power supply voltage supplied to the second power supply line is supplied; and a second power supply higher than the power supply voltage supplied to the third power supply line. A power supply voltage lower than the power supply voltage supplied to the line is connected between the fourth power supply line and the first power supply line and the second power supply line, and based on the switch control signal The low power consumption of the logic circuit block is connected between the first switch unit for performing low power consumption control of the logic circuit block and the fourth power supply line and the third power supply line, and based on the switch control signal. A second switch unit that performs control, and between the second power line and the fourth power line A power supply that monitors the voltage level of the power supply voltage connected to the logic circuit block that is subject to low power consumption control and the first power supply line, and outputs a control signal according to the fluctuation of the voltage level of the power supply voltage Based on the noise measurement unit, the control signal output from the power supply noise measurement unit, and the status signal indicating the operation state of the logic circuit block, the control signal is output to the first switch unit or the second switch unit. A power supply noise measuring unit that outputs a control signal when power supply noise such as power supply resonance noise or undesired potential fluctuation occurs in the power supply voltage supplied to the first power supply line, In response to a control signal output from the power supply noise measurement unit, the controller switches the first switch unit or the second switch unit in any logic circuit block that has entered the sleep state. Part is operated, in which by utilizing the parasitic capacitance of the logic circuit block that is to be a sleep state to suppress power supply noise and undesired potential variation such as the power supply resonance noise.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the power supply noise measuring unit compares the power supply voltage supplied to the first power supply line with the threshold voltage, and when the power supply voltage becomes lower than the threshold voltage, or the power supply voltage is reduced. When the voltage becomes higher than the threshold voltage, the switch controller outputs a control signal. In the switch controller, the power supply noise measurement unit causes the power supply voltage supplied to the first power supply line to be higher than the first threshold voltage. When the control signal output is received, the electric charge accumulated in the second power supply line is released to the third power supply line, and the power supply noise measurement unit determines that the power supply voltage supplied to the first power supply line is the first power supply voltage. When the control signal output when the threshold voltage is lower than 1 is received, the sleep state logic circuit block releases the charge accumulated in the third power supply line to the second power supply line. The switch unit to be connected is controlled.

  Further, according to the present invention, the logic of the sleep state is set so that the switch controller accumulates the charge in the second power supply line after an arbitrary period of time has elapsed since the charge accumulated in the second power supply line has been discharged. The switch unit to which the circuit block is connected is controlled.

  Further, according to the present invention, the power supply noise measurement unit compares the power supply voltage supplied to the first power supply line with a threshold voltage, and when the power supply voltage becomes lower than the threshold voltage, or the power supply voltage When the voltage becomes higher than the threshold voltage, the switch controller outputs a control signal, and the switch controller determines that the power supply noise measuring unit has a power supply voltage supplied to the first power supply line higher than the threshold voltage. When the control signal output at that time is received, the electric charge accumulated in the second power supply line is released, and the power supply noise measurement unit causes the power supply voltage supplied to the first power supply line to be lower than the threshold voltage. When the control signal output is received, the first switch unit to which the logic circuit block in the sleep state is connected is controlled so as to discharge the charge accumulated in the third power supply line to the second power supply line. The charge accumulated in the fourth power supply line is released. As to, and it controls the second switch unit logic circuit block sleep state is connected.

  In addition, according to the present invention, when an arbitrary period of time elapses after the switch controller releases the charges accumulated in the second power supply line and the fourth power supply line, the second power supply line and the fourth power supply line The first switch and the second switch connected to the logic circuit block in the sleep state are each controlled so as to accumulate electric charge in the power supply line.

  Furthermore, the present invention compares the count value output from the counter with the timing information stored in the register unit, and when the count value of the counter matches the timing information of the register unit, the first and second And a switch control unit that outputs a switch control signal for turning on or off the switch unit.

  In the present invention, the switch controller operates the switch unit so as to vary the number of logic circuit blocks in the sleep state to be used according to the operation state of the logic circuit block in the active state.

  Further, according to the present invention, the switch controller varies the on-conduction strength of the switch unit in the logic circuit block in the sleep state to be used according to the operation state of the logic circuit block in the active state.

  In the present invention, each of the switch units includes a switch, and the switch controller controls the number of switches to be operated in accordance with the operation state of the active logic circuit block. is there. The switch unit may be composed of a single switch.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) By using the parasitic resistance in the logic circuit block in the sleep state, power supply noise such as power supply resonance noise and undesired potential fluctuations can be greatly reduced with a simple circuit configuration.

  (2) According to the above (1), an increase in the chip area can be suppressed and the reliability of the semiconductor integrated circuit device can be improved.

1 is a block diagram showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 3 is an explanatory diagram of a power resonance noise suppression operation by a power noise suppression unit provided in the semiconductor integrated circuit device of FIG. 1. FIG. 3 is an explanatory diagram following FIG. 2. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. It is explanatory drawing following FIG. FIG. 2 is a block diagram illustrating an example of a power supply noise measurement circuit provided in the semiconductor integrated circuit device of FIG. 1. FIG. 2 is a block diagram illustrating an example of a switch controller provided in the semiconductor integrated circuit device of FIG. 1. 10 is a timing chart showing an example of a switch control signal generation technique by the switch controller of FIG. 9. 2 is a timing chart showing an example of detailed operations in a switch controller and a power supply noise measurement circuit provided in the semiconductor integrated circuit device of FIG. 1. It is a simulation figure which shows an example of the power supply voltage waveform by power supply resonance noise cancellation at the time of changing the power supply voltage VDD from about 1.8V to about 1.4V by DVS. It is a simulation figure which shows an example of the power supply voltage waveform by the power supply resonance noise cancellation at the time of changing the power supply voltage VDD from about 1.4V to about 1.8V by DVS. FIG. 5 is a simulation diagram illustrating an example of a power supply voltage waveform when a logic circuit block transitions from a sleep state to an active state without changing the power supply voltage VDD. It is a block diagram which shows an example of a structure of the semiconductor integrated circuit device by Embodiment 2 of this invention. It is a block diagram which shows the other example of a structure of the semiconductor integrated circuit device by Embodiment 2 of this invention. It is a block diagram which shows an example of a structure of the semiconductor integrated circuit device by Embodiment 3 of this invention. It is a block diagram which shows the other example of a structure of the semiconductor integrated circuit device by Embodiment 3 of this invention. It is a block diagram which shows the further another example of a structure of the semiconductor integrated circuit device by Embodiment 3 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of a semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG. 2 shows an operation of suppressing power supply resonance noise by a power supply noise suppression unit provided in the semiconductor integrated circuit device of FIG. FIG. 3 is an explanatory diagram following FIG. 2, FIG. 4 is an explanatory diagram following FIG. 3, FIG. 5 is an explanatory diagram following FIG. 4, FIG. 6 is an explanatory diagram following FIG. 6 is an explanatory diagram subsequent to FIG. 6, FIG. 8 is a block diagram showing an example of a power supply noise measuring circuit provided in the semiconductor integrated circuit device of FIG. 1, and FIG. 9 is provided in the semiconductor integrated circuit device of FIG. FIG. 10 is a block diagram showing an example of a switch controller, FIG. 10 is a timing chart showing an example of a switch control signal generation technique by the switch controller of FIG. 9, and FIG. 11 is a switch controller provided in the semiconductor integrated circuit device of FIG. , And power noise measurement FIG. 12 is a timing chart showing an example of detailed operation in the circuit. FIG. 12 is a simulation showing an example of a power supply voltage waveform due to power supply resonance noise cancellation when the power supply voltage VDD is changed from about 1.8 V to about 1.4 V by DVS. FIGS. 13A and 13B are simulation diagrams showing examples of power supply voltage waveforms due to power supply resonance noise cancellation when the power supply voltage VDD is changed from about 1.4V to about 1.8V by DVS, and FIG. 14 shows the power supply voltage VDD. FIG. 6 is a simulation diagram illustrating an example of a power supply voltage waveform when a logic circuit block transitions from a sleep state to an active state without being changed.

  In the first embodiment, the semiconductor integrated circuit device 1 is provided with logic circuit blocks 2 to 5 as shown in FIG. The semiconductor integrated circuit device 1 is not particularly limited, but is formed on a semiconductor substrate such as silicon by a known CMOS (Complementary Metal Oxide Semiconductor) manufacturing process.

  The logic circuit blocks 2 to 5 include a central processing unit (CPU) constituted by a plurality of CMOS logic circuits, an image processing circuit constituted by a plurality of CMOS logic circuits, and a data transfer circuit constituted by a plurality of CMOS logic circuits. Direct memory access controller (DMAC), system control circuit such as interrupt control circuit, voice processing circuit composed of multiple CMOS logic circuits, interrupt control circuit composed of multiple CMOS logic circuits, multiple memory cells And a built-in memory circuit including a memory cell array including a memory peripheral circuit (for example, an address decoder) composed of a plurality of CMOS circuits. The memory circuit is a volatile memory such as a static random access memory (SRAM) or a non-volatile memory such as a flash memory. Depending on the design concept of the semiconductor integrated circuit device 1, the logic circuit blocks 2 to 5 may correspond to the central processing unit (CPU), the image processing circuit, the sound processing circuit, the system control circuit, and the built-in memory circuit. Can be considered.

  The logic circuit blocks 2 to 5 are supplied with a power supply voltage VDD that is dynamically changed by DVS (Dynamic Voltage Scaling) via a power supply wiring (first power supply line) VDDL.

  The logic circuit blocks 2 and 3 are connected to switch units 6 and 7 which are provided to reduce power consumption and are used to shut off the power supply.

  That is, the switch units 6 and 7 are used as a function for shutting off the power supply of the logic circuit blocks 2 and 3. However, in the present invention, the switch units 6 and 7 further have power supply noise such as power supply resonance noise and noise. It is also used to avoid a desired potential fluctuation.

  The switch unit 6 is connected between the logic circuit block 2 and a power supply wiring (third power supply line) supplied with a power supply voltage having a voltage level lower than the power supply voltage VDD or a reference potential VSS as a reference potential. The switch unit 7 is connected between the logic circuit block 3 and the power supply wiring (third power supply line) to which the reference potential VSS is supplied. A power supply wiring (second power supply line) VSSL1 that is set to the virtual reference potential VSSA is provided between the logic circuit block 2 and the switch unit 6.

  Similarly, between the logic circuit block 3 and the switch unit 7, a power supply wiring (second power supply line) VSSL <b> 2 that is set to the virtual reference potential VSSA is provided. The potential of the virtual reference potential VSSA is lower than the power supply voltage VDD and higher than the reference potential VSS. Therefore, the potential relationship is VDD> VSSA> VSS.

  A switch controller 8 is connected to each of the switch units 6 and 7, and a power supply noise measurement circuit 9 serving as a power supply noise measurement unit is connected to the switch controller 8. The power supply noise measurement circuit 9 measures the noise of the power supply voltage VDD, and outputs a control signal CON to the switch controller 8 when the measurement result reaches an arbitrary level. The switch controller 8 receives the control signal CON output from the power supply noise measurement circuit 9 or the state signal JS indicating the operation state of each logic circuit block 2 to 5 externally input, and outputs the switch control signal SWC. ON / OFF control of the switch units 6 and 7 is performed.

  That is, the switch controller 8 includes a first control circuit for controlling the sleep state (rest state) and the active state (activation state, operation state) of the logic circuit block 2 and the logic circuit block 3, and the present invention. It is considered to include a related second control circuit (configuration of FIG. 9 described later).

  The switch unit 6 includes semiconductor elements, for example, transistors 10 and 11 made of N-channel MOS (Metal Oxide Semiconductor). The logic circuit block 2 is connected to one connection portion of the transistors 10 and 11, and the reference potential VSS is connected to the other connection portion of the transistors 10 and 11.

  Further, the gates of the transistors 10 and 11 are respectively connected so that the switch control signal SWC output from the switch controller 8 is input. Here, the gate size (gate width) of the transistor 10 is formed to be larger than the gate size (gate width) of the transistor 11.

  Further, the switch unit 7 is composed of semiconductor elements, for example, transistors 12 and 13 made of an N-channel MOS, and the connection configuration is the same as that of the switch unit 6, and thus the description thereof is omitted.

  The switch units 6 and 7, the switch controller 8, and the power supply noise measurement circuit 9 constitute a power supply noise suppression unit. The power supply noise suppression unit is a resonance frequency band (for example, about 50 MHz to 200 MHz) of the inductance and capacitance of the power supply line due to a change in voltage due to DVS or a sudden change in power supply voltage / current due to ON / OFF of the switch units 6 and 7. The parasitic capacitances parasitic on the plurality of CMOS circuits constituting the logic circuit block in the sleep state (that is, each of the N channel MOS transistor and the P channel MOS transistor constituting the CMOS circuit, etc.) This is suppressed using the parasitic capacitance of the MOS transistor.

  Next, suppression of power supply resonance noise by the power supply noise suppression unit provided in the semiconductor integrated circuit device 1 according to the present embodiment will be described with reference to FIGS.

  2 to 7, the right side of the dotted line indicates the inside of the semiconductor integrated circuit device 1, and the left side of the dotted line indicates the outside of the semiconductor integrated circuit device 1. 2 to 7, the logic circuit block 2 is in the sleep state, the logic circuit block 3 is in the active state (the transistor 12 is ON), and the power supply voltage VDD supplied to the logic circuit block 3 is shown. However, it changes from about 1.6V to about 1.8V by DVS, for example.

  First, in FIG. 2, the switch controller 8 outputs a switch control signal SWC so as to turn on the transistor 11 of the switch unit 6 before the power supply voltage VDD changes from about 1.6V to about 1.8V.

  When the transistor 11 is turned ON, a coupling point (hereinafter referred to as a virtual reference potential VSSA) between the logic circuit block 2 and the switch unit 6 rising to the power supply voltage VDD due to coupling due to the parasitic capacitance of the logic circuit block 2. The voltage level is set to the same level as the reference potential VSS. The parasitic capacitance is constituted by a plurality of CMOS logic circuits included in the logic circuit block 2 and is regarded as a parasitic capacitance.

  The reason why the charge is extracted by the transistor 11 having a small transistor size (gate width) is to minimize the influence on the reference potential VSS and the power supply voltage VDD. Subsequently, the switch controller 8 performs control to turn off the transistor 11 (just before the power supply voltage VDD changes due to DVS), and sets the virtual reference potential VSSA to a floating state.

  Thereafter, as shown in FIG. 3, when DVS is executed and the power supply voltage VDD changes from about 1.6V to about 1.8V, power supply noise is generated accordingly. The noise waveform of the power supply voltage VDD due to the power supply noise (the waveform shown in the upper part of FIG. 3) and the noise waveform of the reference potential VSS (the waveform shown in the lower part of FIG. 3) are in opposite phases, and the noise waveform in the virtual reference potential VSSA ( The waveform shown in the lower part of FIG. 3 has the same phase as the noise waveform of the power supply voltage VDD because of the floating state, and a potential difference is generated between the reference potential VSS and the virtual reference potential VSSA.

  Subsequently, in FIG. 4, when the power supply voltage VDD becomes an arbitrary voltage level higher than about 1.8 V due to power supply resonance noise, the power supply noise measurement circuit 9 outputs the control signal CON and receives the control signal CON. Thus, the switch controller 8 outputs the switch control signal SWC so as to turn on the transistor 10.

  Accordingly, when the transistor 10 is turned on, the virtual reference potential VSSA and the reference potential VSS are short-circuited, and the virtual reference potential VSSA is higher than the reference potential VSS. Therefore, the virtual reference potential VSSA is changed from the reference potential VSS. Current flows through

  As a result, the potential of the reference potential VSS increases and the potential of the power supply voltage VDD decreases, and noise of the power supply voltage VDD is reduced. The switch controller 8 controls the transistor 10 to be turned off again after turning on the transistor 10 for an arbitrary period, and sets the virtual reference potential VSSA to a floating state.

  As a result, the voltage waveform of the virtual reference potential VSSA has the same phase as that of the power supply voltage VDD, and a potential difference is generated between the virtual reference potential VSSA and the reference potential VSS.

  In FIG. 5, the switch controller 8 performs control to turn on the transistor 10 to short-circuit the virtual reference potential VSSA and the reference potential VSS. When the transistor 10 is turned on, the potential of the reference potential VSS is higher than the potential of the virtual reference potential VSSA. Therefore, a current flows from the reference potential VSS to the virtual reference potential VSSA, and the virtual reference potential VSSA is replenished. The charge accumulated in the parasitic capacitance parasitic on the block 2 is lifted.

  As a result, as shown in FIG. 7, the potential of the reference potential VSS is lowered, the potential of the power supply voltage VDD is raised, and noise of the power supply voltage VDD is reduced. After that, again, the transistor 10 is controlled to be turned off, and the virtual reference potential VSSA is brought into a floating state.

  The above processing is repeatedly executed until the power supply noise is substantially eliminated. When the power supply noise is substantially eliminated, the switch controller 8 in FIG. 6 performs control so that both the transistors 10 and 11 of the switch unit 6 are turned off.

  When the transistors 10 and 11 are turned off, the virtual reference potential VSSA rises again to the voltage level of the power supply voltage VDD. Thereby, since the logic circuit block 2 is cut off from the power supply line, the power consumption can be further reduced.

  FIG. 8 is a block diagram showing an example of the power supply noise measurement circuit 9.

  The power supply noise measurement circuit 9 includes a comparator (comparison circuit) 14, a delay unit (delay circuit unit) 15, and an exclusive OR circuit 16 as shown in the figure. One input portion of the comparator 14 is connected so that the power supply voltage VDD is inputted, and the other input portion of the comparator 14 is connected so that the reference voltage VREF is inputted.

  The output unit of the comparator 14 is connected to the input unit of the delay unit 15 and one input unit of the exclusive OR circuit 16. The other input unit of the exclusive OR circuit 16 is connected to the output unit of the delay unit 15.

  The delay unit 15 has, for example, a configuration in which a plurality of inverters are connected in series. The comparator 14 compares the power supply voltage VDD and the reference voltage VREF, and outputs a comparison result signal.

  The comparison result signal output from the comparator 14 becomes a one-shot pulse by the delay unit 15 and the exclusive OR circuit 16, and is output from the exclusive OR circuit 16 as the control signal CON.

  FIG. 9 is a block diagram showing an example of the switch controller 8, that is, the second control circuit related to the present invention.

  The switch controller 8 includes a counter 17, a match-on circuit 18, a match-off circuit 19, a flip-flop 20, registers 21, 22, selectors 23 and 24, a stop counter 25, and a switch 26, as shown in the figure. The switch controller 8 includes the match-on circuit 18, the match-off circuit 19, and the flip-flop 20 in the switch controller 8.

  The counter 17 is connected so that the clock signal CLK and the control signal CON output from the power supply noise measurement circuit 9 are input. Further, an input part of the stop counter 25, one input part of the match-on circuit 18, and one input part of the match-off circuit 19 are connected to the output part of the counter 17.

  The register 21 is connected to the other input of the match-on circuit 18, and the register 22 is connected to the other input of the match-off circuit 19. One connection portion of the switch 26 is connected to the output portion of the match-on circuit 18, and the set terminal of the flip-flop 20 is connected to the other connection portion of the switch 26.

  The switch 26 is controlled to be turned on / off based on a signal output from the stop counter 25. The reset terminal of the flip-flop 20 is connected to the output part of the match-off circuit 19, and the input part of the selector 24 is connected to the output terminal of the flip-flop 20. In addition, a state signal JS indicating an operation state of each of the logic circuit blocks 2 to 5 is connected to an input portion of the selector 23.

  The state signal JS is also connected to be input to the control terminals of the selectors 23 and 24. The selectors 23 and 24 are connected to the logic of the sleep state by the state signal JS indicating the operation state of the logic circuit block. The connection destination is switched so as to select the switch portion of the circuit block.

  When the control signal CON of the power supply noise measurement circuit 9 is input, the counter 17 starts counting the clock signal CLK. In the register 21, the switch unit (the switch unit 6 in FIGS. 2 to 7) connected to the logic circuit block in the sleep state using the parasitic capacitance (the logic circuit block 2 in FIGS. 2 to 7) is ON-controlled. Stores timing information.

  In the register 22, the switch unit (the switch unit 6 in FIGS. 2 to 7) connected to the logic circuit block in the sleep state using the parasitic capacitance (the logic circuit block 2 in FIGS. 2 to 7) is OFF-controlled. Stores timing information.

  The match-on circuit 18 compares the timing information in the register 21 with the count value (for example, 5 bits) output from the counter 17 and outputs a signal when the count value reaches an arbitrary value. The match-off circuit 9 compares the timing information in the register 22 with the count value output from the counter 17 and outputs a signal when the count value reaches an arbitrary value.

  The flip-flop 20 outputs a switch control signal SWC based on signals output from the match-on circuit 18 and the match-off circuit 9. Based on the cancel block selection signal, the selector 23 selects the switch unit connected to the logic circuit block in the sleep state that uses the parasitic capacitance, and outputs the state signal JS as the switch control signal SWC.

  The selector 24 selects a switch unit connected to the logic circuit block in the sleep state using the parasitic capacitance based on the cancel block selection signal, and the signal output from the flip-flop 20 is used as the switch control signal SWC. Output.

  FIG. 10 is a timing chart showing an example of a technique for generating the switch control signal SWC by the switch controller 8.

  10, the voltage waveforms of the power supply voltage VDD and the reference voltage VREF, the counter value of the counter 17, and the timing information stored in the registers 21 and 22 are shown from the top to the bottom. In the power supply voltage VDD of FIG. 10, the waveform indicated by the dotted line indicates the power supply resonance noise, and the waveform indicated by the solid line indicates a case where the power supply resonance noise is suppressed by the power supply noise suppression unit.

  First, when the voltage level of the power supply voltage VDD exceeds the reference voltage VREF, the control signal CON is output from the power supply noise measurement circuit 9 and the counter 17 starts counting. Here, the transistor 10 is set to be turned on when the timing information of the register 21 reaches the count value “00010”, and the timing information of the register 21 is set to the count value “00111”. The transistor 10 is set to be OFF.

  Therefore, the match-on circuit 18 outputs a signal for turning on the transistor 10 every time the count value counted by the counter 17 becomes “00010”. The match-on circuit 18 outputs a signal for turning off the transistor 10 every time the count value becomes “00010”.

  Therefore, the match-on circuit 18 outputs a signal for turning on the transistor 10 every time the count value counted by the counter 17 becomes “00010”, and the match-on circuit 18 turns off the transistor 10 every time the count value becomes “00010”. Output a signal.

  Subsequently, when the voltage level of the power supply voltage VDD becomes lower than the reference voltage VREF, the control signal CON is output from the power supply noise measurement circuit 9 again, the counter 17 is reset, and then the counter 17 starts counting again. .

  Again, the match-on circuit 18 outputs a signal for turning on the transistor 10 every time the count value counted by the counter 17 reaches “00010”, and the match-on circuit 18 turns on the transistor 10 every time the count value becomes “00010”. Outputs a signal to turn off.

  As described above, by storing the timing information in the registers 21 and 22, the ON / OFF timing of the transistor 10 optimal for noise suppression can be set for each period of the power supply resonance noise.

  FIG. 11 is a timing chart showing an example of detailed operations in the switch controller 8 and the power supply noise measurement circuit 9.

  In FIG. 11, from the upper side to the lower side, voltage waveforms of the power supply voltage VDD and the reference voltage VREF, a status signal JS indicating each operation state of the logic circuit blocks 2 to 5, an output signal of a comparison result output from the comparator 14, and a power supply The control signal CON output from the noise measurement circuit 9, the count output values COUT0 to COUT4 output from the counter 17, the input signals input to the set terminal and the reset terminal of the flip-flop 20 (the signals input to the set terminal are The signal timing is indicated by a solid line, the signal input to the reset terminal is indicated by a dotted line), and the signal timing of the switch control signal SWC output from the flip-flop 20. Here, as in FIG. 2, the logic circuit block 2 is in the sleep state and the logic circuit block 3 is in the active state, and the logic circuit block 3 has a power supply voltage VDD of about 1.6V to 1.8V. The noise canceling operation when changing to the extent will be described.

  First, the state signal JS input from the outside before the power supply voltage VDD changes from about 1.6 V to about 1.8 V is output to the transistor 11 of the switch unit 6 via the switch controller 8. As a result, the transistor 11 is turned on, and the voltage level of the virtual reference potential VSSA is set to the same level as the reference potential VSS.

  Thereafter, when the power supply voltage VDD changes from about 1.6 V to about 1.8 V and power supply resonance noise occurs, when the power supply voltage VDD becomes larger than the reference voltage VREF, the comparator 14 of the power supply noise measurement circuit 9 The Hi signal is output.

  This signal generates a one-shot pulse by the delay unit 15 of the power supply noise measurement circuit 9 and the exclusive OR circuit 16 and outputs it as a control signal CON. The counter 17 is reset by the control signal CON, and the counter 17 starts counting the clock signal CLK after setting the counter outputs COUT4 to COUT0 to '000001'.

  The match-on circuit 18 compares the count value output from the counter 17 with the timing information ('00010') stored in the register 21 and outputs a signal to the set terminal of the flip-flop 20 when they match.

  Similarly, the match-off circuit 19 compares the count value output from the counter 17 with the timing information ('00111') stored in the register 22, and outputs a signal to the reset terminal of the flip-flop 20 when they match. Output.

  The flip-flop 20 outputs a switch control signal SWC for turning on the transistor 10 when the signal input to the set terminal is “Hi (1)” and the signal input to the reset terminal is “Lo (0)”. When the signal input to the set terminal is “Lo (0)” and the signal input to the reset terminal is “Hi (1)”, the switch control signal SWC for turning off the transistor 10 is output. Further, when the signal input to the set terminal and the signal input to the reset terminal are 'Lo (0)', the previous state is maintained.

  When the power supply resonance noise is canceled, the power supply noise measurement circuit 9 does not generate the control signal CON that performs counter reset. As a result, when the counter 17 is not reset and the count output values COUT4 to COUT0 become '1111', the set terminal of the flip-flop 20 is set to 'Lo () until the next time the control signal CON is output from the power supply noise measurement circuit 9. 0) '.

  Also, to control the amount of cancellation of power supply resonance noise, change the number of logic circuit blocks in sleep state, the number of transistors used in the switch section, or the gate voltage supplied to the transistors used in the switch section. Can be adjusted.

  12 to 14 are simulation diagrams illustrating an example of power supply resonance noise cancellation when the power supply noise suppression unit of the first embodiment is applied.

  First, FIG. 12 shows a case where the power supply voltage VDD in the active logic circuit block is changed from about 1.8 V to about 1.4 V by DVS, and the solid line indicates cancellation of power supply resonance noise by the power supply noise suppression unit. The simulation waveform of the power supply voltage VDD when the operation is not performed is shown, and the dotted line shows the simulation waveform of the power supply voltage VDD when the power supply resonance noise is canceled using one logic circuit block in the sleep state. Shows a simulation waveform of the power supply voltage VDD when the power supply resonance noise is canceled using two logic circuit blocks in the sleep state.

  As shown in the figure, when the noise canceling operation is not performed when the power supply voltage VDD is changed from about 1.8 V to about 1.4 V, power supply resonance noise of an arbitrary period is generated. It can be seen that when the noise suppression unit cancels the power supply resonance noise by using one or two logic circuit blocks in the sleep state, the power supply resonance noise is greatly reduced.

  First, FIG. 13 shows a case where the power supply voltage VDD is changed from about 1.4V to about 1.8V by DVS, contrary to FIG. In FIG. 13, the solid line shows the simulation waveform of the power supply voltage VDD when the power supply noise suppression unit does not cancel the power supply resonance noise, and the dotted line shows the power supply resonance noise using one logic circuit block in the sleep state. The simulation waveform of the power supply voltage VDD when canceling is shown, and the alternate long and short dash line shows the simulation waveform of the power supply voltage VDD when canceling the power supply resonance noise using two logic circuit blocks in the sleep state.

  Also in this case, similarly to FIG. 12, when the power supply noise suppression unit cancels the power supply resonance noise using one or two logic circuit blocks in the sleep state, the power supply resonance noise is greatly reduced. I understand that.

  In FIG. 14, the power supply voltage VDD does not change to about 1.6 V, any one logic circuit block is in the active state, and any other one logic circuit block has transitioned from the sleep state to the active state. In the simulation, the solid line indicates that the power supply noise suppression unit does not cancel the power supply resonance noise, and the dotted line indicates that the power supply resonance noise is canceled using one sleep logic circuit block. The simulation waveforms of the power supply voltage VDD when the power supply resonance noise is canceled using two logic circuit blocks in the sleep state are shown.

  As shown in FIG. 14, when the logic circuit block transitions from the sleep state to the active state, if the power supply noise suppression unit does not cancel the power supply resonance noise, the voltage waveform of the power supply voltage VDD is affected by the rush current. A big undershoot has occurred.

  On the other hand, when the power supply resonance noise is canceled by using one logic circuit block in the sleep state, the noise can be reduced by about 19.7% as compared with the waveform of the power supply voltage VDD of the solid line. When the power supply resonance noise is canceled by using two logic circuit blocks, the noise can be reduced by about 30.7% compared to the waveform of the power supply voltage VDD of the solid line.

  Thus, according to the first embodiment, the logic circuit block in the sleep state becomes active when the voltage level of the power supply voltage VDD by the DVS changes or by using the parasitic resistance of the logic circuit block in the sleep state. The power supply resonance noise generated at the time can be greatly reduced, and a stable power supply voltage VDD can be supplied to each logic circuit block.

(Embodiment 2)
15 is a block diagram showing an example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 16 is a block diagram showing another example of the configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention. FIG.

  In the first embodiment, the configuration in which the switch units 6 and 7 are connected between the logic circuit blocks 2 and 3 and the reference potential VSS has been described. However, these switch units include, for example, the power supply voltage VDD, the logic circuit block, and the like. Alternatively, the power supply voltage VDD and the logic circuit block may be provided between the logic circuit block and the reference potential VSS.

  FIG. 15 is a block diagram showing an example of the semiconductor integrated circuit device 1 when the switch unit is provided between the power supply voltage VDD and the logic circuit block. In this case, the semiconductor integrated circuit device 1 is provided with logic circuit blocks 2 to 5, switch units 6 a and 7 a, a switch controller 8, and a power supply noise measurement circuit 9 as in FIG. 1 of the first embodiment. Yes.

  A difference from FIG. 1 of the first embodiment is that a switch unit 6 a is connected between the power supply voltage VDD and the logic circuit block 2, and the switch unit 6 a is connected between the power supply voltage VDD and the logic circuit block 3. It is a connected point.

  In the case of FIG. 15, the wiring to which the power supply voltage VDD is supplied is the power supply wiring (first power supply line) VDDL, the wiring to which the reference potential VSS is supplied is the power supply wiring (third power supply wiring) VSSL, A power supply wiring (second power supply line) VDDAL1 is used as a virtual power supply voltage VDDA between the circuit block 2 and the switch unit 6a, and a virtual power supply voltage VDDA is used between the logic circuit block 3 and the switch unit 7a. Power supply wiring (second power supply line) VDDAL2. The potential of the virtual power supply voltage VDDA is lower than the power supply voltage VDD and higher than the reference potential VSS. Therefore, the potential relationship is VDD> VDDA> VSS.

  The switch unit 6a is composed of transistors 10a and 11a made of P-channel MOS, for example. One of the connection portions of the transistors 10a and 11a is connected to be supplied with the power supply voltage VDD.

  The logic circuit block 2 is connected to the other connection portion of the transistors 10a and 11a. The gates of the transistors 10a and 11a are connected so that the switch control signal SWC output from the switch controller 8 is input thereto. Further, the gate size of the transistor 10a is formed to be larger than the gate size of the transistor 11a.

  Similarly, the switch unit 7a is also composed of transistors 12a and 13a made of, for example, P-channel MOS. One connection part of the transistors 12a and 13a is connected to be supplied with the power supply voltage VDD, and the other connection part of the transistors 12a and 13a is connected to the logic circuit block 2. .

  The gates of the transistors 12a and 13a are connected so that the switch control signal SWC output from the switch controller 8 is input thereto. Also here, the gate size of the transistor 12a is formed to be larger than the gate size of the transistor 13a.

  In the case of the semiconductor integrated circuit device shown in FIG. 15, the power cutoff by the switch units 6a and 7a changes from the cutoff of the reference potential VSS to the cutoff of the power supply voltage VDD. The power supply resonance noise is canceled by detecting the fluctuation of the virtual power supply voltage VDDA (for example, the connection part between the transistors 10a and 10b and the logic circuit block 2) with respect to the fluctuation of the VSS.

  Here, the cancellation of the power supply resonance noise may be performed by detecting not only the virtual power supply voltage VDDA but also a fluctuation of the power supply voltage VDD, the reference potential VSS, or the virtual reference potential VSSA, for example.

  FIG. 16 is a block diagram illustrating an example of a semiconductor integrated circuit device when the switch portions are provided between the power supply voltage VDD and the logic circuit block and between the logic circuit block and the reference potential VSS.

  In this case, the semiconductor integrated circuit device 1 is provided with logic circuit blocks 2 to 5, switch units 6, 6 a, 7, 7 a, a switch controller 8, and a power supply noise measurement circuit 9 as shown in the figure.

  In FIG. 16, the switches 6a and 7a of FIG. 15 are added to the configuration of FIG. The connection configuration of the logic circuit blocks 2 to 5, the switch units 6 and 7, the switch controller 8, and the power supply noise measurement circuit 9 is the same as that in FIG. 1, and the connection configuration of the switch units 6a and 7a is the same as that in FIG. It is the same.

  As shown in FIG. 16, the wiring to which the power supply voltage VDD is supplied is the power supply wiring (first power supply line) VDDL, and the power supply that is the virtual power supply voltage VDDA is provided between the logic circuit block 2 and the switch unit 6a. A wiring (second power supply line) VDDAL1 is used, and a power supply wiring (second power supply line) VDDAL2 used as a virtual power supply voltage VDDA is provided between the logic circuit block 2 and the switch unit 7a.

  The switch unit 6 is connected between the logic circuit block 2 and a power supply wiring (fourth power supply line) supplied with a power supply voltage having a voltage level lower than the power supply voltage VDD or a reference potential VSS as a reference potential. The switch unit 7 is connected between the logic circuit block 3 and the power supply wiring (fourth power supply line) to which the reference potential VSS is supplied.

  A power supply wiring (third power supply line) VSSL1 that is set to a virtual reference potential VSSA is provided between the logic circuit block 2 and the switch unit 6. Similarly, between the logic circuit block 3 and the switch unit 7, a power supply wiring (third power supply line) VSSL2 that is set to a virtual reference potential VSSA is provided. The potential of the virtual base power supply voltage VDDA and the potential of the virtual reference potential VSSA have a potential relationship of VDD> VDDA> VSSA> VSS.

  For example, the logic circuit block 2 is in a sleep state and the logic circuit block 3 is in an active state, and the power supply voltage VDD supplied to the logic circuit block 3 is, for example, about 1.6V to about 1.8V by DVS. To cancel the power supply resonance noise when changing, first, the transistor 11 of the switch unit 6 in the logic circuit block 2 in the sleep state is turned on, the virtual reference potential VSSA is raised, and the virtual reference voltage VDDA is lowered.

  After that, all the transistors of the switch units 6 and 6a are turned off, and the voltage level of the virtual reference potential VSSA is set to the same level as the reference potential VSS. At this time, the transistor 11a is turned on, and the voltage level of the virtual power supply voltage VDDA is charged to the voltage level of the power supply voltage VDD.

  After that, before the power supply voltage VDD changes due to DVS, either the transistor 11 or the transistor 11a is turned off, and the virtual reference potential VSSA or the virtual power supply voltage VDDA is brought into a floating state.

  When the transistor 11 is turned off, the subsequent operation is the same as in FIGS. 3 to 7 described above. When the transistor 11a is turned off, the subsequent operation is the same as the configuration of FIG.

(Embodiment 3)
FIG. 17 is a block diagram showing an example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 18 is a block diagram showing another example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention. 19 and 19 are block diagrams showing still another example of the configuration of the semiconductor integrated circuit device according to the third embodiment of the present invention.

  In the third embodiment, the semiconductor integrated circuit device 1 shown in FIG. 17 includes a transistor 11 having a small transistor size and a transistor from the switch sections 6 and 7 in the semiconductor integrated circuit device 1 shown in FIG. 1 of the first embodiment. 13 is deleted. Other configurations and connections are the same as those in FIG.

  Further, in the semiconductor integrated circuit device 1 shown in FIG. 18, the transistor 11a and the transistor 13a having a small transistor size are deleted from the switch portions 6a and 7a in the semiconductor integrated circuit device 1 shown in FIG. 15 of the second embodiment. It has a configuration. Other configurations and connections are the same as those in FIG.

  Further, in the semiconductor integrated circuit device 1 shown in FIG. 19, the transistors 11, 6a, 11a, 11a, The transistor 13 and the transistor 13a are omitted. Other configurations and connections are the same as those in FIG.

  In each of the configurations shown in FIGS. 17 to 19, the logic circuit block on which DVS is performed is in a dormant state, and the logic circuit block to be used as a capacitor is charged by the transistor 10 having a large transistor size, or the transistors 12, 10a, or 12a Then, noise cancellation is performed in the same procedure as in the first or second embodiment.

  Since the virtual reference potential VSSA and the virtual power supply voltage VDDA are rapidly increased with a transistor having a large size, noise may occur in the power supply voltage VDD or the reference potential VSS. For this reason, this charging operation needs to be performed in a sleep state in which the operation of other logic circuit blocks is not affected.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

   The power supply noise measurement circuit 9 may detect not only the virtual power supply voltage VDDA but also fluctuations of the power supply voltage VDD, the reference potential VSS, or the virtual reference potential VSSA, for example. In this case, the VDD potential in FIG. 8 is changed to the virtual power supply voltage VDDA, the reference potential VSS, or the virtual reference potential VSSA, and accordingly, the reference voltage VREF in FIG. 8 is set to a desired value. become.

  The present invention is suitable for a power supply stabilization technique in a semiconductor integrated circuit device in which the voltage level of the power supply voltage changes due to DVS.

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2-5 Logic circuit block 6 Switch part 6a Switch part 7 Switch part 7a Switch part 8 Switch controller 9 Power supply noise measuring circuit 10 Transistor 10a Transistor 11 Transistor 11a Transistor 12 Transistor 12a Transistor 13 Transistor 13a Transistor 14 Comparator 15 Delay unit 16 Exclusive OR circuit 17 Counter 18 Match-on circuit 19 Match-off circuit 20 Flip-flop 21 Register 22 Register 23 Selector 24 Selector 25 Stop counter 26 Switch

Claims (13)

A first power supply line to which a power supply voltage is supplied;
A second power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the first power supply line is supplied;
A third power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the second power supply line is supplied;
A logic circuit block connected between the first power supply line and the second power supply line and subject to low power consumption control;
A switch unit connected between the second power supply line and the third power supply line and performing low power consumption control of the logic circuit block based on a switch control signal;
A power supply noise measuring unit that monitors a voltage level of a power supply voltage supplied to the first power supply line and outputs a control signal according to a change in the voltage level of the power supply voltage;
A switch controller that outputs a switch control signal to the switch unit based on a control signal output from the power supply noise measurement unit and a state signal indicating an operation state of the logic circuit block;
The power supply noise measuring unit is
When power supply noise occurs in the power supply voltage supplied to the first power supply line, a control signal is output,
The switch controller
In response to a control signal output from the power supply noise measurement unit, the switch unit in any logic circuit block that is in a sleep state is operated, and a parasitic capacitance that is parasitic in the logic circuit block that is in a sleep state. A semiconductor integrated circuit device characterized by suppressing power supply noise by using the semiconductor integrated circuit device. A first power supply line to which a power supply voltage is supplied;
A second power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the first power supply line is supplied;
A third power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the second power supply line is supplied;
A logic circuit block connected between the second power supply line and the third power supply line and subject to low power consumption control;
A switch unit connected between the first power supply line and the second power supply line and performing low power consumption control of the logic circuit block based on a switch control signal;
A power supply noise measuring unit that monitors a voltage level of a power supply voltage supplied to the first power supply line and outputs a control signal according to a change in the voltage level of the power supply voltage;
A switch controller that outputs a switch control signal to the switch unit based on a control signal output from the power supply noise measurement unit and a state signal indicating an operation state of the logic circuit block;
The power supply noise measuring unit is
When power supply noise occurs in the power supply voltage supplied to the first power supply line, a control signal is output,
The switch controller
In response to a control signal output from the power supply noise measurement unit, the switch unit in any logic circuit block that is in a sleep state is operated, and a parasitic capacitance that is parasitic in the logic circuit block that is in a sleep state. A semiconductor integrated circuit device characterized by suppressing power supply noise by using the semiconductor integrated circuit device. A first power supply line to which a power supply voltage is supplied;
A second power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the first power supply line is supplied;
A third power supply line to which a power supply voltage having a lower voltage level than a power supply voltage supplied to the second power supply line is supplied;
A fourth power supply line to which a power supply voltage having a voltage level higher than the power supply voltage supplied to the third power supply line and lower than the power supply voltage supplied to the second power supply line is supplied;
A first switch unit connected between the first power supply line and the second power supply line and performing low power consumption control of the logic circuit block based on a switch control signal;
A second switch unit connected between the fourth power line and the third power line, and performing low power consumption control of the logic circuit block based on a switch control signal;
A logic circuit block connected between the second power supply line and the fourth power supply line and subject to low power consumption control;
A power supply noise measuring unit that monitors a voltage level of a power supply voltage supplied to the first power supply line and outputs a control signal according to a change in the voltage level of the power supply voltage;
A switch controller that outputs a control signal to the first switch unit or the second switch unit based on a control signal output from the power supply noise measuring unit and a state signal indicating an operation state of the logic circuit block And
The power supply noise measuring unit is
When power supply noise occurs in the power supply voltage supplied to the first power supply line, a control signal is output,
The switch controller
In response to a control signal output from the power supply noise measurement unit, the first switch unit or the second switch unit in any of the logic circuit blocks in the sleep state is operated to enter the sleep state. A semiconductor integrated circuit device characterized in that power supply noise is suppressed by utilizing a parasitic capacitance parasitic to the logic circuit block. The semiconductor integrated circuit device according to claim 1 or 2,
The power supply noise measuring unit is
The power supply voltage supplied to the first power supply line is compared with a threshold voltage, and when the power supply voltage is lower than the threshold voltage, or the power supply voltage is higher than the threshold voltage. Output the control signal when
The switch controller
When the power supply noise measurement unit receives a control signal that is output when the power supply voltage supplied to the first power supply line is higher than the threshold voltage, the power supply noise measurement unit is stored in the second power supply line. Electric charge is discharged to the third power supply line, and the power supply noise measurement unit receives a control signal output when the power supply voltage supplied to the first power supply line is lower than the threshold voltage. And controlling the switch section to which the logic circuit block in the sleep state is connected so as to discharge the charge accumulated in the third power supply line to the second power supply line. Circuit device. The semiconductor integrated circuit device according to claim 4.
The switch controller
The switch to which the logic circuit block in the sleep state is connected so as to store the charge in the second power supply line after an arbitrary period has elapsed since the charge stored in the second power supply line has been discharged A semiconductor integrated circuit device characterized by controlling a part. The semiconductor integrated circuit device according to claim 3.
The power supply noise measuring unit is
The power supply voltage supplied to the first power supply line is compared with a threshold voltage, and when the power supply voltage is lower than the threshold voltage, or the power supply voltage is higher than the threshold voltage. Output the control signal when
The switch controller
When the power supply noise measurement unit receives a control signal that is output when the power supply voltage supplied to the first power supply line is higher than the threshold voltage, the power supply noise measurement unit is stored in the second power supply line. When the power supply noise measurement unit receives the control signal output when the power supply voltage supplied to the first power supply line becomes lower than the threshold voltage, the third power supply is released. The first switch unit connected to the logic circuit block in the sleep state is controlled so as to discharge the charge accumulated in the line to the second power supply line, and the charge is accumulated in the fourth power supply line. A semiconductor integrated circuit device, wherein the second switch unit to which the logic circuit block in the sleep state is connected is controlled so as to discharge electric charge. The semiconductor integrated circuit device according to claim 6.
The switch controller
When an arbitrary period elapses after the charge accumulated in the second power supply line and the fourth power supply line is discharged, the charge is accumulated in the second power supply line and the fourth power supply line. As described above, the semiconductor integrated circuit device controls each of the first and second switch sections to which the logic circuit block in the sleep state is connected. The semiconductor integrated circuit device according to any one of claims 1, 2, 4, and 5,
The switch controller
A counter for counting clock signals;
A register unit storing timing information for turning on and off the switch unit;
The count value output from the counter is compared with the timing information stored in the register unit, and when the count value of the counter matches the timing information of the register unit, the switch unit is turned on or off And a switch control unit that outputs the switch control signal. The semiconductor integrated circuit device according to any one of claims 3, 6, and 7,
The switch controller
A counter for counting clock signals;
A register unit storing timing information for turning on and off the first switch unit and the second switch unit, respectively;
The count value output from the counter is compared with the timing information stored in the register unit, and when the count value of the counter matches the timing information of the register unit, the first switch unit, and A semiconductor integrated circuit device comprising: a switch control unit that outputs the switch control signal for turning on or off the second switch unit. The semiconductor integrated circuit device according to any one of claims 1 to 9,
The switch controller
A semiconductor integrated circuit device, wherein the switch unit is operated so as to vary the number of the logic circuit blocks in a sleep state to be used according to an operation state of the logic circuit block in an active state. The semiconductor integrated circuit device according to any one of claims 1 to 9,
The switch controller
A semiconductor integrated circuit device characterized in that the on-conduction strength of the switch section in the logic circuit block in the sleep state to be used is varied according to the operation state of the logic circuit block in the active state. The semiconductor integrated circuit device according to any one of claims 1 to 9,
Each of the switch units includes a plurality of switches,
The semiconductor integrated circuit device according to claim 1, wherein the switch controller controls the number of the plurality of switches to be operated in accordance with an operation state of the logic circuit block in an active state. The semiconductor integrated circuit device according to any one of claims 1 to 9,
Each of the switch sections includes one switch, and the semiconductor integrated circuit device.

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