JP2011151155A - Field effect transistor, electronic device, and field effect transistor manufacturing method and using method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor not broken regardless of application of overvoltage and overcurrent without over-increasing the chip area. <P>SOLUTION: In the field effect transistor, a gate electrode 110, a drain electrode 109, a source electrode 108, and a protection diode (a protection diode electrode) 111 are disposed on a semiconductor layer. The drain electrode 109 is formed to surround a part or the entire of the surrounding of the protection diode 111, or a plurality of drain electrodes 109 are provided and formed such that the protection diode 111 is disposed between at least a pair of drain electrodes of the plurality of drain electrodes 109. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a field effect transistor, an electronic device, and a method for manufacturing and using a field effect transistor.

  Semiconductor devices such as field effect transistors are widely used in various electronic devices, and research and development have been conducted from various viewpoints. For example, the field effect transistor is preferably operable at a high voltage. However, when the operating voltage is increased, the surge voltage tends to increase, and it is necessary to protect the transistor from the surge voltage. For example, when an inductive load is driven by the field effect transistor, a surge voltage may be generated due to instantaneous discharge of electric power stored in the load. As a means for protecting the transistor from such overvoltage or overpower, for example, there is a field effect transistor described in Patent Document 1 (Japanese Patent Laid-Open No. 2007-59882). In this field effect transistor, a protection diode is manufactured on the same wafer as the field effect transistor, and the field effect transistor (transistor portion) is protected from a surge voltage by the protection diode.

5A and 5B are schematic views schematically showing the structure of the field effect transistor disclosed in Patent Document 1. FIG. 5A is a circuit diagram, and FIG. 5B is a cross-sectional view. As shown in FIG. 5A, this field effect transistor includes an HFET (heterojunction field effect transistor) portion 1 and pn diode (pn junction diode) portions 2 and 3. In addition, as shown in FIG. 5B, this field effect transistor has an element formation layer 10 in which a GaN layer 12 and an Al _0.26 Ga _0.74 N layer 13 are stacked in the above order on a sapphire substrate 11. A source electrode 14, a drain electrode 15, and a gate electrode 16 are formed on the element formation layer 10, and an HFET portion 10 </ b> A (corresponding to the HFET portion 1 in FIG. 5A) is formed together with the element formation layer 10. Furthermore, a cathode electrode 18 and an anode electrode 17 made of p-Al _0.26 Ga _0.74 N are formed in another region on the element forming layer 10. Pn diode (pn junction diode) portion 10B and second pn diode portion 10C (corresponding to pn diode portions 2 and 3 in FIG. 5A). The anode electrode 17 of the first pn diode section 10B, the gate electrode 16 of the HFET section 10A, the cathode electrode 18 of the first pn diode, the anode electrode 17 of the second pn diode, the second p The cathode electrode 18 of the -n diode and the source electrode 14 of the HFET portion 10A are electrically connected to each other. That is, the first and second pn diodes are connected in series between the gate electrode and the source electrode of the HFET. By using the field effect transistor having such a configuration, a path for releasing an excessive current applied to the gate electrode is formed, and surge resistance can be improved.

JP 2007-59882 A

  However, the field effect transistor of Patent Document 1 has a large chip area because the transistor portion and the diode portion are formed in different regions. In the field effect transistor of Patent Document 1, the diode portion is connected in the forward direction between the gate electrode and the source electrode, and a current flows toward the source electrode when a positive gate voltage is applied. Therefore, it is difficult to apply a positive gate voltage as an input signal.

  Accordingly, an object of the present invention is to provide a field effect transistor, an electronic device, and a method for manufacturing and using the field transistor that are not destroyed even when overvoltage or overpower is applied without increasing the chip area.

In order to achieve the above object, the field effect transistor of the present invention comprises:
On the semiconductor layer, a gate electrode, a drain electrode, a source electrode, and a protective diode are arranged,
The drain electrode is formed so as to surround a part or all of the periphery of the protective diode, or
There are a plurality of drain electrodes, and the protective diode is formed between at least a pair of drain electrodes of the plurality of drain electrodes.

  An electronic device according to the present invention includes the field effect transistor according to the present invention.

Furthermore, the manufacturing method of the field effect transistor of the present invention includes:
Forming a gate electrode, a drain electrode, a source electrode, and a protective diode on the semiconductor layer;
In the step, the drain electrode is formed so as to surround a part or all of the periphery of the protective diode, or
A plurality of the drain electrodes are formed, and the protection diode is formed so that the protection diode is disposed between at least a pair of drain electrodes of the plurality of drain electrodes.

  Further, the field effect transistor of the present invention is used under the condition that overvoltage or overpower is applied to the field effect transistor, or the field effect transistor of the present invention, It is the usage method of the field effect transistor manufactured by a manufacturing method.

  According to the present invention, it is possible to provide a field effect transistor, an electronic device, and a method for manufacturing and using a field transistor that are not destroyed even when overvoltage or overpower is applied without increasing the chip area.

It is a top view which shows roughly the structure of the field effect transistor in one Embodiment of this invention. 1B is a plan view schematically showing a partial structure of the field effect transistor of FIG. 1A. FIG. 1B is a cross-sectional view schematically illustrating the structure of the field effect transistor of FIG. 1B. FIG. It is a top view which shows roughly the structure of the modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is a top view which shows roughly the structure of another modification of the field effect transistor of FIG. It is sectional drawing which shows roughly the structure of the field effect transistor in another embodiment of this invention. It is sectional drawing which shows roughly the structure of the modification of the field effect transistor of FIG. 3A. It is sectional drawing which shows roughly the structure of another modification of the field effect transistor of FIG. 3A. It is sectional drawing which shows schematically the structure of another modification of the field effect transistor of FIG. 3A. It is a top view which illustrates the form in which a diode electrode opposes a drain electrode. It is a top view which shows another example of the form in which a diode electrode opposes a drain electrode. 2 is a circuit diagram schematically showing a structure of a field effect transistor described in Patent Document 1. FIG. It is sectional drawing which shows roughly the structure of the field effect transistor of patent document 1.

  Hereinafter, the present invention will be described in more detail. However, the present invention is not limited by the following description.

  The field effect transistor of the present invention includes a protection diode. The field effect transistor of the present invention can function as a field effect transistor by including the source electrode, the gate electrode, and the drain electrode. Hereinafter, in the field effect transistor of the present invention, a portion that can function as a field effect transistor may be referred to as a “transistor portion”.

  According to the field effect transistor of the present invention, the transistor portion and the protection diode can be formed in the same field effect transistor without increasing the chip area due to the above structure. The field effect transistor of the present invention includes at least two electrode groups each including the gate electrode, the drain electrode, and the source electrode, and the electrode of the protection diode is electrically connected to the source electrode. A pair of the electrode groups is arranged adjacent to the protection diode and upstream and downstream of the current, respectively, and the upstream electrode group is connected to the source electrode from the upstream side of the current, The gate electrode and the drain electrode are arranged in the order, and the downstream electrode group includes the drain electrode, the gate electrode, and the source electrode arranged in the order from the upstream side of the current. It is preferable. In this case, the drain electrodes in the upstream side, the downstream side, and the electrode group may be combined to form one drain electrode.

  Further, in the field effect transistor of the present invention, one electrode unit is formed by the protection diode, the upstream electrode group, and the downstream electrode group, and a plurality of the electrode units have a current flowing direction. It is more preferable that they are arranged continuously along. The source electrode in the electrode unit may be shared with the source electrode in another adjacent electrode unit. In the electrode unit, the drain electrode in the upstream electrode group and the drain electrode in the downstream electrode group may be combined to form one drain electrode.

  In the field effect transistor of the present invention, the drain electrode is formed in a state surrounding a part or all of the periphery of the protection diode, or the protection electrode is provided between at least a pair of drain electrodes of the plurality of drain electrodes. In the portion where the diode is arranged, the total length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode is at least twice the gate width of the gate electrode. Is preferred. Alternatively, the field effect transistor of the present invention further includes a drain bus bar or a drain electrode pad, and the drain bus bar or the drain electrode pad and a region where the gate electrode, the drain electrode, and the source electrode are disposed. It is preferable that the protective diode is disposed between them. According to these structures, the current capacity of the protection diode can be further increased, and the transistor portion can be protected against a larger overpower.

  In the present invention, the `` portion facing the drain electrode '' on the outer periphery of the electrode of the protective diode includes a portion closest to the edge of the drain electrode, and the distance from the edge of the drain electrode is It shall mean a portion within twice the nearest portion. The “portion facing the drain electrode” may not be parallel to the edge of the drain electrode. For example, as shown in FIG. 4A, when the diode electrode 111 whose outer periphery has a curved shape is disposed between the pair of drain electrodes 109, the “portion facing the drain electrode” is indicated by arrows A11 and A12 in the figure. Can be expressed as The total length of the “portion facing the drain electrode” is A11 + A12. Further, for example, as shown in FIG. 4B, when the drain electrode 109 is formed so as to surround a part of the periphery of the diode electrode 111 whose outer periphery has a curved shape, the “part facing the drain electrode” and its The length can be represented by an arrow A13 in the figure. However, the distance between the portion represented by A11 and A12 in FIG. 4A and A13 in FIG. 4B and the edge of the drain electrode 109 is within the above numerical value. 4A and 4B are exemplary schematic diagrams for convenience of explanation, and the present invention is not limited at all.

  The “gate width” refers to the maximum dimension of the gate electrode in the direction perpendicular to the current direction between the source electrode and the drain electrode of the field effect transistor of the present invention. Further, the “gate width” means an effective gate width unless otherwise specified. The “effective gate width” refers to the gate width of a portion of the gate electrode that exists in the active region of the field effect transistor of the present invention. The “active region” refers to a portion through which electricity can flow in the field effect transistor of the present invention. When a plurality of the gate electrodes are present in the field effect transistor of the present invention and each has a different gate width, the total length of the portions facing the drain electrode on the outer periphery of the electrode of the protection diode is the gate width. Of these, it is more preferable that the maximum gate width be twice or more.

  The field effect transistor of the present invention preferably has a substrate and a functional semiconductor layer laminated thereon, and the functional semiconductor layer is preferably formed of a group III nitride semiconductor. By utilizing the properties such as the large band gap, high breakdown field strength, and high electron mobility of group III nitride semiconductors (such as GaN), it is easy to form a field effect transistor capable of high breakdown voltage and high speed operation. is there.

In the field effect transistor of the present invention, the protection diode is a Schottky diode, a pn diode having a two-dimensional electron gas as an n-type layer, or a pin diode having a two-dimensional electron gas as an n-type layer. It is preferable. When the protective diode is a Schottky diode, the semiconductor layer in contact with the electrode of the protective diode is a semiconductor represented by a conductivity type and composition of i-In _x Ga _1-x N (0 ≦ x <1). More preferably, it is a layer. When the protection diode is a pn diode having an n-type layer of a two-dimensional electron gas, the semiconductor layer in contact with the electrode of the protection diode is p-In _y Ga _1-y N (0 ≦ y < A semiconductor layer represented by the conductivity type and composition of 1) is more preferable. If the protective diode is a p-i-n diodes in which the two-dimensional electron gas and the n-type layer, a semiconductor layer in contact with the electrode of the protective _{diode, p-In z Ga 1-} z N (0 ≦ A semiconductor layer represented by a conductivity type and composition of z <1) is more preferable.

When the protection diode is a Schottky diode, a pn diode having a two-dimensional electron gas as an n-type layer, or a pin diode having a two-dimensional electron gas as an n-type layer, the field effect transistor of the present invention Is
Including a gate electrode connection layer and a composition modulation layer,
The gate electrode connection layer is a semiconductor layer electrically connected to the gate electrode and closest to the gate electrode;
The composition modulation layer is disposed between the gate electrode connection layer and the electrode of the protection diode, and has a large band gap on the gate electrode connection layer side and a band gap on the electrode side of the protection diode. It is preferable to have such a composition that changes.
In this case, the composition modulation layer is more preferably a semiconductor layer in contact with the electrode of the protection diode. Alternatively, the field effect transistor of the present invention further includes a protective diode electrode contact layer, the protective diode electrode contact layer is a semiconductor layer in contact with the electrode of the protective diode, and the composition modulation layer is the gate electrode More preferably, it is disposed between the connection layer and the protective diode electrode contact layer.
Further, the composition modulation layer contains Al from the viewpoint of adjusting the band gap, and has a large Al composition ratio on the gate electrode connection layer side and a small Al composition ratio on the electrode side of the protection diode. More preferably, the semiconductor layer has a composition that changes continuously or stepwise. From the same viewpoint, the composition modulation layer is more preferably formed of AlGaN.

  The field effect transistor of the present invention can further increase the reverse breakdown voltage of the protection diode by including the composition modulation layer. This effect is related to whether the protection diode is a Schottky diode, a pn diode having a two-dimensional electron gas as an n-type layer, or a pin diode having a two-dimensional electron gas as an n-type layer. Can be obtained. Thereby, even if the transistor portion operates at a high voltage, it is possible to suppress a leak current from flowing to the protection diode side, and it is possible to protect the transistor portion even against a larger overvoltage.

When the protection diode is a pin diode having a two-dimensional electron gas as an n-type layer,
The semiconductor layer in contact with the electrode of the protective diode is a _{p-In z Ga 1-z} N (0 ≦ z <1) semiconductor layer represented by the conductivity type and composition,
Furthermore, a gate electrode connection layer and an i-GaN layer are included, and the gate electrode connection layer is a semiconductor layer that is electrically connected to the gate electrode and is closest to the gate electrode,
The i-GaN layer is more preferably disposed between said gate electrode connecting layer _{p-In z Ga 1-z} N layer.

Further, when the protection diode is a pin diode having a two-dimensional electron gas as an n-type layer,
The semiconductor layer in contact with the electrode of the protective diode is a _{p-In z Ga 1-z} N (0 ≦ z <1) semiconductor layer represented by the conductivity type and composition,
Furthermore, a gate electrode connection layer and an i-AlGaN layer are included, and the gate electrode connection layer is a semiconductor layer that is electrically connected to the gate electrode and is closest to the gate electrode,
The i-AlGaN layer is more preferably disposed between said gate electrode connecting layer _{p-In z Ga 1-z} N layer. In this case, it is more preferable that the gate electrode connection layer includes Al, and an Al composition ratio of the i-AlGaN layer is equal to or less than an Al composition ratio of the gate electrode connection layer.

  In the field effect transistor of the present invention, when the protective diode is a pn diode having a two-dimensional electron gas as an n-type layer, or a pin diode having a two-dimensional electron gas as an n-type layer, For example, the semiconductor layer in contact with the electrode of the protection diode is a p-type layer. In the n-type layer, for example, a two-dimensional electron gas (2DEG) runs in a semiconductor layer constituting the transistor unit, and the 2DEG also serves as the n-type layer of the protection diode.

  The field effect transistor of the present invention further includes a gate insulating film, and the gate electrode is electrically connected to a part of the semiconductor constituting the field effect transistor via the gate insulating film. It is more preferable. With such a structure, all of the overvoltage and overpower must be released from the protection diode, so that the effect of the present invention becomes more remarkable. The gate insulating film is selected from the group consisting of at least one element selected from the group consisting of Si, Mg, Hf, Al, Ti, Ta, Zr, St, and Ba, and O, N, and C. More preferably, it contains at least one element.

  In the present invention, “electrically connected” means, for example, a direct contact state, a state where they are connected via other components, a state where electricity can be passed, an insulating film or the like. It may be in a state where electrical interaction is possible. The state in which the electrode is electrically connected to the semiconductor layer is, for example, a state in which the source electrode, the drain electrode, or the gate electrode is in direct contact with the semiconductor layer, or the gate electrode is connected to the semiconductor layer through the gate insulating film. There are states that are connected to each other.

  Further, in the present invention, “on” may be in a state of being in direct contact with the upper surface, or may be in a state in which other components are present, unless otherwise specified. Similarly, “under” may be in a state of being in direct contact with the lower surface, or in a state in which other components or the like are present, unless otherwise specified. Further, “on the top surface” indicates a state in which the top surface is in direct contact. Similarly, “on the lower surface” refers to a state of being in direct contact with the lower surface. “On one side” may be in a state of being in direct contact with one side, or in a state in which other components are present, unless otherwise specified. The same applies to “both sides”. “On one side” refers to the state of direct contact with one side. The same applies to “both sides”.

Further, in the present invention, “composition” refers to a quantitative relationship of the number of atoms of elements constituting a semiconductor layer or the like. “Composition ratio” refers to a relative ratio between the number of atoms of a specific element constituting the semiconductor layer and the like and the number of atoms of another element. For example, in a semiconductor layer represented by a composition of Al _x Ga _1-x N, the numerical value of x is referred to as “Al composition ratio”. In the present invention, when comparing the composition of one semiconductor layer and another semiconductor layer, an impurity (dopant) for developing conductivity is not considered as an element constituting the semiconductor layer. For example, a p-type GaN layer and an n-type GaN layer are different in impurities (dopants) but have the same composition. For example, when there is an n-type GaN layer and an n ⁺ GaN layer having a higher impurity concentration, their compositions are assumed to be the same.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. However, the following embodiments and examples are illustrative and do not limit the present invention. In the drawings, similar components are appropriately denoted by the same reference numerals, and detailed description thereof may be omitted as appropriate so as not to overlap. Each drawing is an exemplary schematic diagram, and the dimensional ratio of each part may not match the actual product.

[Embodiment 1]
FIG. 1A is a plan view schematically showing the structure of the field effect transistor 10 of the first embodiment according to the present invention. As shown in the figure, the field effect transistor 10 includes a multi-finger transistor in which a plurality of gate electrodes are arranged in a comb shape at a substantially constant period, and a diode embedded in the drain electrode portion of the transistor. In order to simplify the description, a structure for one cycle will be described below as in a region 10-1 surrounded by a broken line. This field effect transistor 10-1 corresponds to a structure corresponding to one period constituting the field effect transistor 10. In the actual field effect transistor 10, a combination of electrodes constituting one period is repeated two or more periods, for example, several tens to several hundreds. The structure of both ends of the field effect transistor 10 may be different from the combination of electrodes constituting one cycle. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film.

  Next, the field effect transistor 10-1 will be described based on the plan view of FIG. 1B and the cross-sectional view of FIG. 1C. As shown in FIG. 1B, this field effect transistor 10-1 has two sets of electrode groups each including a source electrode 108, a drain electrode 109, and a gate electrode 110, and further includes an electrode 111 of a protective diode. Further, adjacent to the protective diode and its electrode 111, a set of the electrode groups is arranged on the upstream side and downstream side of the current, respectively. In the upstream electrode group, the source electrode 108, the gate electrode 110, and the drain electrode 109 are arranged in the order described above from the upstream side of the current. In the downstream electrode group, the drain electrode 109, the gate electrode 110, and the source electrode 108 are arranged in this order from the upstream side of the current. The source pad portion 112, the gate bus bar 114, and the drain pad portion 113 in the upper part of the figure are respectively connected from one end of the field effect transistor 10-1 along the direction of current flow in the field effect transistor 10-1. Extends to the other end. The electrode 111 of the protection diode is electrically connected to the source electrode 108 via the source pad portion 112. Each drain electrode 109 is connected via a drain pad portion 113. Each gate electrode 110 is connected by a gate bus bar 114. In the field effect transistor of the present invention, the source pad portion, the drain pad portion, and the gate bus bar are not essential, but preferably have at least one of them in order to form the multi-finger structure. .

  The width of the active region of the field effect transistor 10-1 (the length in the direction perpendicular to the current direction) is the same as the width of the drain electrode 109, the gate electrode 110, and the source electrode 108 (the length in the direction perpendicular to the current direction). Is almost equal to In FIG. 1B, a dotted line 1001 is a line connecting the lower ends (lower side in the drawing) of the drain electrode 109, the gate electrode 110, and the source electrode 108, and a dotted line 1002 is the drain electrode 109, the gate electrode 110, and the source. This is a line connecting the upper ends (upper side in the figure) of the electrode 108. The active region of the field effect transistor 10-1 is a region between the dotted line 1001 and the dotted line 1002, and the width of the active region (the length in the direction perpendicular to the current direction) is the distance between the dotted line 1001 and the dotted line 1002. equal. In the field effect transistor of the present invention, the active region is a portion through which electricity can flow as described above, and the width of the active region is completely equal to the widths of the drain electrode, the gate electrode, and the source electrode. Does not necessarily match.

  Further, as shown in FIG. 1C, the field effect transistor 10-1 includes a nucleation layer 102 made of a first semiconductor layer, an electron transit layer 103 made of a second semiconductor layer, and a third semiconductor on a substrate 101. The electron supply layer 104 made of layers, the electric field relaxation layer 105 made of the fourth semiconductor layer, and the p-type layer 106 made of the fifth semiconductor layer have a laminated structure laminated in the order described above. On the upper surface of the electron supply layer 104, the electric field relaxation layer 105 and the p-type layer 106 are partially removed. The diode part can be manufactured by forming the diode electrode 111 made of the first metal on the upper surface of the p-type layer 106 and connecting it to the source pad part 112 via a three-dimensional wiring. Further, a source electrode 108, a drain electrode 109, and a gate electrode 110 are formed in the above-described arrangement in a portion where the electric field relaxation layer 105 and the p-type layer 106 are removed. At the site where the gate electrode 110 is formed, a part of the upper part of the electron supply layer 104 is removed to form an opening (opening embedded part). A gate insulating film 107 made of a first insulating film and a gate electrode 110 made of a second metal are laminated in this order on the upper surface of the opening (opening embedded portion), and a gate pad (see FIG. (Not shown). Further, a source electrode 108 and a drain electrode 109 made of a third metal are formed so as to sandwich the gate electrode 110, and the transistor portion is connected to the source pad portion 112 and the drain pad portion 113 through three-dimensional wirings, respectively. Can be made.

  A separate buffer layer may be inserted between the nucleation layer 102 and the electron transit layer 103. For example, when the difference in lattice constant between the substrate 101 and the buffer layer or the electron transit layer 103 is approximately equal to 3% or less, the nucleation layer 102 may be omitted.

The electron transit layer 103 may be made of a group III nitride compound semiconductor such as GaN, InN, or AlN, for example. An n-type impurity such as Si, S, Se, or O, or a p-type impurity such as beryllium (Be), carbon (C), or magnesium (Mg) may be added to the electron transit layer 103. However, from the viewpoint of preventing a decrease in electron mobility due to the influence of Coulomb scattering, the impurity concentration in the electron transit layer 103 is preferably not too high, for example, 1 × 10 ¹⁷ cm ⁻³ or less. The electron supply layer 104 is a layer heterojunctioned to the upper surface of the electron transit layer 103 and made of a group III nitride compound semiconductor such as GaN, InN, or AlN. In order to supply electrons from the electron supply layer 104 to the electron transit layer 103, the electron supply layer 104 is made of a material or composition having a smaller electron affinity than the electron transit layer 103. In the field effect transistor 10 of this embodiment, two-dimensional electron gas can be generated at and near the heterojunction interface between the electron transit layer 103 and the electron supply layer 104 mainly by the piezo effect and the spontaneous polarization effect. For example, when the AlGaN layer (electron supply layer) 104 is heterojunction with the upper surface of the undoped GaN layer (electron transit layer) 103, positive space fixed charge is generated at the heterojunction interface due to both spontaneous polarization and piezoelectric polarization. Then, a two-dimensional electron gas is formed on the GaN layer side of the heterojunction interface. Note that by introducing an n-type impurity such as Si, S, Se, or O into the electron supply layer 104 having a larger band gap than the electron transit layer 103, the concentration of the two-dimensional electron gas at the heterojunction interface and its vicinity is introduced. Can also be adjusted (modulation doping).

The electric field relaxation layer 105 has a composition represented by In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). In order to suppress punch-through and obtain high breakdown voltage performance, the composition of the electric field relaxation layer 105 is controlled so that negative polarization charges are distributed almost uniformly within the electric field relaxation layer 105. For example, when the upper surface of the electric field relaxation layer 105 is a gallium surface that is a group III surface, the Al composition ratio y of the electric field relaxation layer 105 is gradually (continuously) or stepped from the substrate 101 side toward the diode electrode 111 side. Make it smaller. Thereby, the negative polarization charge can be distributed almost uniformly in the stacking direction inside the electric field relaxation layer 105. Alternatively, the In composition ratio x of the electric field relaxation layer 105 may be increased gradually (continuously) or stepwise from the substrate 101 side toward the diode electrode 111 side. Even in this case, the negative polarization charge can be distributed substantially uniformly in the stacking direction inside the electric field relaxation layer 105. Alternatively, the Al composition ratio y of the electric field relaxation layer 105 is decreased gradually (continuously) or stepwise from the substrate 101 side toward the diode electrode 111 side, and the In composition ratio x of the electric field relaxation layer 105 is decreased to the substrate. You may enlarge gradually (continuously) or in steps as it goes to the diode electrode 111 side from 101 side. Even in this case, the negative polarization charge can be distributed substantially uniformly in the stacking direction inside the electric field relaxation layer 105.

  The electric field relaxation layer 105 has the above composition, and thus has an energy band structure in which the conduction band and the valence band bend toward the vacuum level by a piezo effect and a spontaneous polarization effect. Since this convex energy band is formed with fixed charges resulting from the piezo effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength and to improve the withstand voltage performance.

Examples of the n-type impurity introduced into the electric field relaxation layer 105 include silicon (Si), sulfur (S), selenium (Se), and oxygen (O). The n-type impurity concentration can be set to a desired value, but is preferably 1 × 10 ¹⁸ cm ⁻³ or less in order to relax the electric field. In particular, in order to ensure high breakdown voltage performance, the n-type impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less. The p-type layer 106 is a p-type nitride semiconductor layer having an acceptor concentration of 1 × 10 ¹³ cm ⁻² or more in terms of surface density. Examples of the p-type impurity introduced into the p-type layer 106 at a high concentration include Be, C, and Mg. Examples of the constituent material of the p-type layer 106 include a group III such as GaN, InN, and AlN. Nitride compound semiconductors may be mentioned. The concentration of the p-type impurity introduced into the p-type layer 106 is not particularly limited, but is preferably 1 × 10 ¹⁸ cm ⁻³ or more in order to maintain the formation of a potential barrier against electrons in the high voltage region. . The material for forming the diode electrode 111 is not particularly limited, but a material that is in ohmic contact with the p-type layer 106 is preferable. Alternatively, the gate electrode may be made of the same material.

  Although it is preferable to use a conductive group III nitride compound semiconductor substrate made of GaN, AlN, or the like as the substrate 101, it is not limited to this. For example, a silicon substrate or a silicon carbide substrate may be used for the substrate 101. It is also possible to use a conductive substrate depending on the application.

  The field effect transistor of this embodiment is a MIS transistor having a gate insulating film. For this reason, the formation material of a gate electrode will not be restrict | limited especially if there is electroconductivity, It can be set as arbitrary substances. Specifically, as the material for forming the gate electrode, for example, an impurity is added to a metal material such as Ni, Pd, W, Mo, Ti, Pt, Nb, Al or Au, or a polycrystal mainly composed of Si. Examples include added materials. The gate electrode may be formed of a plurality of materials, or may have a structure in which a plurality of material layers are stacked. However, the material for forming the gate electrode is preferably a material that does not react with the gate insulating film. When the MIS structure is not used (when there is no gate insulating film), the gate electrode 110 may be formed using a material that is in Schottky contact with the base electron supply layer 104, for example.

  The gate insulating film 107 includes, for example, silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti), zirconium (Zr), strontium (St), barium (Ba), and tantalum. What is necessary is just to comprise by 1 type, or 2 or more types of oxides or nitride selected from the group which consists of (Ta). Instead of an inorganic compound such as oxide or nitride, an organic insulator may be used.

  According to the field effect transistor 10 of the present embodiment, for example, the following effects can be obtained.

  First, since the field effect transistor 10 of this embodiment employs an MIS transistor as a transistor, the gate leakage current during normal operation can be reduced. On the other hand, since the field effect transistor of this embodiment cannot flow current through the gate electrode, when a voltage is applied from the outside such as a surge or inductive overpower, the current cannot be released in the transistor portion. In the field effect transistor of the present embodiment, when a voltage is applied from the outside such as a surge or inductive overpower, current can be released from the diode disposed in the drain electrode. In particular, in this embodiment, since a pn diode having an electric field relaxation layer is used, a leakage current does not flow on the diode side even at a high operating voltage (positive drain voltage), and there is a disadvantage of having a diode. Does not happen. In the field effect transistor of this embodiment, when a positive voltage higher than the operating voltage is applied, it can be emitted to the source electrode side (ground) as a reverse current of the diode. At that time, the portion directly under the diode electrode (electrode of the protective diode) is depleted, and current flows only through the outer periphery of the diode electrode. In such a case, even if the current capacity is secured by the area of the diode electrode, the current capacity is insufficient regardless of the electrode area of the diode. However, according to the structure of the field effect transistor of the present invention, it is easy to increase the outer peripheral length (outer peripheral length) of the diode electrode, and thus it is easy to ensure a sufficient current capacity. In particular, in this embodiment, since the outer peripheral length of the diode electrode is equal to or greater than the gate electrode width (gate width), a sufficient current capacity can be realized. In addition, when a negative external voltage is applied, the diode works in the forward direction, the resistance under the diode electrode is low, and a large current can easily flow. In the present embodiment, the total length of the portions facing the drain electrode on the outer periphery of the electrode of the protective diode is at least A1 + A2 shown in FIG. 1B, and more than twice the gate width B1 of the gate electrode. It is. Thereby, the current capacity of the protection diode can be further increased, and the transistor portion can be protected against a large overpower.

  Furthermore, the gate electrode pitch (interval at which the gate electrodes are arranged) is usually defined by the output of the field effect transistor and heat dissipation. In order to ensure sufficient heat dissipation at high output, the value of the gate electrode pitch is preferably, for example, 30 μm or more. However, the effective width of the drain electrode (the width of the portion that can actually function as an electrode) is usually only a few μm from the outer periphery of the drain electrode, and is extremely small relative to the value of the gate electrode pitch. Therefore, when a drain electrode is disposed between the gate electrodes, most of the vicinity of the center of the drain electrode becomes a useless space. If a protective diode is disposed between the gate electrodes, the value of the gate electrode pitch must be further increased, which increases the chip area. However, according to the electrode arrangement such as the field effect transistor of the present embodiment, since the protective diode can be arranged in the useless space, the loss of the area due to the useless space can be suppressed, and the chip area Leads to savings. According to the electrode arrangement of the field effect transistor of the present embodiment, for example, it is also possible to arrange a protective diode without changing the gate electrode pitch from a general field effect transistor, that is, without increasing the chip area at all. It becomes. However, description of this effect is an illustration, Comprising: This invention is not limited by this description.

  In addition, the manufacturing method of the field effect transistor of the present invention is not particularly limited, but it is preferably manufactured by the manufacturing method of the field effect transistor of the present invention. A method of forming each part such as an electrode and a semiconductor layer is not particularly limited, and can be appropriately performed with reference to a general method for manufacturing a semiconductor device, for example. Although the manufacturing (production) method of the field effect transistor 10 (10-1) of FIG. 1 is not particularly limited, for example, it is as in Example 1 described later. The material of each part is not particularly limited. For example, as described above or as shown in the first embodiment.

  Next, a modification of the field effect transistor 10 of FIG. 1 will be described. 2A to 2H are cross-sectional views schematically showing a planar structure of each field effect transistor which is a modification of the present embodiment. Each feature will be described below.

  A field effect transistor 10-2 shown in FIG. 2A represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. The field effect transistor 10-2 has a structure in which three drain electrodes 109 and two diode electrodes 111 are included, and two diodes are included between the drain electrodes. Each diode electrode 111 is sandwiched between the drain electrodes 109, and is arranged in the order of the drain electrode 109, the diode electrode 111, the drain electrode 109, the diode electrode 111, and the drain electrode 109 along the direction in which the current flows. Other than these, the field effect transistor 10-2 is the same as the field effect transistor 10-1 of FIG. As illustrated, in the field effect transistor 10-2, the length of the portion where the drain electrode and the protective diode face each other is twice as long as that of the field effect transistor 10-1. That is, in FIG. 2A, the total length (A3 + A4 + A5 + A6) of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode is more than twice the gate width B2 of the gate electrode. As a result, a large current can flow in both the forward and reverse directions.

  A field effect transistor 10-3 shown in FIG. 2B represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. As illustrated, the field effect transistor 10-3 has a structure in which one protective diode (diode electrode 111) is included between the drain electrodes 109. In this field effect transistor 10-3, two drain electrodes 109 are combined on the drain pad side to form one drain electrode, and the drain pad side surface of the protection diode is also opposed to the drain electrode. Other than these, the field effect transistor 10-3 is the same as the field effect transistor 10-1 of FIG. Compared with the field effect transistor 10-1, the field effect transistor 10-3 also has a portion where the drain electrode and the diode face each other (the total length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode). ) Can be increased, so that a large current can flow in both the forward and reverse directions.

  A field effect transistor 10-4 shown in FIG. 2C represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. The field effect transistor 10-4 has a structure in which one protective diode (diode electrode 111) is included between the drain electrodes 109. In this field effect transistor 10-4, the drain electrode 109 and the diode electrode 111 are each comb-shaped, and are arranged so that the teeth of the comb mesh. The direction of the comb teeth is perpendicular to the direction of current flow. Other than these, the field effect transistor 10-4 is the same as the field effect transistor 10-1 of FIG. Compared with the field effect transistor 10-1, the field effect transistor 10-4 also has a portion where the drain electrode and the diode face each other (the total length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode). ) Can be increased, so that a large current can flow in both the forward and reverse directions.

  A field effect transistor 10-5 shown in FIG. 2D represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. The field effect transistor 10-5 has a structure in which one protective diode (diode electrode 111) is included between the drain electrodes 109. In this field effect transistor 10-5, the diode electrode 111 has a fishbone structure (fish spine-like shape). The drain electrode 109 is disposed around the diode electrode 111 so as to surround the left and right gate electrode 110 sides and the source pad portion 113 side. Other than these, the field effect transistor 10-5 is the same as the field effect transistor 10-1 of FIG. Compared with the field effect transistor 10-1, the field effect transistor 10-5 also has a length of a portion where the drain electrode and the diode face each other (a length of a portion facing the drain electrode on the outer periphery of the electrode of the protective diode). The total current can be made longer, so that a large current can flow in both the forward and reverse directions.

  A field effect transistor 10-6 shown in FIG. 2E represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. As illustrated, the field effect transistor 10-6 has a structure in which seven protective diodes (diode electrodes 111) are included in the drain electrode 109. The diode electrodes 111 are arranged in a lattice shape, and the drain electrodes 109 are arranged so as to surround four sides of the six diode electrodes 111 and three sides of the other one diode electrode 111. Other than these, the field effect transistor 10-6 is the same as the field effect transistor 10-1 of FIG. Compared with the field effect transistor 10-1, this field effect transistor 10-6 also has a portion where the drain electrode and the diode face each other (the total length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode). ) Can be increased, so that a large current can flow in both the forward and reverse directions. In order to make the wiring on the source pad side as short as possible, the drain electrode 109 is arranged on the source pad side of the diode electrode 111 located on the most source pad side (the “other one diode electrode 111”). Absent.

  A field effect transistor 10-7 shown in FIG. 2F represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. As illustrated, the field effect transistor 10-7 has a structure in which one protective diode (diode electrode 111) is included between the drain electrodes 109. In this field effect transistor 10-7, two drain electrodes 109 are combined on the drain pad side and the source pad side to form one drain electrode. The drain electrode 109 is disposed so as to surround the four sides of the diode electrode 111, and the drain pad side surface and the source pad side surface of the protection diode (diode electrode 111) are also opposed to the drain electrode. Other than these, the field effect transistor 10-7 is the same as the field effect transistor 10-1 of FIG. This field effect transistor 10-7 also allows a larger current to flow in both the forward and reverse directions because the length of the portion where the drain electrode and the diode face each other can be made longer than the field effect transistor 10-1. It is.

  A field effect transistor 10-8 shown in FIG. 2G represents one cycle constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. As illustrated, the field effect transistor 10-8 has a structure in which eight protective diodes (diode electrodes 111) are included in the drain electrode 109. Each diode electrode 111 is arranged in a lattice shape, and the drain electrode 109 is arranged so as to surround all four sides of the diode electrode 111. Other than these, the field effect transistor 10-8 is the same as the field effect transistor 10-1 of FIG. Compared with the field effect transistor 10-1, the field effect transistor 10-8 also has a portion where the drain electrode and the diode face each other (the total length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode). ) Can be increased, so that a large current can flow in both the forward and reverse directions.

  A field effect transistor 10-9 shown in FIG. 2H represents one period constituting the field effect transistor 10. In the drawing, a portion indicated by a dotted line indicates an aerial wiring or a three-dimensional wiring through an insulating film. As shown in the drawing, in the field effect transistor 10-9, the protective diode (diode electrode 111) is disposed between the drain electrode 109 and between the drain pad portion 113 and the active region (transistor portion) of the transistor. ing. The diode electrode 111 between the drain electrodes 109 is connected to the diode electrode 111 between the drain pad portion 113 and the transistor portion to form one diode electrode 111. Other than these, the field effect transistor 10-9 is the same as the field effect transistor 10-1 of FIG. That is, in FIG. 2H, the total length of the portions facing the drain electrode on the outer periphery of the electrode of the protective diode is at least (A7 + A8 + A9 + A10), and the gate width of the gate electrode is B3. Therefore, this field effect transistor 10-9 also has a portion where the drain electrode and the diode face each other (the length of the portion facing the drain electrode on the outer periphery of the electrode of the protective diode), as compared with the field effect transistor 10-1. (Total) can be increased, and a large current can flow in both the forward and reverse directions.

[Embodiment 2]
3A to 3C are cross-sectional views schematically showing a cross-sectional structure of a field effect transistor according to another embodiment of the present invention. These are different from the field-effect transistor of Embodiment 1 in particular in the structure of the diode portion. Each will be described below.

  A field effect transistor 10-10 shown in FIG. 3A is a cross-sectional structure diagram showing one period constituting the field effect transistor 10. As illustrated, the field effect transistor 10-10 uses a Schottky diode as a diode. Specifically, the electric field relaxation layer 105 and the p-type layer 106 are not provided, and the diode electrode 111 is in direct contact (Schottky contact) with the upper surface of the electron supply layer 104. Otherwise, this field effect transistor 10-10 is the same as the field effect transistor 10-1 of FIG. Since such a field effect transistor does not require a p-type layer on the electron supply layer 104, epi-growth is easier than a pn diode as shown in FIG. In addition, since the field effect transistor using the Schottky diode has a low forward resistance, it can easily discharge a current when a forward voltage of the diode is applied.

  The field effect transistor 10-10 illustrated in FIG. 3A does not have a gate insulating film, and an opening (opening embedded portion) is not formed on the electron supply layer 104, so that the gate electrode 110 serves as the electron supply layer 104. Direct contact (Schottky contact) with the top surface. Other than this, the structure of the transistor portion of the field effect transistor 10-10 shown in FIG. 3A is the same as that of the field effect transistor 10-1 shown in FIG. The same applies to the field effect transistors of FIGS. 3B and 3C.

  A field effect transistor 10-11 illustrated in FIG. 3B is a cross-sectional structure diagram illustrating one period constituting the field effect transistor 10. As illustrated, the field effect transistor 10-11 uses a pn diode as a diode. Specifically, it is the same as the field effect transistor 10-10 shown in FIG. 3A except that the p-type GaN layer 106 is provided between the electron supply layer 104 and the diode electrode 111. When the p-n diode is used in this way, the p-type layer 106 is necessary, so that the epitaxial growth during manufacturing is increased by one layer as compared with the Schottky diode. However, since the pn diode has less reverse leakage current than the Schottky diode, there is an advantage that the leakage current during normal operation can be reduced. In addition, when p-GaN is used as the p-type layer, it can be selectively etched with the AlGaN layer normally used as the electron supply layer, so that there is an advantage that the characteristics of the transistor can be easily controlled.

  The field effect transistor 10-12 illustrated in FIG. 3C is a cross-sectional structure diagram illustrating one period constituting the field effect transistor 10. As illustrated, the field effect transistor 10-12 uses a pin diode as a diode. Specifically, it is the same as the field effect transistor 10-11 shown in FIG. 3B except that an i-GaN layer (high-purity layer) 115 is provided between the electron supply layer 104 and the p-type GaN layer 106. When the p-i-n diode is used in this way, the p-type layer 106 and the high-purity layer 115 are necessary, so that the epitaxial growth during manufacturing increases by two layers. However, since the p-i-n diode has a smaller reverse leakage current than the Schottky diode and the pn diode, there is an advantage that the leakage current during normal operation can be reduced. In addition, when p-GaN is used as the p-type layer, it can be selectively etched with the AlGaN layer normally used as the electron supply layer, so that there is an advantage that the characteristics of the transistor can be easily controlled. Furthermore, the p-i-n diode has an advantage that the reverse breakdown voltage can be increased as compared with the p-n diode.

  3D does not have a gate insulating film, an opening (an opening embedded portion) is not formed on the electron supply layer 104, and the gate electrode 110 is formed on the upper surface of the electron supply layer 104. Except for direct contact (Schottky contact), it is the same as the field effect transistor 10-1 of FIG. That is, this field effect transistor 10-13 has a pn diode similar to that shown in FIG. 3B except that the field relaxation layer 105 is provided between the electron supply layer 104 and the p-GaN layer 106. As described in Embodiment 1, in such a field effect transistor, the composition of the electric field relaxation layer 105 is continuously or stepwise so that the negative polarization charge is distributed almost uniformly inside the electric field relaxation layer 105. To change. Thereby, punch-through is suppressed and high pressure resistance can be obtained.

  As described above, the field effect transistor according to the present invention is used under the condition that an overvoltage or an overpower is applied to the field effect transistor of the present invention or the field effect transistor manufactured by the manufacturing method of the present invention. It is characterized by using. The field effect transistor of the present invention or the field effect transistor manufactured by the manufacturing method of the present invention has an effect that it is not destroyed even when an overvoltage or overpower is applied. However, the usage method of the field effect transistor of the present invention or the field effect transistor manufactured by the manufacturing method of the present invention is not limited to the usage method of applying overvoltage or overpower, and any usage method may be used. In the present invention, “overvoltage” refers to a voltage exceeding the breakdown voltage when the protective diode is removed from the field effect transistor of the present invention (used only in the transistor portion). In the present invention, the term “overpower” refers to the withstand capacity when the protective diode is removed from the field effect transistor of the present invention (used only in the transistor portion) (the upper limit power that the semiconductor element can withstand breakdown). Power). The field effect transistor of the present invention or the field effect transistor manufactured by the manufacturing method of the present invention can release one or both of overvoltage and overpower by the protection diode. For this reason, the field effect transistor of the present invention or the field effect transistor manufactured by the manufacturing method of the present invention as a whole has one or both of breakdown voltage and withstand capability compared to the case where the protective diode is not present. Will be improved.

  As described above, according to the present invention, it is possible to provide a field effect transistor that is not destroyed even when overvoltage and overpower are applied without excessively increasing the chip area. Since the field effect transistor of the present invention can operate at a high voltage and a large output, it can be used as a power semiconductor element that contributes to energy saving of electronic devices such as a switching power supply and an inverter circuit. As described above, the electronic device of the present invention is characterized by including the field effect transistor of the present invention. The use of the field effect transistor of the present invention is not particularly limited. For example, a motor control device (for example, for an electric vehicle or an air conditioner), a power supply device (for example, for a computer), inverter lighting, a high frequency power generator (for example, a microwave oven) Can be widely used for image display devices, information recording / reproducing devices, communication devices, and the like.

  The field effect transistor 10 (10-1) shown in FIG. 1 was manufactured. Specifically, it is as follows.

First, a (111) plane Si substrate was prepared as the substrate 101. Next, an AlN layer (film thickness 20 nm) is formed thereon as the nucleation layer 102, a GaN operation layer (film thickness 2500 nm) is formed as the electron transit layer 103, and an AlGaN electron supply layer (Al composition ratio 0.25 is formed as the electron supply layer 104). , Film thickness 20 nm, Si addition amount 2 × 10 ¹⁷ cm ⁻³ ), AlGaN as the electric field relaxation layer 105 (Al composition ratio 0.25 on the electron supply layer side, Al composition ratio 0 on the p-type layer side, film thickness 100 nm) As the p-type layer 106, a GaN layer (film thickness: 100 nm, Mg addition amount: 1 × 10 ¹⁹ cm ⁻³ ) was formed by the metal organic vapor phase epitaxy (MOVPE) method in the above order. The growth temperature by the MOVPE method could be as follows.

Nucleation layer 102: Usually 400 to 1100 ° C. (for example, 1080 ° C.)
Electron traveling layer 103 (GaN layer): usually 1000 to 1050 ° C. (eg 1030 ° C.)
Electron supply layer 104 (AlGaN layer): typically 1040 to 1100 ° C. (eg, 1080 ° C.)
Electric field relaxation layer 105 (AlGaN layer): Usually 1040 to 1100 ° C. (for example, 1080 ° C.)
p-type layer 106 (GaN layer): usually 1000 to 1050 ° C. (eg 1030 ° C.)

Next, a photoresist is applied on the upper surface of the p-type layer 106, an opening is provided by exposure and development, and then the p-type layer 106 and the electric field other than the diode electrode portion are formed by dry etching (ICP method) using BCl ₃ gas. The relaxation layer 105 was removed. Further, Ti / Al (Ti layer thickness 10 nm, Al layer thickness 200 nm) is formed on the upper surface of the electron supply layer 104 by electron gun vapor deposition as a third metal, and after lamp-off, lamp annealing (650 ° C., 30 nm Second), the source electrode 108 and the drain electrode 109 were formed. Next, a SiN film (film thickness 100 nm) was formed as an insulating film by P-CVD. Thereafter, a photoresist was applied to the upper surface of the SiN film, and an opening was provided by exposure and development. Thereafter, the SiN film is removed, and Al ₂ O ₃ (film thickness) is formed as a first insulating film 107 on the entire upper surfaces of the electron supply layer 104, the source electrode 108, the drain electrode 109, the p-type layer 106, and the electric field relaxation layer 105. 15 nm) was formed by the ALD method. Next, the first insulating film 107 where the diode electrode is formed was removed. Then, Ni / Au (Ni layer thickness: 10 nm, Au layer thickness: 200 nm) is formed at a predetermined position by electron gun evaporation as the first metal and the second metal, and then lifted off to form the gate electrode 110. A diode electrode 111 was formed. Furthermore, the field effect transistor 10 (10-1) of FIG. 1 was manufactured through the wiring process.

  In the present embodiment, a manufacturing example using a Si substrate as a substrate has been shown, but any other substrate such as sapphire or silicon carbide can be used. Furthermore, although the (111) plane of the Si substrate is used in this embodiment, other planes may be used. For example, if the group III nitride semiconductor is a surface on which the c-axis orientation or an orientation having an inclination of about 55 degrees in an arbitrary direction from the c-axis is grown, and the piezo effect is generated in the same direction as the first embodiment good. For example, in addition to a sapphire c-plane substrate, a substrate having an inclination in an arbitrary direction from the c-plane can be used. However, when using a substrate with an inclination from the sapphire c-plane or a-plane, it becomes difficult to obtain good crystallinity when the inclination angle increases, and therefore the inclination may be within 10 degrees in any direction. preferable.

  Similarly, in this embodiment, GaN is used as the electron transit layer 103, but other group III nitride semiconductor materials can be used as appropriate.

  Similarly, the thickness of each layer can be set to a desired thickness, but is preferably equal to or less than the critical thickness at which dislocation occurs.

  In this embodiment, no impurities are added to the GaN electron transit layer 103. This is from the viewpoint of preventing mobility from being lowered due to Coulomb scattering when impurities are added to the GaN electron transit layer. However, for example, Si, S, Se, or the like can be added as an n-type impurity depending on the purpose, such as giving priority to an increase in electron concentration over a decrease in mobility. Further, as a p-type impurity, for example, Be, C or the like can be added.

  In this embodiment, Ti / Al is used as the source electrode and the drain electrode. However, the source electrode and the drain electrode may be any metal that is in ohmic contact with the GaN which is the electron supply layer in this embodiment. Specifically, for example, a metal such as W, Mo, Si, Ti, Nb, Pt, Al, or Au can be used as the metal, and a structure in which a plurality of the metals are stacked can also be used.

  In this embodiment, Ni / Au is used as the gate metal. However, since the gate electrode is in contact only with the insulating film, any material that does not easily react with the insulating film and has high adhesion to the insulating film may be used. . As the gate metal, for example, W, Ni, Mo, Si, Ti, Pt, Al, Au, or the like can be used, and a structure in which a plurality of the substances are mixed and stacked can also be used.

  In this embodiment, Ni / Au is used as the diode electrode, but the diode electrode is preferably made of a material that makes ohmic contact with the p-type layer 106. For example, W, Ni, Mo, Si, Ti, Pt, Al, Au, or the like can be used as the material, and a structure in which a plurality of the substances are mixed and stacked can also be used.

In this embodiment, Al ₂ O ₃ is used as the first insulating film. However, the first insulating film may be, for example, one or more of Si, Mg, Hf, Zr, Al, Ti, and Ta and O. , N, and C may be used. It is also possible to form a plurality of layers.

  The field effect transistor of this example was not destroyed even when overvoltage and overpower were applied, and thus could operate at a high voltage and a large output. More specifically, the effects as described in the first embodiment can be obtained.

10, 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, 10-8, 10-9, 10-10, 10-11, 10-12, 10-13 Field Effect Transistor 101 Substrate 102 Nucleation Layer 103 Electron Traveling Layer 104 Electron Supply Layer 105 Electric Field Relaxation Layer 106 P-Type Layer 107 Gate Insulating Film 108 Source Electrode 109 Drain Electrode 110 Gate Electrode 111 Diode Electrode 112 Source Pad Part 113 Drain Pad part 114 Gate bus bar 115 i-GaN layer

Claims (26)

On the semiconductor layer, a gate electrode, a drain electrode, a source electrode, and a protective diode are arranged,
The drain electrode is formed so as to surround a part or all of the periphery of the protective diode, or
2. The field effect transistor according to claim 1, wherein there are a plurality of drain electrodes, and the protective diode is disposed between at least a pair of drain electrodes of the plurality of drain electrodes. Having at least two sets of electrode groups each including the gate electrode, the drain electrode, and the source electrode;
An electrode of the protection diode is electrically connected to the source electrode;
Adjacent to the protection diode, a set of the electrode groups is disposed on the upstream side and the downstream side of the current,
In the upstream electrode group, from the upstream side of the current, the source electrode, the gate electrode, and the drain electrode are arranged in the order,
2. The field effect transistor according to claim 1, wherein the drain electrode, the gate electrode, and the source electrode are arranged in the order from the upstream side of the current in the electrode group on the downstream side. One electrode unit is formed by the protection diode, the upstream electrode group, and the downstream electrode group,
The field effect transistor according to claim 2, wherein the plurality of electrode units are continuously arranged along a direction in which a current flows.   4. The field effect transistor according to claim 3, wherein the source electrode in the electrode unit is shared with the source electrode in another adjacent electrode unit.   In the electrode unit, the drain electrode in the upstream electrode group and the drain electrode in the downstream electrode group are combined to form one drain electrode. Item 5. The field effect transistor according to Item 3 or 4. The drain electrode is formed so as to surround part or all of the periphery of the protection diode, or formed so that the protection diode is disposed between at least a pair of drain electrodes of the plurality of drain electrodes. In the part that is
6. The total length of portions of the outer periphery of the electrode of the protective diode facing the drain electrode is at least twice the gate width of the gate electrode. 6. The field effect transistor according to 1. In addition, it has a drain bus bar or drain electrode pad,
7. The protective diode is also disposed between the drain bus bar or the drain electrode pad and a region where the gate electrode, the drain electrode, and the source electrode are disposed. The field effect transistor according to any one of the above.   8. The semiconductor device according to claim 1, further comprising a substrate and a functional semiconductor layer stacked on the substrate, wherein the functional semiconductor layer is formed of a group III nitride semiconductor. The field effect transistor according to 1.   The field effect transistor according to claim 1, wherein the protection diode is a Schottky diode.   9. The field effect transistor according to claim 1, wherein the protection diode is a pn diode having an n-type layer of a two-dimensional electron gas.   9. The field effect transistor according to claim 1, wherein the protection diode is a pin diode having a two-dimensional electron gas as an n-type layer. Including a gate electrode connection layer and a composition modulation layer,
The gate electrode connection layer is a semiconductor layer electrically connected to the gate electrode and closest to the gate electrode;
The composition modulation layer is disposed between the gate electrode connection layer and the electrode of the protection diode, and has a large band gap on the gate electrode connection layer side and a band gap on the electrode side of the protection diode. The field effect transistor according to claim 9, wherein the field effect transistor has a composition that changes as follows.   13. The field effect transistor according to claim 12, wherein the composition modulation layer is a semiconductor layer in contact with an electrode of the protection diode. Further comprising a protective diode electrode contact layer;
The protective diode electrode contact layer is a semiconductor layer in contact with the electrode of the protective diode,
13. The field effect transistor according to claim 12, wherein the composition modulation layer is disposed between the gate electrode connection layer and the protective diode electrode contact layer. The semiconductor layer in contact with the electrode of the protection diode is a semiconductor layer represented by a conductivity type and composition of i-In _x Ga _1-x N (0 ≦ x <1). 15. The field effect transistor according to 9 or 14. The semiconductor layer in contact with the electrode of the protection diode is a semiconductor layer represented by a conductivity type and composition of p-In _y Ga _1-y N (0 ≦ y <1). The field effect transistor according to 10, 11 or 14.   The composition modulation layer includes Al, and the composition changes continuously or stepwise so that the Al composition ratio is large on the gate electrode connection layer side and the Al composition ratio is small on the electrode side of the protective diode. The field effect transistor according to claim 12, wherein the field effect transistor is a semiconductor layer.   The field effect transistor according to claim 17, wherein the composition modulation layer is made of AlGaN. The semiconductor layer in contact with the electrode of the protective diode is a _{p-In z Ga 1-z} N (0 ≦ z <1) semiconductor layer, represented by the conductivity type and composition,
Furthermore, a gate electrode connection layer and an i-GaN layer are included, and the gate electrode connection layer is a semiconductor layer that is electrically connected to the gate electrode and is closest to the gate electrode,
The i-GaN layer, any one of claims 11 to 14 and 16 to 18, characterized in that it is arranged between the gate electrode connecting layer and the _{p-In z Ga 1-z} N layer Item 2. Field effect transistor. The semiconductor layer in contact with the electrode of the protective diode is a _{p-In z Ga 1-z} N (0 ≦ z <1) semiconductor layer represented by the conductivity type and composition,
Furthermore, a gate electrode connection layer and an i-AlGaN layer are included, and the gate electrode connection layer is a semiconductor layer that is electrically connected to the gate electrode and is closest to the gate electrode,
The i-AlGaN layer, any one of claims 11 to 14 and 16-19, characterized in that it is arranged between the gate electrode connecting layer and the _{p-In z Ga 1-z} N layer Item 2. Field effect transistor.   21. The field effect transistor according to claim 20, wherein the gate electrode connection layer contains Al, and an Al composition ratio of the i-AlGaN layer is equal to or less than an Al composition ratio of the gate electrode connection layer.   22. The semiconductor device according to claim 1, further comprising a gate insulating film, wherein the gate electrode is electrically connected to a part of the semiconductor constituting the field effect transistor through the gate insulating film. The field effect transistor according to any one of the above.   The gate insulating film is selected from the group consisting of at least one element selected from the group consisting of Si, Mg, Hf, Al, Ti, Ta, Zr, St, and Ba, and O, N, and C. The field effect transistor according to claim 22, comprising at least one element.   24. An electronic device comprising the field effect transistor according to any one of claims 1 to 23. Forming a gate electrode, a drain electrode, a source electrode, and a protective diode on the semiconductor layer;
In the step, the drain electrode is formed so as to surround a part or all of the periphery of the protective diode, or
A method of manufacturing a field effect transistor, comprising: forming a plurality of the drain electrodes; and forming the protection diode so that the protection diode is disposed between at least a pair of drain electrodes of the plurality of drain electrodes.   The field effect transistor according to any one of claims 1 to 23 or the manufacturing method according to claim 25, wherein the field effect transistor is used under a condition in which overvoltage or overpower is applied to the field effect transistor. How to use a field effect transistor.

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